CN114594850A

CN114594850A - Method for managing operation of system on chip

Info

Publication number: CN114594850A
Application number: CN202111458237.0A
Authority: CN
Inventors: S·朗德勒; H·卡萨涅
Original assignee: STMicroelectronics Rousset SAS
Current assignee: STMicroelectronics Rousset SAS
Priority date: 2020-12-03
Filing date: 2021-12-02
Publication date: 2022-06-07

Abstract

The present disclosure relates to a method for managing operation of a system on chip. A system on a chip (SoC) comprising: a system clock device configured to generate at least one system clock signal; a first area having a central processing unit; and a second region having Direct Memory Access (DMA) circuitry, a peripheral coupled to the DMA, and a memory containing peripheral configuration descriptor(s) executable by the DMA circuitry. In a first SoC mode of operation, the system clock device delivers the system clock signal to all regions. In a second SoC mode of operation, its system clock device does not deliver the system clock signal to any region. In a third SoC mode of operation, the system clock device distributes the system clock signal to a portion of the second region without delivering the system clock signal to other regions, and the DMA circuit configures the peripheral device in response to the execution of the configuration descriptor(s).

Description

Method for managing operation of system on chip

PRIORITY CLAIM

The present application claims priority from french patent application No. 2012630, filed on 3.12.2020, the content of which is incorporated herein by reference in its entirety to the maximum extent allowed by law.

Technical Field

Embodiments and examples relate to microelectronic devices, and in particular to management of operation and management of power consumption of a system on a chip (SOC), such as a microcontroller.

Background

A system on chip, in particular a microcontroller, comprises a number of components, in particular a Central Processing Unit (CPU), such as a processor or a microprocessor, one or more Direct Memory Access (DMA) circuits, a memory and peripherals, which may for example be different types of interfaces, such as inter-integrated circuit (I) support²C) A communication protocol, an interface to a Serial Peripheral Interface (SPI) communication protocol, and a Universal Asynchronous Receiver Transmitter (UART) type interface. All these elements are typically connected to a system bus, for example of the Advanced Microcontroller Bus Architecture (AMBA) type.

The system-on-chip further comprises a system clock device capable of generating a system clock signal for the system-on-chip.

System-on-chip power consumption is a critical parameter, especially for battery-powered systems-on-chips.

Typically, such a system-on-chip has two modes of operation, namely what is referred to as an "active" mode of operation, in which the system bus and system clock are active, the central processing unit configures the peripheral devices and the direct memory access circuit(s) performs the data transfer.

The system-on-chip also has a mode known as a "low power" mode, in which the system bus and system clocks are off, with limited peripheral functionality.

To save power, the system-on-chip may enter its low-power mode and switch back to its active mode when needed, e.g., whenever the device needs to be reconfigured and a clock system is required by the direct memory access circuitry to perform a data transfer.

However, such a switch from the low power mode to the active mode may result in increased consumption and performance loss of the central processing unit, particularly in terms of bandwidth, due to interrupt signals issued by the peripheral device for delivery to the central processing unit.

It is therefore desirable to provide management of a system-on-chip, such as a microcontroller, so that power consumption and bandwidth of the central processing unit of the system-on-chip are saved.

Disclosure of Invention

According to one embodiment and embodiment, it is proposed, inter alia, to provide the system-on-chip with a third operating mode different from the first operating mode (referred to as "active mode") and from the second operating mode (referred to as "low power" mode applicable to the whole system-on-chip), this third operating mode being a local active mode for at least one specific area of the system-on-chip, allowing other areas of the system-on-chip to remain in their "low power" mode.

The area to be "woken up" locally contains direct memory access circuitry (DMA) which is particularly able to reconfigure one or more peripherals of this wake-up area, whereas in the prior art only direct peripheral access circuitry data transfer can be performed in a "low power" mode, whereas peripheral reconfiguration requires switching back to an active mode.

According to one aspect, there is provided a system on a chip, such as a microcontroller, comprising: a system clock device configured to generate at least one system clock signal; a first area containing at least one central processing unit; and at least one second region comprising at least one direct memory access circuit, a peripheral device coupled to the direct memory access circuit, and a memory containing at least one configuration descriptor of the peripheral device and executable by direct memory access.

The second region is different from the first region.

The concept of a region has a very general meaning here.

Thus, it is common for designers of microcontrollers to divide the microcontroller into a number of domains, including, for example, domains known as Central Processing Unit (CPU) domains, which in turn may include, for example, direct memory access circuits.

Also, a region may be an entire system-on-chip domain or a subdomain of a system-on-chip domain.

Thus, if the CPU domain contains, in addition to the central processing unit, direct memory access circuitry and one or more peripheral devices, the first region may be a sub-domain containing the central processing unit and the second region may be a sub-domain containing the direct memory access circuitry and the CPU domain of the peripheral device(s) coupled to the direct memory access circuitry.

Descriptors are DMA data transfer structures that are programmed into direct memory access circuit registers and are typically loaded from memory where they can be stored.

However, it is possible that the descriptors are loaded directly into the registers of the direct memory access circuit, for example when the system on chip is initialized.

For example, a descriptor defines one or more actions that may be performed by a direct memory access circuit when descriptor information is loaded into a register of the direct memory access circuit.

The system on chip according to this aspect has a first mode of operation in which the system clock device delivers a system clock signal to all regions. This first mode of operation is therefore the active mode.

The system-on-chip has a second mode of operation in which the system clock device does not deliver the system clock signal to any region. This second mode of operation is thus an overall "low power" mode.

The system-on-chip additionally has a third mode of operation in which the system clock device distributes the system clock signal to at least a portion of the second region without delivering the system clock signal to other regions, and in which the direct memory access circuitry is capable of configuring the peripheral device in response to execution of the configuration descriptor.

This third mode of operation is thus a local active mode, all other areas remaining in their "low power" mode.

Furthermore, unlike the prior art, the direct memory access circuit is capable of configuring or reconfiguring the peripheral device without having to "wake up" the central processing unit for this purpose.

According to one embodiment, the system on chip is configured to switch from its second mode of operation to its third mode of operation in the presence of a system clock signal request issued by one of the elements of the second region.

And, the system-on-chip is advantageously configured to switch back to its second mode of operation based on the disappearance of any system clock signal request in the second region.

This also contributes to energy saving.

According to one embodiment, the memory may contain a number of descriptors, each descriptor containing a request indication, the request indication being programmable, the descriptor being assigned to a peripheral device capable of communicating a request to the second region of the direct memory access circuit.

Also, each descriptor may contain a first trigger indication, the trigger indication being programmable to indicate whether execution of the descriptor can be triggered by a trigger signal external to the direct memory access circuit, the trigger signal originating from a peripheral device, e.g., the second region.

Furthermore, each descriptor may also contain a second trigger indication, which is programmable, specifying for the descriptor a peripheral device capable of transmitting a second region of trigger signals that allow the execution of the trigger descriptor.

Thus, by these different indications, which may be programmable, for example, by a user according to the application considered by the system-on-chip, it is possible to provide for the execution of complex scenarios, including, for example, the reconfiguration of peripheral devices and the selection of peripheral devices, while keeping other areas of the system-on-chip in their low power mode.

The memory may also be configured to store a list of a number of link descriptors that are sequentially addressable by the direct memory access circuitry and that respectively represent actions to be performed by the direct memory access circuitry.

This list may contain the at least one reconfiguration descriptor.

Furthermore, when the memory contains several descriptors, the system clock device is configured to distribute, in a third operating mode, the system clock signal to all elements of the second area referred to by said descriptors in the presence of the system clock signal issued by one of the elements of this second area.

Thus, the direct memory access circuit can access all involved peripherals and not just one peripheral that needs the system clock signal.

By programming the programmable different indications of request and trigger descriptors, this helps to develop complex implementation scenarios that can be performed locally by keeping the other regions in their low power mode, even when there is a list, since the direct memory access circuitry will have access to all involved elements of the second region that will have received the system clock signal without losing time.

The descriptor list may include a selection of peripheral requests or a selection referred to as a "memory-to-memory" selection (that is, a configuration in which the direct memory access circuitry fetches, for example, data from memory to store the data in one of these registers) and a trigger selection.

According to one embodiment, in the third mode of operation, the direct memory access circuit may be configured to trigger sequential execution of the linked descriptors in response to a trigger signal triggering execution of the first descriptor of the list.

A direct memory access circuit may have multiple processing channels and in this case all descriptors may be assigned to a single channel or several different channels.

Although a further memory separate from the memory may be provided to contain data to be written or read originating from or intended for at least one peripheral device of the second area, respectively, it may be advantageous for the memory to contain at least some of the descriptors which are also intended to contain such data to be written or read originating from or intended for at least one peripheral device of the second area, respectively.

As a non-limiting example, the second region may include at least one peripheral device, the peripheral device including I²A type C interface, a device configured to deliver at least one trigger signal and possibly several trigger signals periodically or aperiodically (such as, but not limited to, a timer, an input output port, a comparator, a device for delivering an asynchronous signal, … …).

And, the memory contains a list of linked descriptors, including: a first configuration descriptor intended to configure I in a first transmission direction (e.g. in a transmission direction)²Interface C; a second descriptor intended to transfer data from the memory to the I according to the first transfer direction²Interface C, and vice versa; a third configuration descriptor intended to configure I in a second transmission direction (e.g. in reception)²Interface C; and a fourth descriptor intended to transfer data from I according to the second direction of transfer²The C interface is transferred to the memory and vice versa.

Also, the first descriptor of this list may be triggered, for example, in the presence of each trigger signal issued by a timer.

According to another aspect, a method for managing operation of a system on chip, such as a microcontroller, is provided.

The system on a chip includes: a system clock device configured to generate at least one system clock signal; a first area containing at least one central processing unit, such as a processor or microprocessor; and at least one second region comprising at least one direct memory access circuit, a peripheral coupled to the direct memory access circuit, and a memory containing at least one configuration descriptor of the peripheral and executable by the direct memory access circuit.

The method according to this aspect optionally includes placing the system-on-chip in: a first mode of operation in which the system clock device delivers a system clock signal to all regions; or a second mode of operation in which the system clock device does not deliver a system clock signal to any region; or a third mode of operation in which the system clock device distributes the system clock signal to at least a portion of the second region without delivering the system clock signal to other regions and in which the direct memory access circuitry configures the peripheral device in response to execution of the configuration descriptor.

According to one embodiment, the method includes switching from the second mode of operation to the third mode of operation in the presence of a system clock signal request issued by one of the elements of the second region.

According to one embodiment, the method includes returning to the second mode of operation with any system clock signal request in the second region disappearing.

According to one embodiment, the memory contains a number of descriptors and the method includes programming, for each descriptor, a request indication specifying for this descriptor a peripheral device capable of communicating the request to the second region of the direct memory access circuit.

According to one embodiment, the method further comprises programming a first trigger indication for each descriptor, said first trigger indication indicating whether execution of this descriptor can be triggered by a trigger signal external to the direct memory access circuit.

According to one embodiment, the method further comprises programming for each descriptor a second trigger indication specifying for this descriptor a peripheral device of the second area capable of transmitting a trigger signal allowing the execution of the trigger descriptor.

According to one embodiment, a method includes storing a list of a number of linked descriptors in a memory, the linked descriptors being sequentially addressable by a direct memory access circuit and respectively representing actions to be performed by the direct memory access circuit.

The list contains, for example, the at least one reconfiguration descriptor.

According to one embodiment, the memory contains a plurality of descriptors and the method comprises distributing a system clock signal to all elements of the second area to which said descriptors refer in the third operating mode in the presence of a system clock signal request issued by one of the elements of this second area.

According to one embodiment, the method includes triggering, by the direct memory access circuit, in a third mode of operation, sequential execution of the linked descriptors in response to a trigger signal triggering execution of a first descriptor of the list.

According to one embodiment, the direct memory access circuit has a number of channels, and the method includes assigning all of the descriptors to a single channel or to a number of different channels.

According to one embodiment, the method comprises storing in the memory data to be written or read originating from or intended for, respectively, at least one peripheral of the second area.

Drawings

Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiments and embodiments, which are in no way limiting, and the accompanying drawings, wherein:

FIG. 1 is a block diagram of a system-on-chip;

FIG. 2 is a block diagram of a direct memory access circuit;

FIG. 3 is a block diagram of a memory circuit;

FIG. 4 illustrates steps of a method;

FIG. 5 is a block diagram of a system-on-chip;

FIG. 6 is a block diagram of a memory having stored descriptors;

7-8 illustrate the performance of actions associated with a given descriptor;

FIG. 9 is a block diagram of a system-on-chip;

FIG. 10 is a block diagram of a memory having stored descriptors; and

FIG. 11 illustrates the performance of actions associated with descriptors.

Detailed Description

In fig. 1, the reference MCU represents a system on chip, here a microcontroller, comprising several areas: z1, Z2 and Z3.

The first zone Z1 contains a Central Processing Unit (CPU)1, such as a processor, and other elements (E) 7.

The second zone Z2, unlike the first zone Z1, comprises a Direct Memory Access (DMA) circuit 2 of conventional structure and known per se, a memory (M)3, such as a Static Random Access Memory (SRAM), and a number of peripherals (P), two of which are shown herein with

reference numerals

40 and 41.

The microprocessor may also contain other zones, such as a third zone Z3.

As will be seen in greater detail below, in this exemplary embodiment, second zone Z2 is a particular zone that may be "woken up" locally while other zones will remain in low power mode.

The microcontroller MCU also contains a clock generation device (C)6 of conventional construction, known per se, configured to generate a system clock signal SCLK.

This system clock signal may be delivered to the various elements of the microcontroller in a controlled manner, for example by means of a clock gating cell.

The microcontroller also contains a system bus BS.

Of course, for the sake of simplicity, the microcontroller MCU may contain other elements not shown here, such as an interconnection circuit known to those skilled in the art under the name "interconnect" to allow transactions to be routed between the master and slave devices of the microcontroller.

Zones Z1 and Z2 may be two domains of the microcontroller or two subdomain regions of the same domain. Z3 may also be a domain or sub-domain of the microcontroller.

The structure of the direct memory access circuit 2 is well known to those skilled in the art and comprises, inter alia (as shown in fig. 2), a Control Logic (CL)20, an Address Register (AR)21 and a number of registers intended to contain data, for example in this case an indication contained in a descriptor stored in the memory 3.

These descriptors may, for example, contain a request indication specifying the peripheral(s) involved that are capable of transmitting a request to the second region of the direct memory access circuit 2.

Each descriptor may also contain a first trigger indication indicating whether execution of the descriptor can be triggered by a trigger signal external to the direct memory access circuit.

Each descriptor may also contain a second trigger indication specifying for this descriptor a peripheral device capable of transmitting a second region of trigger signals that allow execution of the trigger descriptor.

All these indications may be loaded from the memory 3 into the registers (R)22, 23 of the direct memory access circuit 2.

All these indications are programmable by the user of the microcontroller, for example when other areas of the microcontroller are in low power mode, according to the intended application and the scenario to be executed locally in the second zone Z2.

Among the descriptors that can be stored in the memory 3, one or more lists of link descriptors LLI1-LLIN are considered, as schematically shown in fig. 3.

The link descriptors of the list are sequentially addressable by the direct memory access circuitry and respectively represent actions to be performed by the direct memory access circuitry.

As schematically shown in fig. 4, the system-on-chip has a first mode of operation MDF1 in which the system clock device delivers a system clock signal SCLK to all of the zones Zi.

This first mode of operation is a mode referred to as the "active" mode.

The system-on-chip furthermore has a second mode of operation (or "low power" mode), in which the system clock device does not deliver the system clock signal SCLK to any of the zones Zi, and all the zones Zi are in their low power mode.

Furthermore, the system on chip comprises a third operation mode MDF3, wherein the system clock device distributes the system clock signal SCLK to at least a part of the second area Z2, and more specifically, as will be seen in more detail below, to all elements of this second area that are involved in the execution of the descriptor, without delivering the system clock signal to other areas or other elements of the second area that are not involved in the descriptor.

This third operating mode is therefore an active mode located in the area concerned (in this case the second zone Z2), the other zones remaining in their low power mode.

As mentioned above, a particularly simple way of controlling the distribution of the clock signal may consist of: the clock gating cell is used to receive the clock signal SCLK on the one hand and the logic signals originating from the bits of the register allocated to each element of the second region on the other hand. For example, if this bit is a 1, then the system clock apparatus delivers the clock signal SCLK to the element in question, and if this bit is a zero, for example, then the system clock apparatus does not deliver the clock signal SCLK.

Also, the bits of this register are programmable, for example by a user, according to the descriptor used.

As shown in fig. 4, in the case where there is a request for a system clock signal SCLK issued by one of the elements of the second area, for example, the peripheral device 40 (step ST40), the system on chip may switch from the second operation mode MDF2 to the third operation mode MDF 3.

As will be seen in more detail below, the system clock signal is advantageously distributed to all elements of the second region specified by the associated descriptor.

Further, as shown by step ST41, the system on chip may return to the second operation mode MDF2 based on any system clock signal request in the second region disappearing.

Reference is now made more specifically to fig. 5-8 to illustrate examples of implementation of the embodiments.

In fig. 5, it is assumed that the second zone Z2 of the microcontroller MCU contains, in addition to the direct memory access circuit 2 and the memory 3, an analog-to-digital converter (ADC)40, a timer (T)41 and an SPI-type Interface (IF)42 connected to the external module MD by a bus supporting the SPI protocol.

The first zone Z1 contains the central processing unit 1.

In this example, an analog-to-digital converter 40 is connected to the temperature sensor CPT and is configured to convert analog data delivered by the sensor CPT at regular intervals.

The analog-to-digital converter 40 converts the analog data into digital data at the rate of a control signal SC2 periodically delivered by the timer 41, which in turn is clocked by its own clock signal and typically has a frequency lower than that of the system clock signal.

On the other hand, when the analog-to-digital converter 40 is ready to transmit data to the direct memory access circuit 2, the analog-to-digital converter must then use the system clock signal SCLK.

In this example, as shown in FIG. 6, the direct memory access circuit 2 has two processing channels CH1 and CH 2. It is assumed here that the memory 3 stores a list of the descriptor DSC1 related to the first channel CH1 and the four link descriptors LLI1-LLI4 related to the second channel CH 2.

The first descriptor DSC1 relates to transferring digital data converted by the converter 40 to the memory 3.

This descriptor is transferred from the memory 3 into a register of the direct memory access circuit 2 in order to (in particular) define the memory address.

The first descriptor LLI1 of the linked list processed by the second channel CH2 of the direct memory access circuit 2 is a reconfiguration descriptor that allows to increase the threshold of the analog-to-digital converter.

More specifically, the first threshold TH1 is initially defined, for example, as 80 ℃. And when the curve of values delivered by the temperature sensor CPT reaches this threshold TH1, a modification of this first threshold TH1 to a second threshold TH2 with a value of, for example, 100 ℃ is provided.

Also, this first descriptor LLI1 also contains a trigger indication indicating that it can be triggered.

Furthermore, the first descriptor contains a second trigger indication, specifying that the first descriptor can be triggered by the analog-to-digital converter when a first threshold TH1 is reached.

These two trigger indications are intended to be stored in the register 22 of the direct memory access circuit 2.

And execution of this first descriptor LLI1 is triggered by delivery of a trigger signal SDL1 (fig. 5) issued by the analog-to-digital converter 40.

The second descriptor LLI2 of this chain is the descriptor that controls the analog-to-digital converter 40 to issue an interrupt IT intended to wake up the central processing unit 1 when the curve of analog values reaches the second threshold TH 2.

More specifically, execution of this second descriptor LLI2 includes writing an indication into an interrupt register of the converter 40, which indication is provided to issue the interrupt IT when the threshold TH2 is reached.

The third descriptor LLI3 of this linked list is again a reconfiguration descriptor, which this time aims at reconfiguring the timer 41, increasing the sampling frequency of the converter 40, that is to say increasing the delivery frequency of the signal SC 2.

Finally, the fourth descriptor of the linked list is a descriptor allowing to perform the transfer of digital data which has been delivered to the interface 42 via the analog-to-digital converter 40 and stored in the memory 3 for transmission to the external module MD over the SPI bus.

Fig. 7 and 8 schematically depict the performance of actions related to the descriptor DSC1 on channel CH1 and to the descriptors LLI1-LLI4 on channel CH 2.

As shown in fig. 7, in step ST60, once the analog data converted into digital data is ready to be transferred to the direct memory access circuit 2 for storage in the memory 3, the analog-to-digital converter 40 issues a system clock signal SCLK request.

This clock signal SCLK is then distributed here to all elements of the second area, i.e. not only to the analog-to-digital converter 40 but also to the direct memory access circuit 2, the memory 3, the timer 41 and the interface 42, since the execution of the descriptors DSC1, LLI1, LLI2, LLI3 and LLI4 will involve all these elements.

The converted digital data is then transferred by the direct memory access circuit 2 to the memory 3 to the storage address contained in the address register 21 of the direct memory access circuit 2.

For the channel CH2, the first descriptor LLI1 is not executed as long as the value delivered by the temperature sensor does not reach the first threshold TH1 (step ST 71).

When the threshold TH1 is reached, the execution of the first descriptor LLI1 of the linked list is triggered by the transmission of the trigger signal SDL1 (step ST72), which has the result of changing the threshold of the converter 40 from TH1 to TH2 (step ST 73).

Next in step ST74, a second descriptor LLI2 is executed, which causes, upon reaching the second threshold value TH2, an indication intended to trigger the wake-up of the central processing unit 1 by interrupting the emission of IT to be written into an interrupt register of the converter 40.

Next, the third descriptor LLI3 is executed in step ST 75. More specifically, the transmission frequency of signal SC2 is varied in response to control signal SC 1. This added value contained in descriptor LLI3 has been stored in register 22 of direct memory access circuit 2.

Finally, the fourth descriptor LLI4 is executed to allow the value stored in the memory 3 to be transmitted to the interface SPI42 (step ST 76).

Referring now to fig. 9-11, another example embodiment is shown.

In this example, the second zone Z2 contains timers 45 and I in addition to the direct memory access circuit 2 and the memory 3²A type C interface 44, said interface being supported by I²The bus of the C communication protocol is coupled to an external module, for example a sensor MD.

In this application example, provision is made for periodically transmitting the data stored in the memory 3 to the external sensor MD and receiving data from this sensor MD to store the data in the memory 3 at the rate at which the timer 45 delivers the signal SDL 2.

In this regard, memory 3 contains a list with four link descriptors LLI10-LLI40 (FIG. 10).

The first descriptor LLI10 of the list is a "memory-to-memory" type descriptor intended to configure the interface 44 into a transmit mode while setting the number of bytes to be transmitted.

The second descriptor LLI20 is a "memory to peripheral" type descriptor intended to transfer the number of bytes defined by the first descriptor LLI 10.

The third descriptor LLI30 is a "memory-to-memory" type configuration descriptor intended to configure the interface 44 into a receive mode while setting the bytes to be received.

Finally, the fourth descriptor LLI40 is a "memory peripheral" type descriptor intended to allow the reception of the number of bytes defined in the third descriptor LLI 30.

The timer 45 uses its own time base which is slower than the frequency of the system clock signal SCLK.

Also, as shown in fig. 11, when the timer 45 periodically sends the signal SDL2 (step ST100) to the direct memory access circuit 2, this results in the triggering of the first descriptor LLI10 (step ST 101).

Thus, in step ST102 there is a request for the system clock signal SCLK issued by the direct memory access circuit 2 and this system clock signal SCLK is therefore distributed in step ST103 to all elements of the second area involved by the descriptors of the chain, i.e. not only the direct memory access circuit 2 but also the memories 3 and I²The C interface 44.

In step ST104, a descriptor LLI10 is executed, which configures the interface 44 at the time of transmission.

The direct memory access circuit 2 then loads the data relating to the second descriptor LLI20, and then stops the distribution of the clock signal SCLK since there is no longer any request for the clock signal SCLK (step ST 105).

When the interface 44 is ready to transfer data, there is again a request for the clock signal LCLK by the interface (step ST107), and the second descriptor LLI20 is executed (step ST 106).

As shown by the loop back of the data transfer, the clock signal SCLK is allocated only for "DMA" transfer of data (step ST107), and is not distributed between "DMA" transfers (step ST 108).

Next, when all the data are transferred, the third descriptor LLI30 is loaded from the memory 3 into the register of the direct memory access circuit, and the distribution of the clock signal SCLK is stopped again in step ST108 until the third descriptor LLI30 is executed in step ST109 to configure I upon reception²C interface 44.

For this execution, the clock signal SCLK is distributed again in step ST 110.

And, in step ST111, when passing I²When the C interface receives data, the distribution of the signal SCLK is interrupted until the interface is ready to transfer the data to the direct memory access circuit in step ST112 by executing the descriptor LLI 40. The system clock signal SCLK is then distributed (step ST 113).

Again, as shown by the loop back at the time of data reception, the clock signal SCLK is distributed only for "DMA" transfers of data (step ST113), and is not distributed between "DMA" transfers (step ST 114).

Of course, a dialog box with a single sensor MD is described here. Of course, several sensor MDs and multiple lists of linking descriptors similar to the list LLI10-LLI40 may be provided, which are executed in succession in order to interrogate the various sensors in succession.

Claims

1. A system on a chip, comprising:

a system clock device configured to generate at least one system clock signal;

a first area including a central processing unit;

a second region having an element comprising: direct memory access circuitry, a peripheral coupled to the direct memory access circuitry, and a memory containing at least one configuration descriptor for the peripheral, wherein the at least one configuration descriptor is executable by the direct memory access circuitry;

wherein the system on chip has:

a first mode of operation in which the system clock device delivers the system clock signal to all regions;

a second mode of operation in which the system clock device does not deliver the system clock signal to any region; and

a third mode of operation in which the system clock device distributes the system clock signal to at least a portion of the second region without delivering the system clock signal to other regions, and in which the direct memory access circuitry is operative to configure the peripheral device in response to the execution of the at least one configuration descriptor.

2. The system on chip of claim 1, configured to switch from the second mode of operation to the third mode of operation in the presence of a system clock signal request generated by one of the elements of the second region.

3. The system on chip of claim 2, configured to switch from the third mode of operation to the second mode of operation upon a disappearance of the system clock signal request from an element of the second region.

4. The system on a chip of claim 1, wherein the at least one configuration descriptor in the memory comprises a number of descriptors, each descriptor of the number of descriptors containing a programmable request indication specifying for the descriptor the peripheral capable of transmitting requests to the second region of the direct memory access circuit.

5. The system-on-chip of claim 1, wherein the at least one configuration descriptor in the memory comprises a number of descriptors, each descriptor of the number of descriptors containing a first programmable trigger indication indicating whether execution of the descriptor can be triggered by a trigger signal external to the direct memory access circuit.

6. The system on a chip of claim 5, wherein each descriptor of the number of descriptors also contains a second programmable trigger indication specifying, for the descriptor, the peripheral capable of transmitting the second region of the trigger signal that allows triggering of the execution of the descriptor.

7. The system-on-chip of claim 1, wherein the memory is configured to store a list of a number of linked descriptors that are sequentially addressable by the direct memory access circuitry and that respectively represent actions to be performed by the direct memory access circuitry.

8. The system-on-chip of claim 7, wherein the list contains the at least one reconfiguration descriptor.

9. The system-on-chip of claim 7, wherein the at least one configuration descriptor in the memory comprises a number of descriptors, each descriptor of the number of descriptors containing a first programmable trigger indication indicating whether execution of the descriptor can be triggered by a trigger signal external to the direct memory access circuit, and further wherein in the third mode of operation, the direct memory access circuit is configured to trigger the sequential execution of the linked descriptors in response to the trigger signal triggering the execution of a first descriptor in the list.

10. The system on chip of claim 1, configured to switch from the second mode of operation to the third mode of operation in the presence of a system clock signal request generated by one of the elements of the second region, wherein the at least one configuration descriptor in the memory comprises a number of descriptors, and wherein in the third mode of operation the system clock device is configured to distribute the system clock signal to all of the elements of the second region referred to by the number of descriptors in the presence of the system clock signal request issued by one of the elements of the second region.

11. The system on a chip of claim 1, wherein the direct memory access circuit has a number of channels, and wherein the at least one configuration descriptor in the memory comprises a number of descriptors, and wherein the descriptors are assigned to a single channel.

12. The system on a chip of claim 1, wherein the direct memory access circuit has a number of channels, and wherein the at least one configuration descriptor in the memory comprises a number of descriptors, and wherein the descriptors are assigned to a number of different channels.

13. The system on chip of claim 1, wherein the memory is further configured to contain data to be written or read originating from or intended for at least one peripheral device of the second region, respectively.

14. The system-on-chip of claim 1, wherein the second region comprises: at least one peripheral device comprising I²A type C interface and means for delivering at least one trigger signal; and wherein the memory contains a list of link descriptors, including:

a first configuration descriptor for configuring the I in a first transmission direction²Interface C;

a second descriptor for transferring data from the memory to the I according to the first transfer direction²C interface, or the data is transferred from the I²The interface C is transmitted to the memory;

a third configuration descriptor for configuring the I in a second transmission direction²Interface C; and

a fourth descriptor for data from the I according to the second transmission direction²C interface to the memory or data from the memory to the I²A C interface, a first descriptor of the list being capable of being present by the apparatus for deliveryTriggered in the case of each trigger signal issued.

15. A method for managing operation of a system-on-chip, the system-on-chip comprising: a system clock device configured to generate at least one system clock signal; a first area including a central processing unit; and at least one second region having elements including at least one direct memory access circuit, a peripheral coupled to the direct memory access circuit, and a memory containing at least one configuration descriptor of the peripheral executable by the direct memory access circuit, wherein the method comprises:

selectively placing the system-on-chip in a first mode of operation in which the system clock device delivers the system clock signal to all regions;

selectively placing the system-on-chip in a second mode of operation in which the system clock device does not deliver the system clock signal to any region; and

selectively placing the system-on-chip in a third mode of operation, wherein the system clock device distributes the system clock signal to at least a portion of the second region without delivering the system clock signal to other regions, and wherein the direct memory access circuit is operative to configure the peripheral device in response to the execution of the at least one configuration descriptor.

16. The method of claim 15, further comprising: switching from the second mode of operation to the third mode of operation in the presence of a system clock signal request generated by one of the elements of the second region.

17. The method of claim 16, further comprising: switching from the third mode of operation to the second mode of operation upon a disappearance of the system clock signal request from an element of the second region.

18. The method of claim 15, wherein the at least one configuration descriptor in the memory comprises a number of descriptors, and the method comprises: for each descriptor of the number of descriptors, containing a programmable request indication specifying for the descriptor the peripheral capable of transmitting requests to the second region of the direct memory access circuit.

19. The method of claim 15, wherein the at least one configuration descriptor in the memory comprises a number of descriptors, the method further comprising: programming, for each descriptor of the number of descriptors, a first trigger indication indicating whether execution of the descriptor can be triggered by a trigger signal external to the direct memory access circuit.

20. The method of claim 19, further comprising programming a second trigger indication specifying, for the descriptor, the peripheral device of the second region capable of transmitting the trigger signal, the trigger signal allowing triggering of the execution of the descriptor.

21. The method of claim 15, further comprising: storing a list of a number of link descriptors in the memory, the number of link descriptors being sequentially addressable by the direct memory access circuitry and the number of link descriptors each representing an action to be performed by the direct memory access circuitry.

22. The method of claim 21, wherein the list contains the at least one reconfiguration descriptor.

23. The method of claim 21, wherein the at least one configuration descriptor in the memory comprises a number of descriptors, the method further comprising:

programming, for each descriptor of the number of descriptors, a first trigger indication indicating whether execution of the descriptor can be triggered by a trigger signal external to the direct memory access circuit; and

in the third mode of operation, triggering, by the direct memory access circuitry, the sequential execution of the linked descriptors in response to the trigger signal triggering the execution of a first descriptor in the list.

24. The method of claim 15, further comprising:

switching from the second mode of operation to the third mode of operation in the presence of a system clock signal request generated by one of the elements of the second region;

storing a number of descriptors in the memory; and

in the third mode of operation and in the presence of the system clock signal request generated by one of the elements of the second region, distributing the system clock signal to all of the elements in the second region referred to by the descriptor.

25. The method of claim 15, wherein the direct memory access circuit has a number of channels, and the method further comprises: all of the descriptors are assigned to a single lane.

26. The method of claim 15, wherein the direct memory access circuit has a number of channels, and the method further comprises: all of the descriptors are assigned to several different lanes.

27. The method of claim 15, further comprising: storing data to be written or read in the memory originating from or intended for at least one peripheral device of the second area, respectively.