CN114589619B - Semiconductor polishing pad and preparation method thereof - Google Patents

Semiconductor polishing pad and preparation method thereof Download PDF

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Publication number
CN114589619B
CN114589619B CN202011397105.7A CN202011397105A CN114589619B CN 114589619 B CN114589619 B CN 114589619B CN 202011397105 A CN202011397105 A CN 202011397105A CN 114589619 B CN114589619 B CN 114589619B
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China
Prior art keywords
polishing pad
dispersion
semiconductor
pore structure
mixture
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CN202011397105.7A
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CN114589619A (en
Inventor
李善雄
杨涛
张月
田光辉
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/11Lapping tools
    • B24B37/20Lapping pads for working plane surfaces
    • B24B37/24Lapping pads for working plane surfaces characterised by the composition or properties of the pad materials
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00Lapping machines or devices; Accessories
    • B24B37/11Lapping tools
    • B24B37/20Lapping pads for working plane surfaces
    • B24B37/26Lapping pads for working plane surfaces characterised by the shape of the lapping pad surface, e.g. grooved
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24DTOOLS FOR GRINDING, BUFFING OR SHARPENING
    • B24D18/00Manufacture of grinding tools or other grinding devices, e.g. wheels, not otherwise provided for

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)

Abstract

The invention provides a semiconductor polishing pad, comprising: a polishing pad main body; the pore structures are uniformly distributed in the polishing pad main body, and the interface between the pore structures and the polishing pad main body is provided with folds. Also provided is a method for preparing a semiconductor polishing pad, comprising: treating the dispersion in powder form to form scratches on the surface of the dispersion; pouring the dispersion having scratches on the surface thereof into a polishing pad body material in a liquid state to form a mixture of the dispersion and the polishing pad body material; the mixture is cured and shaped to form a polishing pad. The semiconductor polishing pad provided by the invention can improve the absorption capacity of the polishing pad to the polishing liquid and improve the polishing efficiency.

Description

Semiconductor polishing pad and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor grinding pad and a preparation method thereof.
Background
Chemical Mechanical Planarization (CMP) is a technique for planarizing a raised structure on a wafer surface by mechanically and chemically reacting a polishing solution with a polishing pad carried on a polishing head. CMP polishing pads are very important accessories for performing CMP processes due to the polishing phenomena occurring on the wafer surface and the polishing pad surface.
During polishing, the polishing pad absorbs the polishing liquid, and thus, the polishing liquid chemically reacts with the wafer surface along with mechanical polishing.
In the process of realizing the invention, the inventor finds that at least the following technical problems exist in the prior art:
in the prior art, the polishing pad has less absorption amount of polishing liquid, so that the polishing efficiency is lower.
Disclosure of Invention
The semiconductor grinding pad and the preparation method thereof can improve the absorption of the polishing liquid by the grinding pad and improve the grinding efficiency.
In a first aspect, a semiconductor polishing pad is provided, comprising:
a polishing pad main body;
the pore structures are uniformly distributed in the polishing pad main body, and the interface between the pore structures and the polishing pad main body is provided with folds.
Optionally, the shape of the pore structure is ellipsoidal.
Optionally, the pore structure is a solid particle with folds on the surface.
Optionally, the pore structure has a particle size of 20um to 100um.
Optionally, the total volume of the pore structure is 10% to 70% of the total volume of the semiconductor polishing pad.
Optionally, the number of folds on the surface of the hole structure is 10-2000.
In a second aspect, a method for preparing a semiconductor polishing pad is provided, comprising:
treating the dispersion in powder form to form scratches on the surface of the dispersion;
pouring the dispersion having scratches on the surface thereof into a polishing pad body material in a liquid state to form a mixture of the dispersion and the polishing pad body material;
the mixture is cured and shaped to form a polishing pad.
Optionally, the treating the dispersion in a powder state to scratch the surface of the dispersion comprises:
accelerating the rotation of the dispersion and the metal beads by using a centrifugal accelerator; to form scratches on the surface of the dispersion.
Optionally, the polishing pad body material is polyurethane.
Optionally, the curing and shaping the mixture to form the polishing pad comprises:
a hardener is added to the mixture to polymerize the polyurethane prepolymer in the mixture into polyurethane.
According to the technical scheme, the interface of the hole structure in the polishing pad and the main body material is wrinkled, so that the interface area of the main body material is increased, the absorption amount of the polishing liquid in the polishing pad is increased, the polishing efficiency can be increased when the absorption amount of the polishing liquid in the polishing pad is large, and the production cost is reduced.
Drawings
FIG. 1 is a schematic view of a semiconductor polishing pad according to an embodiment of the invention.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
An embodiment of the present invention provides a semiconductor polishing pad, including: a polishing pad main body 1; the pore structures 2 are uniformly distributed in the polishing pad body 1, and the interface between the pore structures 2 and the polishing pad body 1 is provided with folds. The polishing pad body 1 is generally made of a polyurethane material, and specifically, the polishing pad body 1 is formed by polymerizing a polyurethane prepolymer, which is formed by a chemical reaction of an isocyanate including one or a mixture of two of toluene diisocyanate or diphenylmethane diisocyanate, and a polyol including polytetramethylene glycol. The pore structure 2 may include solid powder expansion and hollowing or be caused by gas fusion, and the pore structure is uniformly dispersed in the material of the main body 1, so that an interface is formed between the pore structure 2 and the polishing pad main body 1, and after the interface between the pore structure 2 and the polishing pad main body 1 is wrinkled, the specific surface area of the pore structure can be increased, so that the interface area of the polishing pad main body 1 can be increased.
According to the technical scheme, the interface between the dispersion 2 in the polishing pad and the main body material is wrinkled, so that the interface area of the main body material is increased, the absorption amount of the polishing liquid in the polishing pad is increased, the polishing efficiency can be improved when the absorption amount of the polishing liquid in the polishing pad is large, and the production cost is reduced.
As an alternative embodiment, the shape of the pore structure 2 is ellipsoidal. The ellipsoidal shape is easy to form, so that complex process is not required in the preparation process, and the ellipsoidal shape can be formed simply, conveniently and quickly.
As an alternative embodiment, the pore structure 2 has a particle size of 20um to 100um. The particle size of the pore structure 2 can be selected according to the type of polishing solution and the polishing process, the smaller the particle size of the pore structure 2, the larger the interface area of the polishing pad main body 1, but the smaller the particle size of the pore structure 2, the more difficult the process of the polishing pad is, and the lower the process tolerance is. Specifically, the particle diameter of the pore structure 2 may be selected to be 20um, 40um, 60um, 80um or 100um.
As an alternative embodiment, the total volume of the pore structure 2 is 10% to 70% of the total volume of the semiconductor polishing pad. The proportion of the total volume of the pore structure 2 to the total volume of the semiconductor polishing pad may be selected according to the specific polishing process and polishing liquid used, and the larger the proportion of the dispersion 2, the larger the interface area of the polishing pad body 1, but other parameters such as hardness of the polishing pad may be affected. Specifically, the ratio may be selected from 10%, 30%50% or 70%.
As an alternative embodiment, the number of folds on the surface of the hole structure 2 is 10 to 2000. The larger the number of wrinkles on the surface of the pore structure 2, the larger the interface area of the polishing pad body 1, but the larger the number of wrinkles of the pore structure 2, the finer the process size required in the preparation of the pore structure 2, and the longer the time. Specifically, the number of folds may be 10, 100, 500, 1000, 1500 or 2000.
The embodiment of the invention also provides a preparation method of the semiconductor grinding pad, which comprises the following steps: treating the dispersion in powder form to form scratches on the surface of the dispersion; the dispersion in powder form is expanded and hollow by heating, and scratches formed on the surface of the dispersion are a source of interfacial wrinkles after the completion of the preparation. Pouring the dispersion having scratches on the surface thereof into a polishing pad body material in a liquid state to form a mixture of the dispersion and the polishing pad body material; the liquid state main body material is polyurethane prepolymer, the polyurethane prepolymer is formed by chemical reaction of isocyanate and polyol, the isocyanate comprises one or two mixtures of toluene diisocyanato or diphenylmethane diisocyanate, and the polyol comprises polytetramethylene glycol. Solidifying and shaping the mixture to form a polishing pad; during the curing process, a hardener is added into the prepolymer to link the chemical chains of the prepolymer together to form polyurethane; the prepolymer is heated while the hardener is added, which volatilizes byproducts generated by the chemical reaction, thereby forming a hardened polyurethane. The above process may be reacted in a mold so that the polishing pad is formed after hardening is completed.
As an alternative embodiment, the treating the dispersion in a powder state to scratch the surface of the dispersion comprises: accelerating the rotation of the dispersion and the metal beads by using a centrifugal accelerator; to form scratches on the surface of the dispersion. The metal beads and the dispersion are added into a centrifugal accelerator for accelerating rotation, so that friction is formed between the dispersion and the metal beads, and scratches are formed on the surface of the dispersion, wherein the scratches are the sources of wrinkles on the main body interface of the grinding pad after the preparation is finished.
As an alternative embodiment, the polishing pad body material is polyurethane. The polyurethane has the characteristic of wear resistance, and meanwhile, the preparation process and the material cost of the polishing pad are lower, so that the polishing pad meeting the requirements can be prepared at lower cost.
As an alternative embodiment, the curing and shaping the mixture to form the polishing pad comprises: a hardener is added to the mixture to polymerize the polyurethane prepolymer in the mixture into polyurethane. The hardening agent is added into the mixture to prolong the chemical chain of the prepolymer, and the mixture needs to be heated at the same time, so that the dispersion can maintain the original shape and property in the reaction process, and can be gasified and volatilized or chemically reacted to form gas.
According to the technical scheme, the interface of the dispersion in the polishing pad and the main body material is wrinkled, so that the interface area of the main body material is increased, the absorption amount of the polishing liquid in the polishing pad is increased, the polishing efficiency can be improved when the absorption amount of the polishing liquid in the polishing pad is large, and the production cost is reduced.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The present invention is not limited to the above embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present invention are intended to be included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims (10)

1. A semiconductor polishing pad comprising:
a polishing pad main body;
the pore structures are uniformly distributed in the polishing pad main body, and the interface between the pore structures and the polishing pad main body is provided with folds; wherein the pore structure is a hollow pore structure formed by expanding a dispersion with scratches on the surface after being heated.
2. The semiconductor polishing pad of claim 1, wherein the pore structure has an ellipsoidal shape.
3. The semiconductor polishing pad of claim 1, wherein the pore structure surface has corrugations.
4. The semiconductor polishing pad according to claim 1, wherein the pore structure has a particle diameter of 20um to 100um.
5. The semiconductor polishing pad of claim 1, wherein the total volume of the pore structure comprises 10% to 70% of the total volume of the semiconductor polishing pad.
6. The semiconductor polishing pad according to claim 1, wherein the number of wrinkles on the surface of the pore structure is 10 to 2000.
7. A method for preparing a semiconductor polishing pad, comprising:
treating the dispersion in powder form to form scratches on the surface of the dispersion;
pouring the dispersion having scratches on the surface thereof into a polishing pad body material in a liquid state to form a mixture of the dispersion and the polishing pad body material;
the mixture is cured and shaped to form a polishing pad.
8. The method of manufacturing a semiconductor polishing pad according to claim 7, wherein the treating the dispersion in a powder state to scratch the surface of the dispersion comprises:
accelerating the rotation of the dispersion and the metal beads by using a centrifugal accelerator; to form scratches on the surface of the dispersion.
9. The method of manufacturing a semiconductor polishing pad as recited in claim 7, wherein the polishing pad body material is polyurethane.
10. The method of claim 7, wherein the curing and shaping the mixture to form the polishing pad comprises:
a hardener is added to the mixture to polymerize the polyurethane prepolymer in the mixture into polyurethane.
CN202011397105.7A 2020-12-03 2020-12-03 Semiconductor polishing pad and preparation method thereof Active CN114589619B (en)

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CN114589619B true CN114589619B (en) 2023-04-25

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Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000000755A (en) * 1998-06-16 2000-01-07 Sony Corp Polishing pad and polishing method
KR100497205B1 (en) * 2001-08-02 2005-06-23 에스케이씨 주식회사 Chemical mechanical polishing pad with micro-holes
JP4075403B2 (en) * 2002-02-22 2008-04-16 住友電気工業株式会社 Polishing method and polishing apparatus for GaAs wafer
JP2004260070A (en) * 2003-02-27 2004-09-16 Sumitomo Bakelite Co Ltd Foamed polishing material and polishing method using the same
CN100537148C (en) * 2006-11-28 2009-09-09 中芯国际集成电路制造(上海)有限公司 Polishing pad and chemico-mechanical polishing method
JP2010522093A (en) * 2007-03-21 2010-07-01 スリーエム イノベイティブ プロパティズ カンパニー How to remove surface defects
CN207929220U (en) * 2017-06-23 2018-10-02 江苏果麦环保科技有限公司 A kind of catalyst carrier of internal tooth wheel topology

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