CN114582859B - ESD protection device structure for thin film transistor and preparation method - Google Patents
ESD protection device structure for thin film transistor and preparation method Download PDFInfo
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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Abstract
The invention provides an ESD protective device structure for a thin film transistor and a preparation method thereof, which provides a substrate which is sequentially overlapped with a substrate, a first insulating layer, an intermediate layer, a second insulating layer and a device layer from bottom to top, and forming a first conductive type layer and a second conductive type layer in contact with the first insulating layer in the substrate, thereby preparing the ESD protection diode on the substrate through the first conductive type layer and the second conductive type layer to form a PN junction in the substrate, the PN junction can carry out ESD protection on a thin film transistor circuit prepared in a device layer in the subsequent process, and because the thin film transistor basically belongs to the low-temperature process, therefore, the performance degradation of PN junctions in the substrate cannot be caused by the subsequent preparation process of the thin film transistor, and further, when ESD occurs, the middle layer can also shield the influence of PN junction leakage current on the thin film transistor, so that the voltage withstanding problem of the ESD protection device structure of the thin film transistor can be effectively solved.
Description
Technical Field
The invention belongs to the field of semiconductors, and relates to an ESD (electro-static discharge) protection device structure for a thin film transistor and a preparation method thereof.
Background
Static electricity is a phenomenon commonly found in nature, and is generated when two dielectric materials with different dielectric constants rub against each other. When an object with static electricity returns to a neutral state after releasing the static electricity, the phenomenon of static electricity release is called Electrostatic Discharge (ESD).
Due to high mobility and good heat dissipation performance of thin film channels, microelectronic device technology based on thin film channels is considered as one of effective paths for improving the performance of integrated circuits. However, due to the fact that the thin film channel region is small, doping is difficult, a PN junction is achieved in the transistor, the source-drain junction barrier based on Schottky contact is low, and in addition, the device is easy to break down when high voltage is met due to the small thickness of the device. Therefore, ESD protection of thin film transistors based on thin films as channels is a problem to be solved urgently.
Therefore, it is necessary to provide an ESD protection device structure for a thin film transistor and a method for manufacturing the same.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an ESD protection device structure for a thin film transistor and a method for manufacturing the ESD protection device structure, which are used to solve the problem of voltage withstanding of the ESD protection device structure of the thin film transistor in the prior art.
To achieve the above and other related objects, the present invention provides a method for manufacturing an ESD protection device structure for a thin film transistor, comprising the steps of:
providing a substrate, wherein the substrate comprises a substrate, a first insulating layer, an intermediate layer, a second insulating layer and a device layer which are sequentially stacked from bottom to top;
defining a thin film transistor region in the device layer, and forming a device insulating layer at the periphery of the thin film transistor region;
forming a first groove, wherein the first groove penetrates through the device insulating layer and the second insulating layer and exposes the middle layer;
forming an intermediate insulating layer at the bottom of the first trench, wherein the intermediate insulating layer penetrates through the intermediate layer and is in contact with the first insulating layer;
forming a second groove, wherein the second groove is communicated with the first groove, penetrates through the middle insulating layer and the first insulating layer and exposes the substrate;
forming a first conductive type layer and a second conductive type layer in contact in the substrate based on the first trench and the second trench;
and depositing metal in the first groove and the second groove to form a metal electrode electrically connected with the first conductive type layer and the second conductive type layer.
Optionally, the substrate comprises a double buried layer SOI substrate.
Optionally, the double buried layer SOI substrate is prepared by adopting a 2-time smart cut method.
Optionally, the thin film transistor region is formed with a thin film transistor channel comprising one of a channel composed of doped silicon, composed of carbon nanotubes, or composed of a two-dimensional material.
Optionally, the device insulating layer and the intermediate insulating layer are prepared by a wet oxidation method.
Optionally, the first conductivity type layer and the second conductivity type layer are formed to penetrate and cover the substrate along a transverse direction.
The present invention also provides an ESD protection device structure for a thin film transistor, comprising:
the substrate comprises a substrate, a first insulating layer, an intermediate layer, a second insulating layer and a device layer which are sequentially stacked from bottom to top;
the device insulating layer is positioned at the periphery of a thin film transistor region defined in the device layer;
a first trench penetrating the device insulating layer and the second insulating layer and exposing the intermediate layer;
the middle insulating layer is positioned at the bottom of the first groove, penetrates through the middle layer and is in contact with the first insulating layer;
the second groove is communicated with the first groove, penetrates through the middle insulating layer and the first insulating layer and exposes the substrate;
a first conductivity type layer and a second conductivity type layer in contact, the first conductivity type layer and the second conductivity type layer being located in the substrate;
and the metal electrode is filled in the first groove and the second groove and is electrically connected with the first conductive type layer and the second conductive type layer.
Optionally, the substrate comprises a double buried layer SOI substrate.
Optionally, the thin film transistor region has a thin film transistor channel comprising one of a channel composed of doped silicon, composed of carbon nanotubes, or composed of a two-dimensional material.
Optionally, the first conductivity type layer and the second conductivity type layer laterally penetrate and cover the substrate.
As described above, the ESD protection device structure for thin film transistor and the manufacturing method thereof of the present invention provide a substrate stacked with a substrate, a first insulating layer, an intermediate layer, a second insulating layer and a device layer from bottom to top, and a first conductive type layer and a second conductive type layer in contact with the first insulating layer are formed in the substrate, thereby preparing the ESD protection diode on the substrate through the first conductive type layer and the second conductive type layer to form a PN junction in the substrate, the PN junction can carry out ESD protection on a thin film transistor circuit prepared in a device layer in the subsequent process, and because the thin film transistor basically belongs to the low-temperature process, therefore, the performance degradation of the PN junction in the substrate cannot be caused by the subsequent preparation process of the thin film transistor, and further, when ESD occurs, the middle layer can also shield the influence of PN junction leakage current on the thin film transistor, so that the voltage withstanding problem of the ESD protection device structure of the thin film transistor can be effectively solved.
Drawings
FIG. 1 is a schematic view of a substrate according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a device insulating layer formed in the embodiment of the invention.
Fig. 3 is a schematic structural diagram illustrating a first trench formed in an embodiment of the invention.
Fig. 4 is a schematic structural diagram of the intermediate insulating layer after being formed according to the embodiment of the invention.
Fig. 5 is a schematic structural diagram illustrating a second trench formed in the embodiment of the invention.
Fig. 6 is a schematic structural diagram illustrating a first conductive type layer formed in an embodiment of the invention.
Fig. 7 is a schematic structural diagram illustrating a second conductive type layer formed in the embodiment of the invention.
Fig. 8 is a schematic structural diagram after forming a metal electrode according to an embodiment of the present invention.
Description of the element reference numerals
100-a substrate; 200-a first insulating layer; 300-an intermediate layer; 400-a second insulating layer; 500-a device layer; 501-thin film transistor area; 502-device insulating layer; 601-a first trench; 602-a second trench; 700-an intermediate insulating layer; 801-a first conductivity type layer; 802-a second conductivity type layer; 900-metal electrodes.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Spatially relative terms, such as "under," "below," "lower," "below," "over," "upper," and the like, may be used herein for convenience in describing the relationship of one element or feature to another element or feature illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. When "between … …" is used, both end points are included.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
The embodiment provides a preparation method of an ESD protection device structure for a thin film transistor, which comprises the following steps:
s1: providing a substrate, wherein the substrate comprises a substrate, a first insulating layer, an intermediate layer, a second insulating layer and a device layer which are sequentially stacked from bottom to top;
s2: defining a thin film transistor region in the device layer, and forming a device insulating layer at the periphery of the thin film transistor region;
s3: forming a first groove, wherein the first groove penetrates through the device insulating layer and the second insulating layer and exposes the middle layer;
s4: forming an intermediate insulating layer at the bottom of the first trench, wherein the intermediate insulating layer penetrates through the intermediate layer and is in contact with the first insulating layer;
s5: forming a second groove, wherein the second groove is communicated with the first groove, penetrates through the middle insulating layer and the first insulating layer and exposes the substrate;
s6: forming a first conductive type layer and a second conductive type layer in contact in the substrate based on the first trench and the second trench;
s7: and depositing metal in the first groove and the second groove to form a metal electrode electrically connected with the first conductive type layer and the second conductive type layer.
The method for manufacturing the ESD protection device structure for the thin film transistor of this embodiment provides a substrate on which a substrate, a first insulating layer, an intermediate layer, a second insulating layer and a device layer are sequentially stacked from bottom to top, and a first conductive type layer and a second conductive type layer in contact with the first insulating layer are formed in the substrate, thereby preparing the ESD protection diode on the substrate through the first conductive type layer and the second conductive type layer to form a PN junction in the substrate, the PN junction can carry out ESD protection on a thin film transistor circuit prepared in a device layer in the subsequent process, and because the thin film transistor basically belongs to the low-temperature process, therefore, the performance degradation of the PN junction in the substrate cannot be caused by the subsequent preparation process of the thin film transistor, and further, when ESD occurs, the middle layer can also shield the influence of PN junction leakage current on the thin film transistor, so that the voltage withstanding problem of the ESD protection device structure of the thin film transistor can be effectively solved.
Specifically, referring to fig. 1 to 8, the following describes a method for manufacturing an ESD protection device structure for a thin film transistor in this embodiment with reference to the accompanying drawings.
First, step S1 is performed, and referring to fig. 1, a base including a substrate 100, a first insulating layer 200, an intermediate layer 300, a second insulating layer 400, and a device layer 500 stacked in this order from bottom to top is provided.
As an example, the substrate may include a double buried layer SOI substrate.
Specifically, the base in this embodiment is the double-buried-layer SOI base, that is, in the base, the substrate 100 is an undoped silicon substrate, the first insulating layer 200 is a silicon oxide layer, the intermediate layer 300 is an undoped silicon layer, the second insulating layer 400 is a silicon oxide layer, and the device layer 500 is a silicon layer.
The method for forming the double buried layer SOI substrate may include 2 smart cut processes, and the specific steps for preparing the double buried layer SOI substrate are not limited herein, but the specific material of the substrate is not limited thereto.
Next, step S2 is executed, referring to fig. 2, to define a tft region 501 in the device layer 500, and form a device insulating layer 502 on the periphery of the tft region 501.
As an example, the thin film transistor region 501 may be formed with a thin film transistor channel, wherein the thin film transistor channel may include one of a channel composed of doped silicon, composed of carbon nanotubes, or composed of a two-dimensional material.
Specifically, the thin film transistor region 501 may be used to fabricate a P-type thin film transistor, an N-type thin film transistor, a carbon nano-thin film transistor, a two-dimensional material thin film transistor, or the like, and a method for forming a channel of the thin film transistor may include a solution method or a nano-operation laying, and the like.
As an example, the device insulating layer 502 may be prepared using a wet oxidation process.
Specifically, in the embodiment, the device layer 500 made of silicon is converted into the device insulating layer 502 made of silicon oxide by using a wet oxidation method, but the method for oxidizing the device layer 500 is not limited thereto, and a process such as a thermal oxidation method may be used, which is not limited herein.
Next, step S3 is executed, referring to fig. 3, a first trench 601 is formed, where the first trench 601 penetrates through the device insulating layer 502 and the second insulating layer 400, and exposes the intermediate layer 300.
As an example, the method of forming the first trench 601 may include wet etching.
Specifically, in the embodiment, the method for forming the first trench 601 uses HF acid to perform etching to prepare the first trench 601 having a certain aspect ratio, but is not limited thereto, and if dry etching may also be used, which is not limited herein.
Next, step S4 is executed, referring to fig. 4, an intermediate insulating layer 700 is formed at the bottom of the first trench 601, and the intermediate insulating layer 700 penetrates through the intermediate layer 300 and contacts the first insulating layer 200.
Specifically, after the first trench 601 is formed, the exposed intermediate layer 300 made of silicon may be oxidized into the intermediate insulating layer 700 made of silicon oxide by an oxidation method, and the intermediate insulating layer 700 penetrates through the intermediate layer 300 and contacts with the first insulating layer 200.
As an example, the interlayer insulating layer 700 may be prepared using a wet oxidation method.
Specifically, in the embodiment, the exposed intermediate layer 300 made of silicon is converted into the intermediate insulating layer 700 made of silicon oxide by using a wet oxidation method, but the method for oxidizing the intermediate layer 300 is not limited thereto, and processes such as a thermal oxidation method may be used, which are not described herein.
Next, step S5 is executed, referring to fig. 5, a second trench 602 is formed, the second trench 602 is connected to the first trench 601, and the second trench 602 penetrates through the middle insulating layer 700 and the first insulating layer 200, and exposes the substrate 100.
As an example, the method of forming the second trench 602 may include wet etching.
Specifically, in the present embodiment, the method for forming the second trench 602 uses HF acid for etching to prepare the second trench 602 having a certain aspect ratio, but is not limited thereto, and for example, dry etching may also be used, and the like, which is not limited herein.
Next, step S6 is executed, referring to fig. 6 and 7, to form a first conductive type layer 801 and a second conductive type layer 802 in the substrate 100 in contact with each other based on the first trench 601 and the second trench 602.
Specifically, with the first trench 601 as a window, a P + region is formed by implanting boron or the like into the substrate 100, and lateral diffusion is controlled by high-temperature annealing to form the first conductivity type layer 801; and forming an N + region by implanting arsenic or the like into the substrate 100 with the second trench 602 as a window, and controlling lateral diffusion by high-temperature annealing to form the second conductive type layer 802 in contact with the first conductive type layer 801 to form a PN junction.
As an example, the first conductivity type layer 801 and the second conductivity type layer 802 are preferably formed to penetrate and cover the substrate 100 in a lateral direction; the first conductive type layer 801 and the second conductive type layer 802 are in contact with the first insulating layer 200.
Specifically, the ESD protection diode may be prepared in the substrate 100 through the first conductive type layer 801 and the second conductive type layer 802 to form a PN junction, and preferably, a projection of the thin film transistor region 501 in the device layer 500 along a vertical direction is located in the PN junction formed by the first conductive type layer 801 and the second conductive type layer 802, so that the PN junction may perform ESD protection on the thin film transistor circuit prepared in the device layer 500 in a subsequent process, and since the thin film transistor is basically a low temperature process, performance degradation may not be caused to the PN junction in the substrate 100 in the subsequent process of preparing the thin film transistor; further, the intermediate layer 300 may also shield the influence of the PN junction leakage current on the thin film transistor fabricated in the device layer 500 in the event of ESD.
Next, step S7 is performed, referring to fig. 8, metal is deposited in the first trench 601 and the second trench 602 to form a metal electrode 900 electrically connected to the first conductive type layer 801 and the second conductive type layer 802, wherein the metal electrode 900 may be prepared by depositing metal, such as depositing TiN and tungsten alloy.
As shown in fig. 1 to fig. 8, the present embodiment further provides an ESD protection device structure for a thin film transistor, including:
a base including a substrate 100, a first insulating layer 200, an intermediate layer 300, a second insulating layer 400, and a device layer 500, which are sequentially stacked from bottom to top;
a device insulating layer 502, wherein the device insulating layer 502 is positioned at the periphery of the thin film transistor region 501 defined in the device layer 500;
a first trench 601, wherein the first trench 601 penetrates the device insulating layer 502 and the second insulating layer 400 and exposes the middle layer 300;
an intermediate insulating layer 700, the intermediate insulating layer 700 being located at the bottom of the first trench 601, penetrating the intermediate layer 300 and contacting the first insulating layer 200;
a second trench 602, wherein the second trench 602 is communicated with the first trench 601, penetrates through the middle insulating layer 700 and the first insulating layer 200, and exposes the substrate 100;
a first conductive type layer 801 and a second conductive type layer 802 in contact, the first conductive type layer 801 and the second conductive type layer 802 being located in the substrate 100;
a metal electrode 900, wherein the metal electrode 900 fills the first trench 601 and the second trench 602, and is electrically connected to the first conductive type layer 801 and the second conductive type layer 802.
Specifically, for the preparation of the ESD protection device structure, reference may be made to the above-mentioned contents related to the preparation method, which is not described herein again.
As an example, the substrate may be a double-buried-layer SOI substrate, that is, in the substrate, the substrate 100 is an undoped silicon substrate, the first insulating layer 200 is a silicon oxide layer, the intermediate layer 300 is an undoped silicon layer, the second insulating layer 400 is a silicon oxide layer, and the device layer 500 is a silicon layer.
By way of example, the thin film transistor region 501 may have a thin film transistor channel that may include one of a channel composed of doped silicon, composed of carbon nanotubes, or composed of a two-dimensional material.
Specifically, the thin film transistor region 501 may be used to fabricate a P-type thin film transistor, an N-type thin film transistor, a carbon nano-thin film transistor, a two-dimensional material thin film transistor, or the like, and a method for forming a channel of the thin film transistor may include a solution method or a nano-operation laying, and the like.
As an example, the first conductivity type layer 801 and the second conductivity type layer 802 are preferably formed to penetrate and cover the substrate 100 in a lateral direction; the first conductive type layer 801 and the second conductive type layer 802 are in contact with the first insulating layer 200.
Specifically, the ESD protection diode may be prepared in the substrate 100 through the first conductive type layer 801 and the second conductive type layer 802 to form a PN junction, and preferably, a projection of the thin film transistor region 501 in the device layer 500 along a vertical direction is located in the PN junction formed by the first conductive type layer 801 and the second conductive type layer 802, so that the PN junction may perform ESD protection on the thin film transistor circuit prepared in the device layer 500 in a subsequent process, and since the thin film transistor is basically a low temperature process, performance degradation may not be caused to the PN junction in the substrate 100 in the subsequent process of preparing the thin film transistor; further, the intermediate layer 300 may also shield the PN junction leakage current from affecting the thin film transistor fabricated in the device layer 500 when ESD occurs.
In summary, the ESD protection device structure for thin film transistor and the manufacturing method thereof of the present invention provide a substrate stacked with a substrate, a first insulating layer, an intermediate layer, a second insulating layer and a device layer from bottom to top, and a first conductive type layer and a second conductive type layer in contact with the first insulating layer are formed in the substrate, thereby preparing the ESD protection diode on the substrate through the first conductive type layer and the second conductive type layer to form a PN junction in the substrate, the PN junction can carry out ESD protection on a thin film transistor circuit prepared in a device layer in the subsequent process, and because the thin film transistor basically belongs to the low-temperature process, therefore, the performance degradation of the PN junction in the substrate cannot be caused by the subsequent preparation process of the thin film transistor, and further, when ESD occurs, the middle layer can also shield the influence of PN junction leakage current on the thin film transistor, so that the voltage withstanding problem of the ESD protection device structure of the thin film transistor can be effectively solved.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A preparation method of an ESD protection device structure for a thin film transistor is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises a substrate, a first insulating layer, an intermediate layer, a second insulating layer and a device layer which are sequentially stacked from bottom to top;
defining a thin film transistor region in the device layer, and forming a device insulating layer at the periphery of the thin film transistor region;
forming a first groove, wherein the first groove penetrates through the device insulating layer and the second insulating layer and exposes the middle layer;
forming an intermediate insulating layer at the bottom of the first trench, wherein the intermediate insulating layer penetrates through the intermediate layer and is in contact with the first insulating layer;
forming a second groove, wherein the second groove is communicated with the first groove, penetrates through the middle insulating layer and the first insulating layer and exposes the substrate;
forming a first conductive type layer and a second conductive type layer in contact in the substrate based on the first trench and the second trench;
and depositing metal in the first groove and the second groove to form a metal electrode electrically connected with the first conductive type layer and the second conductive type layer.
2. The method of manufacturing an ESD protection device structure for thin film transistor according to claim 1, wherein: the substrate comprises a double buried layer SOI substrate.
3. The method for manufacturing an ESD protection device structure for a thin film transistor according to claim 2, wherein: and preparing the double-buried-layer SOI substrate by adopting a 2-time intelligent stripping method.
4. The method of manufacturing an ESD protection device structure for thin film transistor according to claim 1, wherein: the thin film transistor region is formed with a thin film transistor channel that includes one of a channel composed of doped silicon, composed of carbon nanotubes, or composed of a two-dimensional material.
5. The method for manufacturing an ESD protection device structure for thin film transistor according to claim 1, wherein: and preparing the device insulating layer and the intermediate insulating layer by adopting a wet oxidation method.
6. The method of manufacturing an ESD protection device structure for thin film transistor according to claim 1, wherein: and the formed first conductive type layer and the second conductive type layer penetrate and cover the substrate along the transverse direction.
7. An ESD protection device structure for a thin film transistor, comprising:
the substrate comprises a substrate, a first insulating layer, an intermediate layer, a second insulating layer and a device layer which are sequentially stacked from bottom to top;
the device insulating layer is positioned at the periphery of a thin film transistor region defined in the device layer;
a first trench penetrating the device insulating layer and the second insulating layer and exposing the intermediate layer;
the middle insulating layer is positioned at the bottom of the first groove, penetrates through the middle layer and is in contact with the first insulating layer;
the second groove is communicated with the first groove, penetrates through the middle insulating layer and the first insulating layer and exposes the substrate;
a first conductivity type layer and a second conductivity type layer in contact, the first conductivity type layer and the second conductivity type layer being located in the substrate;
and the metal electrode is filled in the first groove and the second groove and is electrically connected with the first conductive type layer and the second conductive type layer.
8. The ESD protection device structure for thin film transistors of claim 7, wherein: the substrate comprises a double buried layer SOI substrate.
9. The ESD protection device structure for thin film transistors of claim 7, wherein: the thin film transistor region has a thin film transistor channel that includes one of a channel composed of doped silicon, composed of carbon nanotubes, or composed of a two-dimensional material.
10. The ESD protection device structure for thin film transistor of claim 7, wherein: the first conductive type layer and the second conductive type layer penetrate and cover the substrate along the transverse direction.
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