CN114578719A - Anti-interference method, device, equipment and computer readable storage medium - Google Patents
Anti-interference method, device, equipment and computer readable storage medium Download PDFInfo
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Abstract
The application provides an anti-interference method, an anti-interference device, anti-interference equipment and a storage medium, wherein the method comprises the following steps: determining a first time threshold value based on a target operation instruction if the target operation instruction is detected; controlling a microprocessor to enter a sleep mode, and timing the time length of the microprocessor entering the sleep mode to obtain the sleep time length; and controlling the microprocessor to enter a working mode under the condition that the sleeping time length reaches the first time length threshold value. Therefore, interference generated when the target device executes the target operation instruction cannot influence the microprocessor in the sleep mode, and interference noise generated by the target device can be effectively prevented from influencing normal operation of the microprocessor, so that the reliability of a microprocessor control system is improved.
Description
Technical Field
The present application relates to the field of automation controller technology, and relates to, but is not limited to, an anti-interference method, apparatus, device, and computer-readable storage medium.
Background
The microprocessor control system often needs to control and drive some high-voltage and high-power devices, especially some non-linear inductive loads, when the switching state of these devices changes (from on to off or from off to on), interference may occur on the power supply line, and further electrical noise interference may occur to the microprocessor, which causes abnormal fluctuation of the voltage and current of the power line or signal line, and affects the normal operation of the microprocessor, even the normal use of the whole control system.
In the related art, an anti-interference processing method is that after a microprocessor sends a control command to a device which may generate interference, the microprocessor sends some redundant commands (null commands) immediately, and continues for a certain time to wait for the noise of the interference source device to disappear. When interference occurs, the key devices of the microprocessor (such as the main crystal oscillator, the Analog-to-Digital Converter (ADC) of each processing module, the Random Access Memory (RAM), the Read-Only Memory (ROM), the data bus and the address bus) do not stop working, and thus the interference is likely to cause control system failure.
Disclosure of Invention
In view of this, embodiments of the present application provide an anti-interference method, apparatus, device, and storage medium.
The technical scheme of the embodiment of the application is realized as follows:
the embodiment of the application provides an anti-interference method, which comprises the following steps:
determining a first time threshold value based on a target operation instruction if the target operation instruction is detected;
controlling a microprocessor to enter a sleep mode, and timing the time for the microprocessor to enter the sleep mode to obtain the sleep time;
and controlling the microprocessor to enter a working mode under the condition that the sleeping time length reaches the first time length threshold value.
In some embodiments, the method further comprises:
under the condition that the target operation instruction is not detected, acquiring the idle time length of the microprocessor in an idle state;
when the idle time length is determined to be larger than a second time length threshold value, controlling the microprocessor to enter a sleep mode;
and controlling the microprocessor to enter an operating mode under the condition that a triggering instruction for triggering an event is detected.
In some embodiments, the method further comprises:
acquiring a sleep time length for entering a sleep mode;
correspondingly, in the case that a trigger instruction for triggering an event is detected, controlling the microprocessor to enter an operating mode includes:
controlling the microprocessor to enter an operating mode if the sleep duration reaches a third duration threshold or if a trigger instruction for a trigger event is detected.
In some embodiments, the determining a first duration threshold based on the target operating instruction comprises:
analyzing the target operation instruction to obtain identification information of a target device, wherein the target device is equipment for executing the target operation instruction;
inquiring a target interference duration corresponding to the identification information in a prestored device interference duration table;
a first time threshold is determined based on the target interference duration.
In some embodiments, the determining a first time threshold based on the target interference duration comprises:
determining the target interference duration as a first duration threshold;
alternatively, the first and second electrodes may be,
and determining the sum of the target interference duration and a fourth duration threshold as a first duration threshold.
In some embodiments, the method further comprises:
acquiring initial timing time of a timer;
updating the initial timing time based on the sleep duration to obtain the updated timing time of the timer;
or updating the initial timing time based on the sleep duration to obtain the updated timing time of the timer.
In some embodiments, the controlling the microprocessor to enter a sleep mode includes:
and turning off the main clock of the microprocessor, and turning on the auxiliary clock of the microprocessor to enter a sleep mode, wherein the frequency of the auxiliary clock of the microprocessor is less than the interference frequency generated when the target device executes the target operation instruction.
The embodiment of the application provides an anti jamming unit, the device includes:
the device comprises a determining module, a judging module and a judging module, wherein the determining module is used for determining a first time length threshold value based on a target operation instruction under the condition that the target operation instruction is detected;
the first control module is used for controlling the microprocessor to enter a sleep mode;
the first acquisition module is used for timing the time length of the microprocessor entering the sleep mode to obtain the sleep time length;
and the second control module is used for controlling the microprocessor to enter a working mode under the condition that the sleeping time length reaches the first time length threshold value.
The embodiment of the application provides an anti-interference device, including:
a controller comprising at least one microprocessor;
a memory for storing a computer program operable on the controller;
wherein, the computer program realizes the steps of the anti-interference method when being executed by the controller.
Embodiments of the present application provide a computer-readable storage medium storing computer-executable instructions configured to perform the steps of the foregoing anti-interference method.
The embodiment of the application provides an anti-interference method, an anti-interference device, anti-interference equipment and a storage medium, wherein the method comprises the following steps: determining a first time threshold based on a target operation instruction if the target operation instruction is detected; controlling a microprocessor to enter a sleep mode, and timing the time length of the microprocessor entering the sleep mode to obtain the sleep time length; and controlling the microprocessor to enter a working mode under the condition that the sleeping time length reaches the first time length threshold value. Therefore, interference generated when the target device executes the target operation instruction cannot influence the microprocessor in the sleep mode, and interference noise generated by the target device can be effectively prevented from influencing normal operation of the microprocessor, so that the reliability of a microprocessor control system is improved.
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In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.
Fig. 1 is a schematic flowchart of an implementation process of an anti-interference method according to an embodiment of the present application;
fig. 2 is a schematic flowchart of another implementation of an anti-interference method according to an embodiment of the present application;
fig. 3 is a schematic flowchart of another implementation of the anti-interference method according to the embodiment of the present application;
FIG. 4 is a schematic diagram of a microprocessor control system according to an embodiment of the present disclosure;
fig. 5 is a schematic flowchart of another implementation of the anti-interference method according to the embodiment of the present application;
fig. 6A is a schematic diagram illustrating detection of a level when the apparatus is turned on in the anti-interference method according to the embodiment of the present application;
fig. 6B is a schematic diagram illustrating detection of a level when the apparatus is turned off in the anti-interference method according to the embodiment of the present application;
fig. 7 is a schematic structural diagram of an anti-interference apparatus according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of an anti-interference device according to an embodiment of the present application.
Detailed Description
In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be described in further detail with reference to the attached drawings, the described embodiments should not be considered as limiting the present application, and all other embodiments obtained by a person of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.
In the following description, references to the terms "first \ second \ third" are only to distinguish similar objects and do not denote a particular order, but rather the terms "first \ second \ third" are used to interchange specific orders or sequences, where appropriate, so as to enable the embodiments of the application described herein to be practiced in other than the order shown or described herein.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the application.
Based on the problem that the interference generated when equipment is turned on or turned off in the related art may cause abnormal fluctuation of the voltage and the current of a power supply or a signal line of a microprocessor, affect the normal operation of the microprocessor and cause low reliability of a microprocessor control system, the embodiment of the application provides an anti-interference method applied to the microprocessor control system. The method provided by the embodiment of the present application may be implemented by a computer program, and when the computer program is executed, each step in the anti-interference method provided by the embodiment of the present application is completed. In some embodiments, the computer program may be executed by a controller in a microprocessor controlled system. Fig. 1 is a schematic flow chart of an implementation process of an anti-interference method provided in an embodiment of the present application, and as shown in fig. 1, the anti-interference method includes the following steps:
step S101, under the condition that a target operation instruction is detected, determining a first time length threshold value based on the target operation instruction.
The anti-interference method provided by the embodiment of the application is applied to a microprocessor control system, and the microprocessor control system can be applied to equipment such as a washing machine and a clothes dryer which are controlled by a microprocessor. When the microprocessor control system controls or drives a high-voltage strong electric device, a high-power device or a nonlinear inductive load, the devices generate interference on a power supply line when the switching state is changed, and further noise interference of electrical equipment on the microprocessor can be generated. After the microprocessor is started, whether the microprocessor sends a target operation instruction is detected, and when the microprocessor sends the target operation instruction is detected, a first time length threshold value is determined according to the target operation instruction.
Here, the target operation instruction is to turn on or off a target device. The first time length threshold is a value preset according to the interference time length of interference generated when the target device changes the switch state.
And step S102, controlling the microprocessor to enter a sleep mode.
When the target device is turned on or off, the switching state of the target device changes, and at this time, an interference signal which influences the normal operation of the microprocessor may exist on the power line or the signal line. In the embodiment of the application, when the target operation instruction is detected, the microprocessor is controlled to enter the sleep mode, so that the problem that the normal operation of the microprocessor is influenced by data or program errors, even crash and the like due to the fact that the microprocessor is influenced by interference signals and abnormal fluctuation of voltage and current of a power supply or a signal line can be avoided.
In some embodiments, entering sleep mode may be implemented as: and closing the microprocessor master clock, and opening the microprocessor secondary clock, wherein the frequency of the microprocessor secondary clock is less than the interference frequency generated when the target device executes the target operation instruction.
And step S103, timing the time length of the microprocessor entering the sleep mode to obtain the sleep time length.
After the switching state of the target device is changed, the interference signal disappears, and at this time, the microprocessor needs to be awakened to continue normal operation. In order to ensure that the interference signal disappears when the microprocessor is awakened, timing needs to be started after the microprocessor enters the sleep mode to acquire the sleep time length for the microprocessor to enter the sleep mode.
And step S104, controlling the microprocessor to enter a working mode under the condition that the sleep time reaches the first time threshold.
When the sleep duration reaches the first duration threshold, it can be determined that the interference signal has disappeared, at this time, the microcontroller is awakened from the sleep mode, and the microprocessor is controlled to enter the working mode.
According to the anti-interference method provided by the embodiment of the application, under the condition that a target operation instruction is detected, a first time length threshold value is determined based on the target operation instruction; controlling a microprocessor to enter a sleep mode, and timing the time length of the microprocessor entering the sleep mode to obtain the sleep time length; and controlling the microprocessor to enter a working mode under the condition that the sleeping time length reaches the first time length threshold value. Therefore, interference generated when the target device executes the target operation instruction cannot influence the microprocessor in the sleep mode, and interference noise generated by the target device can be effectively prevented from influencing normal operation of the microprocessor, so that the reliability of a microprocessor control system is improved.
On the basis of the embodiment shown in fig. 1, an anti-interference method is further provided in the embodiment of the present application, and fig. 2 is a schematic view of another implementation flow of the anti-interference method provided in the embodiment of the present application, and as shown in fig. 2, the anti-interference method includes the following steps:
and step S201, controlling the microprocessor to start.
Step S202, judging whether the microprocessor sends a target operation instruction.
Here, the target operation instruction is to turn on or off a target device.
When the microprocessor is detected to send a target operation instruction, an interference signal is generated when the target device executes the target operation instruction, and then the step S203 is executed; when it is not detected that the microprocessor transmits the target operation instruction, it indicates that the microprocessor is currently idle, and then the process proceeds to step S207.
Step S203, determining a first time threshold based on the target operation instruction.
Here, the first time length threshold is a value set in advance according to a disturbance time length in which disturbance occurs when the target device changes the switching state.
Step S204, controlling the microprocessor to enter a sleep mode.
In some embodiments, entering sleep mode may be implemented as: and closing the microprocessor master clock, and opening the microprocessor secondary clock, wherein the frequency of the microprocessor secondary clock is less than the interference frequency generated when the target device executes the target operation instruction.
Step S205, timing the time length when the microprocessor enters the sleep mode to obtain the sleep time length.
In order to ensure that the interference signal disappears when the microprocessor is awakened, timing needs to be started after the microprocessor enters the sleep mode to acquire the sleep time length for the microprocessor to enter the sleep mode.
Step S206, determining whether the sleep duration reaches the first duration threshold.
When the sleep duration reaches the first duration, it may be determined that the interference signal has disappeared, and then step S211 is performed to wake up the microprocessor; when the sleep duration does not reach the first duration threshold, indicating that the interference signal may not disappear, the microprocessor is controlled to maintain the sleep mode, and the method returns to step S205 to obtain a new sleep duration.
Step S207, obtaining the idle time length when the microprocessor is idle.
And when the microprocessor does not execute any operation instruction, determining that the microprocessor is idle.
Step S208, judging whether the idle time length is greater than a second time length threshold value.
When the idle time length is greater than the second time length threshold value, the microprocessor is indicated to be in an idle state for a long time, and then the step S209 is entered; and when the idle time length is less than or equal to the second time length threshold value, indicating that the microprocessor is in an idle state for a short time, returning to the step S202 to continuously detect whether the microprocessor sends the target operation instruction.
Here, the second time period threshold is a preset value, and the second time period threshold may be a factory default value or a value set by a user. In the embodiment of the present application, the second time threshold may be set to 1 minute. When the microprocessor is in the idle state for more than 1 minute, the microprocessor is controlled to enter the sleep mode, so that the electric power loss of the control system can be reduced.
Step S209, controlling the microprocessor to enter a sleep mode.
In some embodiments, entering sleep mode may be implemented as: and closing the microprocessor master clock, and opening the microprocessor secondary clock, wherein the frequency of the microprocessor secondary clock is less than the interference frequency generated when the target device executes the target operation instruction.
Step S210, determining whether a trigger instruction is detected.
Here, the trigger instruction is an instruction for triggering an event.
When the trigger command is detected, it indicates that there is an external event to be executed, and then step S211 is entered to wake up the microprocessor; when the trigger instruction is not detected, the control microprocessor controls the microprocessor to maintain the sleep mode, and returns to step S210 to continue detecting the trigger instruction.
And step S211, controlling the microprocessor to enter a working mode.
If the microprocessor enters the sleep mode, when the sleep time reaches the first time threshold, the interference signal can be determined to disappear, and at the moment, the microcontroller can be awakened from the sleep mode to control the microprocessor to enter the working mode. Or, if the microprocessor enters the sleep mode, when the trigger instruction is detected, the microprocessor can exit the sleep mode, wake up the microcontroller from the sleep mode, and control the microprocessor to enter the working mode.
According to the anti-interference method, when the microprocessor sends the target operation instruction for opening or closing the target device to the target device, the microprocessor is controlled to enter the sleep mode, after the state of the target device is changed, the microprocessor is awakened, the microprocessor enters the normal mode to operate, the sleep mode of the microprocessor is adopted, interference noise generated by equipment can be effectively prevented from influencing the normal operation of the microprocessor, and therefore the reliability of the whole control system is improved. Meanwhile, when the idle time of the microprocessor reaches a certain time, the microprocessor is controlled to enter a sleep mode, and when an external event is triggered, the microprocessor is awakened to enter a normal mode to operate, so that the electric power loss of the control system can be reduced.
In some embodiments, the microprocessor may further be awakened by a timer in the sleep mode, and when the trigger instruction is not detected in step S210, the tamper-resistant method may further include the following steps:
in step S22, a sleep duration for entering the sleep mode is obtained.
After the microprocessor enters the sleep mode, timing is started to acquire the sleep time of the microprocessor entering the sleep mode.
Step S23, determine whether the sleep duration reaches a third duration threshold.
When the sleeping time reaches the third time threshold, step S211 is entered to wake up the microprocessor; and when the sleep duration does not reach the third duration threshold, controlling the microprocessor to control the microprocessor to maintain the sleep mode, and returning to the step S210 to continuously detect the trigger instruction.
Here, the third time duration threshold is a preset value, and the third time duration threshold may be a factory default value or a value set by a user. In the embodiment of the present application, the third duration threshold may be set to 15 minutes. When the sleeping time of the microprocessor in the sleeping mode is longer than 15 minutes, the microprocessor is controlled to automatically wake up, and automatic control of the control system is realized.
In some embodiments, the step S101 or the step S203 "determining the first duration threshold based on the target operation instruction" may be implemented by:
step S1011, analyzing the target operation command to obtain the identification information of the target device.
Here, the target device is a device that executes the target operation instruction, the identification information is used to identify the identity information of the device, and the identification information of different devices is different, for example, the identification information may be unique information such as a serial code of the device. The interference duration of the device can be determined based on the identification information of the device.
Step S1012, querying a target interference duration corresponding to the identification information in a pre-stored device interference duration table.
The method comprises the steps of obtaining interference duration of interference signals generated when different devices are started and closed in advance through modes such as tests and the like, establishing a corresponding device interference duration table according to identification information and the interference duration of the devices, and storing the device interference duration table. And when the first time length threshold is determined, inquiring the device interference time length table according to the identification information of the target device to obtain the target interference time length. The interference duration obtained by testing to a general device is between 1 millisecond and 2 seconds.
In step S1013, a first time threshold is determined based on the target interference duration.
In determining the first time threshold, in one implementation, the target interference duration may be determined as the first time threshold. In this way, it can be ensured that the interference signal generated by the target device has disappeared when the sleep duration reaches the first duration threshold. For example, if the interference duration of a device is 5 ms, the first duration threshold is set to 5 ms.
In another implementation of determining the first time threshold, the sum of the target interference time and the fourth time threshold may also be determined as the first time threshold. Here, the fourth time threshold is any positive value that is set in advance, and in the embodiment of the present application, the fourth time threshold may be set to 0.5 seconds (i.e., 500 milliseconds). The first time length threshold is set to be a value larger than the target interference time length, so that the first time length threshold is larger than the target interference time length, and the fact that the interference signal generated by the target device disappears when the sleep time length reaches the first time length threshold can be guaranteed. For example, if the interference duration of a device is 5 ms, the fourth time threshold is 500 ms, and the first time threshold is 505 ms.
In yet another implementation manner of determining the first time length threshold, a product of the target interference time length and a preset coefficient may be further determined as the first time length threshold. Here, the preset coefficient is a preset value, and the preset coefficient is any positive value greater than 1, for example, a preset value such as 2, 2.5, etc. in the embodiment of the present application, the preset coefficient may be set to 3. The first time length threshold is set to be a value larger than the target interference time length, so that the first time length threshold is larger than the target interference time length, and the interference signal generated by the target device can be further ensured to disappear when the sleep time length reaches the first time length threshold. For example, if the interference duration of a device is 5 ms and the predetermined coefficient is 3 times, the first duration threshold is set to 15 (i.e., 5 × 3) ms.
In some embodiments, to ensure that the time it takes for the microprocessor to enter the sleep mode or hibernate mode does not affect the control system timer, the timer is time compensated based on the sleep time or hibernate time after the microprocessor is awakened. At this time, before the step S104 or S211 of "controlling the microprocessor to enter the operation mode", the method may further include the steps of:
in step S11, a timer initial timing time is acquired.
Step S12, updating the initial timing time based on the sleep duration to obtain an updated timing time of the timer.
It should be noted that, when the microprocessor wakes up from the sleep mode, the initial timing time is updated based on the sleep duration, and the updated timing time of the timer is obtained.
When the microprocessor is awakened from the sleep mode, step S12 may be replaced with:
and step S12', updating the initial timing time based on the sleep time length to obtain the updated timing time of the timer.
And when the microprocessor is awakened from the sleep mode, updating the initial timing time based on the sleep time length to obtain the updated timing time of the timer.
In practical implementation, the microprocessor is awakened, the time occupied by the timer in the sleep mode or the dormant mode is compensated, the sum of the initial timing time and the sleep time length of the timer is updated to the updating timing time of the timer, or the sum of the initial timing time and the sleep time length of the timer is updated to the updating timing time of the timer.
After step S12, the microprocessor is controlled to enter an operation mode in which the microprocessor operates based on the updated timing time of the timer.
Fig. 3 is a schematic flowchart of another implementation flow of the anti-interference method according to the embodiment of the present application, and as shown in fig. 3, the anti-interference method according to the embodiment of the present application includes the following steps:
and step S301, controlling the microprocessor to start.
Step S302, judging whether the microprocessor sends a target operation instruction.
Here, the target operation instruction is to turn on or off a target device.
When the microprocessor is detected to send a target operation instruction, an interference signal is generated when the target device executes the target operation instruction, and then the step S303 is executed; when it is not detected that the microprocessor transmits the target operation instruction, indicating that the microprocessor is currently in the idle mode, the process proceeds to step S309.
Step S303, analyzing the target operation instruction to obtain the identification information of the target device.
Step S304, inquiring the target interference duration corresponding to the identification information in a prestored device interference duration table.
Step S305, determining the target interference duration as a first duration threshold.
In some embodiments, step S305 may be replaced with step S3051, determining a sum of the target interference duration and a fourth duration threshold as a first duration threshold; or step S305 is replaced by step S3052, and a product of the target interference duration and a preset coefficient is determined as a first duration threshold.
Step S306, turning off the main clock of the microprocessor, and turning on the secondary clock of the microprocessor to enter a sleep mode.
Here, the frequency of the microprocessor sub-clock is smaller than the frequency of disturbance generated when the target device executes the target operation instruction.
Step S307, timing the time length of the microprocessor entering the sleep mode to obtain the sleep time length.
Step S308, determining whether the sleep duration reaches the first duration threshold.
When the sleep duration reaches the first duration threshold, determining that the interference signal has disappeared, and then proceeding to step S315; when the sleep duration does not reach the first duration threshold, indicating that the interference signal may not disappear, controlling the microprocessor to maintain the sleep mode, and returning to step S307 to obtain a new sleep duration.
Step S309, obtaining the idle time length of the microprocessor in idle.
Step S310, determining whether the idle time length is greater than a second time length threshold.
When the idle time length is greater than the second time length threshold value, indicating that the microprocessor is in an idle state for a long time, and then entering step S311; when the idle time length is less than or equal to the second time length threshold value, it indicates that the microprocessor is in the idle state for a short time, and at this time, it returns to step S302 to continue to detect whether the microprocessor sends the target operation instruction.
Step S311, turning off the microprocessor master clock, and turning on the microprocessor slave clock to enter a sleep mode.
Here, the frequency of the microprocessor sub-clock is smaller than the frequency of disturbance generated when the target device executes the target operation instruction.
In step S312, it is determined whether a trigger command is detected.
Here, the trigger instruction is an instruction for triggering an event.
When a trigger instruction is detected, indicating that there is an external event to be executed, then entering step S317; when the trigger instruction is not detected, the process proceeds to step S313.
Step S313, obtains the sleep duration of the sleep mode.
Step S314, determining whether the sleep duration reaches a third duration threshold.
When the sleeping time reaches the third time threshold, the step S317 is entered; and when the sleeping time does not reach the third time threshold, controlling the microprocessor to control the microprocessor to maintain the sleeping mode, and returning to the step S312 to continuously detect the trigger instruction.
In step S315, the initial timing time of the timer is obtained.
Step S316, updating the initial timing time based on the sleep duration to obtain an updated timing time of the timer.
In step S317, the initial timing time of the timer is acquired.
Step S318, updating the initial timing time based on the sleep duration to obtain the updated timing time of the timer.
And step S319, controlling the microprocessor to enter a working mode.
According to the anti-interference method provided by the embodiment of the application, when the microprocessor sends the target operation instruction for opening or closing the target device to the target device, the microprocessor is controlled to enter the sleep mode, after the state of the target device is changed, the microprocessor is awakened, the microprocessor enters the normal mode to operate, the sleep mode of the microprocessor is adopted, the interference noise generated by equipment can be effectively prevented from influencing the normal operation of the microprocessor, and therefore the reliability of the whole control system is improved. Meanwhile, when the idle time of the microprocessor in the idle state reaches a certain time, the microprocessor is controlled to enter a sleep mode, and when an external event or a periodic processing event is triggered, the microprocessor is awakened to enter a normal mode for running, so that the electric power consumption of the control system can be reduced.
Next, an exemplary application of the embodiment of the present application in a practical application scenario will be described.
The microprocessor control system or the intelligent control system often needs to control and drive some high-voltage and high-power devices, especially some non-linear inductive loads, when the switch state of the devices changes, interference is generated on a power supply line, further noise interference of electrical devices is possibly generated on the microprocessor, the interference causes abnormal fluctuation of the voltage and current of a power supply or a signal line of the microprocessor, and if the abnormal fluctuation is not subjected to anti-interference processing, the normal work of the microprocessor or even the normal use of the whole control system is influenced.
The available method for anti-interference in the related art mainly relates to two aspects of hardware and software:
1) in terms of hardware, components may be employed to absorb the voltage and current pulses emitted by the interference source. For example, an isolation element and circuit are used between a driver circuit and a microprocessor, an isolation device is used between an interference source device and the driver circuit, and an absorption element such as a Transient Voltage Super (TVS), an inductor, a capacitor, or a resistor is added to a power line of the microprocessor or the interference source device.
2) In terms of software, the interference can be avoided by adding null instructions: after the microprocessor sends a switch control command to equipment which can generate interference noise, some redundant commands (null commands) are added, and the redundant commands are continued for a certain time to wait for the interference source noise to disappear, so that when the microprocessor switches the equipment which can cause the interference noise, the noise of a power supply or a control signal is avoided, and the processing of program data or commands of the microprocessor is prevented from being disordered and even halted. However, this method has a fatal defect that when the interference occurs, the critical devices of the microprocessor, such as the main crystal oscillator, the ADC of each processor module, the RAM, the ROM data and address buses, etc., do not stop working, and are susceptible to the interference to cause system failure.
Aiming at the defects in the related art, the embodiment of the application provides a method for realizing anti-interference through software, which comprises the following steps: after the microprocessor sends a switch operation instruction to the equipment which can generate interference, the microprocessor is switched into a sleep mode from the working state, and the microprocessor is awakened again to continue normal work after the interference. This way, the problems of data or program errors and microprocessor crash caused by the strong interference of the microprocessor can be avoided.
The embodiment of the application provides a novel anti-interference method for a microprocessor control system or an intelligent control system. Firstly, a microprocessor executes an operation instruction (on/off) of a device (a device which may generate interference noise); controlling the microprocessor to enter a sleep mode; after the operation of changing the equipment state is finished, waking up the microprocessor, and enabling the microprocessor to enter a normal mode for operation; when the control system is idle, the microprocessor enters the sleep mode again; when an external event or a periodic processing event is triggered, the microprocessor is awakened to enter a normal mode for operation. The sleep mode of the microprocessor is adopted, so that the interference noise generated by equipment can be effectively prevented from influencing the normal operation of the microprocessor, the reliability of the whole control system is improved, and the electric power loss of the control system can be reduced.
Fig. 4 is a schematic structural diagram of a microprocessor control system according to an embodiment of the present application, and as shown in fig. 4, the microprocessor control system 400: the hardware includes a power supply 401, a Microprocessor (MPU) 402, a device (corresponding to the above device) 404, and a control module 403 that drives the device 404; the control module 403 includes an equipment control instruction module 4031, a microprocessor sleep control module 4032, and a timer control module 4033 according to software division; the device 404 may be plural, and the operation state of the microprocessor MPU 402 is divided into three states: an idle state (corresponding to the microprocessor being idle as in the above), an operational state (corresponding to the operational mode as in the above), and a sleep state (corresponding to the sleep mode as in the above).
Fig. 5 is a schematic flowchart of still another implementation of the anti-interference method according to the embodiment of the present application, and as shown in fig. 5, the anti-interference method includes the following steps:
and step S501, operating the microprocessor.
Step S502, whether an operation instruction exists is detected.
And waiting for the microprocessor to send an operation instruction to the equipment in the running process of the control system. When detecting that there is an operation instruction, indicating that the microprocessor sends the operation instruction to the device, and then entering step S503; when it is detected that there is no operation instruction, that is, when no operation instruction is detected, it indicates that the microprocessor has not issued an operation instruction, and the process proceeds to step S507.
Step S503, an operation instruction is sent to the device.
Here, the operation instruction is for controlling the device to be turned on or off.
Step S504, the microprocessor is set to enter a sleep mode.
Setting the microprocessor to enter sleep mode may be implemented as: and controlling the MPU main clock of the microprocessor to be closed, controlling the MPU auxiliary clock of the microprocessor to be opened, and setting the microprocessor as a timer to wake up so as to wake up the microprocessor to enter a normal working mode when the timer reaches a set time. Here, the timing length of the timer is the sleep length ts 1.
The secondary clock frequency Fb of the microprocessor is far less than the interference noise frequency Fp, and the sleep time ts1 is longer than the interference noise duration tp.
In step S505, the microprocessor sleeps.
In step S506, the microprocessor is awakened by the timer.
The microprocessor is awakened by the timer, the sleep mode is finished, and the process goes to step S511 to adjust all the timers.
Step S507, determine whether the idle duration is greater than the idle duration threshold.
The idle time length is the time length from the last time the microprocessor sends the operation instruction to the current time, and is recorded as the idle time length T, and the preset idle time length threshold is recorded as TF. When T is greater than TF, it indicates that the microprocessor does not send out operation instruction in the idle time length threshold, at this time, in order to reduce the electric power loss of the control system, the microprocessor is controlled to enter a sleep mode, and the step S508 is entered; and when T is less than or equal to TF, the idle time of the microprocessor is shorter, and the condition of entering the sleep mode is not met, at the moment, the operation state of the microprocessor is returned to the step S501 to continuously detect.
Step S508, the microprocessor is set to enter the sleep mode.
Entering the sleep mode may be implemented as: and controlling the main clock to be closed, controlling the auxiliary clock to be opened, and setting the microprocessor to be awakened by a timer and an external event so as to awaken the microprocessor to enter a normal working mode when the timer reaches a set time or the external event is detected to exist. Here, the timing duration of the timer is the sleep duration ts2, and the sleep time ts2 may be any duration.
In step S509, the microprocessor sleeps.
In step S510, the microprocessor is awakened by a timer or an external event.
The microprocessor is awakened when triggered by an external event or a periodic processing event.
In step S511, all timers of the microprocessor are adjusted.
Since the time consumed by the microprocessor after entering the sleep mode or the hibernation mode is long, after the microprocessor is awakened, all timers of the microprocessor need to be updated according to the duration of entering the sleep mode or the hibernation mode.
In practical implementation, the microprocessor is awakened, the time occupied by the sleep mode or the sleep mode of the timer of the control system is compensated, and the sum of the original time t of the timer and the sleep time duration ts1 or the sleep time duration ts2 is updated to be the updating time of the timer.
In step S512, the microprocessor starts the operation mode.
Fig. 6A is a schematic diagram illustrating detection of a level when the apparatus is turned on in the anti-interference method according to the embodiment of the present application, and as shown in fig. 6A, a power supply level 601 is always a high level; the device switches to the on state at a first time T1, and the device level 602 switches from low to high at a first time T1; the microprocessor enters the sleep mode from the first time T1, and the microprocessor level 603 is switched from high to low at the first time T1. The microprocessor wakes up at the second time T2, the microprocessor level 603 is switched from low to high at the second time T2, and the microprocessor enters the operation mode from the second time T2.
Fig. 6B is a schematic diagram illustrating level detection of the anti-interference method according to the embodiment of the present application when the device is turned off, and as shown in fig. 6B, the power supply level 601 is always at a high level; the device switches to the off state at a third time T3, and the device level 602 switches from high to low at a third time T3; the microprocessor enters the sleep mode from the third time T3, and the microprocessor level 603 is switched from high to low at the third time T3. The microprocessor wakes up at the fourth time T4, the microprocessor level 603 is switched from low to high at the fourth time T4, and the microprocessor enters the working mode from the fourth time T4.
According to the anti-interference method provided by the embodiment of the application, when the microprocessor operates the equipment which is likely to generate interference, the sleep mode of the microprocessor is adopted, the secondary clock is used when the microprocessor sleeps, the frequency of the clock is far smaller than that of the noise interference source, the sleeping time is longer than the noise pulse duration, the noise interference generated by the equipment cannot influence the microprocessor in the sleep mode, and the microprocessor can be prevented from being interfered by electrical noise. When the microprocessor is awakened, the set value of the timer of the control system is compensated, so that the timing of the control system is not influenced by the sleeping time.
Based on the foregoing embodiments, the embodiments of the present application provide an anti-jamming device, where each module included in the device and each unit included in each module may be implemented by a controller in a computer device; of course, the implementation can also be realized through a specific logic circuit; in implementation, the controller may include a Central Processing Unit (CPU), a microprocessor Unit (MPU), a Digital Signal Processor (DSP), a Field Programmable Gate Array (FPGA), or the like.
Fig. 7 is a schematic structural diagram of a composition of an anti-interference apparatus according to an embodiment of the present application, and as shown in fig. 7, the anti-interference apparatus 700 includes:
a determining module 701, configured to, in a case that a target operation instruction is detected, determine a first duration threshold based on the target operation instruction;
a first control module 702 for controlling the microprocessor to enter a sleep mode;
a first obtaining module 703, configured to time a duration that the microprocessor enters a sleep mode, so as to obtain a sleep duration;
a second control module 704, configured to control the microprocessor to enter a working mode when the sleep duration reaches the first duration threshold.
In some embodiments, the tamper resistant device 700 may further include:
the second acquisition module is used for acquiring the idle time length of the microprocessor when the target operation instruction is not detected;
the third control module is used for controlling the microprocessor to enter a sleep mode when the idle time is determined to be greater than the second time threshold;
the second control module 704 is further configured to control the microprocessor to enter an operating mode in case a trigger instruction for a trigger event is detected.
In some embodiments, the tamper resistant device 700 may further include:
a third obtaining module, configured to obtain a sleep duration for entering the sleep mode;
correspondingly, the second control module 704 is further configured to control the microprocessor to enter an operating mode when the sleeping time duration reaches a third time duration threshold or a trigger instruction for a trigger event is detected.
In some embodiments, the determining module 701 further includes:
the analysis unit is used for analyzing the target operation instruction to obtain identification information of a target device, wherein the target device is a device for executing the target operation instruction;
the query unit is used for querying the target interference duration corresponding to the identification information in a prestored device interference duration table;
a determining unit, configured to determine a first time threshold based on the target interference duration.
In some implementation examples, the determining unit further includes:
the first determining subunit determines the target interference duration as a first duration threshold;
alternatively, the first and second electrodes may be,
a second determining subunit, configured to determine a sum of the target interference duration and a fourth duration threshold as a first duration threshold;
alternatively, the first and second electrodes may be,
and the third determining subunit is used for determining the product of the target interference duration and the preset coefficient as the first duration threshold.
In some embodiments, the tamper resistant device 700 may further include:
the fourth acquisition module is used for acquiring the initial timing time of the timer;
the first updating module is used for updating the initial timing time based on the sleep duration to obtain the updated timing time of the timer;
or, the second updating module is configured to update the initial timing time based on the sleep duration to obtain an updated timing time of the timer.
In some embodiments, the second control module 704 is further configured to:
and turning off the main clock of the microprocessor, and turning on the auxiliary clock of the microprocessor to enter a sleep mode, wherein the frequency of the auxiliary clock of the microprocessor is less than the interference frequency generated when the target device executes the target operation instruction.
In some embodiments, the second control module 704 is further configured to:
and turning off the main clock of the microprocessor, and turning on the auxiliary clock of the microprocessor to enter a sleep mode, wherein the frequency of the auxiliary clock of the microprocessor is less than the interference frequency generated when the target device executes the target operation instruction.
Here, it should be noted that: the above description of the embodiment of the interference rejection apparatus is similar to the above description of the method, and has the same advantages as the embodiment of the method. For technical details not disclosed in the embodiments of the interference rejection unit of the present application, a person skilled in the art should understand with reference to the description of the embodiments of the method of the present application.
It should be noted that, in the embodiment of the present application, if the anti-interference method is implemented in the form of a software functional module and is sold or used as a standalone product, it may also be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application or portions thereof that contribute to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, or an optical disk. Thus, embodiments of the present application are not limited to any specific combination of hardware and software.
Accordingly, embodiments of the present application provide a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a controller, implements the steps in the anti-jamming method provided in the above embodiments.
Fig. 8 is a schematic structural diagram of the anti-jamming device provided in this embodiment, and according to the exemplary structure of the anti-jamming device 800 shown in fig. 8, other exemplary structures of the anti-jamming device 800 may be foreseen, so that the structures described herein should not be considered as limitations, for example, some components described below may be omitted, or components not described below may be added to adapt to special requirements of some applications.
The tamper resistant device 800 shown in fig. 8 includes: a controller 801, at least one communication bus 802, a user interface 803, at least one external communication interface 804 and a memory 805. Wherein the communication bus 802 is configured to enable connective communication between these components. The user interface 803 may include a display panel, and the external communication interface 804 may include a standard wired interface and a wireless interface, among others. The controller 801 is configured to execute a program of the tamper resistant method stored in the memory to implement the steps in the tamper resistant method provided in the above embodiments.
The above description of the tamper resistant device and storage medium embodiments is similar to the description of the method embodiments above with similar beneficial effects as the method embodiments. For technical details not disclosed in the embodiments of the tamper resistant device and the storage medium of the present application, reference is made to the description of the embodiments of the method of the present application for understanding.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not imply any order of execution, and the order of execution of the processes should be determined by their functions and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units; can be located in one place or distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be separately regarded as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Those of ordinary skill in the art will understand that: all or part of the steps for realizing the method embodiments can be completed by hardware related to program instructions, the program can be stored in a computer readable storage medium, and the program executes the steps comprising the method embodiments when executed; and the aforementioned storage medium includes: a removable storage device, a ROM, a magnetic or optical disk, or other various media that can store program code.
Alternatively, the integrated units described above in the present application may be stored in a computer-readable storage medium if they are implemented in the form of software functional modules and sold or used as independent products. Based on such understanding, the technical solutions of the embodiments of the present application may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a product to perform all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a removable storage device, a ROM, a magnetic or optical disk, or other various media that can store program code.
The above description is only for the embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. An interference rejection method, comprising:
determining a first time threshold based on a target operation instruction if the target operation instruction is detected;
controlling a microprocessor to enter a sleep mode, and timing the time length of the microprocessor entering the sleep mode to obtain the sleep time length;
and controlling the microprocessor to enter a working mode under the condition that the sleeping time length reaches the first time length threshold value.
2. The method of claim 1, further comprising:
under the condition that the target operation instruction is not detected, acquiring the idle time length of the microprocessor in an idle state;
when the idle time length is determined to be larger than a second time length threshold value, controlling the microprocessor to enter a sleep mode;
and controlling the microprocessor to enter an operating mode under the condition that a triggering instruction for triggering an event is detected.
3. The method of claim 2, further comprising:
acquiring a sleep time length for entering a sleep mode;
correspondingly, in the case that a trigger instruction for triggering an event is detected, controlling the microprocessor to enter an operating mode includes:
controlling the microprocessor to enter an operating mode if the sleep duration reaches a third duration threshold or if a trigger instruction for a trigger event is detected.
4. The method of claim 1, wherein determining the first duration threshold based on the target operating instruction comprises:
analyzing the target operation instruction to obtain identification information of a target device, wherein the target device is a device for executing the target operation instruction;
inquiring a target interference duration corresponding to the identification information in a prestored device interference duration table;
a first time threshold is determined based on the target interference duration.
5. The method of claim 4, wherein the determining a first time threshold based on the target interference duration comprises:
determining the target interference duration as a first duration threshold;
alternatively, the first and second electrodes may be,
and determining the sum of the target interference duration and a fourth duration threshold as a first duration threshold.
6. The method according to any one of claims 2 to 5, further comprising:
acquiring initial timing time of a timer;
updating the initial timing time based on the sleep duration to obtain the updated timing time of the timer;
or updating the initial timing time based on the sleep duration to obtain the updated timing time of the timer.
7. The method of any of claims 1 to 5, wherein controlling the microprocessor to enter a sleep mode comprises:
and turning off the main clock of the microprocessor, and turning on the auxiliary clock of the microprocessor to enter a sleep mode, wherein the frequency of the auxiliary clock of the microprocessor is less than the interference frequency generated when the target device executes the target operation instruction.
8. An apparatus for resisting interference, the apparatus comprising:
the device comprises a determining module, a judging module and a judging module, wherein the determining module is used for determining a first time length threshold value based on a target operation instruction under the condition that the target operation instruction is detected;
the first control module is used for controlling the microprocessor to enter a sleep mode;
the first acquisition module is used for timing the time length of the microprocessor entering the sleep mode to obtain the sleep time length;
and the second control module is used for controlling the microprocessor to enter a working mode under the condition that the sleeping time length reaches the first time length threshold value.
9. An interference rejection device, comprising:
a controller comprising at least one microprocessor;
a memory for storing a computer program operable on the controller;
wherein the computer program, when executed by a controller, implements the steps of the interference rejection method of any of claims 1 to 7 above.
10. A computer-readable storage medium having stored thereon computer-executable instructions configured to perform the steps of the tamper-resistant method of any one of claims 1 to 7.
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| CN115421928A (en) * | 2022-11-04 | 2022-12-02 | 摩尔线程智能科技(北京)有限责任公司 | Device and method for reducing electromagnetic interference generated by chip and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115421928A (en) * | 2022-11-04 | 2022-12-02 | 摩尔线程智能科技(北京)有限责任公司 | Device and method for reducing electromagnetic interference generated by chip and electronic equipment |
| CN115421928B (en) * | 2022-11-04 | 2023-01-31 | 摩尔线程智能科技(北京)有限责任公司 | Device and method for reducing electromagnetic interference generated by chip and electronic equipment |
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