CN114567320A - Fractional sample rate converter and phase locked loop - Google Patents

Abstract

A fractional sample rate converter and phase locked loop includes a first-in-first-out FIFO buffer, write logic, read logic, and a fractional interpolator. The write logic is to write input data samples to the FIFO at a first rate. A fractional interpolator is coupled to receive the input data samples from the FIFO and to generate corresponding interpolated data samples as an output of the fractional sample rate converter at a second rate. The read logic is intended to cause the input data samples in the FIFO buffer to be transferred to the fractional interpolator. The ratio of the second rate to the first rate is a fraction greater than 1.

Description

Fractional sample rate converter and phase locked loop

Priority declaration

This patent application, filed on 23/3/2021, application No. 202141012418 entitled "Method for Hardware Efficient Fractional Interpolator and Rate Converter Design for multirate Signal Processing" (Method for hard Efficient Fractional Interpolator and Rate Converter Design), claims priority from pending provisional indian patent application, filed on 7/12/2021, application No. 17/543,762, and claims priority from U.S. patent application, filed on 7/12/2021, both of which are incorporated herein by reference in their entirety.

Technical Field

Embodiments of the present application relate generally to multi-rate signal processing and, more particularly, to a fractional sample rate converter for generating output samples at a higher rate from input samples.

Background

The sample rate converter provides output samples at a different rate (output rate) than the rate at which the input samples are generated (input rate). As is well known in the relevant art, sample rate converters are used in digital signal processing environments such as audio codecs, image processing systems, Phase Locked Loops (PLLs), and the like.

It is often desirable for a sample rate converter to be able to provide samples at an output rate that is higher than the input rate. The output rate needs to be a (non-integer) fractional multiple of the input rate, which in practice means that the output rate is a higher fractional sampling rate than the input rate.

Disclosure of Invention

Aspects of the present application are directed to providing fractional sample rate converters that generate output samples from input samples at a higher rate.

Some embodiments of the present application provide a fractional sample rate converter, including: a first-in first-out FIFO buffer; write logic to write input data samples to the FIFO buffer at a first rate; a fractional interpolator coupled to receive the input data samples from the FIFO buffer, the fractional interpolator generating respective interpolated data samples as an output of the fractional sample rate converter at a second rate Fhi; and read logic to cause input data samples in the FIFO buffer to be transferred to the fractional interpolator, wherein a ratio of the second rate to the first rate is a fraction greater than 1.

In some embodiments, the write logic writes the input data samples to the FIFO buffer at a first constant frequency constituting the first rate Flo, and wherein the read logic is to cause the input data samples in the FIFO buffer to be transmitted to the fractional interpolator at a variable frequency that, on average, constitutes the first rate.

In some embodiments, the fractional interpolator generates the interpolated data samples from the input data samples using linear interpolation.

In some embodiments, the write logic comprises: a register for receiving each of a plurality of input data samples from a source at the first rate, the register for storing the input data sample at a corresponding active edge of a low frequency clock Flo having a frequency equal to the first rate, wherein the stored input data sample is available at an output of the register for one period of the low frequency clock, an output of the register being coupled to an input data port of the FIFO buffer; a flip-flop having a divide-by-2 configuration clocked by the low frequency clock, an output of the flip-flop to switch on each active edge of the low frequency clock; a cross-clock domain synchronizer having an input coupled to the output of the flip-flop, the cross-clock domain synchronizer receiving a high frequency clock Fxo having a frequency equal to Fhi x Lint, where Lint is an integer, and storing the output of the flip-flop at an active edge of the high frequency clock Fxo, the stored output of the flip-flop serving as a synchronization signal at a second output of the cross-clock domain synchronizer; and an edge detector coupled to receive the synchronization signal, the edge detector generating pulses from the synchronization signal at a third output of the edge detector at a rate equal to the first rate,

Wherein the third output is coupled to a write enable of the FIFO buffer, causing input data samples to be written to the FIFO buffer at the first rate synchronized to the high frequency clock.

In some embodiments, the edge detector comprises: a delay element coupled to the second output, the delay element delaying the synchronization signal by a duration equal to one clock cycle of the high frequency clock and generating a delayed synchronization signal at a fourth output of the delay element; and an exclusive-or, XOR, gate coupled to receive the synchronization signal and the delayed synchronization signal and to generate the pulse as a result of an XOR operation of the synchronization signal and the delayed synchronization signal.

In some embodiments, the FIFO buffer is a synchronous FIFO buffer and operates based on the high frequency clock.

In some embodiments, the fractional interpolator is to calculate the current interpolated sample according to the following equation:

wherein Xhi [ m ] represents the current interpolated data sample, Xlo [ k ] and Xlo [ k-1] represent input data samples used to compute the current interpolated sample, Llin represents the ratio of the second rate and the first rate, and 'r' is equal to the expression { m- (k-1) × Llin }, where m and k are sample indices of interpolated and input data samples; the fractional sample rate converter further comprises a real counter clocked by the high frequency clock, the real counter calculating a value of 'r' to be used by the fractional interpolator to obtain each interpolated data sample including the current interpolated data sample, the real counter forwarding the value of 'r' to the fractional interpolator, the real counter further operating as the read logic; wherein the real counter is to: initializing r to zero upon reset of the fractional sample rate converter; adding r to 1 at the second rate based on active edges of an intermediate frequency clock having a rate equal to Fhi, wherein the intermediate frequency clock is derived from the high frequency clock Fxo and is synchronized with the high frequency clock Fxo; and if the increment value of r is greater than or equal to rlin, setting r equal to (r-rlin) and causing the next data sample in the FIFO buffer to be transferred to the fractional interpolator.

In some embodiments, wherein the fractional interpolator is to calculate the current interpolated sample according to the following equation:

wherein Xhi [ m ] represents the current interpolated data sample, Xlo [ k ] and Xlo [ k-1] represent input data samples used to compute the current interpolated sample, Llin represents the ratio of the second rate and the first rate, and 'r' is equal to the expression { m- (k-1) × Llin }, where m and k are sample indices of the interpolated sample and the input data samples; the fractional sample rate converter further comprises a real counter clocked by the high frequency clock, the real counter calculating a value of 'r/Llin', the real counter calculating a value of 'r' to be used by the fractional interpolator to obtain each interpolated data sample including the current interpolated data sample, the real counter forwarding the value of 'r/Llin' to the fractional interpolator, the real counter further operating as the read logic, wherein the real counter is to: initializing r/Llin to zero when the fractional sample rate converter is reset; increasing r/Llin by 1/Llin at the second rate; and if the increment value of r/Llin is greater than or equal to 1.0, setting the increment value equal to (r/Llin-1.0) and causing the next data sample in the FIFO buffer to be transferred to the fractional interpolator, wherein the setting indicates that a rollover condition has occurred.

In some embodiments, the fractional sample rate converter further comprises: a calculation engine to calculate the value 1/Llin, the calculation engine to provide the value 1/Llin to the real counter.

In some embodiments, the compute engine updates the value 1/lllin from time to compensate for frequency drift of the high frequency clock and the low frequency clock, wherein the real counter applies the updated value of 1/lllin when the rollover condition occurs.

In some embodiments, when an overflow condition occurs in the FIFO buffer, logic in the FIFO buffer is to: replacing a previous sample in the FIFO buffer with an arithmetic average of a next input data sample and a previous sample received from the write logic.

In some embodiments, upon an underflow condition, the fractional interpolator is used to calculate the next input data sample Xlo [ k-2] to calculate the next interpolated sample according to the following equation: xlo [ k-2] (2 x Xlo [ k ]) -Xlo [ k-1], where Xlo [ k ] and Xlo [ k-1] are the last two samples currently available in the fractional interpolator.

Some embodiments of the present application further provide a phase-locked loop PLL, including: a data selector (MUX) coupled to receive a first clock and a second clock, the MUX to forward the first clock as a selected clock if a select signal has a first value and to forward the second clock as a selected clock if the select signal has a second value; a phase detector coupled to receive the selected clock and a feedback clock, the phase detector generating an error signal in the form of an error data sample stream, the error signal representing a phase difference between the selected clock and the feedback clock; a digital filter for generating a stream of filtered error data samples by filtering the error data samples; an oscillator coupled to receive the filtered error data samples and to generate an output clock, wherein a frequency of the output clock is determined by a size of the filtered error data samples; and a feedback divider that produces each successive cycle of the feedback clock when a predetermined number of cycles of the output clock is counted, wherein the filtered error data samples have a higher rate than the error data samples, wherein the digital filter includes a digital low pass filter and a fractional sample rate converter that receives the error data samples as input data samples, the fractional sample rate converter generates interpolated data samples from the input data samples by interpolation and provides the interpolated data samples to the digital low pass filter, the digital low pass filter low pass filters the interpolated data samples and provides filtered interpolated data samples as the filtered error data samples; wherein the fractional sample rate converter comprises: a first-in first-out FIFO buffer; write logic to write the error input data samples to the FIFO buffer at a first rate; a fractional interpolator coupled to receive the input data samples from the FIFO buffer, the fractional interpolator generating respective interpolated data samples as an output of the fractional sample rate converter at a second rate Fhi; and read logic to cause input data samples in the FIFO buffer to be transferred to the fractional interpolator, wherein a ratio of the second rate to the first rate is a fraction greater than 1.

In some embodiments, the write logic writes the input data samples to the FIFO buffer at a first constant frequency constituting the first rate Flo, and wherein the read logic is to cause the input data samples in the FIFO buffer to be transmitted to the fractional interpolator at a variable frequency that, on average, constitutes the first rate.

In some embodiments, the fractional interpolator generates the interpolated data samples from the input data samples using linear interpolation.

In some embodiments, the write logic comprises: a register for receiving each of a plurality of input data samples from a source at the first rate, the register for storing the input data sample at a corresponding active edge of a low frequency clock Flo having a frequency equal to the first rate, wherein a stored input data sample is available at an output of the register for one period of the low frequency clock, the output of the register being coupled to an input data port of the FIFO buffer; a flip-flop having a divide-by-2 configuration clocked by the low frequency clock, an output of the flip-flop to switch on each active edge of the low frequency clock; a cross-clock domain synchronizer having its inputs coupled to the outputs of the flip-flops, the cross-clock domain synchronizer receiving a high frequency clock Fxo having a frequency equal to Fhi x Lint, where Lint is an integer, and storing the outputs of the flip-flops on active edges of the high frequency clock Fxo, the stored outputs of the flip-flops used as a synchronization signal at a second output of the cross-clock domain synchronizer; and an edge detector coupled to receive the synchronization signal, the edge detector pulsing from the synchronization signal at a rate equal to the first rate at a third output of the edge detector, wherein the third output is coupled to a write enable of the FIFO buffer, causing input data samples to be written to the FIFO buffer at the first rate synchronized to the high frequency clock.

In some embodiments, the edge detector comprises: a delay element coupled to the second output, the delay element delaying the synchronization signal by a duration equal to one clock cycle of the high frequency clock and generating a delayed synchronization signal at a fourth output of the delay element; and an exclusive-or, XOR, gate coupled to receive the synchronization signal and the delayed synchronization signal and to generate the pulse as a result of an XOR operation of the synchronization signal and the delayed synchronization signal.

In some embodiments, the FIFO buffer is a synchronous FIFO buffer and operates based on the high frequency clock.

In some embodiments, the fractional interpolator is configured to calculate the current interpolated sample according to the following equation:

wherein, Xhi [ m]Represents the current interpolated data sample, Xlo [ k ]]And Xlo [ k-1 ]]Representing input data samples used to compute said current interpolated sample, rlin representing a ratio of said second rate and said first rate, and 'r' being equal to the expression { m- (k-1) × rlin }, where m and k are sample indices of interpolated samples and said input data samples; the fractional sample rate converter further comprises a real counter clocked by the high frequency clock, the real counter calculating a value of 'r/Llin', the real counter calculating a value of 'r' to be used by the fractional interpolator to obtain a signal comprising For each interpolated data sample of said current interpolated data samples, said real counter forwarding said 'r/Llin' value to said fractional interpolator, said real counter also operating as said read logic; wherein the real counter is to: initializing r/Llin to zero when the fractional sample rate converter is reset; increasing r/Llin by 1/Llin at the second rate; and if the increment value of r/Llin is greater than or equal to 1.0, setting the increment value equal to (r/Llin-1.0) and causing the next data sample in the FIFO buffer to be transferred to the fractional interpolator, wherein the setting indicates that a rollover condition has occurred.

In some embodiments, the fractional sample rate converter further comprises a compute engine to compute a value 1/lllin, the compute engine providing the value 1/lllin to the real counter, wherein the compute engine updates the value 1/lllin from time to compensate for frequency drift of the high frequency clock and the low frequency clock, wherein the real counter applies the updated value 1/lllin when the rollover condition occurs, wherein upon an overflow condition occurring in the FIFO buffer, logic in the FIFO buffer is to: replacing a previous sample in the FIFO buffer with an arithmetic average of a next input data sample received from the write logic and the previous sample, and wherein the fractional interpolator is to calculate a next input data sample Xlo [ k-2] upon an underflow condition to calculate a next interpolated sample according to the following equation: xlo [ k-2] (2 x Xlo [ k ]) -Xlo [ k-1], where Xlo [ k ] and Xlo [ k-1] are the last two samples currently available in the fractional interpolator.

Drawings

Example embodiments of the present application will be described with reference to the accompanying drawings, which are briefly described below.

FIG. 1 illustrates a block diagram of an example device in which aspects of the subject application may be implemented.

Fig. 2 shows a block diagram of a low pass filter block used in a Phase Locked Loop (PLL) in an embodiment of the application.

Fig. 3A shows a block diagram of a fractional sample rate converter in an embodiment of the application.

Fig. 3B shows a block diagram depicting implementation details of a synchronizer and edge detector used in the fractional sample rate converter in an embodiment of the present application.

Fig. 4A shows a block diagram depicting relevant details of a FIFO used in a fractional sample rate converter in an embodiment of the application.

Fig. 4B shows a block diagram depicting relevant details of a FIFO for use in a fractional sample rate converter that supports an overflow condition in an embodiment of the application.

Fig. 5 shows a timing diagram of signals at various nodes of a synchronizer and an edge detector used in a fractional sample rate converter to describe an embodiment of the present application.

Fig. 6 shows a schematic diagram illustrating the manner in which linear interpolation is employed in the fractional interpolator provided by the present application.

Fig. 7A and 7B show schematic diagrams depicting an ideal case and an overflow case, respectively, of a FIFO used in a fractional sample rate converter in an embodiment of the present application.

Fig. 8 shows a schematic diagram depicting an underflow condition of a FIFO used in the fractional-sample-rate converter in an embodiment of the present application.

In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.

Detailed Description

1. Overview

According to one aspect of the present application, a fractional sample rate converter includes a first-in-first-out (FIFO) buffer, write logic, read logic, and a fractional interpolator. The write logic is to write input data samples to the FIFO at a first rate. A fractional interpolator is coupled to receive the input data samples from the FIFO and to generate corresponding interpolated data samples as an output of the fractional sample rate converter at a second rate. The read logic is intended to cause the input data samples in the FIFO buffer to be transferred to the fractional interpolator. The ratio of the second rate to the first rate is a fraction greater than 1.

In one embodiment, the write logic writes input data samples to the FIFO buffer at a first constant frequency constituting a first rate (Flo), and the read logic transfers the input data samples in the FIFO buffer to the fractional interpolator at a variable frequency that, on average, constitutes the first rate.

Several aspects of the disclosure are described below in conjunction with examples for purposes of illustration. One skilled in the relevant art will recognize, however, that the application can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown in detail to avoid obscuring aspects of the application. Moreover, for the sake of brevity only some combinations are described herein, but the features/aspects described may be implemented in various combinations.

2. Example apparatus

Fig. 1 shows a block diagram of an example device in which aspects of the present application may be implemented, and illustrates implementation details of a phase-locked loop (PLL). The illustrated PLL 100 includes an input clock divider 110 and 160, a data selector (MUX)115, a phase to digital converter 121, a digital filter 130, a Digitally Controlled Oscillator (DCO)140, an output clock Divider (DIVO)150, a feedback clock divider 185, a clock switching controller 170, and a reference clock generator 195. The specific blocks/components of the PLL 100 are shown by way of illustration only. One skilled in the relevant art will readily recognize upon reading the disclosure herein that: other embodiments of the PLL 100 may be implemented with other blocks/components. For example, the phase digitizer 121 may be replaced by a Time Digitizer (TDC) with a corresponding change in the PLL 100. Furthermore, although feedback clock divider 185 is shown as a combination of fractional (frac-N) feedback divider 180 and Delta Sigma Modulator (DSM)190, feedback clock divider 185 may also be implemented as an integer divider if fractional division is not required.

Input clock divider 110 receives input clock fin-1 on path 108, divides fin-1 to produce a desired frequency, and provides the divided input clock as output (fin-1d) on path 111. Input clock divider 160 receives input clock fin-2 on path 109, divides fin-2 to produce a desired frequency, and provides the divided input clock as output (fin-2d) on path 161. The values of the division ratios used by the input clock divider 110 and the input clock 160 are such that the clock fin-1d and the clock fin-2d have the same frequency (possibly within some error range).

MUX 115 receives fin-1d and fin-2d and forwards one of fin-1d and fin-2d as an output (MUX output/selected clock) on path 112 based on the logic value of select signal 171.

Phase digitizer 121 receives MUX output 112 and feedback clock 182(fb), generates an (internal) error signal having a value proportional to the (current) phase difference between signal 112 and signal 182, and provides the error signal in digital form to path 123. Path 123 may represent one or more digital paths, each path for digitizing a corresponding bit of the error signal. Phase digitizer 121 receives sampling clock Flo (122) and generates a digital error signal at rate Flo to path 123. The clock Flo (122) may be generated internally within the PLL 100.

In an alternative embodiment, the components/blocks 121 may be implemented as time-to-digital converters (TDCs) in a known manner, with corresponding modifications to the implementation of the other blocks of the PLL 100, as will be apparent to those skilled in the art. In general, component 121 functions as a phase detector, receiving signal 112 and signal 182(fb) and generating an error signal in digital form to path 123 that is representative of the phase error between signal 112 and signal 182 (fb).

The digital filter 130 provides data samples at a higher rate (Fxo) to path 134 based on input samples received from path 123 at the lower rate Flo. The output samples on path 134 may be generated based on interpolation. The digital filter 130 also receives clocks Flo (122) and Fxo (131) to enable internal operation, as described below. The clock Fxo (131) may be generated inside the PLL 100. In one embodiment, the digital filter 130 may additionally operate as a digital low pass filter, and further, may introduce any desired delay to the received or generated data samples. Thus, the output samples on path 134 represent a low pass filtered version of the input samples on path 123.

A Digitally Controlled Oscillator (DCO)140 receives the samples from path 134. DCO 140 generates a periodic signal fout (148) having a frequency determined by the size of the data sample currently received as input. DIVO 150 divides the frequency of fout by the desired number to generate fout-d (151).

Feedback clock divider 185 receives fout (148) and divides the frequency of fout to a desired value. In general, the divide ratio provided by the feedback clock divider 185 may cause fout to be generated at a multiple of the frequency of the selected one of the input clock fin-1 and the input clock fin-2. DSM 190 may be programmed by a user (by methods not shown) to cause feedback clock divider 185 to use a fractional division ratio. Depending on the particular divide ratio, the DSM 190 generates a corresponding set of divide values (which are repeatedly provided to the fractional feedback divider 180 to average the frequency of the divided clock fb (182) to the fraction required for the fout frequency). It is also possible to use only integer dividers instead of component 185. Alternatively, DSM 190 may be programmed such that fractional feedback frequency divider 180 also divides fout by an integer divisor.

The clock switching controller 170 receives the clocks fin-1d and fin-2 d. The clock switching controller 170 includes circuitry for determining whether the clock is valid/operating properly. Further, the clock switching controller receives a sampling clock Flo (122) to enable operations (including counting). In one embodiment, such circuitry is implemented as one or more counters that count the number of cycles (in a predetermined duration) of a received clock to determine whether the corresponding clock is operating properly. The clock switching controller 170 may require a non-zero length of time to determine whether the currently used input clock is not functioning properly. In the embodiment of the present application, the clock switching controller 170 needs a count of two cycles to determine whether the corresponding clock is operating normally.

The clock switching controller 170 may be pre-programmed to treat fin-1/fin-1d as the master clock and fin-2/fin-2d as the sub-clock/redundant clock. Thus, by default (e.g., upon power up of the PLL 100), the clock switching controller 170 may program the binary value of the select signal 171 to cause the MUX 115 to forward fin-1d to the path 112. The clock switching controller 170 continues to check whether fin-1d is functioning properly. Upon determining that fin-1d is malfunctioning (inactive/inoperative) or if an explicit command is received from an external device on path 179 (e.g., based on user input or from an external device) to switch to the sub-clock, the clock switch controller 170 implements an interrupt-free switch to fin-2d by controlling the components in the digital filter 130 and the feedback clock divider 185. The clock switching controller 170 may require a non-zero length of time to switch to the sub-clock in response to an explicit command received on path 179. The clock switching controller 170 may operate similarly to switch from using the sub-clock to using the master clock if the sub-clock fails or if an explicit command is received on path 179 to switch back to the master clock.

The reference clock generator 195 generates a (high precision and high stability) reference clock 197. Typically, the ratio of the frequency of the reference clock 197 to the (ideal/desired) frequencies of fin-1d and fin-2d is fixed and known (the ratio may be a fraction or an integer). The reference clock 197 is used to estimate the frequency error of the (actual) frequency of fin-1d and/or fin-2d relative to the ideal/desired frequency and to correct for such errors in the PLL 100 output. The clock switching controller 170 generates a reset signal RST-sync (178) to release the feedback clock divider 185 from being reset synchronously with respect to the clock fin-2d (161). The clock switching controller 170 may be implemented in a known manner.

As described above, the sample rate of the input data samples provided to the digital filter 130 via path 123 is Flo, lower than the sample rate Fxo of the output data on path 134. In the example of fig. 1, DCO 140 is implemented as another PLL (embedded PLL) and runs at rate Fxo, i.e., the reference clock of the embedded PLL is clock Fxo and several other blocks of the embedded PLL also run using Fxo. Several corrections are applied in the digital filter 130 (in the event of a failure or switching of the input clock) and combined with various other corrections (not shown or described due to the non-correlation) are provided as inputs to the DCO 140 on path 134. Such input to DCO 140 also needs to run at rate Fxo.

Thus, the PLL 100 represents an example of a multiple sample rate device or system. Details of implementation of the digital filter block 130 in embodiments of the present application are provided below with reference to fig. 2.

3. Digital filter block

Fig. 2 shows a detailed block diagram illustrating the digital filter 130 of fig. 1 in an embodiment of the present application. The digital filter 130 is shown to include a fractional sample rate converter 210, a Digital Low Pass (DLP) filter 220, and a cascaded integrator-comb (CIC) filter 230. For simplicity, the delay block described above is not shown separately and may be assumed to be provided within 220. It is only necessary to note here that the delay provided by the delay block enables the PLL 100 to switch between the input clocks without causing transients in the output clock fout (148) due to the non-zero time required by the clock switching controller 170 to switch the PLL 100 from the currently used input clock to a different other input clock.

In FIG. 2, each data sample on paths 123, 212, 223, and 134 may be several bits wide, although these paths are shown as a single line.

Fractional sample rate converter 210 receives data samples from path 123 at rate Flo and increases the sample rate by a fraction (lllin) greater than 1 to generate output data samples at Fhi rate using interpolation to path 212. The ratio of the rate Fhi to Flo, Llin, is a fraction greater than 1. In one embodiment, the ratio is 1.66, although other fractional ratios are possible. The fractional sample rate converter 210 receives clocks Flo and Fxo. Rate Fhi is equal to rate Fxo/Lint, where Lint is an integer.

The DLP filter 220 runs at a rate Fxo/Lint (based on a clock having a frequency Fxo/Lint that is generated internally or generally within the PLL 100). Thus, DLP filter 220 is shown as receiving clock Fxo/Lint (221). DLP filter 220 includes one or more digital filters (running at Fxo/Lint) to provide low pass filtering of the samples on path 212 (or equivalently) path 123. DLP filter 220 forwards the low pass filtered samples at rate Fxo/Lint to path 223.

CIC filter 230 increases the sample rate of the samples of path 223 by an integer value Lint to rate Fxo, and is shown receiving clock Fxo/Lint and Fxo. CIC filter 230 provides samples to path 134 at rate Fxo. DLP filter 220 and CIC filter 230 may be implemented in a known manner. It will be appreciated that the increase in overall sample rate from the samples on path 123 to the samples on path 134 is the product (lin) of the fractional sample rate factor (lllin) provided by fractional sample rate converter 210 and the integer sample rate factor provided by CIC filter 230. The particular value of the product L of Llin and Lint (i.e., Fxo/Flo) may be selected according to the particular design requirements of the PLL 100.

The order of the blocks in fig. 2 is for illustration only. In alternative embodiments, the location/order of the blocks may be changed with corresponding changes to the details of their design. For example, the locations of fractional sample rate converter 210 and DLP filter 220 may be interchanged, where DLP filter 220 is directly connected to path 123 and converter 210 may be connected to path 212. In other embodiments, the CIC filter 230 may not be implemented.

Implementation details and operation of the fractional sample rate converter 210 as shown in fig. 2 are provided next.

4. Fractional sample rate converter

Fig. 3A shows a block diagram of a fractional sample rate converter in an embodiment of the application. Fractional sample rate converter 210 is shown to include a register 310, a flip-flop 340, a cross-clock domain synchronizer 350 (synchronizer 350), an edge detector 360, a first-in-first-out buffer (FIFO)320, a fractional interpolator 330, a counter 370, and a 1/lllin compute engine 380. In FIG. 3A, paths that include multiple bit lines are labeled with a slash (/), and all include the same number of bit lines. The register 310 and the flip-flop 340 operate based on (in synchronization with) the clock Flo (122). The remaining blocks of fig. 3A operate based on clock Fxo (351), which is synchronized with clock Fxo (351). Using a higher frequency clock Fxo (equal to Fhi x Lint) instead of Fhi simplifies the implementation and operation of these modules. In the following description, for convenience of explanation and description, it is assumed that the data sample 301 corresponds to the data sample 123 (in fig. 1 and 2) and the interpolated sample 331 corresponds to the data sample 134 (in fig. 1 and 2).

Register 310 receives a multi-bit (N bits, where N may be, for example, 32) input data sample Xlo [ k ] on path 310, where k represents an index (index) or sample number, and stores the sample at the active edge (e.g., rising edge) of clock Flo (122) applied to the clock side of register 310. The input sample is available at the output (Q) of the register until the next active edge of Flo, at which time the next input data sample is stored and available at the output. The output (Q) is connected to the Input (IN) of the FIFO320 via path 312.

Flip-flop (FF)340 and inverter 341 operate together to divide the frequency of clock Flo (122) applied at the clock terminal of FF 340 by 2. The single bit output (Q) of FF 340 is connected to the D input of FF 340 through inverter 341. The divided clock is provided to the input of synchronizer 350 via path 345.

Synchronizer 350 minimizes or eliminates the possibility of metastability when the divided down clock 345 crosses from the domain of clock Flo to the domain of clock Fxo. Clock Flo and clock Fxo are asynchronous to each other except that they have different frequencies. As can be seen from fig. 3A, blocks 310 and 340 operate in the domain of Flo (122), while the other blocks operate in the domain of Fxo (351). Synchronizer 350 is shown in fig. 3B as being implemented as a pair of flip- flops 355A and 355B connected in series such that signal 345 passes through both flip-flops (each clocked by Fxo) to be provided as a synchronized divided clock to path 356. Although synchronizer 350 is shown implemented as only a pair of series flip-flops, more than two series flip-flops may be employed for synchronous operation, for example, when Fxo is very high, depending on the frequency of Fxo, as is well known in the relevant art. Synchronizer 350 provides a synchronized divided clock 356 as an input to edge detector 360.

Referring again to fig. 3A, the edge detector 360 receives the clock Fxo (351) and generates a pulse at each edge of the divided clock 356. An implementation of the edge detector 360 in one embodiment is shown in FIG. 3B, where the edge detector 360 is implemented using a flip-flop 365 and an exclusive OR (XOR) gate 390. FF 365 delays Fxo divided-down clock 356 by one cycle (received on the clock terminal of FF 365) and provides the delayed clock to path 369. The XOR gate generates the result of the XOR operation of input 356 and input 369 to generate a pulse on output 362 at each clock edge of clock 356.

Fig. 5 shows a timing diagram of the generation of pulses on path 362, showing several cycles of clock Flo (122), input data sample Xlo (on path 301), divided clock 345, synchronous clock 356, delayed clock 369, and pulses 362. FIG. 5 also shows four input data samples Xlo [ k ], Xlo [ k +1], Xlo [ k +2], and Xlo [ k +3], with a sample rate of Flo. The time interval t51-t52 equals two cycles of Fxo and the time interval t52-t53 equals one cycle of Fxo. The pulses on path 362 are also generated at rate Flo, synchronized with Fxo, and generated at or corresponding to each edge (rising and falling) of the synchronous and divided clock 356, which is therefore at or corresponding to each active (here rising) edge of Flo.

Referring again to FIG. 3A, the pulse on path 362 is applied as a write enable (WREN) signal to the write enable (WR) terminal of FIFO 320. Thus, the input data samples Xlo provided by the path 312 are written to the FIFO in a synchronized manner (relative to the clock Fxo) at the Flo rate. As shown in the timing diagram of fig. 5, the combination of register 310, FF340, synchronizer 350, and edge detector 360 may be viewed as "write logic" that writes input data samples Xlo into a FIFO at a constant frequency that constitutes a first rate (Flo). Specifically, if we ignore the uncertainty of one Fxo cycle of synchronizer 350 (i.e., the duration between pulses may have an error equal to 0 or 1 cycle of Fxo clocks), the duration between the rising edges of the pulses is the same/constant. The frequency may be considered constant.

As described above, the FIFO 320 is a synchronous FIFO and buffers input data samples written thereto via the IN input. In other operations, counter 370 generates a read enable signal (applied at the RD terminal of FIFO 320) to cause the input data samples stored in FIFO 320 to be provided as output (through the OUT terminal) at a rate that varies, but whose average value with the varying rate is equal to rate Flo, as described below.

Fig. 4A shows internal details of FIFO 320, where FIFO 320 is shown to include a write control 410, a write pointer 415, an input register 420, flag logic 430, a Dual Port Random Access Memory (DPRAM)450, an output register 470, a read control 475, and a read pointer 480. The specific details of the synchronization FIFO 320 are for illustration only. The synchronization FIFO 320 may be implemented to include more or fewer blocks, as is well known in the relevant art. Both writes and reads to the synchronization FIFO 320 are synchronized with respect to the clock Fxo. The FIFO 320 may be implemented in a known manner, the internal details of which are only briefly described below.

DPRAM 450 represents a memory array. Writing and reading to the memory array may be performed simultaneously. Input register 420 is connected to path 312 (the IN end of FIFO 320, as shown IN FIG. 3A), and register 310 provides data samples to path 312. The data samples are stored in the input register 420 at the active edge of the signal 412. Signal 412 is a pulse (or pulses) generated synchronously with Fxo when WREN 362 is active (e.g., interval t52-t53 in FIG. 5). The data sample captured in the input register 420 is moved/written to the appropriate memory location based on the address currently included in the write pointer 415. The write pointer 415 is then incremented to the next address in the array, assuming the FIFO (or DPRAM 450) is not full, or reset to the lowest address (the address of the first cell in the FIFO 320) if the write pointer 415 points to the highest memory address. However, if the FIFO is full, the write pointer will not be incremented and no write operation will be performed. In an embodiment of the present application, DPRAM 450 is implemented in a known manner using flip-flops.

The read pointer 480 includes the current address of the memory location in the DPRAM 450 to be read. Output register 470 receives a stored data sample from a memory location (in DPRAM 450) whose address is currently included in read pointer 480 on the active edge of signal 477. The data samples are available on path 323 (the OUT end of FIFO 320, as shown in fig. 3A). Signal 477 is a pulse generated synchronously with Fxo when RDEN 372 is active. As described below, RDEN 372 is generated by counter 370 (e.g., in the form of pulses). After reading, assuming the FIFO (or DPRAM 450) is non-empty, the read pointer 480 is incremented to the next address in the array or, if the read pointer 480 points to the highest memory address, reset to the lowest address (the address of the first cell in the FIFO 320). However, if the FIFO is empty, the read pointer will not increment and the data sample on path 323 will be invalid/indeterminate.

The flags are logically connected to the write pointer 415 and the read pointer 480 and include a plurality of flags that indicate the state of the FIFO 320 based on the addresses in the current write pointer 415 and read pointer 480. Fig. 4A shows only two markers 321(E) and 322 (F). When FIFO 320 is empty, flag 321 is asserted (e.g., binary 1), and when FIFO 320 is full, flag 322 is asserted. Flags 321 and 322 are connected to the E (empty) and F (full) terminals, respectively, of interpolator 330. At reset/power up, the read pointer 480 and write pointer 415 are initialized to the lowest cell address (zero). The flag is reset to the appropriate value.

It is noted that although labeled as synchronous FIFO, FIFO 320 may be implemented as an asynchronous FIFO in other embodiments as well, as will be apparent to those skilled in the relevant art. In an asynchronous FIFO, the read and write pointers will run in separate (separate/distinct) read and write clock domains. To detect FIFO full and FIFO empty etc., the read and write pointers must be compared by read and write logic implemented in the asynchronous FIFO. Before any such comparison is performed, it is necessary to transfer one of the pointers to the clock domain of the other pointer. It will be appreciated that such a transfer is not required in the synchronization FIFO 320. In general, it is noted that synchronous FIFOs are generally simpler, smaller, faster, and consume less power than asynchronous FIFOs.

With continued reference to fig. 3A, non-integer (fractional) interpolator 330 receives an input data sample (sample rate of Flo) from path 323, which is controlled by the RDEN signal from the ROL terminal of counter 370. Fractional interpolator 330 generates an Llin interpolated data sample for each input data sample received, where Llin is a fraction greater than 1. Fractional interpolator 330 provides interpolated data samples Xhi [ m ], which is an index or sample number, to path 331 at a rate Fhi. As mentioned above, the ratio of frequency Fhi to frequency Flo is equal to lllin, a fraction greater than 1. An example value for Llin is 1.66.

The operation of counter 370 and fractional interpolator 330 will now be briefly described, where counter 370 causes input data samples to be read and fractional interpolator 330 causes interpolated data samples to be generated at rate Fhi.

5. Fractional interpolation

In an embodiment of the present application, fractional interpolator 330 employs linear interpolation. However, the techniques described herein may also use other types of (e.g., higher order) interpolation techniques. Fig. 6 is a graph illustrating several samples of Xlo and Xhi. Reference 600 denotes the envelope of the sampled input signal. Xlo are used to obtain Xhi linear interpolated samples. Times t61, t62, t63, t64, and t65 correspond to (m-1) × Thi, (k-1) × Tlo, m × Thi, k × Tlo, and (m +1) × Thi, respectively, where m and k are the indices of interpolated data samples Xhi and input data samples Xlo, respectively, and Thi and Tlo are the inverses of sampling rates Fhi and Flo, respectively. At time 0, indices k and m are each 0. Markers 650 and 670 indicate the amplitude values Xlo [ k ] and Xlo [ k-1] of the input data samples at (k) × Tlo and (k-1) × Tlo, respectively. Reference 660 represents the interpolated amplitude Xhi [ m ] of the interpolated (i.e., output) data samples at m × Thi generated by fractional interpolator 330 using a pair of input data samples Xlo [ k ] and Xlo [ k-1] using a straight line approximation. Reference 601 denotes a straight line formed by samples Xlo [ k ] and Xlo [ k-1 ]. Reference 605 denotes a time interval equal to { m- (k-1) × Llin } × Thi, which is equal to r × Thi. For clarity, the input data samples (k-1) × Tlo and k × Tlo are indicated by bold lines in fig. 6, and the interpolated (i.e., output) data samples m × Thi and (m +1) × Thi are indicated by dashed lines. In the following description, Xlo [ k ] represents the current input data sample, Xlo [ k-1] represents the next input data sample, and so on. Similarly, Xhi [ m ] represents the current interpolated data sample, Xhi [ m-1] represents the next interpolated data sample, and so on.

Using a two-point form of the straight-line equation, xhi [ m ] can be estimated based on the following mathematical relationship:

wherein the content of the first and second substances,

m and k are the time indices of samples Xhi and Xlo, respectively, and

llin is the fractional interpolation ratio Fhi/Flo.

Rearranging equation 1 provides the expression of xhi [ m ], as follows:

it will be appreciated that implementing equation 2 directly may present some difficulties. For example, the discrete time indices m and k need to be tracked. The index m needs to be incremented for each cycle of the output clock Fhi and k needs to be incremented for each cycle of the input clock Flo. For each output sample Xhi, r needs to be evaluated, i.e., { m- (k-1) × Llin }. Such an implementation is impractical because the counters used to generate the indices m and k need to have infinite widths. Furthermore, the input samples Xlo [ k ] in the clock domain Flo and the interpolated samples Xhi [ m ] in the clock domain Fhi present corresponding difficulties in implementation.

The techniques of this application recognize the following relationships associated with indices m and k and variable r:

1. at each point of Fhi, m ≧ (k-1) × Llin

The value of r ═ m- (k-1) × Llin always falls within the range [0, Llin ]

3. If r +1< Llin, then the next value of r is r +1

4. If r +1 ≧ Llin, the next value of r is r + 1-Llin

(As used herein, '> gtoreq' means greater than or equal to the condition,

'<' means less than condition, and

' denotes a multiplication operation).

Based on the above description, the variable r is generated using a real counter. Counter 370 in fig. 3A represents such a counter. Counter 370 receives clock Fhi (at rate Fxo/Lint, and therefore synchronized to clock Fxo) on input 'INCR' (371), and implements the following logic:

a. r is initialized to 0 when the sample rate converter 210 is reset/powered on.

b. At the next tick (active edge) of Fhi, r is incremented by 1. If the increment value of r is greater than or equal to Llin (point 4 above), r is set to r + 1-Llin (the inverted case of the counter 370).

c. Each time r +1 ≧ Llin (i.e., a counter 370 flip condition occurs), FIFO 320 is read by pulse RDEN 372, and the next sample Xlo in FIFO 320 is provided to fractional interpolator 330.

d. Repeat from b.

Counter 370 provides the current value of r to fractional interpolator 330 via an output named "r" and path 374.

In one embodiment of the present application, fractional interpolator 330 receives as input (labeled r on the input and also labeled r at the output of counter 370) the value of 'r' calculated by counter 370 as described above via path 374. Fractional interpolator 330 calculates the "current" interpolated sample Xhi [ m ] according to equation 2. Fractional interpolator 330 provides computed samples Xhi [ m ] to path 331. Fractional interpolator 330 includes one or more multiplication units, division units, and addition/subtraction units internally to implement equation 2.

Due to the fractional (non-integer) nature of lllin, the number of active edges of Fhi between two roll-over events of counter 370 averages to lllin. However, in terms of actual number, fractional interpolator 330 generates floor (lllin) or ceil (lllin) interpolated samples for each input data sample. Floor (lllin) and ceil (lllin) represent the largest integer equal to or less than lllin and the smallest integer equal to or greater than lllin, respectively.

Samples Xlo [ k ] are read from FIFO 320 at a non-uniform rate (i.e., a non-constant rate). If a fixed-size buffer is used instead of FIFO 320, situations may arise where there are insufficient or missing input data samples. The use of a FIFO (320 in this example) rather than a fixed delay buffer allows the buffer to be scaled up or down as required. If enough samples have been buffered in the FIFO 320, the synchronization uncertainty problem (due to the asynchronous nature of the clocks Flo and Fhi) and the r-flip condition in the floor (Llin) Fhi period will be addressed. If there is enough room to accommodate more samples, the r flip case in ceil (Llin) Fhi cycles will be handled. In one embodiment, the ratio Fxo/Flo is greater than or equal to 6 and the depth of the FIFO 320 is 5. On reset, the FIFO 320 is initialized to include three zero-valued input data samples in case of an r (or equivalently counter 370) flip condition in floor (lllin) Fhi cycles before the first sample at Xlo is written into the FIFO 320.

Thus, for each sample of the input Xlo, on average, the fractional interpolator 330 generates an Llin interpolated sample to the path 331. Thus, fractional interpolator 330 "averages" the input samples consumed at rate Fhi/Llin. Since Fhi/Llin is equal to Flo, counter 370 causes the input data samples in FIFO 320 to be transmitted (on path 323) to fractional interpolator 330 at a "variable frequency" that is, on average, equal to rate Flo.

In accordance with another aspect of the present application, in an alternative embodiment, rather than fractional interpolator 330 calculating r/Llin to generate each interpolated sample Xhi, the value r/Llin itself (rather than just r) is calculated and provided by counter 370 at each active edge of Fhi (371) on terminal "COUNT" and provided to fractional interpolator 330 via path 373, fractional interpolator 330 receiving the value on terminal r/Llin. Fractional interpolator 330 calculates Xhi [ m ] according to equation 2. In an embodiment, counter 370 increments by 1/Llin per active edge of Fhi. Correspondingly, the flip condition of the counter 370 is when r/Llin evaluates to greater than or equal to 1.0, in which case r/Llin is set to (r/Llin-1.0). The addition of 1/lllin and the inversion condition r/lllin > of 1.0 can be derived from the relationship in points 2, 3 and 4 described above.

Counter 370 receives the value 1/Llin from 1/Llin calculation engine 380. In an embodiment, 1/Llin calculation engine 380 is additionally implemented to calculate 1/Llin and provide 1/Llin to counter 370 via path 387. In the exemplary environment of the PLL 100 of fig. 1, engine 380 calculates lllin according to the following equation:

hlin ═ Fhi/Flo ═ (I2+ P2/Q2)/(I1+ P1/Q1)/Nadc _ P4/Nadc _ down … equation 3

Among them, the parameters I1, P1, Q1, I2, P2, Q2, Nadc _ P4 and Nadc _ down are internal parameters (381) of the PLL 100 (fig. 1), which can be obtained/realized in a known manner.

However, in other environments, the Llin may be determined based on other considerations, depending on the requirements of the environment. Engine 380 receives each of the above parameters and calculates 1/Llin based on equation 3 above. The frequency of clock Fxo (from which Fhi is derived) and Flo may drift over time. Thus, from time to time (e.g., periodically), the engine 380 calculates the I/Llin. If the calculated value is different from the current value of 1/Llin, engine 380 forwards the new value of 1/Llin to counter 370, which is applied to determine r/Llin (sent on path 373) when counter 370 rolls over.

Due to rounding errors in the register storing 1/lllin (within engine 380, and 32 bits wide in one embodiment), and the very large drift in one or both of clocks Flo and Fxo, FIFO 320 may overflow or underflow before calculating and applying the new value 1/lllin as described above. According to another aspect of the application, such overflow or underflow of the FIFO 320 is detected by the fractional sample rate converter 210 and corresponding corrective measures are taken. Thus, in the example embodiment of fig. 3A, FIFO 320 provides empty (E) and full (F) flags to fractional interpolator 320 via paths 321 and 322, respectively. An empty (E) flag asserted indicates underflow and a full (F) flag asserted indicates overflow. The flag logic 430 (fig. 4A) may use the values in the write and read pointers in the FIFO 320 and the depth (size) of the FIFO 320 to determine whether an underflow or overflow condition has occurred.

It will be appreciated from the above description that the fractional interpolator 330 always has the last two samples Xlo [ k ] and Xlo [ k-1] assuming no overflow or underflow condition has occurred. When an overflow occurs, the next sample that should be fetched from the FIFO 320 is overwritten by the next subsequent sample. Fig. 7A and 7B illustrate an ideal case and an overflow case, respectively, for the "current" time instant, assuming for illustrative purposes only that the depth of the FIFO 320 is 3. With respect to FIG. 7A, Xlo [ k-1] and Xlo [ k ] are available within fractional interpolator 330 and have been used to calculate the latest interpolated sample Xhi [ m ]. Cells 710, 711, and 712 of FIFO 320 are shown as including samples Xlo [ k-2], Xlo [ k-3], and Xlo [ k-4], respectively, and no overflow occurs. To calculate the next value of interpolated samples (and the counter 370 has flipped, fractional interpolator 330 obtains Xlo [ k-2], Xlo [ k-1] becomes Xlo [ k ], Xlo [ k-2] becomes Xlo [ k-1], fractional interpolator uses "current" Xlo [ k ] and Xlo [ k-1] to calculate Xhi [ m ], now Xhi [ m ] is the current interpolated sample.

However, if an overflow condition occurs, additional logic (as shown in FIG. 4B) included in the FIFO 320 replaces the previous sample in the FIFO with the arithmetic average of the next sample Xlo [ k-5] (received on path 312 and available, for example, in the input register 420 of FIG. 4) and the previous sample Xlo [ k-4], as shown in FIG. 7B, i.e.:

Xlo [ k-4] (Xlo [ k-4] + Xlo [ k-5])/2 … equation 4

As described herein, fractional interpolator 330 will eventually receive sample values (Xlo [ k-4] + Xlo [ k-5])/2) and use the sample values in calculating interpolated samples.

Fig. 4B illustrates a modification to the FIFO buffer 320 of fig. 4A to support the above-described operation in the event of an overflow. FIFO buffer 320B of fig. 4B includes all of the blocks of FIFO buffer 320 of fig. 4A, as well as an additional block named overflow logic 490, and corresponding connections to/from overflow logic 490 and modifications to the corresponding blocks, e.g., write control 410, read control 475, etc. It should be noted that the specific details of FIFO buffer 320B are provided for illustration only, and that there are other ways to implement the additional logic shown. In operation, when overflow flag 322 indicates an overflow condition, overflow logic 490 signals write control 410 through bi-directional path 491 to signal back through path 491 when the next input data sample (Xlo [ k-5]) has been written to input register 420. When an indication is received via path 491 that the next input data sample has been written to input register 420, overflow logic 490 obtains the data sample in input register 420 via bidirectional path 429 (Xlo [ k-5 ]). Overflow logic 490 signals read control 475 via bidirectional path 497 to fetch the last sample Xlo [ k-4] (in dual port RAM 450). The read control 475 and read pointer 480 take the last sample Xlo [ k-4], the last sample Xlo [ k-4] being available at the output 457 of the DPRAM 450. Read control 475 signals overflow logic 490 via path 497 that the last sample Xlo [ k-4] is available at output 457 of DPRAM 450. Overflow logic 490 then reads the last sample Xlo [ k-4] at output 457. The overflow logic internally includes logic to generate the arithmetic mean of the next sample Xlo [ k-5] and the previous sample Xlo [ k-4 ]. The above operations may be performed simultaneously or sequentially or in combination. The overflow logic 490 then writes the calculated arithmetic average back to the input register 420 via path 429 and signals the write control 410 via path 491 to write the current contents of the input register 420 to the location of the last sample. The combination of the write control 410 and the write pointer 415 writes the arithmetic mean to the position of the last sample.

As shown in FIG. 8, when an underflow occurs, the FIFO 320 does not include any valid samples. The cells 810, 811, 812 and other cells of the FIFO include invalid data. Fractional interpolator 330 "current" includes Xlo [ k-1] and Xlo [ k ]. Since there is no Xlo [ k-2] active in FIFO 320, the fractional interpolator calculates Xlo [ k-2] as follows:

xlo [ k-2] (2 x Xlo [ k ]) -Xlo [ k-1] … equation 5

Xlo [ k-1] becomes Xlo [ k ], the computed Xlo [ k-2] becomes Xlo [ k-1], and the fractional interpolator uses the "current" Xlo [ k ] and Xlo [ k-1] to compute Xhi [ m ].

As can be seen from equations 4 and 5, the fractional interpolator applies a linear technique to obtain the correct value of the next input sample for use in overflow and underflow conditions.

6. Conclusion

Reference throughout this specification to "one embodiment" or "an embodiment" or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, appearances of the phrases "in one embodiment" and "in an embodiment" or similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

Although in the illustrations of fig. 1, 2, 3A, 3B, 4A, and 4B, although the terminals/nodes/blocks are shown as being directly connected (i.e., "connected") to various other terminals/nodes/blocks, it should be understood that additional components/blocks (as appropriate for the particular environment) may also be present in the path, and thus the connections may be viewed as being "electrically coupled" to the same connected terminals/nodes/blocks.

While various embodiments of the present application have been described above, it should be understood that they have been presented by way of example only, and not limitation. Thus, the breadth and scope of the present application should not be limited by any of the above-described embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims (20)

1. A fractional sample rate converter comprising:

a first-in first-out FIFO buffer;

write logic to write input data samples to the FIFO buffer at a first rate;

a fractional interpolator coupled to receive the input data samples from the FIFO buffer, the fractional interpolator generating respective interpolated data samples as an output of the fractional sample rate converter at a second rate Fhi; and

read logic to cause input data samples in the FIFO buffer to be transferred to the fractional interpolator,

Wherein a ratio of the second rate and the first rate is a fraction greater than 1.

2. The fractional sample rate converter of claim 1, wherein the write logic writes the input data samples to the FIFO buffer at a first constant frequency constituting the first rate Flo, and

wherein the read logic is to cause the input data samples in the FIFO buffer to be transmitted to the fractional interpolator at a variable frequency that, on average, constitutes the first rate.

3. The fractional sample rate converter of claim 2 wherein the fractional interpolator generates the interpolated data samples from the input data samples using linear interpolation.

4. The fractional sample rate converter of claim 3, wherein the write logic comprises:

a register for receiving each of a plurality of input data samples from a source at the first rate, the register for storing the input data sample at a corresponding active edge of a low frequency clock Flo having a frequency equal to the first rate, wherein the stored input data sample is available at an output of the register for one period of the low frequency clock, an output of the register being coupled to an input data port of the FIFO buffer;

A flip-flop having a divide-by-2 configuration clocked by the low frequency clock, an output of the flip-flop to switch on each active edge of the low frequency clock;

a cross-clock domain synchronizer having its inputs coupled to the outputs of the flip-flops, the cross-clock domain synchronizer receiving a high frequency clock Fxo having a frequency equal to Fhi x Lint, where Lint is an integer, and storing the outputs of the flip-flops on active edges of the high frequency clock Fxo, the stored outputs of the flip-flops used as a synchronization signal at a second output of the cross-clock domain synchronizer; and

an edge detector coupled to receive the synchronization signal, the edge detector to produce pulses from the synchronization signal at a third output of the edge detector at a rate equal to the first rate,

wherein the third output is coupled to a write enable of the FIFO buffer, causing input data samples to be written to the FIFO buffer at the first rate synchronized with the high frequency clock.

5. The fractional sample rate converter of claim 4, wherein the edge detector comprises:

a delay element coupled to the second output, the delay element delaying the synchronization signal by a duration equal to one clock cycle of the high frequency clock and generating a delayed synchronization signal at a fourth output of the delay element; and

An exclusive-OR (XOR) gate coupled to receive the synchronization signal and the delayed synchronization signal and to generate the pulse as a result of an XOR operation of the synchronization signal and the delayed synchronization signal.

6. The fractional sample rate converter of claim 4, wherein the FIFO buffer is a synchronous FIFO buffer and operates based on the high frequency clock.

7. The fractional sample rate converter of claim 6, wherein the fractional interpolator is to calculate the current interpolated sample according to the following equation:

wherein the content of the first and second substances,

xhi m represents the current interpolated data sample,

xlo [ k ] and Xlo [ k-1] represent input data samples used to compute the current interpolated sample,

llin represents a ratio of the second rate and the first rate, and

'r' is equal to the expression m- (k-1) × Llin, where m and k are the sample indices of the interpolated samples and the input data samples,

the fractional sample rate converter further comprising a real counter clocked by the high frequency clock, the real counter calculating a value of 'r' to be used by the fractional interpolator to obtain each interpolated data sample including the current interpolated data sample, the real counter forwarding the value of 'r' to the fractional interpolator, the real counter further operating as the read logic,

Wherein the real counter is to:

initializing r to zero upon reset of the fractional sample rate converter;

adding r to 1 at the second rate based on active edges of an intermediate frequency clock having a rate equal to Fhi, wherein the intermediate frequency clock is derived from the high frequency clock Fxo and is synchronized with the high frequency clock Fxo; and is provided with

If the increment value of r is greater than or equal to Llin, then r is set equal to (r-Llin) and the next data sample in the FIFO buffer is transferred to the fractional interpolator.

8. The fractional sample rate converter of claim 6 wherein the fractional interpolator is configured to calculate the current interpolated sample according to the following equation:

wherein the content of the first and second substances,

xhi m represents the current interpolated data sample,

xlo [ k ] and Xlo [ k-1] represent input data samples used to compute the current interpolated sample,

llin represents a ratio of the second rate and the first rate, and

'r' is equal to the expression m- (k-1) × Llin, where m and k are the sample indices of the interpolated samples and the input data samples,

the fractional sample rate converter further comprising a real counter clocked by the high frequency clock, the real counter calculating a value of 'r/Llin', the real counter calculating a value of 'r' to be used by the fractional interpolator to obtain each interpolated data sample including the current interpolated data sample, the real counter forwarding the 'r/Llin' value to the fractional interpolator, the real counter further operating as the read logic,

Wherein the real counter is to:

initializing r/Llin to zero when the fractional sample rate converter is reset;

increasing r/Llin by 1/Llin at the second rate; and is

If the increment value of r/Llin is greater than or equal to 1.0, setting the increment value equal to (r/Llin-1.0) and causing the next data sample in the FIFO buffer to be transferred to the fractional interpolator, wherein the setting indicates that a rollover condition has occurred.

9. The fractional sample rate converter of claim 8, further comprising:

a calculation engine to calculate the value 1/Llin, the calculation engine to provide the value 1/Llin to the real counter.

10. The fractional sample rate converter of claim 9 wherein the compute engine updates the value 1/lllin from time to compensate for frequency drift of the high frequency clock and the low frequency clock, wherein the real counter applies the updated value of 1/lllin when the rollover condition occurs.

11. The fractional sample rate converter of claim 8, wherein when an overflow condition occurs in the FIFO buffer, logic in the FIFO buffer is to: replacing a previous sample in the FIFO buffer with an arithmetic average of a next input data sample and a previous sample received from the write logic.

12. The fractional sample rate converter of claim 11, wherein the fractional interpolator is configured to calculate the next input data sample Xlo [ k-2] upon an underflow condition to calculate the next interpolated sample according to the following equation:

Xlo[k-2]＝(2*Xlo[k])–Xlo[k–1]，

wherein, the first and the second end of the pipe are connected with each other,

xlo [ k ] and Xlo [ k-1] are the last two samples currently available in the fractional interpolator.

13. A phase locked loop, PLL, comprising:

a data selector (MUX) coupled to receive a first clock and a second clock, the MUX to forward the first clock as a selected clock if a select signal has a first value and to forward the second clock as a selected clock if the select signal has a second value;

a phase detector coupled to receive the selected clock and a feedback clock, the phase detector generating an error signal in the form of an error data sample stream, the error signal representing a phase difference between the selected clock and the feedback clock;

a digital filter for generating a stream of filtered error data samples by filtering the error data samples;

an oscillator coupled to receive the filtered error data samples and to generate an output clock, wherein a frequency of the output clock is determined by a size of the filtered error data samples; and

A feedback divider to generate each successive cycle of the feedback clock while counting a predetermined number of cycles of the output clock,

wherein the filtered error data samples have a higher rate than the error data samples, wherein the digital filter comprises a digital low pass filter and a fractional sample rate converter that receives the error data samples as input data samples, the fractional sample rate converter generates interpolated data samples from the input data samples by interpolation and provides the interpolated data samples to the digital low pass filter, the digital low pass filter low pass filters the interpolated data samples and provides filtered interpolated data samples as the filtered error data samples;

wherein the fractional sample rate converter comprises:

a first-in first-out FIFO buffer;

write logic to write the error input data samples to the FIFO buffer at a first rate;

a fractional interpolator coupled to receive the input data samples from the FIFO buffer, the fractional interpolator generating respective interpolated data samples as an output of the fractional sample rate converter at a second rate Fhi; and

Read logic to cause input data samples in the FIFO buffer to be transferred to the fractional interpolator,

wherein a ratio of the second rate and the first rate is a fraction greater than 1.

14. The PLL of claim 13, wherein the write logic writes the input data samples to the FIFO buffer at a first constant frequency constituting the first rate Flo, and

wherein the read logic is to cause the input data samples in the FIFO buffer to be transmitted to the fractional interpolator at a variable frequency that, on average, constitutes the first rate.

15. The PLL of claim 14, wherein the fractional interpolator generates the interpolated data samples from the input data samples using linear interpolation.

16. The PLL of claim 15, wherein the write logic comprises:

a register for receiving each of a plurality of input data samples from a source at the first rate, the register for storing the input data sample at a corresponding active edge of a low frequency clock Flo having a frequency equal to the first rate, wherein a stored input data sample is available at an output of the register for one period of the low frequency clock, the output of the register being coupled to an input data port of the FIFO buffer;

A flip-flop having a divide-by-2 configuration clocked by the low frequency clock, an output of the flip-flop to switch on each active edge of the low frequency clock;

a cross-clock domain synchronizer having an input coupled to the output of the flip-flop, the cross-clock domain synchronizer receiving a high frequency clock Fxo having a frequency equal to Fhi x Lint, where Lint is an integer, and storing the output of the flip-flop at an active edge of the high frequency clock Fxo, the stored output of the flip-flop serving as a synchronization signal at a second output of the cross-clock domain synchronizer; and

an edge detector coupled to receive the synchronization signal, the edge detector to generate pulses from the synchronization signal at a third output of the edge detector at a rate equal to the first rate,

wherein the third output is coupled to a write enable of the FIFO buffer, causing input data samples to be written to the FIFO buffer at the first rate synchronized with the high frequency clock.

17. The PLL of claim 16, wherein the edge detector comprises:

a delay element coupled to the second output, the delay element delaying the synchronization signal by a duration equal to one clock cycle of the high frequency clock and generating a delayed synchronization signal at a fourth output of the delay element; and

An exclusive-OR (XOR) gate coupled to receive the synchronization signal and the delayed synchronization signal and to generate the pulse as a result of an XOR operation of the synchronization signal and the delayed synchronization signal.

18. The PLL of claim 16, wherein the FIFO buffer is a synchronous FIFO buffer and operates based on the high frequency clock.

19. The PLL of claim 18, wherein the fractional interpolator is to calculate a current interpolated sample according to the equation:

wherein, the first and the second end of the pipe are connected with each other,

xhi m represents the current interpolated data sample,

xlo [ k ] and Xlo [ k-1] represent input data samples used to compute the current interpolated sample,

llin represents a ratio of the second rate and the first rate, and

'r' is equal to the expression m- (k-1) × Llin, where m and k are the interpolated samples and the sample indices of the input data samples,

the fractional sample rate converter further comprising a real counter clocked by the high frequency clock, the real counter calculating a value of 'r/Llin', the real counter calculating a value of 'r' to be used by the fractional interpolator to obtain each interpolated data sample including the current interpolated data sample, the real counter forwarding the 'r/Llin' value to the fractional interpolator, the real counter further operating as the read logic,

Wherein the real counter is to:

initializing r/Llin to zero upon reset of the fractional sample rate converter;

increasing r/Llin by 1/Llin at the second rate; and

if the increment value of r/Llin is greater than or equal to 1.0, setting the increment value equal to (r/Llin-1.0) and causing the next data sample in the FIFO buffer to be transferred to the fractional interpolator, wherein the setting indicates that a rollover condition has occurred.

20. The PLL of claim 19, wherein the fractional sample rate converter further comprises a calculation engine to calculate a value 1/Llin, the calculation engine to provide the value 1/Llin to the real counter,

wherein the compute engine updates the value 1/Llin from time to compensate for frequency drift of the high frequency clock and the low frequency clock, wherein the real counter applies the updated value 1/Llin when the rollover condition occurs,

wherein, upon an overflow condition occurring in the FIFO buffer, logic in the FIFO buffer is to: replacing a previous sample in the FIFO buffer with an arithmetic average of a next input data sample received from the write logic and the previous sample, and

Wherein upon an underflow condition, the fractional interpolator is configured to calculate a next input data sample Xlo [ k-2] to calculate a next interpolated sample according to the following equation:

Xlo[k-2]＝(2*Xlo[k])–Xlo[k–1],

wherein, the first and the second end of the pipe are connected with each other,

xlo [ k ] and Xlo [ k-1] are the last two samples currently available in the fractional interpolator.

Images