CN114567295B

CN114567295B - Hybrid phase latch with multiplexer function

Info

Publication number: CN114567295B
Application number: CN202210455773.3A
Authority: CN
Inventors: 范志军; 田文博; 孔维新; 杨作兴; 郭海丰
Original assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Current assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Priority date: 2022-04-28
Filing date: 2022-04-28
Publication date: 2023-01-24
Anticipated expiration: 2042-04-28
Also published as: CN114567295A

Abstract

The present disclosure relates to a hybrid phase latch with multiplexer functionality, comprising: a transmission gate having a data input configured to receive a first data signal and a clock input configured to receive a first clock signal; a tri-state gate having a data input configured to receive a second data signal and a clock input configured to receive a second clock signal; and an inverter having an input coupled to the output of the transmission gate and the output of the tristate gate, the output of the inverter providing the output of the hybrid phase latch, wherein the first clock signal and the second clock signal cause the transmission gate and the tristate gate to conduct at different times.

Description

Hybrid phase latch with multiplexer function

Technical Field

The invention relates to a hybrid phase latch with multiplexer functionality.

Background

The evaluation indexes of a chip are generally Performance, power and Area (PPA). Performance refers to the speed of operation. The power consumption refers to static leakage and power consumption during operation. Area refers to the area of the chip, which represents cost. Many application areas (e.g., mining machines and artificial intelligence) are sensitive to PPA (especially power consumption). Thus, PPA represents the core competitiveness of a chip.

Chip manufacturing has yield problems. Design for Test (DFT) is a technology necessary for large-scale chips. The chips with errors can be screened out or classified by DFT. The DFT inserts various hardware logics for improving the testability (including controllability and observability) of the chip into the original design of the chip, thereby making the chip easy to test and greatly saving the cost of chip testing.

Disclosure of Invention

According to an aspect of the present disclosure, there is provided a hybrid phase latch having a multiplexer function, including: a transmission gate having a data input configured to receive a first data signal and a clock input configured to receive a first clock signal; a tri-state gate having a data input configured to receive a second data signal and a clock input configured to receive a second clock signal; and an inverter having an input coupled to the output of the transmission gate and the output of the tristate gate, the output of the inverter providing the output of the hybrid phase latch, wherein the first clock signal and the second clock signal cause the transmission gate and the tristate gate to conduct at different times.

According to yet another aspect of the present disclosure, there is provided an operational circuit comprising a plurality of the hybrid phase latches of the present disclosure.

According to yet another aspect of the present disclosure, there is provided a computing apparatus comprising: a memory; and a processor comprising the operational circuitry of the present disclosure.

Drawings

A better understanding of the present disclosure may be obtained when the following detailed description of the embodiments is considered in conjunction with the following drawings. The same or similar reference numbers are used throughout the drawings to refer to the same or like parts. The accompanying drawings, which are incorporated in and form a part of the specification, illustrate embodiments of the present invention and, together with the detailed description, serve to explain the principles and advantages of the invention.

FIGS. 1A-1D show block diagrams of original circuits tested by inserting additional hardware circuits between logic blocks of the original circuits.

Fig. 2A shows a schematic diagram of replacing the normal D flip-flop with the scan DFF in the scan replacement step, and fig. 2B shows a schematic diagram of connecting the scan DFFs together to form a scan chain in the scan splicing step.

Fig. 3A and 3B show a logic diagram and truth table, respectively, of an alternative multiplexer (MUX 2).

Fig. 4A and 4B show Complementary Metal-Oxide-Semiconductor (CMOS) circuits of the inverting alternative multiplexer (MUXI 2) and the alternative multiplexer (MUX 2), respectively.

Fig. 5 illustrates a hybrid phase latch 500 with multiplexer functionality according to an embodiment of the disclosure.

Fig. 6A and 6B illustrate

CMOS circuits

600A and 600B implementing the hybrid phase latch 500 of fig. 5, according to an embodiment of the disclosure.

Fig. 7 illustrates a hybrid phase latch 700 with multiplexer functionality according to an embodiment of the disclosure.

Fig. 8A and 8B illustrate

CMOS circuits

800A and 800B implementing the hybrid phase latch 700 of fig. 7, according to an embodiment of the disclosure.

Fig. 9A and 9B illustrate

CMOS circuits

900A and 900B implementing the hybrid phase latch 700 of fig. 7, according to embodiments of the present disclosure.

Fig. 10A and 10B illustrate clock signal generators 1000A and 1000B for generating a first clock signal according to an embodiment of the present disclosure.

Fig. 11A and 11B illustrate

clock signal generators

1100A and 1100B for generating a second clock signal according to an embodiment of the present disclosure.

Fig. 12A and 12B illustrate

clock signal generators

1200A and 1200B for generating a third clock signal according to an embodiment of the present disclosure.

Fig. 13 illustrates a signal timing diagram when the first and second clock signals according to an embodiment of the present disclosure are applied to the CMOS circuit of fig. 6A.

Fig. 14 shows an operational circuit 1400 to which a hybrid phase latch according to an embodiment of the present disclosure may be applied.

Fig. 15 shows an operational circuit 1500 to which a hybrid phase latch according to an embodiment of the present disclosure may be applied.

Detailed Description

The following detailed description of embodiments presents various details of specific embodiments of the invention. However, the invention can be embodied in a multitude of different ways as defined and covered by the claims. In this specification, like reference numbers may indicate identical or functionally similar elements.

FIGS. 1A-1D show block diagrams of original circuits tested by inserting additional hardware circuits between logic blocks of the original circuits. Fig. 1A shows the original circuit. FIG. 1B illustrates the insertion of an observation point between logic block A and logic block B to observe the values passed from logic block A to logic block B. Fig. 1C shows that an or gate is inserted between logic block a and logic block B to control the value passed from logic block a to logic block B, i.e. to force the value to 1. FIG. 1D illustrates that an AND gate is inserted between logic block A and logic block B to control the value passed from logic block A to logic block B, i.e., to force the value to 0.

In a large-scale chip, the main components of a digital circuit are sequential logic cells and combinational logic cells. The test procedure for combinational logic cells is relatively simple, and usually only a single test vector is needed to detect the target error. The testing process of sequential logic cells is complicated. In most cases, there is no way to rely on only one test vector, but rather a sequence of test vectors is required to ultimately detect the target error.

Scan (Scan) technology can transform a difficult-to-test (differential-to-test) sequential circuit into an easy-to-test (easy-to-test) combinational circuit. The scanning technique mainly comprises two steps. The first step is scan replacement, which replaces a normal register (e.g., a D flip-flop (DFF)) in the circuit with a scan register (e.g., a scan DFF). The second step is scan stitching, which connects the scan registers in the first step together to form a scan chain. Fig. 2A shows a schematic diagram of replacing the normal DFF with the scan DFF in the scan replacement step. Fig. 2B shows a schematic diagram of the scan DFFs being connected together to form a scan chain in the scan stitching step.

The scan DFF is composed of an alternative multiplexer (MUX 2) and a DFF. The logical expression of MUX2 is

. sel is a select signal, a0 is a first inputAnd a1 is a second input. Fig. 3A and 3B show a logic diagram and truth table, respectively, of an alternative multiplexer (MUX 2). When the select signal sel is logic 0, the output X is the first input a0. When the select signal sel is logic 1, the output X is the second input a1. Fig. 4A and 4B show Complementary Metal-Oxide-Semiconductor (CMOS) circuits of the inverting alternative multiplexer (MUXI 2) and the alternative multiplexer (MUX 2), respectively. MUXI2 differs from MUX2 in that the output of MUXI2 is the inverse of the input. But as can be seen from fig. 4A and 4B, the implementation of MUXI2 is simpler because MUXI2 saves one inverter compared to MUX 2.

However, whether MUX2 or MUXI2 is used in the scan DFF, more CMOS transistors are added, resulting in increased area, power consumption, and cost of the scan DFF. In addition, in the scan DFF, MUX2 (or MUXI 2) and DFF are two separate units, which also results in a large area occupied by the scan DFF.

In addition, in the chip, the data participating in the operation and storage itself has a bit width, for example, 8 bits, 16 bits, 32 bits, 64 bits, and the like. Therefore, the register has a high occupancy, typically 50% of the chip area. If these registers are replaced by scan DFFs, the chip area, power consumption and cost are large.

The present disclosure provides a hybrid phase latch with multiplexer functionality that can be used as a scan register to replace a normal register in a chip to enable testing of the chip. In the prior art, a scanning DFF is used for replacing a common register in a chip to realize the test of the chip. Compared with scanning DFFs, the hybrid phase latch of the present disclosure occupies a small area, consumes less power, and is low cost. Therefore, utilizing the hybrid phase latch with multiplexer function of the embodiments of the present disclosure in a chip has the advantages of small area, low power consumption and low cost.

Fig. 5 illustrates a hybrid phase latch 500 with multiplexer functionality according to an embodiment of the present disclosure. Hybrid phase latch 500 includes transmission gate 510, tristate gate 520, and inverter 530. The data input of the transmission gate 510 is configured to receive the first data signal D and, when turned on, transmit the first data signal to the input of the inverter 530. The data input of tri-state gate 520 is configured to receive the second data signal SI and, when turned on, transmit an inverted second data signal to the input of inverter 530. The input of inverter 530 is connected to the output of transmission gate 510 and the output of tri-state gate 520. The output of inverter 530 provides the output Q of hybrid phase latch 500.

In addition, the clock input (not shown) of the transmission gate 510 and the clock input (not shown) of the tri-state gate 520 are configured to receive different clock signals such that the transmission gate 510 and the tri-state gate 520 are turned on at different times. Accordingly, the first data signal and the inverted second data signal are transmitted to the input terminal of the inverter 530 at different times. That is, by configuring the clock signal applied to the transmission gate 510 and the tri-state gate 520, it is possible to select whether the first data signal or the inverted second data signal is transmitted to the input of the inverter 530. The output of hybrid phase latch 500 is either the inverted first data signal or the second data signal, since the outputs of transmission gate 510 and tristate gate 520 pass through inverter 530.

Thus, hybrid phase latch 500 has not only a register function but also a multiplexer function. The transmission gate and the tristate gate in the hybrid phase latch are sequential logic cells. It can be seen that hybrid phase latch 500 implements both a register function and a multiplexer function by utilizing sequential logic cells. However, the multiplexers in the existing scan DFF are combinational logic units, and the DFF is a sequential logic unit. That is, existing scan DFFs require separate combinational and sequential logic cells to implement both register and multiplexer functions. Therefore, the hybrid phase latch according to embodiments of the present disclosure has advantages of small area, low power consumption, and low cost compared to conventional scan DFFs.

In some embodiments of the present disclosure, one of the first data signal and the second data signal is a functional data signal and the other of the first data signal and the second data signal is a scan data signal. Therefore, when a circuit needs to be tested, the scan data signal or the inverted scan data signal may be transmitted to the input terminal of the inverter 530 under the control of the clock signal, so that the scan data signal or the inverted scan data signal is output from the output terminal of the inverter 530 for circuit testing.

Fig. 6A and 6B illustrate

CMOS circuits

600A and 600B implementing the hybrid phase latch 500 of fig. 5, according to embodiments of the disclosure. The transmission gate 510 is implemented by a PMOS transistor 511 and an NMOS transistor 512 connected in parallel. The tri-state gate 520 is implemented by

PMOS transistors

521 and 522 and

NMOS transistors

523 and 524 connected in series between a power supply terminal VDD and a ground terminal VSS. The inverter 530 is implemented by a PMOS transistor 531 and an NMOS transistor 532 connected in series between a power supply terminal VDD and a ground terminal VSS. That is, the inverter 530 is implemented as a not gate.

As shown in fig. 6A and 6B, the tri-state gate 520 adopts the following configuration: the gate of PMOS transistor 521 and the gate of NMOS transistor 524 are connected together as the data input of tristate gate 520, the drain of PMOS transistor 522 and the drain of NMOS transistor 523 are connected together as the output of tristate gate 520, and the gate of PMOS transistor 522 and the gate of NMOS transistor 523 are configured to receive clock signals having opposite phases, respectively.

In some embodiments of the present disclosure, the tri-state gate 520 may take another configuration: the gate of PMOS transistor 522 and the gate of NMOS transistor 523 are connected together as the data input of tristate gate 520, the drain of PMOS transistor 522 and the drain of NMOS transistor 523 are connected together as the output of tristate gate 520, and the gate of PMOS transistor 521 and the gate of NMOS transistor 524 are configured to receive clock signals having opposite phases, respectively.

In fig. 6A, the gate of the PMOS transistor 511 and the gate of the NMOS transistor 512 are configured to receive the inverted signal clk1n and the in-phase signal clk1p having opposite phases of the first clock signal, respectively. Since the PMOS transistor 511 is applied with the inverted signal clk1n of the first clock signal and the NMOS transistor 512 is applied with the in-phase signal clk1p of the first clock signal, the transmission gate 510 is turned on and transmits the first data signal D to the input terminal of the inverter 530 when clk1p is high and clk1n is low.

The gate of the PMOS transistor 522 and the gate of the NMOS transistor 523 are configured to receive the inverted signal clk2n and the in-phase signal clk2p having opposite phases of the second clock signal, respectively. Since the PMOS transistor 522 is applied with the inverted signal clk2n of the second clock signal and the NMOS transistor 523 is applied with the in-phase signal clk2p of the second clock signal, the tri-state gate 520 is turned on and transmits the inverted second data signal to the input terminal of the inverter 530 when clk2p is high and clk2n is low.

The in-phase signal clk1p of the first clock signal and the in-phase signal clk2p of the second clock signal are high at different times, and thus the transmission gate 510 and the tri-state gate 520 are turned on at different times. Thus, the first data signal and the inverted second data signal are transmitted to the input terminal of the inverter 530 at different times.

In fig. 6B, the PMOS transistor 511 is applied with the in-phase signal clk1p of the first clock signal, and the NMOS transistor 512 is applied with the inverted signal clk1n of the first clock signal. Thus, the transmission gate 510 will transmit the first data signal D to the input of the inverter 530 when clk1p is low and clk1n is high. The PMOS transistor 522 is applied with the in-phase signal clk2p of the second clock signal, and the NMOS transistor 523 is applied with the inverted signal clk2n of the second clock signal. Thus, the tri-state gate 520 will transmit the inverted second data signal to the input of the inverter 530 when clk2p is low and clk2n is high.

The in-phase signal clk1p of the first clock signal and the in-phase signal clk2p of the second clock signal are low at different times, and thus the transmission gate 510 and the tri-state gate 520 are turned on at different times. Thus, the first data signal and the inverted second data signal are transmitted to the input terminal of the inverter 530 at different times.

In some embodiments of the present disclosure, the in-phase signal clk1p of the first clock signal may be obtained by performing an and operation on the common clock signal and the inverted select signal, and the inverted signal clk1n of the first clock signal may be obtained by performing an not operation on clk1p. An in-phase signal clk2p of the second clock signal is obtained by performing an and operation on the common clock signal and the selection signal, and an inverted signal clk2n of the second clock signal is obtained by performing an not operation on clk2p.

In some embodiments of the present disclosure, the in-phase signal clk1p of the first clock signal may be obtained by performing an and operation on the common clock signal and the selection signal, and the inverted signal clk1n of the first clock signal may be obtained by performing an not operation on clk1p. An in-phase signal clk2p of the second clock signal is obtained by performing an and operation on the common clock signal and the inversion selection signal, and an inversion signal clk2n of the second clock signal is obtained by performing an negation operation on clk2p.

Hybrid phase latch 500 is a dynamic latch that has leakage problems at its output. In order to further solve the problem of electric leakage, the invention also provides a static latch which can effectively relieve the problem of electric leakage of an output end.

Fig. 7 illustrates a hybrid phase latch 700 with multiplexer functionality according to an embodiment of the disclosure. Hybrid phase latch 700 includes transmission gate 510, tristate gate 520, inverter 530, and inverting feedback unit 740. The configuration of transmission gate 510, tri-state gate 520 and inverter 530 of hybrid phase latch 700 has been described with reference to fig. 5. Hybrid phase latch 700 differs from hybrid phase latch 500 in that hybrid phase latch 700 adds an inverting feedback unit 740. The data input of the inverting feedback unit 740 is connected to the output of the inverter 530. An output of the inverting feedback unit 740 is connected to an input of the inverter 530.

A clock input (not shown) of the inverting feedback unit 740 is configured to receive the third clock signal. The third clock signal may be a common clock signal for generating the first clock signal and the second clock signal. The third clock signal causes inverting feedback unit 740 to turn off when one of transmission gate 510 and tri-state gate 520 is turned on. The third clock signal causes inverting feedback unit 740 to turn on when both transmission gate 510 and tri-state gate 520 are off. Accordingly, the inverting feedback unit 740 can invert the charge of the output terminal of the inverter 530 and feed back to the input terminal of the inverter 530. Thus, hybrid phase latch 700, which is a static latch, can effectively alleviate the leakage problem at the output.

The inverting feedback unit 740 may be implemented by a tri-state gate, or by an inverter and a transmission gate connected in series. Fig. 8A and 8B illustrate

CMOS circuits

800A and 800B implementing the hybrid phase latch 700 of fig. 7, according to an embodiment of the disclosure. In fig. 8A and 8B, the inverting feedback unit 740 is implemented by

PMOS transistors

741 and 742 and NMOS transistors 743 and 744 connected in series between a power supply terminal VDD and a ground terminal VSS. That is, the inverting feedback unit 740 is implemented as a tri-state gate. As shown in fig. 8A and 8B, the inverting feedback unit 740 employs the following configuration of tri-state gates: the gate of the PMOS transistor 741 and the gate of the NMOS transistor 744 are connected together as a data input of the inverting feedback unit 740. The drain of PMOS transistor 742 and the drain of NMOS transistor 743 are connected together as the output of inverting feedback unit 740. The gates of the PMOS transistor 742 and the NMOS transistor 743 are respectively configured to receive clock signals having opposite phases.

In some embodiments of the present disclosure, the inverting feedback unit 740 may adopt another configuration of tri-state gates: the gate of the PMOS transistor 742 and the gate of the NMOS transistor 743 are connected together as a data input of the inverting feedback unit 740, the drain of the PMOS transistor 742 and the drain of the NMOS transistor 743 are connected together as an output of the inverting feedback unit 740, and the gate of the PMOS transistor 741 and the gate of the NMOS transistor 744 are respectively configured to receive clock signals having opposite phases.

In fig. 8A, the gate of the PMOS transistor 742 and the gate of the NMOS transistor 743 are configured to receive the in-phase signal clk3p and the inverted signal clk3n having opposite phases of the third clock signal, respectively. Thus, the inverting feedback unit 740 is turned off when clk3p is high and clk3n is low, and is turned on when clk3p is low and clk3n is high.

In fig. 8B, the gate of the PMOS transistor 742 is configured to receive the inverted signal clk3n of the third clock signal, and the gate of the NMOS transistor 743 is configured to receive the in-phase signal clk3p of the third clock signal. Accordingly, the inverting feedback unit 740 is turned on when clk3p is high and clk3n is low, and is turned off when the in-phase signal clk3p of the third clock signal is low and clk3n is high.

Fig. 9A and 9B illustrate

CMOS circuits

900A and 900B implementing the hybrid phase latch 700 of fig. 7, according to an embodiment of the disclosure. In fig. 9A and 9B, the inverting feedback unit 740 is implemented by an inverter 941 and a transmission gate 942 in series. The PMOS transistor 745 and the NMOS transistor 746 connected in series between the power supply terminal VDD and the ground terminal VSS constitute an inverter 941. PMOS transistor 747 and NMOS transistor 748 in parallel form transmission gate 942. The input of inverter 941 is taken as the input of inverting feedback unit 740. The output of transmission gate 942 is provided as the output of inverting feedback unit 740.

In fig. 9A, the gate of the PMOS transistor 747 is configured to receive the in-phase signal clk3p of the third clock signal, and the gate of the NMOS transistor 748 is configured to receive the inverted signal clk3n of the third clock signal. Thus, the inverting feedback unit 740 is turned on when clk3p is low and clk3n is high, and turned off when clk3p is high and clk3n is low.

In fig. 9B, the gate of the PMOS transistor 747 is configured to receive the inverted signal clk3n of the third clock signal, and the gate of the NMOS transistor 748 is configured to receive the in-phase signal clk3p of the third clock signal. Thus, the inverting feedback unit 740 is turned on when clk3p is high and clk3n is low, and turned off when clk3p is low and clk3n is high.

Fig. 10A illustrates a clock signal generator 1000A for generating a first clock signal according to an embodiment of the disclosure. The clock signal generator 1000A includes a nand gate 1010, a not gate 1020, and a not gate 1030 in series. The nand gate 1010 includes

PMOS transistors

1011 and 1012 and

NMOS transistors

1013 and 1014. The not gate 1020 includes a PMOS transistor 1021 and an NMOS transistor 1022. The not gate 1030 includes a PMOS transistor 1031 and an NMOS transistor 1032. The nand gate 1010 is configured to receive a common clock signal clk and an inverted select signal sen, and provide an output to the not gate 1020. The not gate 1020 is configured to output an in-phase signal clk1p of the first clock signal and provide clk1p to the not gate 1030. The not gate 1030 is configured to output an inverted signal clk1n of the first clock signal. Thus, the in-phase signal clk1p = clk & sen of the first clock signal.

Fig. 10A is merely an example of a clock signal generator for generating the first clock signal. In some embodiments of the present disclosure, the output of the nand gate 1010 may also provide the inverted signal clk1n of the first clock signal. However, the number of loads that each not gate can connect is limited. Thus, the ability of the clock signal generator 1000A to drive a load may be enhanced by connecting more not gates after the nand gate 1010. In some embodiments of the present disclosure, two or more not gates may be connected after the nand gate 1010 to form a clock tree. The output of nand gate 1010 serves as the root node of the clock tree. These NOT gates may be connected in an H-tree, fishbone or mesh structure.

Fig. 10B illustrates a clock signal generator 1000B for generating a first clock signal according to an embodiment of the disclosure. In contrast to clock signal generator 1000A, clock signal generator 1000B also includes a clock tree 1040 of two or more not gates. In addition, the clock signal generator 1000B also includes K pairs of NOT gates in series, i.e., (1020-1, 1030-1), …, (1020-K, 1030-K). The K pairs of series-connected NOT gates may output K pairs of signals having opposite phases, i.e., (clk 1p-1, clk1 n-1), …, (clk 1p-K, clk1 n-K). Each pair of signals output by each pair of not gates may be used as a first clock signal. Each pair of signals may be provided to several loads (e.g., a hybrid phase latch of the present disclosure). Therefore, the clock signal generator 1000B can drive more loads than the clock signal generator 1000A.

Fig. 11A illustrates a clock signal generator 1100A for generating a second clock signal according to an embodiment of the disclosure. The clock signal generator 1100A includes a nand gate 1110, a not gate 1120, and a not gate 1130 connected in series. Nand gate 1110 includes

PMOS transistors

1111 and 1112 and

NMOS transistors

1113 and 1114. The not gate 1120 includes a PMOS transistor 1121 and an NMOS transistor 1122. The not gate 1130 includes a PMOS transistor 1131 and an NMOS transistor 1132. The nand gate 1110 is configured to receive a common clock signal clk and a selection signal se, and provide an output to the not gate 1120. The not gate 1120 is configured to output an in-phase signal clk2p of the second clock signal and provide clk2p to the not gate 1130. The not gate 1130 is configured to output an inverted signal clk2n of the second clock signal. Thus, the in-phase signal clk2p = clk & se of the second clock signal.

Fig. 11A is merely an example of a clock signal generator for generating the second clock signal. In some embodiments of the present disclosure, the output of the nand gate 1110 may also provide the inverted signal clk2n of the first clock signal. However, the number of loads that each not gate can connect is limited. Thus, the ability of the clock signal generator 1100A to drive a load can be enhanced by connecting more not gates after the nand gate 1110. In some embodiments of the present disclosure, two or more not gates may be connected after the nand gate 1110 to form a clock tree. The output of nand gate 1110 serves as the root node of the clock tree. These NOT gates may be connected as H-trees, fishbones or a net.

Fig. 11B illustrates a clock signal generator 1100B for generating a second clock signal according to an embodiment of the disclosure. In contrast to the clock signal generator 1100A, the clock signal generator 1100B further includes a clock tree 1140 made up of two or more not gates. In addition, the clock signal generator 1100B also includes L pairs of NOT gates in series, i.e., (1120-1, 1030-1), …, (1120-L, 1130-L). The L pairs of series-connected NOT gates may output L pairs of signals having opposite phases, i.e., (clk 2p-1, clk2 n-1), …, (clk 2p-L, clk2 n-L). Each pair of signals output by each pair of not gates may be used as a second clock signal. Each pair of signals may be provided to several loads (e.g., a hybrid phase latch of the present disclosure). Therefore, the clock signal generator 1100B can drive more loads than the clock signal generator 1100A.

The selection signal se is configured to select whether the first data signal D or the second data signal SI is transmitted to the input of the inverter 530. The inverted select signal sen is an inverted signal of the select signal se. The inverted select signal sen may be obtained by applying the select signal se to the inverter.

Fig. 12A illustrates a clock signal generator 1200A for generating a third clock signal according to an embodiment of the disclosure. The clock signal generator 1200A includes a not gate 1210 and a not gate 1220 connected in series. The not gate 1210 includes a PMOS transistor 1211 and an NMOS transistor 1212. The not gate 1220 includes a PMOS transistor 1221 and an NMOS transistor 1222. The not gate 1210 is configured to receive the common clock signal clk and output an inverted signal clk3n of the third clock signal, and provide clk3n to the not gate 1220. The not gate 1220 is configured to output an in-phase signal clk3p of the third clock signal. However, the number of loads that each not gate can connect is limited. Thus, the ability of the clock signal generator 1200A to drive a load may be enhanced by more not gates.

Fig. 12B illustrates a clock signal generator 1200B for generating a third clock signal according to an embodiment of the disclosure. In contrast to clock signal generator 1200A, clock signal generator 1200B also includes a clock tree 1230 of two or more not gates. Clock tree 1230 may be an H-tree, fishbone, or mesh structure. In addition, clock signal generator 1200B also includes J pairs of NOT gates in series, i.e., (1210-1, 1220-1), …, (1210-J, 1220-J). The J pairs of series-connected NOT gates may output J pairs of signals having opposite phases, i.e., (clk 3p-1, clk3 n-1), …, (clk 3p-J, clk3 n-J). Each pair of signals output by each pair of not gates may be used as a third clock signal. Each pair of signals may be provided to several loads (e.g., a hybrid phase latch of the present disclosure). Therefore, the clock signal generator 1200B can drive more loads than the clock signal generator 1200A.

Fig. 13 illustrates a signal timing diagram when the first and second clock signals according to an embodiment of the present disclosure are applied to the CMOS circuit of fig. 6A. The transmission gate 510 latches the first data signal D when clk1p is low and clk1n is high, and outputs the first data signal D when clk1p is high and clk1n is low. The tri-state gate 520 latches the second data signal SI when clk2p is low and clk2n is high, and outputs an inverted second data signal when clk2p is high and clk2n is low. Thus, the transmission gate 510 and the tri-state gate 520 both act as a latch unit. Further, since the se signal is merged into the first clock signal and the second clock signal, the first clock signal and the second clock signal can be used both as clock signals to latch data and as selection signals to select whether to output the first data signal from the transmission gate 510 or the inverted second data signal from the tri-state gate 520. In addition, since only one of the in-phase signal clk1p of the first clock signal and the in-phase signal clk2p of the second clock signal is high at any time, only one of the first data signal and the inverted second data signal is supplied to the input terminal of the inverter 530 by the transmission gate 510 and the tri-state gate 520 at any time. Thus, hybrid phase latch 500 outputs only one of the inverted first data signal and the second data signal at any one time.

Fig. 14 shows an operational circuit 1400 to which a hybrid phase latch according to an embodiment of the present disclosure may be applied. The arithmetic circuit 1400 includes a register group 1410 that stores input data a [15 ] 0, a register group 1420 that stores input data B [15 ]. Each of the register sets 1410, 1420, and 1440 may include a plurality of mixed phase latches according to embodiments of the present disclosure.

Fig. 15 shows an operational circuit 1500 to which a hybrid phase latch according to an embodiment of the present disclosure may be applied. The operational circuit 1500 includes an inverter 1501 configured to receive the selection signal se and output an inverted selection signal sen. The arithmetic circuit 1500 further includes

clock signal generators

1511, 1512, and 1513. The clock signal generator 1511 may be the clock signal generator 1000A in fig. 10A or the clock signal generator 1000B in fig. 10B. The clock signal generator 1511 is configured to receive the inverted select signal sen and the common clock signal clka, and output a first clock signal clk1. The clock signal generator 1512 may be the clock signal generator 1100A in fig. 11A or the clock signal generator 1100B in fig. 11B. The clock signal generator 1512 is configured to receive the selection signal se and the common clock signal clka, and output a second clock signal clk2. The clock signal generator 1513 may be the clock signal generator 1200A in fig. 12A or the clock signal generator 1200B in fig. 12B. The clock signal generator 1513 is configured to receive the common clock signal clka and output a third clock signal clk3. The operational circuit 1500 also includes a plurality of hybrid phase latches 1521-1, 1521-2 … 1521-n. Since the inverter 1501 and

clock signal generators

1511 and 1512 are shared by multiple hybrid phase latches 1521-1, 1521-2 … 1521-n, the cost increase incurred by the inverter 1501 and

clock signal generators

1511 and 1512 is negligible.

In some embodiments of the present disclosure, the operational circuitry 1500 may also include

clock signal generators

1514, 1515, and 1516 and a plurality of hybrid phase latches 1522-1, 1522-2 … 1522-m. The clock signal generator 1514 may be the clock signal generator 1000A in fig. 10A or the clock signal generator 1000B in fig. 10B. The clock signal generator 1514 is configured to receive the inverted select signal sen and the common clock signal clkb, and output a fourth clock signal clk4. The clock signal generator 1515 may be the clock signal generator 1100A in fig. 11A or the clock signal generator 1100B in fig. 11B. The clock signal generator 1515 is configured to receive the selection signal se and the common clock signal clkb, and output a fifth clock signal clk5. The clock signal generator 1516 may be the clock signal generator 1200A in fig. 12A or the clock signal generator 1200B in fig. 12B. The clock signal generator 1516 is configured to receive the common clock signal clkb and output a sixth clock signal. The fourth clock signal clk4, the fifth clock signal clk5, and the sixth clock signal clk6 may be provided to a plurality of hybrid phase latches 1522-1, 1522-2 … 1522-m.

In practical applications, a plurality of hybrid phase latches 1521-1, 1521-2 … 1521-n may be included on a first processing chip and a plurality of hybrid phase latches 1522-1, 1522-2 … 1522-m may be included on a second processing chip. The processing chip may be a processing chip such as a CPU and a GPU.

Some embodiments of the disclosure may be implemented as a hybrid phase latch with multiplexer functionality, comprising: a transmission gate having a data input configured to receive a first data signal and a clock input configured to receive a first clock signal; a tri-state gate having a data input configured to receive a second data signal and a clock input configured to receive a second clock signal; and an inverter having an input coupled to the output of the transmission gate and the output of the tristate gate, the output of the inverter providing the output of the hybrid phase latch, wherein the first clock signal and the second clock signal cause the transmission gate and the tristate gate to conduct at different times.

In some embodiments of the present disclosure, the first clock signal includes an in-phase signal and an inverted signal having opposite phases, and the second clock signal includes an in-phase signal and an inverted signal having opposite phases.

In some embodiments of the present disclosure, the in-phase signal of the first clock signal is obtained by performing an and operation on the common clock signal and one of the selection signal and the inverted selection signal, the inverted signal of the first clock signal is obtained by performing a non-operation on the in-phase signal of the first clock signal, the in-phase signal of the second clock signal is obtained by performing an and operation on the common clock signal and the other of the selection signal and the inverted selection signal, and the inverted signal of the second clock signal is obtained by performing a non-operation on the in-phase signal of the second clock signal.

In some embodiments of the present disclosure, the hybrid phase latch further comprises an inverting feedback unit, a data input of the inverting feedback unit being connected to the output of the inverter, an output of the inverting feedback unit being connected to the input of the inverter, a clock input of the inverting feedback unit being configured to receive a third clock signal, wherein the third clock signal is such that the inverting feedback unit is turned off when one of the transmission gate and the tristate gate is turned on, and the inverting feedback unit is turned on when both the transmission gate and the tristate gate are turned off.

In some embodiments of the present disclosure, the inverting feedback unit is one of: a second tri-state gate; a second inverter and a second transmission gate connected in series.

In some embodiments of the present disclosure, the third clock signal includes an in-phase signal and an anti-phase signal having opposite phases.

In some embodiments of the present disclosure, the in-phase signal of the third clock signal is the common clock signal, and the inverted signal of the third clock signal is obtained by negating the common clock signal.

In some embodiments of the present disclosure, one of the first data signal and the second data signal is a functional data signal and the other of the first data signal and the second data signal is a scan data signal.

Some embodiments of the disclosure may be implemented as an operational circuit comprising a plurality of the hybrid phase latches of the disclosure.

In some embodiments of the disclosure, the arithmetic circuitry further comprises: a third inverter having an input configured to receive a select signal and output an inverted select signal; a first clock signal generator configured to receive the common clock signal and the inverted selection signal output from the third inverter and output a first clock signal; a second clock signal generator configured to receive the common clock signal and the selection signal and output a second clock signal.

In some embodiments of the disclosure, the arithmetic circuitry further comprises: a third inverter having an input configured to receive a select signal and output an inverted select signal; a first clock signal generator configured to receive the common clock signal and one of the selection signal and an inverted selection signal output from the third inverter and output a first clock signal; and a second clock signal generator configured to receive the common clock signal and the other of the selection signal and the inverted selection signal output from the third inverter and output a second clock signal.

In some embodiments of the disclosure, the arithmetic circuitry further comprises: a third clock signal generator configured to receive the common clock signal and output a third clock signal.

Some embodiments of the disclosure may be implemented as a computing device comprising: a memory; and a processor comprising the operational circuitry of the present disclosure.

The hybrid phase latch of the present disclosure has been described above in connection with specific embodiments. However, it is to be understood that any feature of any one embodiment may be combined with and/or substituted for any other feature of any other embodiment.

Aspects of the present disclosure may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronics, components of consumer electronics, electronic test equipment, cellular communication infrastructure such as base stations, and the like. Examples of electronic devices may include, but are not limited to, mobile phones such as smart phones, wearable computing devices such as smart watches or headsets, telephones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, personal Digital Assistants (PDAs), microwave ovens, refrigerators, in-vehicle electronic systems such as automotive electronic systems, stereos, DVD players, CD players, digital music players such as MP3 players, radios, camcorders, cameras such as digital cameras, portable memory chips, washing machines, dryers, washer/dryers, peripherals, clocks, and the like. Further, the electronic device may include an incomplete product.

Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", "have", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense. That is, it means "including but not limited to". As generally used herein, the term "coupled" refers to two or more elements that may be connected directly or through one or more intermediate elements. Likewise, the term "connected," as used generally herein, refers to two or more elements that may be connected directly or through one or more intermediate elements. Additionally, as used in this application, the words "herein," "above," "below," "hereinafter," "above," and words of similar import shall refer to this application as a whole and not to any particular portions of this application.

Furthermore, conditional language, e.g., "may," e.g., "such as" and the like, as used herein are generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements, and/or states, unless expressly stated otherwise or otherwise understood in the context of such usage. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments or are included or performed in any particular embodiment.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the present disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the blocks are presented in a given arrangement, alternative embodiments may perform similar functions with different components and/or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. The various features and processes described above may be implemented independently of one another or may be combined in various ways. All suitable combinations and subcombinations of the features of the disclosure are intended to be within the scope of the disclosure.

Claims

1. A hybrid phase latch with multiplexer functionality, wherein the hybrid phase latch is configured to function as a scan register for an arithmetic circuit, the hybrid phase latch comprising:

a transmission gate having a data input configured to receive a first data signal and a clock input configured to receive a first clock signal;

a tri-state gate having a data input configured to receive a second data signal and a clock input configured to receive a second clock signal, wherein one of the first and second data signals is a functional data signal and the other of the first and second data signals is a scan data signal; and

an inverter having an input coupled to the output of the transmission gate and the output of the tristate gate, an output of the inverter providing the output of the hybrid phase latch,

wherein the first and second clock signals cause the transmission gate and the tri-state gate to be turned on at different times, and the scan register is configured to output a scan data signal or an inverted scan data signal when the arithmetic circuit is tested.

2. The hybrid phase latch of claim 1, wherein the first clock signal comprises an in-phase signal and an inverted signal having opposite phases, and the second clock signal comprises an in-phase signal and an inverted signal having opposite phases.

3. The hybrid phase latch of claim 2,

the in-phase signal of the first clock signal is obtained by AND-operating the common clock signal and one of the selection signal and the inverted selection signal, the inverted signal of the first clock signal is obtained by not-operating the in-phase signal of the first clock signal,

the in-phase signal of the second clock signal is obtained by performing an and operation on the common clock signal and the other of the selection signal and the inverted selection signal, and the inverted signal of the second clock signal is obtained by performing a non-operation on the in-phase signal of the second clock signal.

4. The hybrid phase latch of claim 1, further comprising an inverting feedback unit having a data input coupled to an output of the inverter, an output of the inverting feedback unit coupled to an input of the inverter, a clock input of the inverting feedback unit configured to receive a third clock signal,

the third clock signal enables the inverting feedback unit to be turned off when one of the transmission gate and the tristate gate is turned on, and enables the inverting feedback unit to be turned on when the transmission gate and the tristate gate are turned off.

5. The hybrid phase latch of claim 4, wherein the inverting feedback unit is one of:

a second tri-state gate;

a second inverter and a second transmission gate connected in series.

6. The hybrid phase latch of claim 4, wherein the third clock signal comprises an in-phase signal and an inverted signal having opposite phases.

7. The hybrid phase latch of claim 4, wherein the in-phase signal of the third clock signal is the common clock signal and the inverted signal of the third clock signal is obtained by negating the common clock signal.

8. An arithmetic circuit comprising a plurality of hybrid phase latches as claimed in any one of claims 1 to 3.

9. The arithmetic circuit of claim 8, further comprising:

a third inverter having an input configured to receive a select signal and output an inverted select signal;

a first clock signal generator configured to receive the common clock signal and one of the selection signal and an inverted selection signal output from the third inverter and output a first clock signal; and

a second clock signal generator configured to receive the common clock signal and the other of the selection signal and the inverted selection signal output by the third inverter and output a second clock signal.

10. An arithmetic circuit comprising a plurality of hybrid phase latches as claimed in any one of claims 4 to 7.

11. The arithmetic circuit of claim 10, further comprising:

a first clock signal generator configured to receive the common clock signal and one of the selection signal and an inverted selection signal output from the third inverter and output a first clock signal;

a second clock signal generator configured to receive the common clock signal and the other of the selection signal and the inverted selection signal output from the third inverter and output a second clock signal; and

a third clock signal generator configured to receive the common clock signal and output a third clock signal.

12. A computing device, comprising:

a memory; and

a processor comprising an arithmetic circuit comprising a plurality of hybrid phase latches as claimed in any one of claims 1 to 7.