CN114566127A

CN114566127A - Pixel circuit, driving method thereof and display panel

Info

Publication number: CN114566127A
Application number: CN202210208442.XA
Authority: CN
Inventors: 黄锐啸; 张娣
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2022-03-04
Filing date: 2022-03-04
Publication date: 2022-05-31

Abstract

The invention discloses a pixel circuit, a driving method thereof and a display panel, belonging to the technical field of display, wherein the pixel circuit at least comprises a driving transistor, a data writing module, a first reset module, a reset control module and a light-emitting device; before the light-emitting device emits light, the data writing module provides a data voltage signal for the driving transistor at least twice, the first reset module provides a first reset signal for the driving transistor at least twice when the reset control module is switched on, and the process of providing the data voltage signal for the driving transistor once by the data writing module and the process of providing the first reset signal for the driving transistor once by the first reset module are alternately carried out. The driving method of the pixel circuit is applied to the pixel circuit for driving. The display panel comprises the pixel circuit. The invention can avoid the difference between the brightness of the first frame and the brightness of other frames, and effectively improve the phenomenon of smear.

Description

Pixel circuit, driving method thereof and display panel

Technical Field

The invention relates to the technical field of display, in particular to a pixel circuit, a driving method thereof and a display panel.

Background

Organic Light Emitting Displays (OLEDs) are one of the hot spots in the current field of flat panel display research. Compared with Liquid Crystal displays, OLEDs have the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle, fast response speed, and the like, and at present, in the flat panel Display field of mobile phones, PDAs, digital cameras, and the like, OLEDs have begun to replace traditional Liquid Crystal Displays (LCDs). The design of the driving circuit is a key technology for realizing the display function. The driving circuit can generally include a scan driving circuit, a light emitting control circuit, a data driving circuit, a pixel circuit, etc., wherein the pixel circuit design is the core technology content of the OLED display, and has important research significance.

In the related OLED display process, when two different pictures are displayed, due to the difference in picture brightness, in the picture switching process, for example, when a black-and-white picture is switched, the picture brightness may have a process of slowly changing, that is, the brightness in the initial time period cannot reach the target brightness, resulting in a low first frame brightness, and the brightness change process is long in time and easily perceived by human eyes, thereby causing the problem of image smearing, and making the picture display effect poor.

Therefore, it is an urgent need to provide a pixel circuit, a driving method thereof, and a display panel that can avoid the difference between the first frame luminance and the other frame luminance, effectively improve the smear phenomenon, and thereby improve the display quality.

Disclosure of Invention

In view of the above, the present invention provides a pixel circuit, a driving method thereof, and a display panel, so as to solve the problem that the brightness of a first frame is low easily when a black-and-white picture is switched in the related art, which causes a smear on the picture and a poor picture display effect.

The invention provides a pixel circuit, at least comprising: the device comprises a driving transistor, a data writing module, a first reset module, a reset control module and a light-emitting device; the first end of the data writing module is connected with a data voltage signal, the second end of the data writing module is connected with the first pole of the driving transistor, and the data writing module is used for providing the data voltage signal for the driving transistor; the first end of the first reset module is connected with a first reset signal, the second end of the first reset module is connected with the first end of the reset control module, the second end of the reset control module is connected with the grid electrode of the driving transistor, and the first reset module provides the first reset signal for the driving transistor when the reset control module is conducted; before the light-emitting device emits light, the data writing module provides a data voltage signal to the driving transistor at least twice, the first reset module provides a first reset signal to the driving transistor at least twice when the reset control module is switched on, and a process of providing the data voltage signal to the driving transistor once by the data writing module and a process of providing the first reset signal to the driving transistor once by the first reset module are alternately performed.

Based on the same inventive concept, the invention also discloses a driving method of the pixel circuit, which is applied to the pixel circuit for driving; the driving method includes: in a driving period, at least two reset phases, at least two data writing phases and a light-emitting phase are included; in a reset phase, the first reset module provides a first reset signal to the driving transistor when the reset control module is conducted; in a data writing stage, the data writing module provides a data voltage signal for the driving transistor; in the light emitting stage, the light emitting device emits light in response to the driving current; wherein, the reset phase and the data writing phase are executed before the light-emitting phase; the data writing phase and the reset phase are alternately performed.

Based on the same inventive concept, the invention also discloses a display panel which comprises the pixel circuit.

Compared with the related art, the pixel circuit, the driving method thereof and the display panel provided by the invention at least realize the following beneficial effects:

before the light-emitting stage of the pixel circuit provided by the invention, the processes of providing the first reset signal for the grid electrode of the driving transistor by the first reset module and providing the data voltage signal for the driving transistor by the data writing module are repeatedly and alternately carried out when the reset control module is switched on, so that the grid electrode of the driving transistor can be repeatedly reset and charged. When the first reset module provides the first reset signal to the driving transistor when the reset control module 30 is turned on, the data write module provides the first data voltage signal to the driving transistor, that is, after the first reset and charge are completed to the gate of the driving transistor, the voltage of the gate of the driving transistor has been written to the data voltage signal in the white state, and at this time, the potential of the first node is much lower than the high potential in the initial black state, then when the first reset module provides the second first reset signal to the driving transistor when the reset control module is turned on, and after the data write module provides the second data voltage signal to the driving transistor, that is, after the second reset and charge are completed to the gate of the driving transistor, the potential of the first node after the first reset and charge is not the high potential in the original initial black state, but is pulled down correspondingly after the first reset and charge, therefore, the difference between the first node and the second node is smaller on the basis of the low potential, even if the potential of the first node is pulled up due to the capacitive coupling between the two nodes of the first node and the second node, the coupling effect is weakened, and the pulled-up amplitude of the potential of the first node is smaller, so that in the second resetting and charging process, even if the potential of the first node is pulled up again due to the capacitive coupling effect, the potential of the first node is not pulled up too high, and after the first node is reset and charged for the second time, the potential of the first node is closer to the ideal low potential required by a white state, so that the brightness of a first frame can be better improved, the problem that the brightness of the first frame is lower during the switching of a black-white picture is avoided, the difference between the brightness of the first frame and the brightness of other subsequent frames is weakened, and the smear phenomenon is effectively improved, the display quality of a display panel applying the pixel circuit is improved.

Of course, it is not necessary for any product in which the present invention is practiced to be specifically designed to achieve all of the above-described technical effects simultaneously.

Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

fig. 2 is a graph of luminance per frame with time upon switching of a black-and-white picture by a pixel circuit provided in the related art;

FIG. 3 is a graph showing the change of the luminance of each frame with time when the black and white frames are switched by the pixel circuit according to the embodiment of the present invention;

FIG. 4 is a schematic diagram of another structure of a pixel circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of another structure of a pixel circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of another structure of a pixel circuit according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of another structure of a pixel circuit according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of another structure of a pixel circuit according to an embodiment of the present invention;

FIG. 9 is a timing diagram of the operation of the pixel circuit of FIG. 8;

FIG. 10 is a timing diagram of the first reset signal and the second reset signal of FIG. 8;

FIG. 11 is another timing diagram for operation of the pixel circuit of FIG. 8;

FIG. 12 is another timing diagram for operation of the pixel circuit of FIG. 8;

FIG. 13 is another timing diagram for operation of the pixel circuit of FIG. 8;

fig. 14 is a contrast diagram of the luminance of the first frame in which the pixel circuit provided in the present embodiment performs a plurality of times of resetting and a plurality of times of data writing before the light-emitting phase;

fig. 15 is a schematic plan view of a display panel according to an embodiment of the present invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be discussed further in subsequent figures.

The display panel in the related art generally includes a plurality of sub-pixels, and the sub-pixels may include pixel circuits that supply driving currents to light emitting devices, such as light emitting diodes, in the sub-pixels to cause the light emitting devices to emit light to display a picture. In the actual display process, when the image is switched, for example, when the black and white image is switched, the brightness of the first frame is low, which is mainly influenced by two reasons, namely parasitic capacitance coupling in the circuit and the hysteresis effect of the thin film transistor. In the film structure design of the display panel, even if nodes in a pixel circuit are not overlapped, parasitic capacitance (space capacitance) is easily formed due to the fact that the space distance is short, and therefore the potentials of the nodes are easily influenced with each other, wherein the potential of the grid electrode node of the driving transistor has a large influence on the brightness of a first frame, once other nodes which are close to the node and form the space parasitic capacitance with the node appear, the grid electrode potential of the driving transistor is easily influenced, and therefore the display effect is influenced. The pixel circuit generally comprises a plurality of thin film transistors such as driving transistors, and due to the hysteresis effect of the thin film transistors, when a sub-pixel displays a plurality of frames of black pictures, the driving transistors are in a cut-off state for a long time, at the moment, because the gate potential of the driving transistors is higher than an ideal state, the driving transistors are under positive bias for a long time, the threshold voltage drifts, when a white picture is to be switched, because the threshold voltage of the driving transistors cannot be recovered in time, namely, the display brightness of the first frame of white picture is lower due to the hysteresis effect of the driving transistors, the brightness of an initial time period after the picture is switched cannot reach the target brightness, and the smear phenomenon easily occurs, so that the display effect is poor, and the visual experience of a user is influenced.

Based on the above problems, the present application provides a pixel circuit, a driving method thereof, and a display panel, which can avoid the difference between the first frame luminance and the other frame luminance, effectively improve the smear phenomenon, and improve the display quality. Specific embodiments of the pixel circuit, the driving method thereof, and the display panel according to the present application are described in detail below.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, and a pixel circuit 00 according to the embodiment at least includes: a driving transistor DT, a data writing module 10, a first reset module 20, a reset control module 30, and a light emitting device E;

a first end of the data writing module 10 is connected to a data voltage signal Vdata, a second end of the data writing module 10 is connected to a first pole of the driving transistor DT, and the data writing module 10 is configured to provide the data voltage signal Vdata to the driving transistor DT;

the first terminal of the first reset module 20 is connected to the first reset signal Vref1, the second terminal of the first reset module 20 is connected to the first terminal of the reset control module 30, the second terminal of the reset control module 30 is connected to the gate of the driving transistor DT, and the first reset module 20 provides the first reset signal Vref1 to the driving transistor DT when the reset control module 30 is turned on; before the light emitting device E emits light, the data writing module 10 supplies the data voltage signal Vdata to the driving transistor DT at least twice, the first reset module 20 supplies the first reset signal Vref1 to the driving transistor DT at least twice when the reset control module 30 is turned on, and the process of supplying the data voltage signal Vdata to the driving transistor DT once by the data writing module 10 and the process of supplying the first reset signal Vref1 to the driving transistor DT once by the first reset module 20 are alternately performed.

Specifically, the pixel circuit 00 provided in this embodiment may be disposed in an organic light emitting diode display panel, and is used to provide a driving circuit for the sub-pixels of the display panel, so that each sub-pixel emits light for display. The pixel circuit 00 at least comprises a driving transistor DT, a data writing module 10, a first reset module 20, a reset control module 30 and a light emitting device E, wherein the light emitting device E may be an organic light emitting diode, and the pixel circuit 00 is configured to transmit a driving signal to the pixel circuit 00 under the action of signals provided by various driving signal lines on the display panel, so that a light emitting driving current provided by the driving transistor DT in a light emitting phase is transmitted to the light emitting device E to provide the driving current for the light emitting device E, and the light emitting device E emits light in response to the light emitting driving current. The first end of the data writing module 10 is connected to a data voltage signal Vdata, and optionally, the first end of the data writing module 10 may be connected to a data line (not shown) in the display panel, and the data voltage signal Vdata is provided to the first end of the data writing module 10 through the data line. The second terminal of the data writing module 10 is connected to the first electrode of the driving transistor DT (which may be the source electrode of the driving transistor DT), and the data writing module 10 is configured to provide the data voltage signal Vdata to the first electrode of the driving transistor DT in a conducting state thereof. The first terminal of the first reset module 20 is connected to the first reset signal Vref1, and optionally, the first terminal of the first reset module 20 may be connected to a first reset signal line (not shown) in the display panel, and the first reset signal line is used to provide the first reset signal Vref1 to the first terminal of the first reset module 20. The second terminal of the first reset module 20 is connected to the first terminal of the reset control module 30, the second terminal of the reset control module 30 is connected to the gate of the driving transistor DT, that is, the reset control module 30 is located between the first reset module 20 and the gate of the driving transistor DT, the reset control module 30 is configured to control whether the first reset module 20 and the gate of the driving transistor DT are turned on or off before the light emitting device E emits light, when the reset control module 30 is turned on, the first reset signal Vref1 received by the first terminal of the first reset module 20 may be transmitted to the gate of the driving transistor DT, and when the reset control module 30 is not turned on, the gate of the driving transistor DT and the first reset module 20 are in an off state.

Optionally, the gate of the driving transistor DT in this embodiment may be understood as the first node N1, and the first pole of the driving transistor DT may be understood as the second node N2, when the pixel circuit 00 of this embodiment is designed in a film structure of a display panel, because each sub-pixel has a smaller area, a spatial distance between the first node N1 and the second node N2 in the pixel circuit 00 corresponding to the same sub-pixel is also smaller, and a spatial parasitic capacitance is often easily generated between the two nodes. When the potential of the second node N2 changes, the potential of the first node N1 also changes due to coupling, which affects the gate potential of the driving transistor DT, and the on-state performance of the driving transistor DT is affected.

The present embodiment provides a process in which the data writing module 10 supplies the data voltage signal Vdata to the driving transistor DT at least twice before the light emitting device E emits light, the first reset module 20 supplies the first reset signal Vref1 to the driving transistor DT at least twice when the reset control module 30 is turned on, the data writing module 10 supplies the data voltage signal Vdata to the driving transistor DT once, in conjunction with the first reset module 20 providing the first reset signal Vref1 to the driving transistor DT once, the two are alternated, that is, before the pixel circuit 00 proceeds to the light emitting phase, the process of the first reset module 20 providing the gate (the first node N1) of the driving transistor DT with the first reset signal Vref1 and the data writing module 10 providing the driving transistor DT with the data voltage signal Vdata when the reset control module 30 is turned on are repeatedly alternated, so that the first node N1 (the gate of the driving transistor DT) can be repeatedly reset and charged.

In the related art, when the pixel circuit 00 needs to control the black frame to be switched to the white frame, the gate (the first node N1) of the driving transistor DT starts to be a black state voltage (a control voltage when the light emitting device E does not emit light), and the black state voltage is a high voltage, which is a low voltage required for not immediately changing to the white state even through one reset process performed by the first reset module 20 due to parasitic capacitance coupling between nodes and the hysteresis effect of the driving transistor itself, and is still higher than the low voltage required for the white state. For example, in the first frame after the black-and-white conversion, the light emitting device E connected to the pixel circuit 00 starts to light from the initial black state, at this time, the first node N1 is at a high potential, after the first reset module 20 completes one reset of the gate (the first node N1) of the driving transistor DT, the first reset signal Vref is written into the first node N1, the first node N1 is written from the high potential to the low potential, and due to the capacitive coupling effect of the first node N1 and the second node N2, the potential of the second node N2 is also pulled low; then, the data writing module 10 writes the data voltage signal Vdata into the second node N2, at this time, the second node N2 is pulled up from an originally relatively low potential to be written into the data voltage signal Vdata, due to the capacitive coupling between the first node N1 and the second node N2, the potential of the first node N1 is also pulled up, and the potential of the first node N1 pulled up at this time is not the ideal low potential required by the white state, and is higher than the ideal low potential required by the white state, so that the brightness of the first frame is lower when the black-and-white image is switched. As shown in fig. 2, fig. 2 is a graph of luminance change of each frame with time when a black-and-white picture is switched in a pixel circuit provided in the related art, wherein an abscissa is time, an ordinate is a luminance percentage (compared to a percentage of a maximum luminance value of a light emitting device), each large step represents one frame, luminance detection of the light emitting device in the pixel circuit illustrated in fig. 2 is performed in a case where a first reset module provides a first reset signal to a driving transistor only once before the light emitting device emits light, and a data write module provides a data voltage signal to the driving transistor only once, as can be seen from fig. 2, an average luminance of the light emitting device in a first frame is only about 40%, and an average luminance of other frames is substantially about 100%, that is, if the first reset module is adopted to provide the first reset signal to the driving transistor only once in the related art, the data writing module only provides a data voltage signal once for the driving transistor, and when the black and white picture is switched, the difference value between the first frame brightness and the other frame brightness is about 60%, the brightness difference is large, and the smear phenomenon is serious.

Therefore, in order to solve the above problem, before the driving operation of the pixel circuit 00 is performed to the light emitting phase, the first reset module 20 repeatedly and alternately provides the first reset signal Vref1 to the gate of the driving transistor DT (the first node N1) and the data voltage signal Vdata to the driving transistor DT by the data writing module 10 when the reset control module 30 is turned on, so that the first node N1 (the gate of the driving transistor DT) can be repeatedly reset and charged. When the first reset module 20 of this embodiment provides the first reset signal Vref1 to the driving transistor DT for the first time when the reset control module 30 is turned on, the data write module 10 provides the first data voltage signal Vdata to the driving transistor DT, that is, after the first reset and charging to the gate (the first node N1) of the driving transistor DT, the voltage of the gate (the first node N1) of the driving transistor DT is already written to the data voltage signal Vdata of the white state, at which time the potential of the first node N1 is much less than the high potential at the initial black state, then when the first reset module 20 of this embodiment provides the second first reset signal Vref1 to the driving transistor DT when the reset control module 30 is turned on, after the data write module 10 provides the second data voltage signal Vdata to the driving transistor DT, that is, after the second reset and charging to the gate (the first node N1) of the driving transistor DT, the potential of the first node N1 is not the high potential of the original black state after the first reset and charge, but is pulled down correspondingly after the first reset and charge, so that the difference between the potential of the first node N1 and the second node N2 is smaller based on the low potential, even if the capacitive coupling exists between the two nodes of the first node N1 and the second node N2 and the potential of the first node N1 is pulled up, the coupling effect is weakened, the amplitude of the pulled up potential of the first node N1 is smaller, that is, the amplitude of the jump of the potential of the first node N1 is reduced, therefore, even if the potential of the first node N1 is pulled up again due to the capacitive coupling effect during the second reset and charge process, the potential of the first node N1 is not pulled up too much, and then after the second reset and charge of the first node N1, the potential of the first node N1 is closer to the ideal low potential required by the white state, therefore, the brightness of the first frame can be better improved, the problem that the brightness of the first frame (the brightness of the initial time period after the picture is switched) is low when the black and white picture is switched is avoided, the difference between the brightness of the first frame and the brightness of other subsequent frames is weakened, the phenomenon of smear is effectively improved, and the display quality of the display panel applying the pixel circuit of the embodiment is improved.

As shown in fig. 3, fig. 3 is a graph of luminance change of each frame with time when a black and white frame is switched in a pixel circuit provided in an embodiment of the present invention, where an abscissa is time, an ordinate is luminance percentage (percentage compared to a maximum luminance value of a light emitting device), each large step represents one frame, luminance detection of the light emitting device in the pixel circuit illustrated in fig. 3 is performed in a case where a first reset module provides a first reset signal to a driving transistor at least two times before the light emitting device emits light, a data write module provides a data voltage signal to the driving transistor at least two times, as can be seen from fig. 3, an average luminance of the light emitting device in a first frame is increased to about 70%, and an average luminance of other frames is substantially about 100%, as can be seen by comparing fig. 3 with fig. 2, a pixel circuit 00 of this embodiment uses the first reset module to provide the first reset signal to the driving transistor at least two times, the data writing module provides data voltage signals for the driving transistor at least twice, when black and white pictures are switched, the difference value between the first frame brightness and other frame brightness can be reduced to about 30%, the difference between the first frame brightness and other subsequent frame brightness is weakened, and the smear phenomenon is effectively improved.

It should be noted that, in the drawings of the present embodiment, only the driving transistor DT is exemplified as a P-type transistor, optionally, the driving transistor DT may be a P-type low temperature polysilicon transistor, and characteristics of high mobility and high driving speed of the low temperature polysilicon transistor may be utilized, so that when the data writing module 10 writes the data voltage signal Vdata, the response speed of the driving transistor DT is fast, the data voltage signal Vdata may be written fast, and a phenomenon of insufficient charge caused by a long on-time of the driving transistor DT is avoided. In some other optional embodiments, the driving transistor DT may also be an N-type transistor, and when the driving transistor DT is selected as a P-type transistor, the P-type transistor is turned on when the gate of the P-type transistor is at a low voltage level, that is, when the driving transistor DT is selected as an N-type transistor, the N-type transistor is turned on when the gate of the N-type transistor is at a high voltage level, that is, the transistor is turned on.

It should be understood that this embodiment is only an example of a module structure that the pixel circuit 00 may include, and in implementation, the connection structure between the pixel circuit 00 and the light emitting device E includes, but is not limited to, this, and other connection structures may also be included, and specific reference may be made to the connection structure of the pixel circuit in the organic light emitting display panel in the related art for understanding, and this embodiment is not limited herein. It can be understood that, in fig. 1 of this embodiment, the data writing module 10, the first resetting module 20, and the resetting control module 30 are all illustrated in block diagrams, but do not show actual structures thereof, in a specific implementation, the connection structures of the data writing module 10, the first resetting module 20, and the resetting control module 30 themselves may include structures of electrical connections of transistors, and the conduction of the transistors in each module is controlled by an enable signal of a gate of the transistor to implement the connection between the module and the driving transistor DT.

In some optional embodiments, with reference to fig. 1, in the present embodiment, the data writing module 10 provides the driving transistor DT with the same value of the data voltage signal Vdata at least twice, and the first resetting module 20 provides the driving transistor DT with the same value of the first resetting signal Vref at least twice.

The present embodiment explains that before the driving operation of the pixel circuit 00 is set to proceed to the light-emitting phase, the first reset module 20 repeatedly alternates the processes of supplying the first reset signal Vref1 to the gate of the driving transistor DT (the first node N1) when the reset control module 30 is turned on and supplying the data voltage signal Vdata to the driving transistor DT by the data writing module 10, that is, repeatedly resetting and charging the first node N1 (the gate of the driving transistor DT), before the light-emitting device E emits light, the first reset module 20 supplies the first reset signal Vref1 to the gate of the driving transistor DT (the first node N1) at least twice when the reset control module 30 is turned on, and as before the light-emitting device E emits light, when the first reset module 20 supplies the first reset signal Vref1 to the gate of the driving transistor DT (the first node N1) two times when the reset control module 30 is turned on, the values of the twice first reset signal Vref input to the first node N1 at the first reset time and the second reset time are the same, so that the same degree of resetting the potential of the first node N1 (the gate of the driving transistor DT) can be ensured; before the light-emitting device E emits light, the data writing module 10 provides the driving transistor DT with the same value of the data voltage signal Vdata at least twice, for example, before the light-emitting device E emits light, when the data writing module 10 provides the driving transistor DT with the data voltage signal Vdata twice, the values of the data voltage signal Vdata input to the driving transistor DT during the first charging and the second charging are the same, so that the same degree of the data voltage written into the first node N1 (the gate of the driving transistor DT) can be ensured, the accurate light-emitting brightness of the light-emitting device E can be maintained as much as possible, and the false light emission of the light-emitting device E and the influence on the light-emitting effect caused by signal disorder due to multiple resetting and multiple data writing can be avoided.

Optionally, as shown in fig. 1, in the pixel circuit 00 of this embodiment, the first pole of the driving transistor DT is connected to the first power supply signal Vpvdd, and is used for providing the first power supply signal Vpvdd to the pixel circuit 00; the second pole of the driving transistor DT is connected to the anode of the light emitting device E, and the cathode of the light emitting device E is connected to the second power supply signal Vpvee for supplying the second power supply signal Vpvee to the pixel circuit 00; wherein the value of the first power supply signal Vpvdd is greater than the value of the second power supply signal Vpvee.

This embodiment explains that the pixel circuit 00 can be further connected with a power signal, and the power signal is used to provide power for the pixel circuit so that the pixel circuit 00 can perform its driving operation; the first electrode of the driving transistor DT is connected to the first power signal Vpvdd, optionally, other structures of the pixel circuit 00 may be further included between the first electrode of the driving transistor DT and the first power signal Vpvdd, for example, other transistors may be further included between the first electrode of the driving transistor DT and the first power signal Vpvdd, and the connection between the first electrode of the driving transistor DT and the first power signal Vpvdd is realized through conduction of the transistors, the connection in this embodiment may refer to direct electrical connection or indirect electrical connection, the first power signal Vpvdd may be used as a positive power signal of the pixel circuit 00, further, the optional first electrode of the driving transistor DT may be indirectly connected to a first power signal line (not shown in the figure) in the display panel, and the first power signal line provides the first power signal Vpvdd for the first electrode of the driving transistor DT. The second electrode of the driving transistor DT is connected to the anode of the light emitting device E, optionally, other structures of the pixel circuit 00 may be further included between the second electrode of the driving transistor DT and the anode of the light emitting device E, for example, other transistors may be further included between the second electrode of the driving transistor DT and the anode of the light emitting device E, and the connection between the second electrode of the driving transistor DT and the anode of the light emitting device E is implemented by turning on the transistors, and the connection in this embodiment may refer to direct electrical connection or indirect electrical connection. The cathode of the light emitting device E is connected to the second power signal Vpvee, which can be used as a negative power signal of the pixel circuit 00, the cathode of the further optional light emitting device E can be indirectly connected to a second power signal line (not shown in the figure) in the display panel, the second power signal Vpvee is provided to the cathode of the light emitting device E through the second power signal line, the value of the first power signal Vpvdd is set to be greater than that of the second power signal Vpvee, so that a current path is formed between the driving transistor DT and the light emitting device E in the light emitting stage of the pixel circuit 00, and the driving current generated by the pixel circuit flows from the anode to the cathode of the light emitting device E to drive the light emitting device E to emit light.

In some alternative embodiments, please refer to fig. 1 and fig. 4 in combination, fig. 4 is another structural schematic diagram of the pixel circuit according to the embodiment of the present invention, in which in the present embodiment, the first reset module 20 is turned on under the control of the first enable signal S1N, and the first enable signal S1N is a high-level signal. Optionally, the first reset module 20 includes an N-type oxide transistor.

This embodiment explains that the driving transistor DT in the pixel circuit 00 can be a P-type low temperature polysilicon transistor, so that the characteristics of high mobility and high driving speed of the low temperature polysilicon transistor can be utilized, so that when the data writing module 10 writes the data voltage signal Vdata, the response speed of the driving transistor DT is fast, the data voltage signal Vdata can be written quickly, and the phenomenon of insufficient charging caused by long on time of the driving transistor DT is avoided, at the same time, the first reset module 20 can be set to be turned on under the control of the first enabling signal S1N, the first enabling signal S1N is a high level signal, when the first reset module 20 includes a transistor, optionally, the first reset module 20 includes an N-type oxide transistor, such as an N-type IGZO (indium gallium zinc oxide) transistor, the gate of the N-type oxide transistor is the first enabling signal S1N, when the first enable signal S1N is a high-level signal, the source and drain of the N-type oxide transistor are turned on to turn on the first reset block 20, that is, when the gate of the N-type oxide transistor is the first enable signal S1N of the high-level signal, the first reset signal Vref is transmitted from the first end of the first reset block 20 to the second end of the first reset block 20, that is, to the first end of the reset control block 30. Because the IGZO transistor has lower mobility and smaller leakage current than the low-temperature polysilicon transistor, the N-type IGZO transistor is disposed in the first reset module 20 in this embodiment, so that when the first reset module 20 is electrically connected to the gate of the driving transistor DT, the charge leakage of the gate of the driving transistor DT during low-frequency driving can be prevented, and the leakage current problem during low-frequency driving can be effectively solved, so that the pixel circuit 00 is suitable for low-frequency driving, and the power consumption of a display panel using the pixel circuit 00 can be reduced.

Optionally, if the data writing module 10 in other modules in this embodiment includes a transistor, the transistor of the module may still be designed as a low temperature polysilicon transistor, so that the pixel circuit can maintain strong driving capability by using the low temperature polysilicon transistor, and only the portion (e.g., the portion connected to the gate of the driving transistor DT) of the pixel circuit 00 that is easy to leak current needs to be an IGZO transistor. The pixel circuit 00 of this embodiment combines two thin film transistors, i.e., low temperature polysilicon and indium gallium zinc oxide, so that a display panel using the pixel circuit 00 has the characteristics of strong driving capability and low power consumption, and is suitable for high frequency display and low frequency display.

In some optional embodiments, please refer to fig. 5, fig. 5 is another structural schematic diagram of the pixel circuit provided in the embodiment of the present invention, in this embodiment, the pixel circuit 00 further includes a first light emitting control module 40, a second light emitting control module 50, and a compensation module 60;

a first terminal of the first lighting control module 40 is connected to the first power signal Vpvdd, and a second terminal of the first lighting control module 40 is connected to the first pole (the second node N2) of the driving transistor DT;

a first end of the second light emission control module 50 is connected to the second electrode of the driving transistor DT, and a second end of the second light emission control module 50 is connected to the anode of the light emitting device E;

a first terminal of the compensation module 60 is connected to the gate electrode (first node N1) of the driving transistor DT, and a second terminal of the compensation module 60 is connected to the second pole of the driving transistor DT.

This embodiment explains that the pixel circuit 00 further includes a first light emission control module 40, a second light emission control module 50, and a compensation module 60; the first light emitting control module 40 is connected in series between the first power signal Vpvdd and the first pole of the driving transistor DT, the second light emitting control module 50 is connected in series between the anode of the light emitting device E and the second pole of the driving transistor DT, and the first light emitting control module 40 and the second light emitting control module 50 are configured to provide a light emitting control signal to the light emitting device E during a light emitting phase of the light emitting device E. Optionally, the first light emitting control module 40 and the second light emitting control module 50 of this embodiment may further respectively include a first light emitting control signal EM1 and a second light emitting control signal EM2, and the first light emitting control signal EM1 and the second light emitting control signal EM2 are used to respectively control whether the light emitting control modules are turned on or off. Specifically, the first terminal of the first light-emitting control module 40 may be connected to a first power signal Vpvdd, and when the first light-emitting control signal EM1 is an active signal to control the first light-emitting control module 40 to be turned on, the first power signal Vpvdd is transmitted to the first electrode of the driving transistor DT, and further optionally, the first light-emitting control signal EM1 may be connected to a first light-emitting control signal line (not shown) in the display panel, and the second light-emitting control signal EM2 may be connected to a second light-emitting control signal line (not shown) in the display panel. The first terminal of the second light-emitting control module 50 is connected to the second pole of the driving transistor DT, the second terminal of the second light-emitting control module 50 is connected to the anode of the light-emitting device E, and when the second light-emitting control signal EM2 is an active signal to control the second light-emitting control module 50 to be turned on, the driving current generated by the driving transistor DT can drive the light-emitting device E to emit light.

In this embodiment, through the control of the first emission control signal EM1 and the second emission control signal EM2, the first emission control module 40 and the second emission control module 50 can be turned on in the emission phase of the light emitting device E to provide a current path for the light emitting device E, so that the light emitting device E emits light, and the first emission control module 40 and the second emission control module 50 are controlled to be turned off in other phases (such as a reset phase or a data writing phase) to prevent the light emitting device E from emitting light by mistake in the non-emission phase. Alternatively, as shown in fig. 5, the first emission control signal EM1 and the second emission control signal EM2 may be connected together to provide the emission control signals of the two emission control modules through the same emission control signal line, that is, the first emission control module 40 and the second emission control module 50 may receive the same emission control signal EM, and the first emission control signal EM1 for turning on the first emission control module 40 and the second emission control signal EM2 for turning on the second emission control module 50 may be shared, which is beneficial to reducing the number of signal lines in a display panel using the pixel circuit 00, improving the transmittance of the display panel, or increasing the wiring space of the display panel.

The first terminal of the compensation module 60 of this embodiment is connected to the gate electrode (the first node N1) of the driving transistor DT, the second terminal of the compensation module 60 is connected to the second pole of the driving transistor DT, the compensation module 60 is configured to compensate the threshold voltage of the driving transistor DT, the compensation module 60 can short-circuit the gate electrode and the second pole of the driving transistor DT in the on state, a voltage difference is generated between the gate electrode and the first pole of the driving transistor DT by the threshold voltage of the driving transistor DT, at this time, the driving transistor DT is turned on, and the data writing module 10 inputs a data voltage signal Vdata to the second node N2, wherein the data voltage signal Vdata includes the threshold voltage to be compensated and is transmitted to the gate electrode of the driving transistor DT, so as to compensate the threshold voltage deviation of the driving transistor DT.

It can be understood that, in fig. 5 of this embodiment, the first light-emitting control module 40, the second light-emitting control module 50, and the compensation module 60 are illustrated in block diagrams, but actual structures of the first light-emitting control module 40, the second light-emitting control module 50, and the compensation module 60 are not shown, in a specific implementation, a connection structure of the first light-emitting control module 40, the second light-emitting control module 50, and the compensation module 60 itself may include a structure of electrical connection of transistors, and the connection structure of the transistors in each module is controlled by an enable signal of a transistor gate to implement whether the module is connected with the driving transistor DT.

Optionally, as shown in fig. 6, fig. 6 is another structural schematic diagram of the pixel circuit provided in the embodiment of the present invention, in the pixel circuit 00 of this embodiment, the first light-emitting control module 40 includes a first transistor M1, a gate of the first transistor M1 is connected to the first light-emitting control signal EM1, a first pole of the first transistor M1 is connected to the first power signal Vpvdd, and a second pole of the first transistor M1 is connected to a first pole (a second node N2) of the driving transistor DT;

the second light emission control module 50 includes a second transistor M2, a gate of the second transistor M2 is connected to the second light emission control signal EM2, a first pole of the second transistor M2 is connected to the second pole of the driving transistor DT, and a second pole of the second transistor M2 is connected to the anode of the light emitting device E;

the first reset module 20 includes a third transistor M3, a gate of the third transistor M3 is connected to a first scan signal S1N (a first enable signal), and a first pole of the third transistor M3 is connected to a first reset signal Vref 1;

the compensation module 60 includes a fourth transistor M4, a gate of the fourth transistor M4 is connected to the second scan signal S2N, a first pole of the fourth transistor M4 is connected to the gate of the driving transistor DT (the first node N1), and a second pole of the fourth transistor M4 is connected to the second pole of the driving transistor DT;

the reset control module 30 includes a fifth transistor M5, a gate of the fifth transistor M5 is connected to the first control signal S1P, a first pole of the fifth transistor M5 is connected to the second pole of the third transistor M3, and a second pole of the fifth transistor M5 is connected to the gate of the driving transistor DT (the first node N1);

the data writing module 10 includes a sixth transistor M6, a gate of the sixth transistor M6 is connected to the second control signal S2P, a first pole of the sixth transistor M6 is connected to the data voltage signal Vdata, and a second pole of the sixth transistor M6 is connected to the first pole of the driving transistor DT (the second node N2).

The present embodiment explains an electrical connection structure of each block of the pixel circuit 00, in which the first light emission control module 40 includes a first transistor M1, the second light emission control module 50 includes a second transistor M2, the first reset module 20 includes a third transistor M3, the compensation module 60 includes a fourth transistor M4, the reset control module 30 includes a fifth transistor M5, the data write module 10 includes a sixth transistor M6, optionally, the third transistor M3 and the fourth transistor M4 may be N-type oxide transistors, the driving transistor DT, the first transistor M1, the second transistor M2, the fifth transistor M5, and the sixth transistor M6 may be P-type low temperature polysilicon transistors, that is, when the first transistor M1 is turned on when the first light emission control signal EM1 is low level, the second transistor M2 is turned on when the second light emission control signal EM2 is low level, the first transistor M3 is turned on when the first scan signal S1N (the first enable signal) is high level, the fourth transistor M4 is turned on when the second scan signal S2N is at a high level, the fifth transistor M5 is turned on when the first control signal S1P is at a low level, and the sixth transistor M6 is turned on when the second control signal S2P is at a low level. Since the oxide transistor has lower mobility and smaller leakage current than the low temperature polysilicon transistor, the third transistor M3 and the fourth transistor M4 electrically connected to the gate of the driving transistor DT are configured as N-type IGZO transistors in this embodiment, which can prevent the charge leakage of the gate of the driving transistor DT during low frequency driving, and effectively solve the problem of leakage current during low frequency driving, so that the pixel circuit 00 is suitable for implementing low frequency driving, and the transistors of other modules of the pixel circuit 00 can still be low temperature polysilicon transistors, so that the pixel circuit 00 can still maintain strong driving capability under low frequency driving by using the low temperature polysilicon transistors, which is beneficial to reducing the power consumption of the display panel using the pixel circuit 00.

It is because in the pixel circuit 00 of this embodiment, the third transistor M3 of the first reset module 20 and the fourth transistor M4 of the compensation module 60 are both N-type transistors in oxide transistors, and different from other P-type transistors, the third transistor M3 and the fourth transistor M4 are both turned on at high level, and because the fifth transistor M5 of the reset control module 30 and the third transistor M3 of the first reset module 20 are different in type, the P-type transistor is turned on at low level, and the N-type transistor is turned on at high level, so the control signals of the gates of the two transistors are different, that is, the third transistor M3 and the fifth transistor M5 need to be controlled separately, the first scan signal S1N and the first control signal S1P need to be independent from each other, if the gate of the third transistor M3 is also connected to the first control signal S1P, the fifth transistor M5 is turned off when the third transistor M3 is turned on, and the communication between the first reset module DT 20 and the driving transistor is not good, the first reset signal Vref1 cannot be transmitted to the gate of the driving transistor DT for resetting. Therefore, the third transistor M3 in this embodiment is turned on when the first scan signal S1N is at a high level, and the fifth transistor M5 is turned on when the first control signal S1P is at a low level, which are controlled independently of each other.

Optionally, as shown in fig. 7, fig. 7 is another schematic structural diagram of the pixel circuit provided in the embodiment of the present invention, where the pixel circuit 00 of the embodiment further includes a second reset module 70, a first end of the second reset module 70 is connected to the second reset signal Vref2, a second end of the second reset module 70 is connected to the anode of the light emitting device E, and the second reset module 70 is configured to reset the anode of the light emitting device E before the light emitting device E emits light, further optionally, the second reset module 70 includes a seventh transistor M7, a gate of the seventh transistor M7 is connected to the first control signal S1P, a first pole of the seventh transistor M6 is connected to the second reset signal Vref2, and a second pole of the seventh transistor M7 is connected to the anode of the light emitting device E.

The embodiment explains that the second reset module 70 including the seventh transistor M7 is connected to the anode of the light emitting device E, and the second reset module 70 is configured to reset the anode of the light emitting device E when the seventh transistor M7 is turned on, so that the anode of the light emitting device E is initialized, thereby improving the residual of the previous frame data signal, improving the image sticking phenomenon, and improving the display effect when the pixel circuit 00 is applied to a display panel. Optionally, the seventh transistor M7 may be a P-type low-temperature polysilicon transistor, so that the pixel circuit 00 may still maintain a strong driving capability under low-frequency driving, in this embodiment, resetting the anode of the light emitting device E by the seventh transistor M7 may keep the potential of the anode of the light emitting device E stable, alleviate the change of the emission luminance of the light emitting device E caused by the influence of leakage current, and particularly alleviate the problem of poor display effect under the condition of a low refresh frequency.

It is understood that the fifth transistor M5 of the reset control module 30 in this embodiment is used to connect the third transistor M3 and the driving transistor DT of the first reset module 20 when they are turned on, if the reset control module 30 is not provided in the pixel circuit 00, only the first transistor M1, the second transistor M2, the sixth transistor M6, the seventh transistor M7, the driving transistor DT, the third transistor M3 and the fourth transistor M4 of indium gallium zinc oxide are included, while the gate of the third transistor M3 and the gate of the seventh transistor M7 are controlled by the same first control signal S1P, during the light emitting phase of the light emitting device E, the seventh transistor M7 needs to be kept in the off state, i.e. the first control signal S1P needs to be kept in the high level state, and at this time, if the gates of the third transistor M3 and the fifth transistor M5 are controlled by the first control signal S1P, the third transistor M3 of the N type will be always kept in the high level, therefore, if the fifth transistor M5 of the reset control module 30 is not provided in the pixel circuit combining the low temperature polysilicon transistor and the ingaga-zn transistor, the N-type third transistor M3 cannot be turned off during the light emitting period of the light emitting device E, the first reset signal Vref1 will always reset the first node N1, and the pixel circuit 00 cannot proceed to the period of writing the data voltage signal Vdata through the data writing module 10. Therefore, in the present embodiment, the fifth transistor M5 of the reset control module 30 is disposed in the pixel circuit combining the low temperature polysilicon transistor and the ingaga-zn transistor, and whether the fifth transistor M5 is turned on or off can be controlled by the first control signal S1P, even if the N-type third transistor M3 is turned on all the time under the control of the first scan signal S1N of the high level signal, the fifth transistor M5 can be turned off and on by the first control signal S1P, when the first node N1 needs to be reset, the first control signal S1P is a low level signal, the first reset signal Vref1 resets the first node N1, when the data writing is needed, the first control signal S1P is a high level signal, even if the first reset signal Vref1 is still transmitted to the first pole of the fifth transistor M5, but at this time, the fifth transistor M5 controlled by the first control signal S1P of the high level signal is in a turned off state, therefore, the first reset signal Vref1 is not transmitted to the first node N1, and the data writing can be performed normally.

Optionally, as shown in fig. 8, fig. 8 is another schematic structural diagram of the pixel circuit provided in the embodiment of the present invention, and the pixel circuit 00 of the embodiment further includes a storage capacitor Cst, a first pole of the storage capacitor Cst is connected to the gate electrode (the first node N1) of the driving transistor DT, and a second pole of the storage capacitor Cst is connected to the first power signal Vpvdd. The first pole of the storage capacitor Cst is connected to the gate of the driving transistor DT through the first node N1, and the second pole of the storage capacitor Cst is connected to the first power signal Vpvdd, so as to store the data voltage signal Vdata after the data voltage signal Vdata is transmitted to the first node N1, which is beneficial to maintaining the stability of the whole circuit.

Alternatively, as shown in fig. 8 and fig. 9, fig. 9 is an operation timing diagram of the pixel circuit in fig. 8, and the pixel circuit 00 of this embodiment may at least include a first reset phase t1, a first data writing phase t2, a second reset phase t3, a second reset writing phase t4, and a light emitting phase t5 during operation; it can be understood that the driving method of the present embodiment is such that the data writing module 10 supplies the data voltage signal Vdata to the driving transistor DT twice before the light emitting period, the first reset module 20 supplies the first reset signal Vref1 to the driving transistor DT twice when the reset control module 30 is turned on, the data writing module 10 supplies the data voltage signal Vdata once to the driving transistor DT, the process of the first reset module 20 providing the first reset signal Vref1 to the driving transistor DT once is alternatively exemplified, and in the implementation, the number of times that the data writing module 10 supplies the data voltage signal Vdata to the driving transistor DT before the light emitting period is not limited to two, and the number of times that the first reset module 20 supplies the first reset signal Vref1 to the driving transistor DT when the reset control module 30 is turned on is not limited to two, and the embodiment is not limited thereto.

In the first reset phase t1, the first scan signal S1N is a high level signal, the second scan signal S2N is a high level signal, the first control signal S1P is a low level signal, the second control signal S2P is a high level signal, the first emission control signal EM1 and the second emission control signal EM2 are high level signals, the third transistor M3 is turned on, the fourth transistor M4 is turned on, the fifth transistor M5 is turned on, the seventh transistor M7 is turned on, the sixth transistor M6 is turned off, the first transistor M1 is turned off, the second transistor M2 is turned off, the first reset signal Vref1 is transmitted to the gate of the driving transistor DT (the first node N1) for the first time, and the first node N1 is pulled low; since the seventh transistor M7 is turned on, the anode of the light emitting device E receives the second reset signal Vref2 to be reset.

In the first data writing phase t2, the first scan signal S1N is a high level signal, the second scan signal S2N is a high level signal, the first control signal S1P is a high level signal, the second control signal S2P is a low level signal, the first emission control signal EM1 and the second emission control signal EM2 are high level signals, the third transistor M3 is turned on, the fourth transistor M4 is turned on, the fifth transistor M5 is turned off, the seventh transistor M7 is turned off, the sixth transistor M6 is turned on, the first transistor M1 is turned off, the second transistor M2 is turned off, since the potential of the first node N1 is low at this time, the gate and the second pole of the driving transistor DT are shorted after the fourth transistor M4 is turned on, and a voltage difference is generated between the gate (the first node N1) and the first pole (the second node N2) of the driving transistor DT by the threshold voltage of the driving transistor DT, the sixth transistor M6 is turned on to input a data voltage signal Vdata, which contains a compensated threshold voltage, to the second node N2 for the first time and is input to the gate electrode of the driving transistor DT, thereby compensating for a threshold voltage deviation of the driving transistor DT. The written data voltage signal Vdata charges the first node N1 through the driving transistor DT until the voltage of the first node N1 becomes Vdata-Vth and the driving transistor DT is turned off.

In the second reset period t3, the first scan signal S1N is a high level signal, the second scan signal S2N is a high level signal, the first control signal S1P is a low level signal, the second control signal S2P is a high level signal, the first emission control signal EM1 and the second emission control signal EM2 are high level signals, the third transistor M3 is turned on, the fourth transistor M4 is turned on, the fifth transistor M5 is turned on, the seventh transistor M7 is turned on, the sixth transistor M6 is turned off, the first transistor M1 is turned off, the second transistor M2 is turned off, and at this time, the voltage of the gate (the first node N1) of the driving transistor DT is written to the data voltage signal Vdata in the white state, so that the potential of the first node N5739 is much smaller than the high potential at the initial black state, then in the second reset period t 695t 2, the first reset signal Vref 56 is transferred to the gate (the first node N828653) of the driving transistor DT, and the first reset period N867 is written to the gate (the first node N8653) of the first reset period N867, and the data voltage of the first reset period N867 is written to the data voltage of the first reset period N1 After the first reset phase t1, the high voltage level of the black state at the beginning of the first reset phase t1 is not originally high, but is correspondingly pulled down after the reset of the first reset phase t1 and the charge of the first data writing phase t2, so that the difference between the voltage level of the first node N1 and the voltage level of the second node N2 is smaller on the basis of the low voltage level, even if the voltage level of the first node N1 is pulled up due to the capacitive coupling between the two nodes of the first node N1 and the second node N2, the coupling effect is weakened, the amplitude of the pulled-up voltage level of the first node N1 is smaller, that is, the transition amplitude of the voltage level of the first node N1 is reduced.

In the second data writing phase t4, the first scan signal S1N is a high level signal, the second scan signal S2N is a high level signal, the first control signal S1P is a high level signal, the second control signal S2P is a low level signal, the first emission control signal EM1 and the second emission control signal EM2 are high level signals, the third transistor M3 is turned on, the fourth transistor M4 is turned on, the fifth transistor M5 is turned off, the seventh transistor M7 is turned off, the sixth transistor M6 is turned on, the first transistor M1 is turned off, the second transistor M2 is turned off, since the potential of the first node N1 is low at this time, the gate and the second pole of the driving transistor DT are shorted after the fourth transistor M4 is turned on, and a voltage difference is generated between the gate (the first node N1) and the first pole (the second node N2) of the driving transistor DT by the threshold voltage of the driving transistor DT, the sixth transistor M6 is turned on to input the data voltage signal Vdata, which includes the compensated threshold voltage, to the second node N2 for the second time, and is input to the gate electrode of the driving transistor DT, thereby compensating for the threshold voltage deviation of the driving transistor DT. The written data voltage signal Vdata charges the first node N1 through the driving transistor DT until the voltage of the first node N1 becomes Vdata-Vth and the driving transistor DT is turned off. After the second data writing phase t4 is finished, that is, after the gate (the first node N1) of the driving transistor DT is reset and charged for the second time, even if the potential of the first node N1 is pulled up again due to the capacitive coupling effect, the potential of the first node N1 is not pulled up too high, and then after the first node N1 is reset and charged for the second time, the potential of the first node N1 is closer to the ideal low potential required for the white state.

After at least the first reset phase t1, the first data writing phase t2, the second reset phase t3, and the second reset writing phase t4 are performed alternately, so that the potential of the first node N1 is closer to the desired low potential required by the white state, the display panel can enter the light-emitting phase t5, and since the potential of the first node N1 is closer to the desired low potential required by the white state instead of the high potential at the beginning of the black state, the display panel enters the light-emitting phase t5 at this time, the brightness of the first frame can be better improved, the problem that the brightness of the first frame (the brightness of the initial period after the frame is switched) is lower when the black and white frame is switched is avoided, which is beneficial to weakening the difference between the brightness of the first frame and the brightness of other subsequent frames, effectively improving the smear phenomenon, and improving the display quality of the display panel using the pixel circuit of the embodiment.

In the light emitting period t5, the first scan signal S1N is a low level signal, the second scan signal S2N is a low level signal, the first control signal S1P is a high level signal, the second control signal S2P is a high level signal, the first emission control signal EM1 and the second emission control signal EM2 are low level signals, the third transistor M3 is turned off, the fourth transistor M4 is turned off, the fifth transistor M5 is turned off, the seventh transistor M7 is turned off, the sixth transistor M6 is turned off, the first transistor M1 is turned on, the second transistor M2 is turned on, and a current path between the first power signal Vpvdd and the second power signal Vpvee is turned on, that is, a current flowing from the first power signal Vpvdd to the driving transistor DT and a current flowing from the driving transistor DT to an anode of the light emitting device E are turned on, and the light emitting device E operates to emit light under the action of the driving current flowing therethrough.

In the pixel circuit 00 provided by this embodiment, the third transistor M3 and the fourth transistor M4 are oxide transistors, and in the light-emitting period t5, by using the characteristic of low leakage current of the oxide transistors, the fourth transistor M4 can keep the potential between the first node N1 and the second pole of the driving transistor DT stable, and the third transistor M3 can keep the potential of the first node N1 stable, so as to alleviate the change of the light-emitting brightness of the light-emitting device E caused by the influence of the leakage current, and in particular, alleviate the problem of poor display effect under the condition of low refresh frequency. Meanwhile, by using the characteristics of high mobility and high driving speed of the low-temperature polysilicon transistors, in the first data writing phase t2 and the second data writing phase t4, the response speed of the sixth transistor M6 and the driving transistor DT is high, so that the data voltage signal Vdata can be quickly written, and insufficient charging caused by long on time is avoided, and in the light emitting phase t5, the response speed of the first transistor M1 and the second transistor M2 is high, so that the driving current can quickly flow into the light emitting device E, and the display image delay caused by too slow on is avoided. The pixel circuit 00 of this embodiment adopts the mutual combination of the low-temperature polysilicon transistor and the oxide transistor, and makes full use of the characteristics of the low-temperature polysilicon transistor, such as high mobility, fast driving speed, and low leakage current of the oxide transistor, so that the display of the display panel manufactured by using the pixel circuit is more stable, and the power consumption is lower.

In some alternative embodiments, please refer to fig. 8, 9 and 10 in combination, where fig. 10 is a timing diagram of the first reset signal and the second reset signal in fig. 8, the pixel circuit 00 of this embodiment includes a first reset module 20 and a second reset module 70, the first reset module 20 includes a third transistor M3, a gate of the third transistor M3 is connected to the first scan signal S1N, and a first pole of the third transistor M3 is connected to the first reset signal Vref 1; the second reset module 70 includes a seventh transistor M7, a gate of the seventh transistor M7 is connected to the first control signal S1P, a first pole of the seventh transistor M6 is connected to the second reset signal Vref2, a second pole of the seventh transistor M7 is connected to an anode of the light emitting device E, and the value of the first reset signal Vref1 is different from the value of the second reset signal Vref 2.

The present embodiment explains that not only the first reset module 20 but also the second reset module 70 may be included in the pixel circuit 00, the first reset module 20 is configured to provide the first reset signal Vref1 for the pixel circuit 00, and the first reset module 20 resets the gate of the driving transistor DT by the received first reset signal Vref1, so that the conduction of the driving transistor DT during threshold compensation can be facilitated. The second reset module 70 resets the anode of the light emitting device E by receiving the second reset signal Vref2, so that the anode of the light emitting device E is initialized, thereby improving the residual of the previous frame data signal, improving the image sticking phenomenon, and improving the display effect of the pixel circuit 00 when applied to the display panel. In the reset phase of the pixel circuit 00 of this embodiment, the first reset module 20 and the second reset module 70 can improve the residual of the previous frame data signal, improve the image sticking phenomenon, and facilitate the conduction of the driving transistor DT during the threshold compensation. The value of the first reset signal Vref1 and the value of the second reset signal Vref2 of the present embodiment may be set to be different, that is, when the pixel circuit 00 of the present embodiment is applied to a display panel, the value of the first reset signal Vref1 and the value of the second reset signal Vref2 are different, so that the first reset module 20 and the second reset module 20 are enabledThe two reset modules 70 reset the gate of the driving transistor DT and the anode of the light emitting device E with different reset signals, and optionally, the value of the first reset signal Vref1 may be greater than that of the second reset signal Vref2, as shown in fig. 10, when the first reset signal Vref1 is a square wave signal, the first reset signal Vref1 includes a low potential V_1LAnd a high potential V_1HLow potential V of the first reset signal Vref1_1LPotential V greater than second reset signal Vref2₂. Since the first reset signal Vref1 cannot be too low and the potential of the first reset signal Vref1 is too low, when the data writing module 10 writes the fixed data voltage signal Vdata into the gate of the driving transistor DT in the data writing phase, the first reset signal Vref1 pulls the original potential of the gate of the driving transistor DT low, which may result in insufficient charging of the gate of the driving transistor DT. The potential value of the second reset signal Vref2 is desirably lower in order to more completely reset the anode of the light emitting device E and avoid the occurrence of a phenomenon of sneak luminance of the sub-pixel due to a lateral leakage current between the light emitting devices E of adjacent sub-pixels.

In the embodiment, the value of the first reset signal Vref1 is different from the value of the second reset signal Vref2, the first reset signal Vref1 and the second reset signal Vref2 are controlled independently, and when the second reset signal Vref2 needs to be pulled down to improve the problem of the light-emitting device E lighting stealing, the low potential of the first reset signal Vref1 does not need to be pulled down along with the pulling down of the second reset signal Vref2, so that the low potential V of the first reset signal Vref1 can be enabled to be lower_1LA potential V higher than the second reset signal Vref2 after being pulled down₂When the data voltage signal Vdata is written into the gate of the driving transistor DT after the gate of the driving transistor DT is reset, a slightly higher low potential V can be applied_1LThe writing of the data voltage signal Vdata is beneficial to reducing the voltage difference between the initial potential of the grid electrode of the driving transistor DT and the data signal needing to be written, so that the data signal can be written more fully in the data writing stage.

It is understood that, in this embodiment, the types of the first reset signal Vref1 and the second reset signal Vref2 are not specifically limited, and the first reset signal Vref1 and the second reset signal Vref2 may both be direct current signals, or the first reset signal Vref1 may be a square wave alternating current signal, and the second reset signal Vref2 may be a direct current signal, or the first reset signal Vref1 and the second reset signal Vref2 may also be other types of signals, and it is only required that the value of the first reset signal Vref1 is greater than the value of the second reset signal Vref2, and this embodiment is not specifically limited.

In some alternative embodiments, please refer to fig. 8 and fig. 9 in combination, in this embodiment, during the same time period in the operation phase of the pixel circuit 00, the polarity of the first control signal S1P is opposite to the polarity of the second control signal S2P, and the first control signal S1P and the second control signal S2P alternately output the active signals.

In the present embodiment, the first control signal S1P connected to the gate of the fifth transistor M5 in the reset control block 30 and the second control signal S2P connected to the gate of the sixth transistor M6 in the data write block 10 are explained, both of which are in the same period of time before the light emitting device E emits light, the polarity of the first control signal S1P is opposite to the polarity of the second control signal S2P, so that the first control signal S1P and the second control signal S2P can alternately output valid signals, that is, in the first reset phase t1, in order to allow the first reset signal Vref1 to be transmitted to the first node N1, the first control signal S1P is an active signal of low level, the reset control module 30 is turned on, and the sixth transistor M6 of the data writing module 10 may be turned off, it is thus possible to prevent the data voltage signal from being written when the reset of the first node N1 has not been completed, and thus the second control signal S2P is an inactive signal of a high level at this time; after the first data writing phase t2 is entered, the sixth transistor M6 of the data writing module 10 needs to be turned on, so at this time, the second control signal S2P is an active signal with a low level, in order to prevent the first reset signal Vref1 from being transmitted to the first node N1, the first control signal S1P is a non-active signal with a high level, so that the reset control module 30 is turned off, and so on, the second reset phase t3 and the second data writing phase t4 are entered, so that before the light emitting device E emits light, the processes of resetting and data writing can be performed alternately for many times, so as to improve the problem that the luminance of the first frame is low after the light emitting phase is entered.

In some alternative embodiments, with continuing reference to fig. 8 and 9, in the present embodiment, before the light-emitting device E emits light, i.e., before the operation of the pixel circuit 00 enters the light-emitting period t5, both the first transistor M1 and the second transistor M2 are in the off state.

The present embodiment explains that before the pixel circuit 00 operates to the light emitting stage, the first light emitting control signal EM1 connected to the gate of the first transistor M1 of the first light emitting module 40 and the second light emitting control signal EM2 connected to the gate of the second transistor M2 of the second light emitting module 50 can be both controlled to be inactive signals, such as high level signals illustrated in the figure, so that both the first transistor M1 and the second transistor M2 are in the off state, and therefore, the light emitting device E can be prevented from emitting light by mistake in the non-light emitting stage, and the product yield is prevented from being affected.

Alternatively, referring to fig. 8 and fig. 11 in combination, fig. 11 is another operation timing diagram of the pixel circuit in fig. 8, in this embodiment, the first emission control signal EM1 and the second emission control signal EM2 may be the same emission control signal EM, the emission control signal EM needs to ensure that the inactive signal with the high level is maintained in the whole data writing phase (multiple data writing) and the resetting phase (multiple resetting), so that the light emitting device E does not emit light, and in order to avoid the delay of signal transmission caused by signal loading, the time period t0 during which the emission control signal EM is the high level inactive signal may be set to cover the pulse phases (such as t1-t4 in fig. 11) of the whole data writing phase (multiple data writing) and the resetting phase (multiple resetting), that is, the emission control signal EM shown in fig. 11 is in the first control signal S1P, the second control signal S2P, and the first control signal S1, The first scanning signal S1N and the second scanning signal S2N are kept as high-level non-effective signals in advance before pulse signals appear, and the light-emitting control signal EM still keeps the high-level non-effective signals for a period of time after the pulse signals of the first control signal S1P, the second control signal S2P, the first scanning signal S1N and the second scanning signal S2N are ended, so that the phenomenon that the light-emitting device E emits light by mistake in an illegal light stage is better avoided, and the light-emitting effect is ensured.

In some alternative embodiments, with continuing reference to fig. 8 and 9 and 11, in the present embodiment, before the light emitting device E emits light, the fifth transistor M5 and the sixth transistor M6 are turned on alternately; during the process in which the fifth transistor M5 and the sixth transistor M6 are alternately turned on, the third transistor M3 and the fourth transistor M4 are both in a turned-on state.

In the present embodiment, the first control signal S1P connected to the gate of the fifth transistor M5 in the reset control module 30 and the second control signal S2P connected to the gate of the sixth transistor M6 in the data writing module 10 are explained, and in the same time period before the light emitting device E emits light, the polarity of the first control signal S1P is opposite to that of the second control signal S2P, so that the first control signal S1P and the second control signal S2P can be made to alternately output the active signal, that is, in the process of alternately turning on the fifth transistor M5 and the sixth transistor M6, the third transistor M3 of the first reset module 20 and the fourth transistor M4 of the compensation module 60 are both in the on state, so that the power consumption of switching the first scan signal S1N and the second scan signal S2N in the process of repeatedly alternating between reset and data writing can be reduced, and the alternating output of the active light emitting signal E1 and the second control signal S8656 can be realized by only the first control signal S1P and the second control signal S2P to alternately output the light emitting device E a plurality of times The process of resetting and data writing is replaced to solve the problem that the luminance of the first frame is low after the light-emitting phase is started.

In some alternative embodiments, please refer to fig. 8 and 12 in combination, fig. 12 is another operation timing diagram of the pixel circuit in fig. 8, in this embodiment, before the light emitting device E emits light, after the third transistor M3 is turned on, the fourth transistor M4 is turned on.

In this embodiment, it is explained that, when the pixel circuit 00 operates, before the light emitting device E emits light, that is, before the pixel circuit 00 enters a light emitting phase, the third transistor M3 of the first reset module 20 is turned on, and then the fourth transistor M4 of the compensation module 50 is turned on again, that is, when the first reset phase t1 needs to enter the first data writing phase t2 after being performed, the fourth transistor M4 of the compensation module 50 is turned on, instead of performing resetting, the fourth transistor M4 of the compensation module 50 is turned on at the same time, as shown in fig. 12, the first scan signal S1N first provides an effective signal, and the second scan signal S2N provides an effective signal again, so that the power consumption of the device for providing an effective signal for the second scan signal S2N of the pixel circuit 00 is reduced.

In some alternative embodiments, referring to fig. 8 and 13 in combination, fig. 13 is another operation timing diagram of the pixel circuit in fig. 8, in this embodiment, before the light emitting device E emits light, the data writing module 10 provides the data voltage signal Vdata to the driving transistor DT three times, and the first reset module 20 provides the first reset signal Vref1 to the driving transistor DT three times when the reset control module 30 is turned on.

This embodiment explains that before the driving operation of the pixel circuit 00 proceeds to the light-emitting phase, the first reset module 20 may be configured to provide the gate of the driving transistor DT (the first node N1) with the first reset signal Vref1 three times and the data writing module 10 provides the driving transistor DT with the data voltage signal Vdata three times when the reset control module 30 is turned on, and repeatedly and alternately perform, that is, the operation phase of the pixel circuit 00 includes the first reset phase t1, the first data writing phase t2, the second reset phase t3, the second data writing phase t4, the third reset phase t31, the third data writing phase t41 and the light-emitting phase t5, so that the first node N1 (the gate of the driving transistor DT) can be repeatedly reset and charged. When the first reset module 20 of this embodiment provides the first reset signal Vref1 to the driving transistor DT for the first time when the reset control module 30 is turned on, the data write module 10 provides the first data voltage signal Vdata to the driving transistor DT, that is, after the first reset and charging to the gate (the first node N1) of the driving transistor DT, the voltage of the gate (the first node N1) of the driving transistor DT is already written to the data voltage signal Vdata of the white state, at which time the potential of the first node N1 is much less than the high potential at the initial black state, then when the first reset module 20 of this embodiment provides the second first reset signal Vref1 to the driving transistor DT when the reset control module 30 is turned on, after the data write module 10 provides the second data voltage signal Vdata to the driving transistor DT, that is, after the second reset and charging to the gate (the first node N1) of the driving transistor DT, the potential of the first node N1 is not the high potential of the original black state after the first reset and charge, but is pulled down correspondingly after the first reset and charge, so that the difference between the potential of the first node N1 and the second node N2 is smaller based on the low potential, even if the capacitive coupling exists between the two nodes of the first node N1 and the second node N2 and the potential of the first node N1 is pulled up, the coupling effect is weakened, the amplitude of the pulled up potential of the first node N1 is smaller, that is, the amplitude of the jump of the potential of the first node N1 is reduced, therefore, even if the potential of the first node N1 is pulled up again due to the capacitive coupling effect during the second reset and charge process, the potential of the first node N1 is not pulled up too much, and then after the second reset and charge of the first node N1, the potential of the first node N1 is closer to the ideal low potential required by the white state, and in the third reset and charge process, the potential of the first node N1 can be better consolidated, so that the potential of the first node N1 is closer to the ideal low potential required for the white state. In this embodiment, the process of setting three times of reset and three times of charge is performed alternately before the light-emitting stage of the pixel circuit 00, as shown in fig. 14, fig. 14 is a contrast graph of the luminance of the first frame in which the pixel circuit provided in this embodiment performs multiple times of reset and multiple times of data writing before the light-emitting stage, in which the ordinate represents the luminance percentage of the first frame (percentage compared to the maximum luminance value of the light-emitting device), four sets of histograms are illustrated on the abscissa, and the columnar structure filled with four different patterns arranged in the left-to-right direction of the figure in each set of histograms represents the luminance a of the first frame in which the process of setting one time of reset and one time of charge is performed, the luminance B of the first frame in which the process of setting two times of reset and three times of charge is performed alternately, the luminance C of the first frame in which the process of setting four times of reset and four times of charge is performed alternately, the luminance a of the first frame in which the process of setting four times of reset and four times of charge is performed alternately before the light-emitting stage of the pixel circuit 00, respectively, The luminance D of the first frame, in which the process of five resets and five charges are alternately performed, is set, and can be obtained from the experimental data obtained in fig. 14, as shown in table one below:

as can be seen from fig. 14 in conjunction with the above table one, the luminance B of the first frame in which the process of setting two times of resets and three times of charges is alternately performed is improved by about 30% from the luminance a (difference of 82% and 46% of the first group data, difference of 82% and 49% of the second group data, difference of 83% and 48% of the third group data, difference of 84% and 47% of the fourth group data) compared to the luminance a of the first frame in which the process of setting one time of resets and one time of charges is performed, but the luminance C of the first frame in which the process of setting four times of resets and four times of charges is alternately performed is improved by about 5% from the luminance B of the first frame in which the process of setting two times of resets and three times of charges is alternately performed (difference of 87% and 82% of the first group data, difference of 88% and 82% of the second group data, difference of 86% and 83% of the third group data, the difference of 87% and 84% for the fourth set of data), the luminance D of the first frame in which the process of setting five resets and five charges is performed alternately and the luminance C of the first frame in which the process of setting four resets and four charges is performed alternately are improved by only about 3% or so than the luminance C even without improvement (the difference of 90% and 87% for the first set of data, the difference of 88% and 88% for the second set of data, the difference of 88% and 86% for the third set of data, and the difference of 88% and 87% for the fourth set of data), i.e., the improvement of the luminance of the first frame by more resets and charges is not significant. Therefore, the pixel circuit 00 of this embodiment sets three times of resetting and three times of charging to be performed alternately before the light-emitting stage, which not only can avoid multiple times of resetting and data writing to increase the power consumption of the circuit to a certain extent, but also can greatly improve the brightness of the first frame by performing the three times of resetting and three times of charging alternately, weaken the difference between the brightness of the first frame and the brightness of other subsequent frames, effectively improve the smear phenomenon, and improve the display quality of the display panel using the pixel circuit of this embodiment.

In some alternative embodiments, please continue to refer to fig. 1 to fig. 12 in combination, the present embodiment provides a driving method of a pixel circuit, which is applied to the pixel circuit 00 in the above embodiments to perform a light emitting driving operation; the driving method of the present embodiment includes: in one driving period, at least two reset phases, at least two data writing phases, and a light emitting phase are included, as shown in fig. 12, the driving method of the present embodiment is exemplified by including two reset phases, two data writing phases, and a light emitting phase in one driving period, where one driving period can be understood as a time of one frame during which the pixel circuit 00 drives the light emitting device E to emit light, that is, a time of displaying a still picture. Wherein in the reset phase, the first reset module 20 provides the first reset signal Vref to the driving transistor DT when the reset control module 30 is turned on; in the data writing phase, the data writing module 10 provides a data voltage signal Vdata to the driving transistor DT; in the light emitting stage, the light emitting device E emits light in response to the driving current; wherein, the reset phase and the data writing phase are executed before the light-emitting phase; before the data writing phase and the resetting phase are alternated, that is, before the driving operation of the pixel circuit 00 is set to be performed to the light emitting phase, the first reset module 20 provides the gate (the first node N1) of the driving transistor DT with the first reset signal Vref1 for the first time when the reset control module 30 is turned on and the data writing module 10 provides the driving transistor DT with the data voltage signal Vdata for the first time, then the first reset module 20 provides the gate (the first node N1) of the driving transistor DT with the first reset signal Vref1 for the second time when the reset control module 30 is turned on and the data writing module 10 provides the driving transistor DT with the data voltage signal Vdata for the second time, which are repeatedly and alternately performed, and then the light emitting phase is entered, so that the first reset module 20 provides the driving transistor DT with the first reset signal Vref1 for the second time when the reset control module 30 is turned on, and the data writing module 10 provides the driving transistor DT with the data voltage signal Vdata for the second time, after the gate (the first node N1) of the driving transistor DT is reset and charged for the second time, the potential of the first node N1 is not already high in the original black state after the first reset and charge, but is pulled down correspondingly after the first reset and charge, so that the difference between the potential of the first node N1 and the second node N2 is smaller on the basis of the low potential, even if the potential of the first node N1 is pulled up due to the capacitive coupling between the two nodes of the first node N1 and the second node N2, the coupling effect is weakened, the amplitude of the pulled-up potential of the first node N1 is smaller, that is, the amplitude of the jump of the potential of the first node N1 is reduced, so that even if the potential of the first node N1 is pulled up again due to the capacitive coupling effect during the second reset and charge, the potential of the first node N1 is pulled up too high, then, after the first node N1 is reset and charged for the second time, the potential of the first node N1 is closer to the ideal low potential required by the white state, so that the brightness of the first frame can be better improved, the problem that the brightness of the first frame (the brightness of the initial time period after the frame is switched) is low when the black and white frames are switched is avoided, the difference between the brightness of the first frame and the brightness of other subsequent frames can be weakened, the phenomenon of smear can be effectively improved, and the display quality of the display panel using the pixel circuit of the embodiment is improved.

In some alternative embodiments, please continue to refer to fig. 1-8, 13 and 14 in combination, this embodiment provides a driving method of a pixel circuit, which is applied to the pixel circuit 00 in the above embodiments to perform a light emitting driving operation; the driving method of the present embodiment includes: in one driving period, three reset phases, three data writing phases and a light-emitting phase are included, as shown in fig. 13, at least two reset phases include a first reset phase t1, a second reset phase t3 and a third reset phase t31, and at least two data writing phases include a first data writing phase t2, a second data writing phase t4 and a third data writing phase t 41; the first data writing phase t2 is performed between the first reset phase t1 and the second reset phase t3, and the second data writing phase t4 is performed between the second reset phase t3 and the third reset phase t 31; the second reset phase t3 is performed between the first data write phase t2 and the second data write phase t4, and the third reset phase t31 is performed between the second data write phase t4 and the third data write phase t 41; when the pixel circuit 00 of this embodiment performs a driving operation, the driving method includes:

in the first reset phase t1, the first reset module 20 provides the first sub-reset signal Vref11 to the driving transistor DT when the reset control module 30 is turned on;

in the first data writing phase t2, the data writing module 10 provides the first data voltage signal Vdata1 to the driving transistor DT;

in the second reset phase t3, the first reset module 20 provides the second sub-reset signal Vref12 to the driving transistor DT when the reset control module 30 is turned on;

in the second data writing phase t4, the data writing module 10 provides the second data voltage signal Vdata2 to the driving transistor DT;

in the third reset phase t31, the first reset module 20 provides the third sub-reset signal Vref13 to the driving transistor DT when the reset control module 30 is turned on;

in the third data writing phase t41, the data writing module 10 provides a third data voltage signal Vdata3 to the driving transistor DT;

in the light emitting period t5, the light emitting device E emits light in response to the driving current.

The driving method of the pixel circuit 00 provided in this embodiment explains that before the light-emitting stage, the processes of three times of resetting and three times of charging are set to be performed alternately, which not only can avoid that the power consumption of the circuit is increased to a certain extent by multiple times of resetting and data writing, but also can greatly improve the brightness of the first frame by performing the processes of three times of resetting and three times of charging alternately, weaken the difference between the brightness of the first frame and the brightness of other subsequent frames, effectively improve the smear phenomenon, and improve the display quality of the display panel to which the pixel circuit of this embodiment is applied.

Optionally, the values of the first sub-reset signal Vref11, the second sub-reset signal Vref12, and the third sub-reset signal Vref13 are the same, and the values of the first data voltage signal Vdata1, the second data voltage signal Vdata2, and the third data voltage signal Vdata3 are the same.

This embodiment explains that in the repeated resetting and charging process of the pixel circuit 00 to the first node N1 (the gate of the driving transistor DT) before the light-emitting period t5, the first reset module 20 provides the same value of the first reset signal Vref1 for three times to the gate of the driving transistor DT (the first node N1) when the reset control module 30 is turned on, that is, the same values of the first sub-reset signal Vref11, the second sub-reset signal Vref12 and the third sub-reset signal Vref13, so as to ensure that the potential of the first node N1 (the gate of the driving transistor DT) is reset to the same degree; before the light-emitting device E emits light, the data writing module 10 provides the driving transistor DT with the same value of the data voltage signal Vdata three times, that is, the first data voltage signal Vdata1, the second data voltage signal Vdata2, and the third data voltage signal Vdata3, so as to ensure that the data voltage written to the first node N1 (the gate of the driving transistor DT) has the same degree, and further maintain the accurate light-emitting brightness of the light-emitting device E as much as possible, thereby avoiding signal disorder caused by multiple resets and multiple data writes, causing the light-emitting device E to emit light by mistake, and affecting the light-emitting effect.

In some optional embodiments, please refer to fig. 15, where fig. 15 is a schematic plane structure diagram of a display panel provided in an embodiment of the present invention, the display panel 111 provided in this embodiment includes the pixel circuit 00 provided in the foregoing embodiment of the present invention, and optionally, the pixel circuit 00 may be located in each sub-pixel range of the display area of the display panel 111. The embodiment of fig. 15 only takes a mobile phone as an example to describe the display panel 111, and it should be understood that the display panel 111 provided in the embodiment of the present invention may be a display panel 111 with other display functions, such as a computer, a television, a vehicle-mounted display panel, etc., and the present invention is not limited thereto. The display panel 111 provided in the embodiment of the present invention includes the pixel circuit 00 provided in the above embodiment, so that the display panel has the beneficial effects of the pixel circuit 00 provided in the embodiment of the present invention, and specific descriptions of the pixel circuit 00 in the above embodiments may be specifically referred to, and the detailed description of the embodiment is not repeated herein.

As can be seen from the above embodiments, the pixel circuit, the driving method thereof, and the display panel provided by the invention at least achieve the following beneficial effects:

Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A pixel circuit, comprising at least: the device comprises a driving transistor, a data writing module, a first reset module, a reset control module and a light-emitting device;

the first end of the data writing module is connected with a data voltage signal, the second end of the data writing module is connected with the first pole of the driving transistor, and the data writing module is used for providing the data voltage signal for the driving transistor;

the first end of the first reset module is connected with a first reset signal, the second end of the first reset module is connected with the first end of the reset control module, the second end of the reset control module is connected with the grid electrode of the driving transistor, and the first reset module provides the first reset signal for the driving transistor when the reset control module is conducted;

before the light-emitting device emits light, the data writing module provides the data voltage signal to the driving transistor at least twice, the first reset module provides the first reset signal to the driving transistor at least twice when the reset control module is turned on, and a process of providing the data voltage signal to the driving transistor once by the data writing module and a process of providing the first reset signal to the driving transistor once by the first reset module alternate.

2. The pixel circuit according to claim 1, wherein the data writing module provides the same value of the data voltage signal to the driving transistor at least twice, and the first resetting module provides the same value of the first resetting signal to the driving transistor at least twice.

3. The pixel circuit according to claim 1, wherein the first reset module is turned on under control of a first enable signal, and the first enable signal is a high-level signal.

4. The pixel circuit of claim 3, wherein the first reset module comprises an N-type oxide transistor.

5. The pixel circuit according to claim 1,

the first pole of the driving transistor is connected with a first power supply signal and used for providing the first power supply signal for the pixel circuit;

the second pole of the driving transistor is connected with the anode of the light-emitting device;

the cathode of the light-emitting device is connected with a second power supply signal and is used for providing the second power supply signal for the pixel circuit; the value of the first power supply signal is greater than the value of the second power supply signal.

6. The pixel circuit according to claim 5, further comprising a first light emission control module, a second light emission control module, a compensation module;

the first end of the first light-emitting control module is connected with the first power supply signal, and the second end of the first light-emitting control module is connected with the first pole of the driving transistor;

the first end of the second light-emitting control module is connected with the second pole of the driving transistor, and the second end of the second light-emitting control module is connected with the anode of the light-emitting device;

the first end of the compensation module is connected with the grid electrode of the driving transistor, and the second end of the compensation module is connected with the second pole of the driving transistor.

7. The pixel circuit of claim 6,

the first light emitting control module comprises a first transistor, wherein the grid electrode of the first transistor is connected with a first light emitting control signal, the first pole of the first transistor is connected with the first power supply signal, and the second pole of the first transistor is connected with the first pole of the driving transistor;

the second light-emitting control module comprises a second transistor, wherein the grid electrode of the second transistor is connected with a second light-emitting control signal, the first pole of the second transistor is connected with the second pole of the driving transistor, and the second pole of the second transistor is connected with the anode of the light-emitting device;

the first reset module comprises a third transistor, the grid electrode of the third transistor is connected with a first scanning signal, and the first pole of the third transistor is connected with the first reset signal;

the compensation module comprises a fourth transistor, wherein the grid electrode of the fourth transistor is connected with a second scanning signal, the first pole of the fourth transistor is connected with the grid electrode of the driving transistor, and the second pole of the fourth transistor is connected with the second pole of the driving transistor;

the reset control module comprises a fifth transistor, wherein the grid electrode of the fifth transistor is connected with a first control signal, the first pole of the fifth transistor is connected with the second pole of the third transistor, and the second pole of the fifth transistor is connected with the grid electrode of the driving transistor;

the data writing module comprises a sixth transistor, a grid electrode of the sixth transistor is connected with a second control signal, a first pole of the sixth transistor is connected with the data voltage signal, and a second pole of the sixth transistor is connected with a first pole of the driving transistor.

8. The pixel circuit according to claim 7, wherein the driving transistor, the first transistor, the second transistor, the fifth transistor, and the sixth transistor are P-type low temperature polysilicon transistors, and wherein the third transistor and the fourth transistor are N-type oxide transistors.

9. The pixel circuit according to claim 7, wherein a polarity of the first control signal is opposite to a polarity of the second control signal in a same period, and the first control signal and the second control signal alternately output an active signal.

10. The pixel circuit according to claim 7, further comprising a second reset module, wherein a first terminal of the second reset module is connected to a second reset signal, a second terminal of the second reset module is connected to the anode of the light emitting device for resetting the anode of the light emitting device, and a value of the first reset signal is different from a value of the second reset signal.

11. The pixel circuit according to claim 10, wherein the second reset module comprises a seventh transistor, a gate of the seventh transistor is connected to the first control signal, a first pole of the seventh transistor is connected to the second reset signal, and a second pole of the seventh transistor is connected to the anode of the light emitting device.

12. The pixel circuit according to claim 7, further comprising a storage capacitor, wherein a first pole of the storage capacitor is connected to the gate of the driving transistor, and a second pole of the storage capacitor is connected to the first power signal.

13. The pixel circuit according to claim 7, wherein the first transistor and the second transistor are both in an off state before the light emitting device emits light.

14. The pixel circuit according to claim 7, wherein the fifth transistor and the sixth transistor are alternately turned on before the light emitting device emits light;

in a process in which the fifth transistor and the sixth transistor are alternately turned on, the third transistor and the fourth transistor are both in a turned-on state.

15. The pixel circuit according to claim 7, wherein the fourth transistor is turned on after the third transistor is turned on before the light emitting device emits light.

16. The pixel circuit according to claim 1, wherein the data writing module supplies the data voltage signal to the driving transistor three times before the light emitting device emits light, and the first reset module supplies the first reset signal to the driving transistor three times when the reset control module is turned on.

17. A driving method of a pixel circuit, wherein the driving method is applied to the pixel circuit according to any one of claims 1 to 16 for driving operation; the driving method includes:

in a driving period, at least two reset phases, at least two data writing phases and a light-emitting phase are included; in the reset phase, the first reset module provides the first reset signal to the driving transistor when the reset control module is turned on; in the data writing phase, the data writing module provides the data voltage signal to the driving transistor; in the light emitting stage, the light emitting device emits light in response to the driving current; wherein the reset phase and the data writing phase are performed before the light emitting phase; the data writing phase alternates with the resetting phase.

18. The driving method according to claim 17,

the at least two reset phases comprise a first reset phase, a second reset phase and a third reset phase, and the at least two data write phases comprise a first data write phase, a second data write phase and a third data write phase; the first data writing phase is performed between the first reset phase and the second reset phase, and the second data writing phase is performed between the second reset phase and the third reset phase; the second reset phase is performed between the first data write phase and the second data write phase, and the third reset phase is performed between the second data write phase and the third data write phase;

the driving method includes:

in the first reset phase, the first reset module provides a first sub-reset signal to the driving transistor when the reset control module is turned on;

in the first data writing phase, the data writing module provides a first data voltage signal to the driving transistor;

in the second reset phase, the first reset module provides a second sub-reset signal to the driving transistor when the reset control module is turned on;

in the second data writing phase, the data writing module provides a second data voltage signal to the driving transistor;

in the third reset phase, the first reset module provides a third sub-reset signal to the driving transistor when the reset control module is turned on;

in the third data writing phase, the data writing module provides a third data voltage signal to the driving transistor;

in the light emitting stage, the light emitting device emits light in response to a driving current.

19. The driving method according to claim 18, wherein the first sub reset signal, the second sub reset signal, and the third sub reset signal have the same value, and the first data voltage signal, the second data voltage signal, and the third data voltage signal have the same value.

20. A display panel comprising the pixel circuit according to any one of claims 1 to 16.