CN114566124A - Light emitting unit driving circuit, display panel and display device - Google Patents
Light emitting unit driving circuit, display panel and display device Download PDFInfo
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- CN114566124A CN114566124A CN202210459063.8A CN202210459063A CN114566124A CN 114566124 A CN114566124 A CN 114566124A CN 202210459063 A CN202210459063 A CN 202210459063A CN 114566124 A CN114566124 A CN 114566124A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present application relates to a light emitting unit driving circuit, a display panel and a display device, wherein, the light-emitting unit drive circuit comprises a drive transistor, a first switch circuit, a delay output circuit and a second switch circuit, when the light-emitting unit drive circuit works, in a preset time period, the first switch circuit is controlled to be conducted first and outputs a first preset voltage to control the conduction of the driving transistor, the light-emitting unit is powered on to emit light, after the delay output circuit delays for a second preset time period, the first level signal with the third preset duration is output, the second switch circuit is conducted, the voltage of the output end of the driving transistor is equal to the voltage of the input end, the bias time is prevented from being overlong, the recovery of various characteristics under bias is realized, meanwhile, the positive voltage continues to supply power through the second switch circuit, and the light-emitting unit continues to receive power and emit light, so that the light-emitting operation of the light-emitting unit is ensured.
Description
Technical Field
The application belongs to the technical field of display, and particularly relates to a light-emitting unit driving circuit, a display panel and a display device.
Background
Light Emitting units such as Active-Matrix Organic Light-Emitting diodes (AM OLEDs) and Active-Matrix Micro Light-Emitting diodes (AM Mini LEDs) and Micro LEDs (Micro LEDs) have the characteristics of fast response, wide color gamut, large viewing angle, high brightness and the like, and gradually become mainstream display technologies of displays such as mobile phones, televisions, computers and the like.
Each light-emitting unit constitutes a pixel unit or a light-emitting point, and each light-emitting unit can receive power and emit light, and can be addressed and driven to light independently.
Generally, the light emitting unit is driven by the driving transistor, but when the driving transistor works in the same bias voltage for a long time, the characteristics of the driving transistor, such as temperature, threshold voltage, and tube voltage drop, are easily changed, which affects the light emitting effect of the light emitting unit.
Disclosure of Invention
An object of the present application is to provide a light emitting unit driving circuit, which aims to solve the problem that the characteristics of a conventional driving transistor for driving a light emitting unit change when the driving transistor works in a bias voltage, which affects the light emitting effect of the light emitting unit.
A first aspect of an embodiment of the present application provides a light emitting unit driving circuit, including:
the light-emitting diode comprises a driving transistor, a first diode and a second diode, wherein the input end of the driving transistor is used for being connected with a positive voltage, the output end of the driving transistor is connected with a light-emitting unit, and the driving transistor is triggered and conducted by a first preset voltage;
the input end of the first switch circuit is used for inputting a data signal, the controlled end of the first switch circuit is used for inputting a first scanning signal, the output end of the first switch circuit is connected with the grid electrode of the driving transistor, and the first switch circuit is triggered by the first scanning signal to output the first preset voltage for a first preset duration;
the input end of the delay output circuit, the output end of the driving transistor and the light-emitting unit are interconnected, the controlled end of the delay output circuit is used for inputting a second scanning signal, the delay output circuit is triggered by the second scanning signal to delay a first level signal with a third preset duration after being triggered by the second scanning signal, and the time sum of the second preset duration and the third preset duration is less than or equal to the first preset duration;
and the input end of the second switch circuit is used for inputting the positive voltage, the output end of the second switch circuit is interconnected with the light-emitting unit, the output end of the driving transistor and the input end of the delay output circuit, and the second switch circuit is triggered to be conducted by the first level signal.
Optionally, the first scanning signal is input before the second scanning signal by a fourth preset time length, and a time sum of the second preset time length, the third preset time length and the fourth preset time length is less than or equal to the first preset time length;
the delay output circuit includes:
the input end of the switching output circuit, the output end of the driving transistor and the light emitting unit are interconnected, the controlled end of the switching output circuit is used for inputting the second scanning signal, the switching output circuit is triggered by the second scanning signal to output a second preset voltage for a second preset duration, and triggers to output a third preset voltage for a third preset duration after the second preset duration, the second preset voltage is greater than or equal to a reference voltage, and the third preset voltage is less than the reference voltage;
the first input end of the voltage comparison circuit is connected with the output end of the switching output circuit, the second input end of the voltage comparison circuit is used for inputting the reference voltage, the output end of the voltage comparison circuit is connected with the controlled end of the second switch circuit, the voltage comparison circuit receives the second preset voltage and compares and outputs the second level signal, receives the third preset voltage and compares and outputs the first level signal, and the first level signal and the second level signal are level signals with opposite potentials.
Optionally, the first switching circuit comprises a first transistor and a first capacitor;
the input end of the first transistor is used for inputting the data signal, the output end of the first transistor and the first end of the first capacitor are interconnected to form the output end of the first switch circuit, the controlled end of the first transistor is used for inputting the first scanning signal, and the second end of the first capacitor is grounded.
Optionally, the second switch circuit includes a second transistor, and an input terminal, an output terminal, and a controlled terminal of the second transistor respectively constitute the input terminal, the output terminal, and the controlled terminal of the second switch circuit.
Optionally, the switching output circuit comprises a third transistor and a second capacitor;
the input end of the third transistor, the output end of the driving transistor and the light emitting unit are interconnected, the controlled end of the third transistor is used for inputting the second scanning signal, the output end of the third transistor and the first end of the second capacitor are interconnected to form the output end of the switching output circuit, and the second end of the second capacitor is grounded.
Optionally, the voltage comparison circuit comprises a comparator;
the positive phase input end of the comparator forms the first input end of the voltage comparison circuit, the negative phase input end of the comparator is used for inputting the reference voltage, and the output end of the comparator forms the output end of the voltage comparison circuit.
Optionally, the light emitting unit driving circuit further comprises:
the input end of the switch energy storage circuit, the output end of the driving transistor, the input end of the delay output circuit and the output end of the second switch circuit are interconnected, the output end of the switch energy storage circuit is connected with the light-emitting unit, and the controlled end of the switch energy storage circuit is used for inputting corresponding scanning signals;
and the switch energy storage circuit is triggered by the corresponding scanning signal, is synchronously switched on with the driving transistor, performs charging energy storage, and is triggered to be switched off and discharged within the third preset time period.
Optionally, the switched tank circuit comprises a fourth transistor and a third capacitor;
the input end of the fourth transistor, the output end of the driving transistor, the input end of the delay output circuit and the output end of the second switch circuit are interconnected, the output end of the fourth transistor and the first end of the third capacitor are connected in common to form the output end of the switch energy storage circuit, the second end of the third capacitor is grounded, and the controlled end of the fourth transistor is used for inputting the second scanning signal or the third scanning signal.
A second aspect of the embodiments of the present application provides a display panel, which includes a plurality of light emitting units and a plurality of light emitting unit driving circuits as described above, wherein each of the light emitting units is connected to one of the light emitting unit driving circuits.
A third aspect of the embodiments of the present application provides a display device, which includes a control module and the display panel as described above, where the control module is correspondingly connected to the display panel.
Compared with the prior art, the embodiment of the application has the beneficial effects that: when the light emitting unit driving circuit works, in a preset time period, the first switch circuit is controlled to be switched on firstly, and outputs first preset voltage to control the conduction of the driving transistor, the light emitting unit is powered on to emit light, the output circuit is delayed for second preset time, and then outputs a first level signal with third preset time, the second switch circuit is switched on, the voltage of the output end of the driving transistor is equal to the voltage of the input end, the bias time is prevented from being overlong, the recovery of various characteristics under bias is realized, meanwhile, the positive voltage is used for continuously supplying power through the second switch circuit, the light emitting unit is continuously powered on to emit light, and the light emitting work of the light emitting unit is ensured.
Drawings
Fig. 1 is a schematic structural diagram of a light emitting unit driving circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a light emitting unit driving circuit according to a second embodiment of the present disclosure;
fig. 3 is a circuit diagram of a light emitting unit driving circuit according to a third embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a light emitting unit driving circuit according to a fourth embodiment of the present disclosure;
fig. 5 is a circuit diagram of a light emitting unit driving circuit according to a fifth embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a display panel according to a sixth embodiment of the present application;
fig. 7 is a schematic structural diagram of a display device according to a seventh embodiment of the present application.
Wherein, the figures are numbered:
100. a display panel; 200. a control module; 1. a light emitting unit driving circuit; 2. a light emitting unit; 10. a first switching circuit; 20. a delay output circuit; 30. a second switching circuit; 40. a switched energy storage circuit; 21. a switching output circuit; 22. a voltage comparison circuit; q1, drive transistor; k1, a first transistor; k2, a second transistor; k3, a third transistor; k4, a fourth transistor; c1, a first capacitance; c2, a second capacitor; c3, a third capacitance; vdata, a data signal; s1, a first scanning signal; s2, a second scanning signal; VDD, positive voltage; VREF, reference voltage.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Example one
A first aspect of the embodiment of the present application provides a light emitting unit driving circuit 1, as shown in fig. 1, fig. 1 is a schematic structural diagram of the light emitting unit driving circuit 1 provided in a first embodiment of the present application, in this embodiment, the light emitting unit driving circuit 1 includes:
the driving transistor Q1, an input end of the driving transistor Q1 is used for accessing a first positive voltage VDD, an output end of the driving transistor Q1 is connected with the light emitting unit 2, and the driving transistor Q1 is triggered and conducted by a first preset voltage;
the driving circuit comprises a first switch circuit 10, wherein an input end of the first switch circuit 10 is used for inputting a data signal Vdata, a controlled end of the first switch circuit 10 is used for inputting a first scanning signal S1, an output end of the first switch circuit 10 is connected with a gate of a driving transistor Q1, and the first switch circuit 10 is triggered by the first scanning signal S1 to output a first preset voltage for a first preset duration;
the input end of the delay output circuit 20, the output end of the driving transistor Q1 and the light emitting unit 2 are interconnected, the controlled end of the delay output circuit 20 is used for inputting the second scanning signal S2, the delay output circuit 20 is triggered by the second scanning signal S2 to delay the second preset time length and then output the first level signal of the third preset time length, and the time sum of the second preset time length and the third preset time length is less than or equal to the first preset time length;
and a second switch circuit 30, an input terminal of the second switch circuit 30 being for inputting a positive voltage VDD, an output terminal of the second switch circuit 30 being interconnected with the light emitting unit 2, an output terminal of the driving transistor Q1, and an input terminal of the delay output circuit 20, the second switch circuit 30 being triggered to be turned on by the first level signal.
In this embodiment, the light emitting unit 2 may be an OLED, Micro LED, or other light emitting unit 2, the light emitting unit 2 is disposed on the corresponding lamp panel structure to form a display panel 100, a lighting device or a backlight source, etc., correspondingly, the data signal Vdata, the first scan signal S1 and the second scan signal S2 are according to the arrangement of the light emitting cells 2, can be single output or multiple output, when the single output is performed, the light emitting unit driving circuit 1 controls the light emitting unit 2 to be correspondingly lighted in a preset time period, when the data signal Vdata and the scanning signal are not received, the light-emitting unit 2 is triggered to be turned off, the purposes of illumination, backlight source supply and the like are realized, when the data signal Vdata and the scanning signal are output repeatedly, the light emitting unit 2 is controlled to perform the alternate actions of turning on and off according to the preset time period and time interval to form different frame pictures or backlight sources, and the specific types of the data signal Vdata, the first scanning signal S1 and the second scanning signal S2 are specifically set according to the application structure.
Wherein, when the light emitting unit driving circuit 1 works for a single time, the first scanning signal S1 is inputted to the first switch circuit 10, the first switch circuit 10 is triggered to be turned on, the data signal Vdata is inputted to the first switch circuit 10, and the corresponding power conversion is performed in the first switch circuit 10, such as charging and discharging, voltage increasing and decreasing, voltage stabilizing conversion, outputting a first preset voltage after the conversion, the first preset voltage lasting for a first preset duration, wherein, the first preset time period and the input time period of the first scanning signal S1 may be equal, or not equal, for example, when the energy storage module is disposed in the first switch circuit 10, after the first scan signal S1 is turned off, the first switch circuit 10 can still output the first preset voltage with a preset duration through the energy storage module, the input duration of the first scanning signal S1 is made to be less than the output duration of the first preset voltage, which is set correspondingly according to the requirement.
When the first preset voltage is input to the driving transistor Q1, the driving transistor Q1 is controlled to be turned on, and the positive voltage VDD is applied to the light emitting unit 2, the light emitting unit 2 lights up to emit light, and the voltage at the input terminal of the driving transistor Q1 is greater than that at the output terminal, and when the driving transistor Q1 is operated in this state for a long time, the characteristic of the driving transistor Q1 changes, which causes a temperature rise, a threshold voltage decrease, and the like.
The second scan signal S2 is input to the delay output circuit 20 synchronously with the first scan signal S1 or delayed, and after a delay of a second predetermined duration after the input, that is, after the driving transistor Q1 is biased for a period of time, the delay output circuit 20 triggers to output the first level signal for a third preset duration according to the first scanning signal S1, and after the first level signal is input to the second switch circuit 30, the second switch circuit 30 is controlled to be turned on for the third preset duration, thereby outputting the positive voltage VDD to the output terminal of the driving transistor Q1 through the second switch circuit 30, the voltages of the output end and the input end of the driving transistor Q1 are equal, the driving transistor Q1 is cut off and works under bias voltage, the situation that the bias time of the driving transistor Q1 is too long is prevented, the characteristic of the driving transistor Q1 is recovered to the initial state, for example, the temperature, the threshold voltage and the like are recovered to the initial state, and the characteristic stability of the driving transistor Q1 is improved.
Meanwhile, the light emitting unit 2 receives the positive power through the second switch circuit 30, and the light emitting unit 2 continues to keep lighting and emitting light without affecting the operation of the light emitting unit 2.
Wherein, the offset time and the off-offset time of the driving transistor Q1, the input time of the second scan signal S2, and the delay time of the first level signal output by the delay output circuit 20 are correspondingly designed, and the delay output circuit 20 is correspondingly designed according to the output requirements of the second preset time period and the third preset time period.
By providing the first switch circuit 10, the second switch circuit 30 and the delay output circuit 20, when the light emitting unit 2 is controlled to be turned on respectively at different periods, the same period can be turned off with the bias, while the operation characteristic of the driving transistor Q1 in the next period is not affected.
For example, when the light emitting unit 2 is disposed on the display panel 100 as a pixel unit, the driving transistor Q1 is biased in the second preset time period in one frame, and is turned off in the third preset time period to recover the driving characteristics, when the sum of the times of the second preset time period and the third preset time period is equal to the first preset time period, the driving transistor Q1 implements the biasing and off-biasing operations in one frame, and repeats the biasing and off-biasing operations in the next frame, and the light emitting unit 2 receives a stable driving voltage in different frames, maintains the same lighting effect, and reduces the afterimage phenomenon of the display device.
When the first preset time is equal to the sum of the second preset time and the third preset time, the first preset voltage is cut off and output after the driving transistor Q1 is cut off and biased for the third preset time, the driving transistor Q1 is controlled to be turned off, the same work is repeated in the next stage, and when the first preset time is equal to the sum of the second preset time and the third preset time, the driving transistor Q1 can repeat the biasing and cut-off biasing work for multiple times in the first preset time, and is specifically designed according to the lighting requirements.
The first predetermined voltage may be a single constant voltage or a voltage threshold.
Compared with the prior art, the embodiment of the application has the advantages that: when the light-emitting unit driving circuit 1 works, in a preset time period, the first switch circuit 10 is controlled to be turned on in advance, and outputs a first preset voltage to control the driving transistor Q1 to be turned on, the light-emitting unit 2 receives power to emit light, the delay output circuit 20 outputs a first level signal with a third preset duration after a second preset duration, the second switch circuit 30 is turned on, the output end voltage of the driving transistor Q1 is equal to the input end voltage, the bias time is prevented from being too long, recovery of various characteristics under bias is realized, meanwhile, power is continuously supplied by the positive voltage VDD through the second switch circuit 30, the light-emitting unit 2 continues to receive power to emit light, and the light-emitting operation of the light-emitting unit 2 is ensured.
Example two
Based on the first embodiment, the refinement and optimization are performed, wherein the first scanning signal S1 is input before the second scanning signal S2 by a fourth preset time period, and the time sum of the second preset time period, the third preset time period and the fourth preset time period is less than or equal to the first preset time period;
alternatively, the delay output circuit 20 includes:
the switching output circuit 21, an input end of the switching output circuit 21, an output end of the driving transistor Q1 and the light emitting unit 2 are interconnected, a controlled end of the switching output circuit 21 is used for inputting a second scanning signal S2, the switching output circuit 21 is triggered by the second scanning signal S2 to output a second preset voltage for a second preset duration, and triggers to output a third preset voltage for a third preset duration after the second preset duration, the second preset voltage is greater than or equal to a reference voltage VREF, and the third preset voltage is less than the reference voltage VREF;
a voltage comparison circuit 22, a first input terminal of the voltage comparison circuit 22 is connected to an output terminal of the switching output circuit 21, a second input terminal of the voltage comparison circuit 22 is used for inputting a reference voltage VREF, an output terminal of the voltage comparison circuit 22 is connected to a controlled terminal of the second switch circuit 30, the voltage comparison circuit 22 compares and outputs a second level signal when receiving a second preset voltage, and compares and outputs a first level signal when receiving a third preset voltage, and the first level signal and the second level signal are level signals of opposite potentials.
In this embodiment, in order to avoid switching the operating state of the driving transistor Q1 too early, the first scan signal S1 is input before the second scan signal S2 by a fourth preset time period, i.e., after the first scan signal S1 is input, the second scan signal S2 is input to the switching output circuit 21 by delaying the fourth preset time period, after the switching output circuit 21 receives the second scan signal S2, the corresponding power conversion and voltage switching output is performed, i.e., the second preset voltage is output for the second preset time period, and the third preset voltage is output for the following third preset time period, meanwhile, the second preset voltage is compared with the reference voltage VREF and the second level signal is output to the second switch circuit 30 during the second preset time period, the second switch circuit 30 is kept in the off state, and the third preset voltage is compared with the reference voltage VREF during the third preset time period, and outputs the first level signal to the second switch circuit 30, the second switch circuit 30 is controlled to be turned on for a third preset time period, the driving transistor Q1 is turned off and biased within the third preset time period, and the characteristics and various parameters of the driving transistor Q1 are restored to the original state.
Meanwhile, the light emitting unit 2 acquires a positive voltage VDD through the first switch circuit 10 and is energized to light for a second preset period, and acquires a positive voltage VDD through the second switch circuit 30 and is energized to light for a third preset period.
The second preset voltage and the third preset voltage may be single constant values, or preset voltage threshold values, and the corresponding voltage threshold values or the single constant values are respectively compared with the reference voltage VREF, so as to output a first level signal or a second level signal.
Meanwhile, according to the second preset duration, the third preset duration, and the output requirements of the second preset voltage and the third preset voltage, the switching output circuit 21 may adopt corresponding circuit structures, such as a combination circuit of a switch circuit and an energy storage circuit, a combination circuit of a multi-switch and a power conversion circuit, and the specific structure is not limited.
The voltage comparison circuit 22 implements voltage comparison output and outputs a corresponding level signal, and the voltage comparison circuit 22 may be implemented by a switch structure and a comparator structure, and the specific structure is not limited.
EXAMPLE III
Based on the second embodiment, refinement and optimization are performed, as shown in fig. 3, optionally, the first switch circuit 10 includes a first transistor K1 and a first capacitor C1;
an input terminal of the first transistor K1 is used for inputting the data signal Vdata, an output terminal of the first transistor K1 and a first terminal of the first capacitor C1 are interconnected to form an output terminal of the first switch circuit 10, and a controlled terminal of the first transistor K1 is used for inputting the first scan signal S1, and a second terminal of the first capacitor C1 is grounded.
The second switch circuit 30 includes a second transistor K2, and an input terminal, an output terminal, and a controlled terminal of the second transistor K2 constitute an input terminal, an output terminal, and a controlled terminal of the second switch circuit 30, respectively.
The switching output circuit 21 includes a third transistor K3 and a second capacitor C2;
an input terminal of the third transistor K3, an output terminal of the driving transistor Q1, and the light emitting unit 2 are interconnected, a controlled terminal of the third transistor K3 is used for inputting the second scan signal S2, an output terminal of the third transistor K3 and a first terminal of the second capacitor C2 are interconnected to constitute an output terminal of the switching output circuit 21, and a second terminal of the second capacitor C2 is grounded.
The voltage comparison circuit 22 includes a comparator U1;
the non-inverting input of the comparator U1 forms the first input of the voltage comparison circuit 22, the inverting input of the comparator U1 is used for inputting the reference voltage VREF, and the output of the comparator U1 forms the output of the voltage comparison circuit 22.
In this embodiment, when the light emitting unit driving circuit 1 is in operation, the first transistor K1 receives the first scan signal S1, the first transistor K1 is triggered to turn on, the data signal Vdata is output to the driving transistor Q1 and the first capacitor C1 through the first transistor K1, the driving transistor Q1 is turned on, meanwhile, the first capacitor C1 stores energy and charges, after the first scan signal S1 is turned off and input, the first transistor K1 is controlled to be turned off, at this time, the first capacitor C1 discharges, the driving transistor Q1 continues to be controlled to be turned on, after a period of time, the terminal voltage of the first capacitor C1 drops to the threshold turn-off voltage, the driving transistor Q1 turns off, that is, the first preset time period is equal to the sum of the input time of the first scan signal S1 and the time for the first capacitor C1 to discharge to the threshold off voltage, when the driving transistor Q1 is turned on, the light emitting unit 2 is turned on to emit light, and the voltage at the input terminal of the driving transistor Q1 is greater than the voltage at the output terminal.
In order to avoid the excessive bias time of the driving transistor Q1, the second scan signal S2 is input after the first scan signal S1 is delayed for a fourth predetermined time period, and the third transistor K3 is controlled to be turned on, the voltage at the output terminal of the driving transistor Q1 charges the second capacitor C2 through the third transistor K3, and at the same time, the voltage is input to the comparator U1, the comparator U1 compares and outputs the second level signal with the high level, the second transistor K2 is turned off, after the predetermined time period, the second scan signal S2 is turned off, the third transistor K3 is turned off by triggering, the second capacitor C2 discharges to the comparator U1, when the voltage at the terminal of the second capacitor C2 drops to the reference voltage VREF after the second predetermined time period, the comparator U1 inverts and outputs the first level signal with the low level, the second transistor K2 is controlled to be turned on, and the positive voltage is input to the output terminal of the driving transistor Q1 and the light emitting unit 2 through the second transistor K2, the light-emitting unit 2 continues to emit light, and meanwhile, the characteristics and various parameters of the driving transistor Q1 are restored to the original state, so that the light-emitting effect of the light-emitting unit 2 is prevented from being influenced by the overlong bias time of the driving transistor Q1, the light-emitting unit 2 is driven at a constant voltage, and the display effect is improved.
The input time of the first scan signal S1 and the input time of the second scan signal S2, that is, the charging time of the first capacitor C1 and the second capacitor C2, are correspondingly adjusted according to the first preset time period and the third preset time period, and further, the time for discharging the first capacitor C1 and the second capacitor C2 to the corresponding voltage is adjusted, so as to implement the corresponding state switching, for example, the longer the charging time of the second capacitor C2 is, the longer the off-bias time of the driving transistor Q1 is, the longer the charging time of the first capacitor C1 is, and the longer the on-state time of the driving transistor Q1 is.
The first transistor K1, the second transistor K2, the third transistor K3, and the driving transistor Q1 can be selected according to on-off characteristics, and can be selected as an N-type transistor and a P-type transistor, and optionally, the driving transistor Q1, the first transistor K1, and the third transistor K3 are N-type transistors, and the second transistor K2 is a P-type transistor.
Example four
Based on the first embodiment, the refinement and optimization are performed, and optionally, the light emitting unit driving circuit 1 further includes:
the input end of the switch energy storage circuit 40, the output end of the driving transistor Q1, the input end of the delay output circuit 20 and the output end of the second switch circuit 30 are interconnected, the output end of the switch energy storage circuit 40 is connected with the light-emitting unit 2, and the controlled end of the switch energy storage circuit 40 is used for inputting corresponding scanning signals;
and the switch energy storage circuit 40 is triggered by the corresponding scanning signal, is synchronously switched on with the driving transistor Q1, performs charging energy storage, and is triggered to be switched off and discharged within a third preset time period.
In this embodiment, the switch energy storage circuit 40 and the switching output circuit 21 are in opposite working states, that is, when the driving transistor Q1 receives the first preset voltage, the switch energy storage circuit 40 receives the corresponding scanning signal and is controlled to be turned on, receives the positive voltage VDD output by the driving transistor Q1, the positive voltage VDD is output to the light emitting unit 2 through the switch energy storage circuit 40, the light emitting unit 2 is triggered to light up, and meanwhile, the switch energy storage circuit 40 stores energy.
When the driving transistor Q1 needs to be turned off and biased, that is, the voltage comparison circuit 22 outputs the first level signal for the third predetermined duration, and the second switch circuit 30 is turned on for the third predetermined duration, the driving transistor Q1 is turned off and biased, and the switch energy storage circuit 40 is turned off and discharged to the light emitting unit 2, so that the light emitting unit 2 continues to emit light.
And after the off-bias is finished, the switch energy storage circuit 40 and the driving transistor Q1 are controlled to be turned on synchronously, and the bias and the off-bias work are repeated.
By arranging the switch energy storage circuit 40, the situation that the voltage instability is caused when the positive voltage VDD output by the second transistor K2 is simultaneously responsible for cut-off bias and the lighting of the light-emitting unit 2, the cut-off bias effect and the light-emitting effect are influenced, and the driving reliability of the light-emitting unit 2 is improved.
The switch energy storage circuit 40 may be a combined circuit having a switch circuit and a charge and discharge circuit, and the specific structure is not limited.
EXAMPLE five
Based on the fourth embodiment, as shown in fig. 5, the switch energy storage circuit 40 optionally includes a fourth transistor K4 and a third capacitor C3;
the input end of the fourth transistor K4, the output end of the driving transistor Q1, the input end of the delay output circuit 20 and the output end of the second switch circuit 30 are interconnected, the output end of the fourth transistor K4 and the first end of the third capacitor C3 are connected in common to form the output end of the switch energy storage circuit 40, the second end of the third capacitor C3 is grounded, and the controlled end of the fourth transistor K4 is used for inputting the second scan signal S2 or the third scan signal.
In this embodiment, when the first transistor K1 is controlled to be turned on, the fourth transistor K4 is controlled to be turned on by receiving the corresponding scan signal and outputs the positive voltage VDD to the light emitting unit 2, the third capacitor C3 is synchronously charged, when the off-bias operation is performed, the third transistor K3 is controlled to be turned on after a fourth preset time delay, and outputs a third preset voltage for a third preset duration after the second preset duration, the comparator U1 outputs a first level signal for the third preset duration to the second transistor K2, the second transistor K2 is controlled to be turned on, at this time, in a third preset time period, the fourth transistor K4 is controlled to be turned off, the driving transistor Q1 is turned off and biased, and in a time period of returning to the original characteristic, the third capacitor C3 supplies power to the light emitting unit 2, the light emitting unit 2 continues to emit light, meanwhile, when the off-bias is ended, the fourth transistor K4 and the driving transistor Q1 are controlled to be turned on in synchronization.
According to the on-off time requirement, the types of the fourth transistor K4 and the third transistor K3 can be selected correspondingly, and corresponding scanning signals are input to trigger on or off respectively.
Alternatively, in an embodiment, the fourth transistor K4 is an N-type transistor, the fourth transistor K4 receives another third scan signal, and when the first transistor K1 is controlled to be turned on, the fourth transistor K4 receives the third scan signal and is controlled to be turned on, and outputs a positive voltage VDD to the light emitting unit 2, the third capacitor C3 is charged synchronously, when the off-bias operation is performed, the third transistor K3 is controlled to be turned on after a fourth preset duration, and outputs a third preset voltage for a third preset duration after a second preset duration, the comparator U1 outputs a first level signal for a third preset duration to the second transistor K2, the second transistor K2 is controlled to be turned on, and at this time, during the third preset duration, the fourth transistor K4 does not receive the third scan signal, is controlled to be turned off, the driving transistor Q1 is turned off and biased, and returns to the original characteristic duration, and the light emitting unit 2 is powered by the third capacitor C3, the light emitting unit 2 continues to emit light while the fourth transistor K4 and the driving transistor Q1 are controlled to be turned on in synchronization with each other after the off bias is ended.
In another embodiment, the fourth transistor K4 is a P-type transistor, and the controlled terminal of the fourth transistor K4 is connected to the controlled terminal of the third transistor K3.
When the first transistor K1 is controlled to be turned on, the fourth transistor K4 does not receive the second scan signal S2, the fourth transistor K4 is controlled to be turned on, and outputs a positive voltage VDD to the light emitting unit 2, the third capacitor C3 is synchronously charged, when the off-bias operation is performed, the third transistor K3 is controlled to be turned on after a fourth preset time delay, and outputs a third preset voltage for a third preset duration after the second preset duration, the comparator U1 outputs a first level signal for the third preset duration to the second transistor K2, the second transistor K2 is controlled to be turned on, at this time, in a third preset time period, the fourth transistor K4 is controlled to turn off without receiving the second scan signal S2, the driving transistor Q1 is turned off and biased to return to the original characteristic time period, the third capacitor C3 supplies power to the light emitting unit 2, the light emitting unit 2 continues to emit light, meanwhile, when the off-bias is ended, the fourth transistor K4 and the driving transistor Q1 are controlled to be turned on in synchronization.
EXAMPLE six
As shown in fig. 6, the present application further provides a display panel 100, where the display panel 100 includes a plurality of light emitting units 2 and a plurality of light emitting unit driving circuits 1, and the specific structure of the light emitting unit driving circuit 1 refers to the above embodiments, and since the display panel 100 adopts all technical solutions of all the above embodiments, at least all beneficial effects brought by the technical solutions of the above embodiments are achieved, and details are not repeated here. Wherein, each light-emitting unit 2 is respectively connected with a light-emitting unit driving circuit 1.
In this embodiment, the light emitting units 2 form a pixel unit, the plurality of light emitting units 2 are arranged in an array and correspondingly connected to the corresponding light emitting unit driving circuits 1 to form the display panel 100, and the light emitting units 2 are set to have different colors, so that different image information is displayed under the driving of the control module 200 and the light emitting unit driving circuits 1.
Optionally, the light emitting unit 2 is a Micro LED, the Micro LED constitutes a pixel, each pixel is addressable and independently driven to light, and the distance between pixels is reduced from millimeter level to micron level.
The control module 200 is connected to the display panel 100, so that the brightness of each Micro LED can be precisely controlled, and image display can be realized.
EXAMPLE seven
As shown in fig. 7, the display device includes a control module 200 and a display panel 100, and the specific structure of the display panel 100 refers to the above embodiments, and since the display device adopts all technical solutions of all the above embodiments, the display device at least has all beneficial effects brought by the technical solutions of the above embodiments, and details are not repeated herein. The control module 200 is correspondingly connected to the display panel 100.
In this embodiment, the control module 200 may be a corresponding control board, a control chip, etc. and a corresponding power module, the power module provides the positive voltage VDD required by the light emitting unit driving circuit 1, and the control module 200 provides the corresponding data signal Vdata and the scanning signal.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A light emitting cell driving circuit, comprising:
the light-emitting diode comprises a driving transistor, a first diode and a second diode, wherein the input end of the driving transistor is used for being connected with a positive voltage, the output end of the driving transistor is connected with a light-emitting unit, and the driving transistor is triggered and conducted by a first preset voltage;
the input end of the first switch circuit is used for inputting a data signal, the controlled end of the first switch circuit is used for inputting a first scanning signal, the output end of the first switch circuit is connected with the grid electrode of the driving transistor, and the first switch circuit is triggered by the first scanning signal to output the first preset voltage for a first preset duration;
the input end of the delay output circuit, the output end of the driving transistor and the light-emitting unit are interconnected, the controlled end of the delay output circuit is used for inputting a second scanning signal, the delay output circuit is triggered by the second scanning signal to delay a second preset time length and then outputs a first level signal of a third preset time length, and the time sum of the second preset time length and the third preset time length is less than or equal to the first preset time length;
and the input end of the second switch circuit is used for inputting the positive voltage, the output end of the second switch circuit is interconnected with the light-emitting unit, the output end of the driving transistor and the input end of the delay output circuit, and the second switch circuit is triggered to be conducted by the first level signal.
2. The light emitting cell driving circuit according to claim 1, wherein the first scan signal is input ahead of the second scan signal by a fourth preset period, a time sum of the second preset period, the third preset period, and the fourth preset period being less than or equal to the first preset period;
the delay output circuit includes:
the input end of the switching output circuit, the output end of the driving transistor and the light emitting unit are interconnected, the controlled end of the switching output circuit is used for inputting the second scanning signal, the switching output circuit is triggered by the second scanning signal to output a second preset voltage for a second preset duration, and triggers to output a third preset voltage for a third preset duration after the second preset duration, the second preset voltage is greater than or equal to a reference voltage, and the third preset voltage is less than the reference voltage;
the first input end of the voltage comparison circuit is connected with the output end of the switching output circuit, the second input end of the voltage comparison circuit is used for inputting the reference voltage, the output end of the voltage comparison circuit is connected with the controlled end of the second switch circuit, the voltage comparison circuit receives the second preset voltage and compares and outputs the second level signal, receives the third preset voltage and compares and outputs the first level signal, and the first level signal and the second level signal are level signals with opposite potentials.
3. The light-emitting-unit driving circuit according to claim 1, wherein the first switching circuit includes a first transistor and a first capacitor;
the input end of the first transistor is used for inputting the data signal, the output end of the first transistor and the first end of the first capacitor are interconnected to form the output end of the first switch circuit, the controlled end of the first transistor is used for inputting the first scanning signal, and the second end of the first capacitor is grounded.
4. The light emitting cell driving circuit according to claim 1, wherein the second switching circuit includes a second transistor, and an input terminal, an output terminal, and a controlled terminal of the second transistor constitute the input terminal, the output terminal, and the controlled terminal of the second switching circuit, respectively.
5. The light emitting cell drive circuit according to claim 2, wherein the switching output circuit includes a third transistor and a second capacitor;
the input end of the third transistor, the output end of the driving transistor and the light emitting unit are interconnected, the controlled end of the third transistor is used for inputting the second scanning signal, the output end of the third transistor and the first end of the second capacitor are interconnected to form the output end of the switching output circuit, and the second end of the second capacitor is grounded.
6. The light-emitting-unit driving circuit according to claim 2, wherein the voltage comparing circuit includes a comparator;
the positive phase input end of the comparator forms the first input end of the voltage comparison circuit, the negative phase input end of the comparator is used for inputting the reference voltage, and the output end of the comparator forms the output end of the voltage comparison circuit.
7. The light-emitting-unit driving circuit according to claim 2, further comprising:
the input end of the switch energy storage circuit, the output end of the driving transistor, the input end of the delay output circuit and the output end of the second switch circuit are interconnected, the output end of the switch energy storage circuit is connected with the light-emitting unit, and the controlled end of the switch energy storage circuit is used for inputting corresponding scanning signals;
and the switch energy storage circuit is triggered by a corresponding scanning signal, is synchronously switched on with the driving transistor, is charged and stores energy, and is triggered to be switched off and discharged within the third preset time.
8. The light-emitting cell drive circuit according to claim 7, wherein the switched tank circuit comprises a fourth transistor and a third capacitor;
the input end of the fourth transistor, the output end of the driving transistor, the input end of the delay output circuit and the output end of the second switch circuit are interconnected, the output end of the fourth transistor and the first end of the third capacitor are connected in common to form the output end of the switch energy storage circuit, the second end of the third capacitor is grounded, and the controlled end of the fourth transistor is used for inputting the second scanning signal or the third scanning signal.
9. A display panel comprising a plurality of light emitting cells and a plurality of light emitting cell driving circuits according to any one of claims 1 to 8, wherein each of the light emitting cells is connected to one of the light emitting cell driving circuits.
10. A display device comprising a control module and the display panel according to claim 9, wherein the control module is correspondingly connected with the display panel.
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