CN114564082B - Load card and load test system - Google Patents
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- CN114564082B CN114564082B CN202210076105.XA CN202210076105A CN114564082B CN 114564082 B CN114564082 B CN 114564082B CN 202210076105 A CN202210076105 A CN 202210076105A CN 114564082 B CN114564082 B CN 114564082B
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- 238000012360 testing method Methods 0.000 title claims abstract description 21
- 238000005070 sampling Methods 0.000 claims abstract description 6
- 230000005856 abnormality Effects 0.000 claims description 16
- 230000004044 response Effects 0.000 claims description 16
- 230000002159 abnormal effect Effects 0.000 claims description 6
- 230000003321 amplification Effects 0.000 abstract description 5
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 5
- 230000008859 change Effects 0.000 description 4
- 230000001276 controlling effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000014509 gene expression Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
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- 238000012986 modification Methods 0.000 description 2
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- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 230000005669 field effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/18—Packaging or power distribution
- G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
- G06F1/184—Mounting of motherboards
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/18—Packaging or power distribution
- G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
- G06F1/185—Mounting of expansion boards
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a load card, comprising: the grid electrode of each first MOS tube is used for receiving a control level, and the drain electrode is used for connecting the positive electrode of the voltage to be tested; one end of each resistor is connected with the source stage of one of the first MOS tubes, and the other end of each resistor is grounded; the two input ends of each first amplifier are connected with two ends of the resistor, and the two output ends are used as sampling output ends; the control unit is connected with each first amplifier and connected with the first receiving end; wherein the control unit is configured to detect a control level size received by the first receiving unit and to use the first amplifier of the corresponding multiple according to the control level size. The invention further provides a load test system. The invention controls and selects the amplifiers with different amplification factors to amplify the sampled voltage signals through detecting and controlling the level range, thereby ensuring that the output of the load can be controlled with the highest precision even if the load is not large.
Description
Technical Field
The invention relates to the field of load testing, in particular to a load card and a load testing system.
Background
With the rapid development of server performance, the diversity and structure of servers are also more complex. The server motherboard composition is also more cumbersome. Therefore, the test work for the main board is more and more complex, and the pull-load test precision requirement is higher and higher.
The integrity test of the power supply of the server main board can always keep the load at the back end at a certain level, or when the load changes according to certain conditions, a series of indexes such as output voltage change, loop stability, protection function realization and the like are seen. Therefore, in a more and more severe and more complex test process, improvement of the accuracy of the test has become a necessary trend.
In the prior art, when testing the dynamic stability of a power supply, an electronic load is generally used, and the electronic load is welded at the output end of the power supply to be tested through two pulling cables (power supply and ground). The electronic load is provided with a load test condition, then the load is carried out, and meanwhile, the stability of the voltage is monitored or the loop index is evaluated.
For some application environments with small loads and high requirements on the slope of load change, some power-stage MOS (field effect transistor) can be utilized, and the effect of regulating load current is achieved by controlling Vgs voltage (voltage between a grid electrode and a source electrode) to enable the voltage to work in a constant current area and changing the Vgs voltage.
The prior art has the following disadvantages:
(1) The electronic load is large, so that two long load lines are needed to pass through when the electronic load is used. The load slope of the test condition is affected due to the parasitic inductance of the load line;
(2) The performance limit of the electronic load, the load change slope is generally lower, and for the test of some core power supplies, the slope requirement of the integrity of the server power supply is hardly met by using the electronic load test;
(3) For a load card with special functions in industry, although the slope requirement can be met, the MOS number is fixed and the amplification factor is also fixed no matter how large the current is. Limited by the range, the accuracy of sensing the current cannot be ensured when the current is smaller;
(4) The load card has no abnormal early warning function, so that the load is overlarge or power failure is caused by carelessness, and the load card and the mainboard to be tested are required to be restarted.
Disclosure of Invention
In view of this, in order to overcome at least one aspect of the above-mentioned problems, an embodiment of the present invention proposes a load card, including:
the grid electrode of each first MOS tube is used for receiving a control level, and the drain electrode is used for connecting the positive electrode of the voltage to be tested;
one end of each resistor is connected with the source stage of one of the first MOS tubes, and the other end of each resistor is grounded;
the two input ends of each first amplifier are connected with two ends of the resistor, and the two output ends are used as sampling output ends;
the control unit is connected with each first amplifier and the first receiving end;
wherein the control unit is configured to detect a control level size received by the first receiving unit and use a first amplifier of a corresponding multiple according to the control level size.
In some embodiments, the control unit is further configured to:
in response to detecting that the control level is not less than a first threshold, using a first amplifier of a first multiple;
in response to detecting that the control level is greater than the first threshold and not less than the second threshold, using a first amplifier of a second multiple;
in response to detecting that the control level is greater than the second threshold and not less than the third threshold, using a first amplifier of a third multiple;
in response to detecting that the control level is greater than the third threshold and not less than the fourth threshold, a fourth multiple of the first amplifier is used.
In some embodiments, further comprising:
the drain electrode of the second MOS tube is used for receiving the control level, and the grid electrode of the second MOS tube is connected with the control unit;
the second amplifier is connected with the source stage of the second MOS tube and the grid electrode of each first MOS tube respectively so as to amplify the control level of the output of the second MOS tube and then input the amplified control level into the first MOS tube.
In some embodiments, further comprising:
the normal indicating unit comprises a plurality of indicating lamps, wherein each indicating lamp corresponds to one of the first amplifiers;
the normal indication unit is connected with the control unit and lights the corresponding indication lamp according to the control signal of the control unit.
In some embodiments, further comprising:
the early warning indication unit comprises an abnormal indication lamp and is connected with the control unit;
wherein the control unit is configured to generate a control signal to turn on the abnormality indicator when the control level is detected to be greater than a first threshold.
In some embodiments, further comprising:
the abnormality indication unit comprises an abnormality indication lamp and is connected with the control unit;
wherein the control unit is configured to generate a control signal to illuminate the abnormality indicator when the control level is detected to be greater than a second threshold, wherein the second threshold is greater than the first threshold.
In some embodiments, the control unit is further configured to close the second MOS transistor when the control level is detected to be greater than a second threshold.
In some embodiments, the second threshold is less than a Vgs threshold voltage of the first MOS transistor.
In some embodiments, the control unit includes a logic control chip and a management control chip connected to the logic control chip;
the logic control chip is connected with each first amplifier, and the management control chip is connected with the first receiving end.
Based on the same inventive concept, an embodiment of the present invention also proposes a load test system, including a load card as described in any one of the above embodiments.
The invention has one of the following beneficial technical effects: according to the scheme provided by the embodiment of the invention, the load card framework is formed by the hard disk backboard, the chassis backboard and the main board, so that the storage load card structure is simplified, the redundant cables are reduced, the long-distance storage can be realized, and the storage expandability and the sharability are improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are necessary for the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention and that other embodiments may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a load card according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
It should be noted that, in the embodiments of the present invention, all the expressions "first" and "second" are used to distinguish two entities with the same name but different entities or different parameters, and it is noted that the "first" and "second" are only used for convenience of expression, and should not be construed as limiting the embodiments of the present invention, and the following embodiments are not described one by one.
According to one aspect of the present invention, as shown in fig. 1, an embodiment of the present invention proposes a load card, where the load card includes a plurality of first MOS transistors (Q1-Q8), and a gate of each of the first MOS transistors (Q1-Q8) is configured to receive a control level (Vgs), and a drain is configured to connect to an anode of a voltage to be measured;
one end of each resistor (R1-R8) is connected with the source of one of the first MOS tubes, and the other end of each resistor is grounded;
the two input ends of each first amplifier are connected with two ends of the resistor, and the two output ends are used as sampling output ends;
the control unit is connected with each first amplifier and the first receiving end;
wherein the control unit is configured to detect a control level size received by the first receiving unit and use a first amplifier of a corresponding multiple according to the control level size.
According to the scheme provided by the invention, the sampled voltage signals are amplified by the amplifiers with different amplification factors through detecting the control level (Vgs voltage) range control, so that the output of a load can be controlled with the highest precision even if the load is not large.
In some embodiments, as shown in fig. 1, the first MOS transistors are Q1 to Q8, respectively, and Vgs voltages of the first MOS transistors are controlled in a constant current region, and a current flowing through the DS can be controlled by controlling the Vgs voltages. The S-stage of the first MOS tube is connected with a resistor, namely Q1-Q8 are respectively connected with R1-R8, a plurality of amplifiers with different multiples are connected with two ends of one resistor, the amplifiers amplify the differential pressure of the precision resistor obtained by sampling and output the differential pressure to an oscilloscope, and the current flowing through the first MOS tube is known through a voltage signal. In some embodiments, the resistances of the resistors may be equal, for example, each precision resistor is 2mΩ, and the multiple of the amplifier may be 1000 times, 500 times, 250 times, 125 times.
In some embodiments, the control unit is further configured to:
in response to detecting that the control level is not less than a first threshold, using a first amplifier of a first multiple;
in response to detecting that the control level is greater than the first threshold and not less than the second threshold, using a first amplifier of a second multiple;
in response to detecting that the control level is greater than the second threshold and not less than the third threshold, using a first amplifier of a third multiple;
in response to detecting that the control level is greater than the third threshold and not less than the fourth threshold, a fourth multiple of the first amplifier is used.
Specifically, the control unit controls the channel selection of the four-way amplifier according to the voltage conditions by monitoring the G pole voltages of Q1-Q8, and simultaneously controls the on-off of the corresponding signal indicating lamps by Q10-Q15. The management control chip monitors 5 reference levels, vlim, valert, vref, vref2 and Vref3, wherein the voltage of Vlim > Valert > Vref3> Vref2> Vref1 and the voltage of Vlim is reasonably set according to the relevant parameters of the power level MOS and is smaller than the Vgs threshold voltage of the fully conducted MOS, for example, 80% of the fully conducted Vgs threshold voltage can be selected as the Vlim.
In some embodiments, further comprising:
the drain electrode of the second MOS tube Q9 is used for receiving a control level, and the grid electrode of the second MOS tube Q9 is connected with the control unit;
the second amplifier is connected with the source stage of the second MOS tube and the grid electrode of each first MOS tube respectively so as to amplify the control level of the output of the second MOS tube and then input the amplified control level into the first MOS tube.
In some embodiments, further comprising:
the normal indicating unit comprises a plurality of indicating lamps, wherein each indicating lamp corresponds to one of the first amplifiers;
the normal indication unit is connected with the control unit and lights the corresponding indication lamp according to the control signal of the control unit.
In some embodiments, further comprising:
the early warning indication unit comprises an abnormal indication lamp and is connected with the control unit;
wherein the control unit is configured to generate a control signal to turn on the abnormality indicator when the control level is detected to be greater than a first threshold.
In some embodiments, further comprising:
the abnormality indication unit comprises an abnormality indication lamp and is connected with the control unit;
wherein the control unit is configured to generate a control signal to illuminate the abnormality indicator when the control level is detected to be greater than a second threshold, wherein the second threshold is greater than the first threshold.
In some embodiments, the control unit is further configured to close the second MOS transistor when the control level is detected to be greater than a second threshold.
In some embodiments, the second threshold is less than a Vgs threshold voltage of the first MOS transistor.
In some embodiments, the control unit includes a logic control chip and a management control chip connected to the logic control chip;
the logic control chip is connected with each first amplifier, and the management control chip is connected with the first receiving end.
Specifically, as shown in fig. 1, the positive and negative electrodes of VOUT (output voltage) are respectively welded at the output end of a power supply to be subjected to load test or at a current sink (current sink) point, then a load card and a main board to be tested are respectively powered on, and an oscilloscope probe is connected to a current sense end. After the load card is electrified, the external function signal generator gives a V-signal, the V-signal is fed to the Vgs of the first MOS tube after passing through the second amplifier, at the moment, because the V-signal is increased from a very small level, when sink current is smaller, the control unit detects the Vgs < Vref1, and the control unit controls the first amplifier of the X1000 to amplify a precision resistor voltage signal, meanwhile, the signal indicator L3 of the X1000 is lightened, and a tester is informed of measuring the voltage signal according to the ratio of 250mV/A to obtain a current value (the total resistance is 0.25mΩ and 0.25mΩ is 1000=250 mV).
When the external signal V-signal continues to increase and sink current also increases correspondingly, when Vgs is detected to be more than or equal to Vref1, the control unit controls the amplifier of X500 to amplify the precision resistor voltage signal, and meanwhile, the signal indicator lamp L4 of the X500 is turned on to inform a tester that the voltage signal can be measured according to the ratio of 125mV/A to obtain a current value (0.25 mΩ 500=125 mV).
When Vgs is detected to be more than or equal to Vref2, the control unit controls the amplifier of X250 to amplify the precision resistor voltage signal, meanwhile, the signal indicator lamp L5 of the X250 is turned on, and a tester is informed of measuring the voltage signal according to the ratio of 31.25mV/A to obtain a current value (0.25 mΩ×250=62.5 mV).
When Vgs is detected to be more than or equal to Vref3, the logic control chip can control an amplifier of X125 to amplify a precision resistor voltage signal, meanwhile, a signal indicator lamp L6 of the X125 is lightened, and a tester is informed of measuring the voltage signal according to the ratio of 31.25mV/A to obtain a current value (0.25 mΩ & lt125+ & gt=31.25 mV).
When the external signal V-signal continues to increase and Vgs is detected to be larger than or equal to Valert, the logic chip controls the early warning indicator lamp L1 to be turned on, and a tester needs to pay attention to slow adjustment of the voltage of the V-signal or terminate the test.
When the external signal V-signal continues to increase, vgs is detected to be more than or equal to Vlim, the logic chip controls Q9 to be turned off, no load is generated at the moment, the load card is protected, meanwhile, the abnormal indicator lamp L2 is lightened, a tester is informed of overcurrent protection, and the test process is forced to be terminated.
According to the scheme provided by the invention, the sampled voltage signals are amplified by detecting the Vgs voltage range and controlling and selecting the amplifiers with different amplification factors, so that the output of a load can be controlled with the highest precision even if the load is not large, meanwhile, a logic control circuit is added to indicate a channel with the amplification factors, and meanwhile, an early warning circuit and a protection circuit are added.
Therefore, the load is directly changed by adjusting the Vgs of the MOS, so that the load slope is basically matched with the set slope of the signal generator, and the problem that the load change slope cannot meet the requirement when the load current requirement is not large is effectively solved. And when the control current is smaller, a higher-magnification amplifier is used, so that the sense-to-current precision can be ensured. And two functional circuits are additionally arranged for early warning and protection, and the complex work such as power failure caused by too strong blind loading or incapability of being saturated when the load card needs to be restarted can be solved near the saturation early warning function.
According to the same inventive concept, the embodiment of the invention also provides a load test system, which comprises a load card, wherein the load card comprises a plurality of first MOS tubes, the grid electrode of each first MOS tube is used for receiving a control level, and the drain electrode is used for connecting the anode of the voltage to be tested;
one end of each resistor is connected with the source stage of one of the first MOS tubes, and the other end of each resistor is grounded;
the two input ends of each first amplifier are connected with two ends of the resistor, and the two output ends are used as sampling output ends;
the control unit is connected with each first amplifier and the first receiving end;
wherein the control unit is configured to detect a control level size received by the first receiving unit and use a first amplifier of a corresponding multiple according to the control level size.
In some embodiments, the control unit is further configured to:
in response to detecting that the control level is not less than a first threshold, using a first amplifier of a first multiple;
in response to detecting that the control level is greater than the first threshold and not less than the second threshold, using a first amplifier of a second multiple;
in response to detecting that the control level is greater than the second threshold and not less than the third threshold, using a first amplifier of a third multiple;
in response to detecting that the control level is greater than the third threshold and not less than the fourth threshold, a fourth multiple of the first amplifier is used.
In some embodiments, further comprising:
the drain electrode of the second MOS tube is used for receiving the control level, and the grid electrode of the second MOS tube is connected with the control unit;
the second amplifier is connected with the source stage of the second MOS tube and the grid electrode of each first MOS tube respectively so as to amplify the control level of the output of the second MOS tube and then input the amplified control level into the first MOS tube.
In some embodiments, further comprising:
the normal indicating unit comprises a plurality of indicating lamps, wherein each indicating lamp corresponds to one of the first amplifiers;
the normal indication unit is connected with the control unit and lights the corresponding indication lamp according to the control signal of the control unit.
In some embodiments, further comprising:
the early warning indication unit comprises an abnormal indication lamp and is connected with the control unit;
wherein the control unit is configured to generate a control signal to turn on the abnormality indicator when the control level is detected to be greater than a first threshold.
In some embodiments, further comprising:
the abnormality indication unit comprises an abnormality indication lamp and is connected with the control unit;
wherein the control unit is configured to generate a control signal to illuminate the abnormality indicator when the control level is detected to be greater than a second threshold, wherein the second threshold is greater than the first threshold.
In some embodiments, the control unit is further configured to close the second MOS transistor when the control level is detected to be greater than a second threshold.
In some embodiments, the second threshold is less than a Vgs threshold voltage of the first MOS transistor.
In some embodiments, the control unit includes a logic control chip and a management control chip connected to the logic control chip;
the logic control chip is connected with each first amplifier, and the management control chip is connected with the first receiving end.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and many other variations of the different aspects of the embodiments of the invention as described above exist, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.
Claims (5)
1. A load card, comprising:
the grid electrode of each first MOS tube is used for receiving a control level, and the drain electrode is used for connecting the positive electrode of the voltage to be tested;
one end of each resistor is connected with the source stage of one of the first MOS tubes, and the other end of each resistor is grounded;
the two input ends of each first amplifier are connected with two ends of the resistor, and the two output ends are used as sampling output ends;
the control unit is connected with each first amplifier and connected with the first receiving end;
wherein the control unit is configured to detect a control level size received by the first receiving unit and use a first amplifier of a corresponding multiple according to the control level size;
the control unit is further configured to:
in response to detecting that the control level is not less than a first threshold, using a first amplifier of a first multiple;
in response to detecting that the control level is greater than the first threshold and not less than the second threshold, using a first amplifier of a second multiple;
in response to detecting that the control level is greater than the second threshold and not less than the third threshold, using a first amplifier of a third multiple;
in response to detecting that the control level is greater than the third threshold and not less than the fourth threshold, using a fourth multiple of the first amplifier;
the load card further includes:
the drain electrode of the second MOS tube is used for receiving the control level, and the grid electrode of the second MOS tube is connected with the control unit;
the second amplifier is respectively connected with the source stage of the second MOS tube and the grid electrode of each first MOS tube so as to amplify the control level of the output of the second MOS tube and then input the amplified control level into the first MOS tube;
the normal indicating unit comprises a plurality of indicating lamps, wherein each indicating lamp corresponds to one of the first amplifiers;
the normal indication unit is connected with the control unit and lights a corresponding indication lamp according to a control signal of the control unit;
the early warning indication unit comprises an abnormal indication lamp and is connected with the control unit;
wherein the control unit is configured to generate a control signal to light the abnormality indicator when the control level is detected to be greater than a first threshold;
the abnormality indication unit comprises an abnormality indication lamp and is connected with the control unit;
wherein the control unit is configured to generate a control signal to illuminate the abnormality indicator when the control level is detected to be greater than a second threshold, wherein the second threshold is greater than the first threshold.
2. The load card of claim 1, wherein the control unit is further configured to turn off the second MOS transistor when the control level is detected to be greater than a second threshold.
3. The load card of claim 1, wherein the second threshold is less than a Vgs threshold voltage of the first MOS transistor.
4. The load card of claim 1, wherein the control unit comprises a logic control chip and a management control chip connected to the logic control chip;
the logic control chip is connected with each first amplifier, and the management control chip is connected with the first receiving end.
5. A load testing system comprising a load card according to any one of claims 1-4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210076105.XA CN114564082B (en) | 2022-01-23 | 2022-01-23 | Load card and load test system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210076105.XA CN114564082B (en) | 2022-01-23 | 2022-01-23 | Load card and load test system |
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| CN114564082A CN114564082A (en) | 2022-05-31 |
| CN114564082B true CN114564082B (en) | 2023-07-14 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9429629B1 (en) * | 2013-03-11 | 2016-08-30 | Magna-Power Electronics, Inc. | Electronic loads |
| CN205720464U (en) * | 2016-04-22 | 2016-11-23 | 苏州大学 | Electronic load device |
| CN108459645A (en) * | 2017-02-22 | 2018-08-28 | 苏州普源精电科技有限公司 | Constant current control loop and electronic load |
| CN109347312A (en) * | 2018-11-30 | 2019-02-15 | 常州拓晶照明科技有限公司 | A kind of electric source filter circuit integrated |
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2022
- 2022-01-23 CN CN202210076105.XA patent/CN114564082B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9429629B1 (en) * | 2013-03-11 | 2016-08-30 | Magna-Power Electronics, Inc. | Electronic loads |
| CN205720464U (en) * | 2016-04-22 | 2016-11-23 | 苏州大学 | Electronic load device |
| CN108459645A (en) * | 2017-02-22 | 2018-08-28 | 苏州普源精电科技有限公司 | Constant current control loop and electronic load |
| CN109347312A (en) * | 2018-11-30 | 2019-02-15 | 常州拓晶照明科技有限公司 | A kind of electric source filter circuit integrated |
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| CN114564082A (en) | 2022-05-31 |
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