CN114564082A - Load card and load test system - Google Patents
Load card and load test system Download PDFInfo
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- CN114564082A CN114564082A CN202210076105.XA CN202210076105A CN114564082A CN 114564082 A CN114564082 A CN 114564082A CN 202210076105 A CN202210076105 A CN 202210076105A CN 114564082 A CN114564082 A CN 114564082A
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- 238000012360 testing method Methods 0.000 title claims abstract description 21
- 238000005070 sampling Methods 0.000 claims abstract description 5
- 230000005856 abnormality Effects 0.000 claims description 15
- 230000004044 response Effects 0.000 claims description 13
- 230000002159 abnormal effect Effects 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 3
- 230000003321 amplification Effects 0.000 abstract description 7
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 7
- 230000008859 change Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/18—Packaging or power distribution
- G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
- G06F1/184—Mounting of motherboards
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/16—Constructional details or arrangements
- G06F1/18—Packaging or power distribution
- G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
- G06F1/185—Mounting of expansion boards
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a load card, comprising: the grid electrode of each first MOS tube is used for receiving a control level, and the drain electrode is used for connecting the anode of the voltage to be measured; one end of each resistor is connected with the source electrode of one of the first MOS tubes, and the other end of each resistor is grounded; the two input ends of each first amplifier are connected with the two ends of the resistor, and the two output ends of each first amplifier are used as sampling output ends; the control unit is connected with each first amplifier and connected with the first receiving end; the control unit is configured to detect the magnitude of the control level received by the first receiving end and use the first amplifier with the corresponding multiple according to the magnitude of the control level. The invention also provides a load testing system. The invention controls and selects amplifiers with different amplification factors to amplify the sampled voltage signals by detecting the control level range, thereby ensuring that the output of the load can be controlled with the highest precision even if the load is not large.
Description
Technical Field
The invention relates to the field of load testing, in particular to a load card and a load testing system.
Background
With the rapid development of server performance, the diversity and structure of the server are more complicated. The server motherboard assembly is also more cumbersome. Therefore, the test work for the mainboard is more and more complicated, and the requirement on the pull load test precision is higher and higher.
The integrity test of the power supply of the server mainboard can ensure that the load at the rear end is maintained at a certain level, or when the load changes according to certain conditions, a series of indexes such as output voltage change, loop stability, realization of a protection function and the like can be seen. Therefore, in the increasingly more rigorous and complicated testing process, the trend of improving the testing precision is inevitable.
In the prior art, when testing the dynamic stability of a power supply, an electronic load is generally used and is welded at the output end of the power supply to be tested through two pull-load cables (power supply and ground). The electronic load sets the test condition of the load, then loads the load, and simultaneously monitors the stability of the voltage or evaluates the loop index and the like.
For some application environments with small loads but high requirements on load change slope, some power stage MOS (field effect transistor) may be used to control the Vgs voltage (voltage between the gate and the source) to operate in the constant current region, so as to change the Vgs voltage to achieve the effect of regulating the load current.
The prior art has the following disadvantages:
(1) the electronic load is bulky and therefore must be used over two very long load lines. Due to the existence of the parasitic inductance of the load line, the load slope under the test condition is influenced;
(2) the performance of the electronic load is limited, the load change slope is generally lower, and for the test of core (core) power supplies, the slope requirement of the integrity of the power supply of the server is difficult to meet by using the electronic load test;
(3) although the slope requirement can be met for the load card with special functions in the industry, the number of the MOS is fixed no matter how large the current is, and the amplification factor is also fixed. The current is limited by the range, and when the current is small, the accuracy of sensing the current cannot be ensured;
(4) the load card has no abnormal early warning function, so that the load is too large or the load card is not cared about to cause power failure, and the load card and the mainboard to be tested need to be restarted.
Disclosure of Invention
In view of the above, in order to overcome at least one aspect of the above problems, an embodiment of the present invention provides a load card, including:
the grid electrode of each first MOS tube is used for receiving a control level, and the drain electrode is used for connecting the anode of a voltage to be measured;
one end of each resistor is connected with the source electrode of one of the first MOS tubes, and the other end of each resistor is grounded;
the two input ends of each first amplifier are connected with the two ends of the resistor, and the two output ends of each first amplifier are used as sampling output ends;
the control unit is connected with each first amplifier and connected with the first receiving end;
the control unit is configured to detect the magnitude of the control level received by the first receiving end and use the first amplifier with the corresponding multiple according to the magnitude of the control level.
In some embodiments, the control unit is further configured to:
in response to detecting that the control level is not less than a first threshold, using a first amplifier of a first multiple;
using a second multiple of the first amplifier in response to detecting that the control level is greater than the first threshold and not less than a second threshold;
responsive to detecting that the control level is greater than the second threshold and not less than a third threshold, using a third multiple of the first amplifier;
in response to detecting that the control level is greater than the third threshold and not less than the fourth threshold, using a fourth multiple of the first amplifier.
In some embodiments, further comprising:
the drain electrode of the second MOS tube is used for receiving a control level, and the grid electrode of the second MOS tube is connected with the control unit;
and the second amplifiers are respectively connected with the source stage of the second MOS tube and the grid electrode of each first MOS tube so as to amplify the control level output by the second MOS tube and then input the amplified control level to the first MOS tubes.
In some embodiments, further comprising:
a normal indicating unit including a plurality of indicator lamps, each of which corresponds to one of the first amplifiers;
and the normal indicating unit is connected with the control unit and lights the corresponding indicating lamp according to the control signal of the control unit.
In some embodiments, further comprising:
the early warning indicating unit comprises an abnormal indicating lamp and is connected with the control unit;
wherein the control unit is configured to generate a control signal to light the abnormality indicator lamp when detecting that the control level is greater than a first threshold.
In some embodiments, further comprising:
the abnormality indicating unit comprises an abnormality indicating lamp and is connected with the control unit;
wherein the control unit is configured to generate a control signal to light the abnormality indicator lamp when detecting that the control level is greater than a second threshold value, wherein the second threshold value is greater than the first threshold value.
In some embodiments, the control unit is further configured to turn off the second MOS transistor when detecting that the control level is greater than a second threshold.
In some embodiments, the second threshold is less than a Vgs threshold voltage of the first MOS transistor.
In some embodiments, the control unit comprises a logic control chip and a management control chip connected with the logic control chip;
the logic control chip is connected with each first amplifier, and the management control chip is connected with the first receiving end.
Based on the same inventive concept, an embodiment of the present invention further provides a load testing system, including the load card according to any one of the above embodiments.
The invention has one of the following beneficial technical effects: according to the scheme provided by the embodiment of the invention, the load card framework is formed by the hard disk backboard, the chassis backboard and the mainboard, so that the structure of the storage load card is simplified, the redundant cables are reduced, the remote storage can be realized, and the storage expandability and the sharability are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a load card according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
According to an aspect of the present invention, an embodiment of the present invention provides a load card, as shown in fig. 1, the load card includes a plurality of first MOS transistors (Q1-Q8), a gate of each of the first MOS transistors (Q1-Q8) is configured to receive a control level (Vgs), and a drain is configured to connect a positive electrode of a voltage to be measured;
a plurality of resistors (R1-R8), one end of each resistor is connected with the source of one of the first MOS tubes, and the other end of each resistor is grounded;
the two input ends of each first amplifier are connected with the two ends of the resistor, and the two output ends of each first amplifier are used as sampling output ends;
the control unit is connected with each first amplifier and connected with the first receiving end;
the control unit is configured to detect the magnitude of the control level received by the first receiving end and use the first amplifier with the corresponding multiple according to the magnitude of the control level.
The scheme provided by the invention controls and selects amplifiers with different amplification factors to amplify the sampled voltage signals by detecting the range of the control level (Vgs voltage), thereby ensuring that the output of the load can be controlled with the highest precision even if the load is not large.
In some embodiments, as shown in fig. 1, the first MOS transistors are Q1-Q8, respectively, the Vgs voltage of the first MOS transistor is controlled in the constant current region, and the current flowing through the DS can be controlled by controlling the voltage of the Vgs. The S-stage of the first MOS tube is connected with a resistor, namely Q1-Q8 are respectively connected with R1-R8, a plurality of amplifiers with different multiples are connected with two ends of one resistor, the amplifier amplifies the voltage difference of the sampled precise resistor and outputs the amplified voltage difference to an oscilloscope, and the current flowing through the first MOS tube is known through a voltage signal. In some embodiments, the resistances of the resistors may be equal, for example, each precision resistor is 2m Ω, and the multiple of the amplifier may be 1000 times, 500 times, 250 times, 125 times.
In some embodiments, the control unit is further configured to:
in response to detecting that the control level is not less than a first threshold, using a first amplifier of a first multiple;
using a second multiple of the first amplifier in response to detecting that the control level is greater than the first threshold and not less than a second threshold;
responsive to detecting that the control level is greater than the second threshold and not less than a third threshold, using a third multiple of the first amplifier;
in response to detecting that the control level is greater than the third threshold and not less than a fourth threshold, using a fourth multiple of the first amplifier.
Specifically, the control unit controls the channel selection of the four-way amplifier by monitoring the G voltage of Q1-Q8 according to the voltage condition, and controls the on and off of the corresponding signal indicator lamp by Q10-Q15. The management control chip monitors 5 reference levels, namely Vlim, Valert, Vref1, Vref2 and Vref3, wherein Vlim > Valert > Vref3> Vref2> Vref1, the voltage of Vlim is reasonably set according to relevant parameters of the power stage MOS and is smaller than the Vgs threshold voltage of the MOS which is fully turned on, and for example, 80% of the fully turned on Vgs threshold voltage can be selected as Vlim.
In some embodiments, further comprising:
a second MOS transistor Q9, a drain of the second MOS transistor Q9 is configured to receive a control level, and a gate thereof is connected to the control unit;
and the second amplifiers are respectively connected with the source stage of the second MOS tube and the grid electrode of each first MOS tube so as to amplify the control level output by the second MOS tube and then input the amplified control level to the first MOS tubes.
In some embodiments, further comprising:
a normal indicating unit including a plurality of indicator lamps, each of which corresponds to one of the first amplifiers;
and the normal indicating unit is connected with the control unit and lights the corresponding indicating lamp according to the control signal of the control unit.
In some embodiments, further comprising:
the early warning indicating unit comprises an abnormal indicating lamp and is connected with the control unit;
wherein the control unit is configured to generate a control signal to light the abnormality indicator lamp when detecting that the control level is greater than a first threshold.
In some embodiments, further comprising:
the abnormality indicating unit comprises an abnormality indicating lamp and is connected with the control unit;
wherein the control unit is configured to generate a control signal to light the abnormality indicator lamp when detecting that the control level is greater than a second threshold value, wherein the second threshold value is greater than the first threshold value.
In some embodiments, the control unit is further configured to turn off the second MOS transistor when detecting that the control level is greater than a second threshold.
In some embodiments, the second threshold is less than a Vgs threshold voltage of the first MOS transistor.
In some embodiments, the control unit comprises a logic control chip and a management control chip connected with the logic control chip;
the logic control chip is connected with each first amplifier, and the management control chip is connected with the first receiving end.
Specifically, as shown in fig. 1, the positive electrode and the negative electrode of VOUT (output voltage) are respectively welded to the output end of the power supply to be subjected to the load test or the current sink point, then the load card and the main board to be tested are respectively powered on, and the oscilloscope probe is connected to the current sense end. After the load card is powered on, the external function signal generator provides a V-signal, the V-signal passes through the second amplifier and then is provided for Vgs of the first MOS tube, at the moment, the V-signal is increased from a very small level, the control unit detects that Vgs is less than Vref1 when the sink current is relatively small, the control unit controls the first amplifier of X1000 to be used for amplification of a precise resistance voltage signal, meanwhile, the signal indicator lamp L3 of the path of X1000 is lightened, and a tester is informed of obtaining a current value by measuring a voltage signal according to the ratio of 250mV/A (each resistance is 2m omega, the total resistance is 0.25m omega, and 0.25m omega is 1000 mV).
When the external signal V-signal continues to increase and the sink current correspondingly increases, when Vgs is detected to be larger than or equal to Vref1, the control unit controls the amplifier of X500 to amplify a precision resistor voltage signal, and meanwhile, the signal indicator lamp L4 of the path X500 lights up, so that a tester is informed of measuring a voltage signal according to the ratio of 125mV/A to obtain a current value (0.25m Ω 500-125 mV).
When Vgs is detected to be larger than or equal to Vref2, the control unit controls the amplifier of X250 to amplify a precision resistance voltage signal, and simultaneously, the signal indicator lamp L5 of the path X250 lights up, so that a tester is informed to measure a voltage signal according to the ratio of 31.25mV/A to obtain a current value (0.25m Ω 250-62.5 mV).
When Vgs is detected to be larger than or equal to Vref3, the logic control chip controls the amplifier of X125 to amplify a precise resistance voltage signal, and at the same time, the signal indicator lamp L6 of the path X125 lights up, so that the tester can obtain the current value by measuring the voltage signal according to the ratio of 31.25mV/A (0.25m omega 125-31.25 mV).
When the external signal V-signal continues to increase and Vgs is detected to be larger than or equal to Valert, the logic chip controls the early warning indicator lamp L1 to light up, and a tester needs to pay attention to slowly adjust the voltage of the V-signal or terminate the test.
When the external signal V-signal is continuously increased and Vgs is detected to be larger than or equal to Vlim, the logic chip controls Q9 to be turned off, no load exists at the moment, the load card is protected, meanwhile, the abnormal indicator lamp L2 is turned on, the tester is informed that overcurrent protection is performed, and the test process is forced to be terminated.
The scheme provided by the invention controls and selects amplifiers with different amplification factors to amplify and sample voltage signals by detecting the Vgs voltage range, ensures that the output of the load can be controlled with highest precision even if the load is not large, and simultaneously increases a logic control circuit to indicate channels of the amplification factors and simultaneously increases two function circuits of early warning and protection.
Therefore, the load is directly changed by adjusting Vgs of the MOS, so that the load slope basically matches with the set slope of the signal generator, and the problem that the load change slope cannot meet the requirement when the load current requirement is not large is effectively solved. And when the control current is smaller, an amplifier with higher amplification factor is used, so that the accuracy from the sense to the current can be ensured. And an early warning and protection function circuit is added, and a saturation early warning function is approached, so that the power failure problem caused by blind loading too hard or saturation only when not known can be solved, and the complex work such as restarting a load card is required.
According to the same inventive concept, an embodiment of the present invention further provides a load testing system, including a load card, where the load card includes a plurality of first MOS transistors, a gate of each of the first MOS transistors is used for receiving a control level, and a drain is used for connecting an anode of a voltage to be tested;
one end of each resistor is connected with the source electrode of one of the first MOS tubes, and the other end of each resistor is grounded;
the two input ends of each first amplifier are connected with the two ends of the resistor, and the two output ends of each first amplifier are used as sampling output ends;
the control unit is connected with each first amplifier and connected with the first receiving end;
the control unit is configured to detect the magnitude of the control level received by the first receiving end and use the first amplifier with the corresponding multiple according to the magnitude of the control level.
In some embodiments, the control unit is further configured to:
in response to detecting that the control level is not less than a first threshold, using a first amplifier of a first multiple;
in response to detecting that the control level is greater than the first threshold and not less than the second threshold, using a second multiple of the first amplifier;
responsive to detecting that the control level is greater than the second threshold and not less than a third threshold, using a third multiple of the first amplifier;
in response to detecting that the control level is greater than the third threshold and not less than a fourth threshold, using a fourth multiple of the first amplifier.
In some embodiments, further comprising:
the drain of the second MOS tube is used for receiving a control level, and the grid of the second MOS tube is connected with the control unit;
and the second amplifiers are respectively connected with the source stage of the second MOS tube and the grid electrode of each first MOS tube so as to amplify the control level output by the second MOS tube and then input the amplified control level to the first MOS tubes.
In some embodiments, further comprising:
a normal indicating unit including a plurality of indicator lamps, each of which corresponds to one of the first amplifiers;
and the normal indicating unit is connected with the control unit and lights the corresponding indicating lamp according to the control signal of the control unit.
In some embodiments, further comprising:
the early warning indicating unit comprises an abnormal indicating lamp and is connected with the control unit;
wherein the control unit is configured to generate a control signal to light the abnormality indicator lamp when detecting that the control level is greater than a first threshold.
In some embodiments, further comprising:
the abnormality indicating unit comprises an abnormality indicating lamp and is connected with the control unit;
wherein the control unit is configured to generate a control signal to illuminate the abnormal indicator light when detecting that the control level is greater than a second threshold, wherein the second threshold is greater than the first threshold.
In some embodiments, the control unit is further configured to turn off the second MOS transistor when detecting that the control level is greater than a second threshold.
In some embodiments, the second threshold is less than a Vgs threshold voltage of the first MOS transistor.
In some embodiments, the control unit comprises a logic control chip and a management control chip connected with the logic control chip;
the logic control chip is connected with each first amplifier, and the management control chip is connected with the first receiving end.
The foregoing are exemplary embodiments of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A load card, comprising:
the grid electrode of each first MOS tube is used for receiving a control level, and the drain electrode is used for connecting the anode of a voltage to be measured;
one end of each resistor is connected with the source electrode of one of the first MOS tubes, and the other end of each resistor is grounded;
a plurality of first amplifiers with different multiples, wherein two input ends of each first amplifier are connected with two ends of the resistor, and two output ends of each first amplifier are used as sampling output ends;
the control unit is connected with each first amplifier and connected with the first receiving end;
the control unit is configured to detect the magnitude of the control level received by the first receiving end and use the first amplifier with the corresponding multiple according to the magnitude of the control level.
2. The method of claim 1, wherein the control unit is further configured to:
in response to detecting that the control level is not less than a first threshold, using a first amplifier of a first multiple;
in response to detecting that the control level is greater than the first threshold and not less than the second threshold, using a second multiple of the first amplifier;
in response to detecting that the control level is greater than the second threshold and not less than a third threshold, using a third multiple of the first amplifier;
in response to detecting that the control level is greater than the third threshold and not less than a fourth threshold, using a fourth multiple of the first amplifier.
3. The load card of claim 1, further comprising:
the drain electrode of the second MOS tube is used for receiving a control level, and the grid electrode of the second MOS tube is connected with the control unit;
and the second amplifiers are respectively connected with the source stage of the second MOS tube and the grid electrode of each first MOS tube so as to amplify the control level output by the second MOS tube and then input the amplified control level to the first MOS tubes.
4. The load card of claim 1, further comprising:
a normal indicating unit including a plurality of indicator lamps, each of which corresponds to one of the first amplifiers;
and the normal indicating unit is connected with the control unit and lights the corresponding indicating lamp according to the control signal of the control unit.
5. The load card of claim 1, further comprising:
the early warning indicating unit comprises an abnormal indicating lamp and is connected with the control unit;
wherein the control unit is configured to generate a control signal to light the abnormality indicator lamp when detecting that the control level is greater than a first threshold.
6. The load card of claim 3, further comprising:
the abnormality indicating unit comprises an abnormality indicating lamp and is connected with the control unit;
wherein the control unit is configured to generate a control signal to light the abnormality indicator lamp when detecting that the control level is greater than a second threshold value, wherein the second threshold value is greater than the first threshold value.
7. The load card of claim 6, wherein the control unit is further configured to turn off the second MOS transistor when detecting that the control level is greater than a second threshold.
8. The load card of claim 6, wherein the second threshold is less than a Vgs threshold voltage of the first MOS transistor.
9. The load card of claim 1, wherein the control unit comprises a logic control chip and a management control chip connected to the logic control chip;
the logic control chip is connected with each first amplifier, and the management control chip is connected with the first receiving end.
10. A load testing system comprising a load card according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210076105.XA CN114564082B (en) | 2022-01-23 | 2022-01-23 | Load card and load test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210076105.XA CN114564082B (en) | 2022-01-23 | 2022-01-23 | Load card and load test system |
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| CN114564082B CN114564082B (en) | 2023-07-14 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9429629B1 (en) * | 2013-03-11 | 2016-08-30 | Magna-Power Electronics, Inc. | Electronic loads |
| CN205720464U (en) * | 2016-04-22 | 2016-11-23 | 苏州大学 | Electronic load device |
| CN108459645A (en) * | 2017-02-22 | 2018-08-28 | 苏州普源精电科技有限公司 | Constant current control loop and electronic load |
| CN109347312A (en) * | 2018-11-30 | 2019-02-15 | 常州拓晶照明科技有限公司 | A kind of electric source filter circuit integrated |
-
2022
- 2022-01-23 CN CN202210076105.XA patent/CN114564082B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9429629B1 (en) * | 2013-03-11 | 2016-08-30 | Magna-Power Electronics, Inc. | Electronic loads |
| CN205720464U (en) * | 2016-04-22 | 2016-11-23 | 苏州大学 | Electronic load device |
| CN108459645A (en) * | 2017-02-22 | 2018-08-28 | 苏州普源精电科技有限公司 | Constant current control loop and electronic load |
| CN109347312A (en) * | 2018-11-30 | 2019-02-15 | 常州拓晶照明科技有限公司 | A kind of electric source filter circuit integrated |
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| CN114564082B (en) | 2023-07-14 |
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