CN114554705A

CN114554705A - Circuit board and preparation method thereof

Info

Publication number: CN114554705A
Application number: CN202011331849.9A
Authority: CN
Inventors: 钟仕杰; 刘瑞武
Original assignee: Avary Holding Shenzhen Co Ltd; Qing Ding Precision Electronics Huaian Co Ltd
Current assignee: Avary Holding Shenzhen Co Ltd; Qing Ding Precision Electronics Huaian Co Ltd
Priority date: 2020-11-24
Filing date: 2020-11-24
Publication date: 2022-05-27

Abstract

The application provides a circuit board and a preparation method thereof. The preparation method comprises the following steps: providing a double-sided copper-clad substrate, wherein the double-sided copper-clad substrate comprises a base layer, a first copper foil and a second copper foil, and the first copper foil and the second copper foil are respectively arranged on two opposite surfaces of the base layer; etching a portion of the first copper foil to obtain a copper foil layer; electroplating on the copper foil layer to form an electroplated layer, wherein the copper foil layer and the electroplated layer jointly form a reinforcing plate; laminating an adhesive layer, an insulating layer and a third copper foil on the surface of the base layer with the reinforcing plate; etching the third copper foil and the second copper foil to obtain a first conductive circuit layer and a second conductive circuit layer, wherein the first conductive circuit layer comprises a first welding pad, the second conductive circuit layer comprises a second welding pad, and the first welding pad and the second welding pad correspond to the reinforcing plate in position; and respectively mounting a first electronic element and a second electronic element on the first bonding pad and the second bonding pad. The electronic components can be arranged on two sides of the same area of the circuit board.

Description

Circuit board and preparation method thereof

Technical Field

The application relates to the field of circuit board preparation, in particular to a circuit board with electronic elements pasted on two sides and a preparation method thereof.

Background

Along with the increasing lightness, thinness and multifunctionality of electronic products, the integration level of the flexible circuit board is higher and higher, so that electronic components are often required to be welded on the two sides of the flexible circuit board.

However, if electronic components need to be soldered on both sides of the same region of the flexible printed circuit board, the surface of the region cannot be provided with the reinforcing plate, so that the flatness and rigidity of the region are poor, and the problems of empty soldering and the like are easy to occur during subsequent soldering of the electronic components. On the other hand, if the requirements on the flatness and rigidity of the circuit board are high, electronic components cannot be welded on two sides of the same area, and at the moment, the electronic components need to be arranged on the surface of the circuit board in a staggered mode, so that the space utilization rate of the circuit board is reduced.

Disclosure of Invention

In order to solve at least one of the above disadvantages of the prior art, it is necessary to provide a method for manufacturing a circuit board and a circuit board manufactured by the method.

The application provides a preparation method of a circuit board, which comprises the following steps: providing a double-sided copper-clad substrate, wherein the double-sided copper-clad substrate comprises a base layer, a first copper foil and a second copper foil, and the first copper foil and the second copper foil are respectively arranged on two opposite surfaces of the base layer; etching a portion of the first copper foil to obtain a copper foil layer; electroplating on the copper foil layer to form an electroplated layer, wherein the copper foil layer and the electroplated layer jointly form a reinforcing plate; laminating an adhesive layer, an insulating layer and a third copper foil on the surface of the base layer with the reinforcing plate; etching the third copper foil and the second copper foil to obtain a first conductive circuit layer and a second conductive circuit layer, wherein the first conductive circuit layer comprises two first welding pads, the second conductive circuit layer comprises two second welding pads, and the first welding pads and the second welding pads correspond to the reinforcing plate in position; and respectively mounting a first electronic element and a second electronic element on the first welding pad and the second welding pad to obtain the circuit board.

In some possible implementations, before mounting the first electronic component and the second electronic component, the manufacturing method further includes the steps of: forming a first protective layer and a second protective layer on the first conductive circuit layer and the second conductive circuit layer respectively to obtain a circuit substrate; part of the first conductive circuit layer is exposed out of the first protective layer to form the first bonding pad, and part of the second conductive circuit layer is exposed out of the second protective layer to form the second bonding pad.

In some possible implementations, the circuit substrate forms a first mounting region of the first electronic component in a region corresponding to the two first pads, forms a second mounting region of the second electronic component in a region corresponding to the two second pads, and both a vertical projection of the first mounting region on the reinforcing plate and a vertical projection of the second mounting region on the reinforcing plate are located within a range of the reinforcing plate.

In some possible implementations, the plating layer is made of one material selected from copper, beryllium, molybdenum, tungsten, and osmium, and the first mounting region and the second mounting region each have a stiffness greater than or equal to 3.2N/mm.

In some possible implementations, etching a portion of the first copper foil to obtain a copper foil layer specifically includes the steps of: covering a first dry film and a second dry film on the first copper foil and the second copper foil respectively, wherein the first dry film covers part of the surface of the first copper foil, and the second dry film covers the whole surface of the second copper foil; etching the first copper foil which is not covered by the first dry film by using the first dry film as a photomask in an exposure and development mode to obtain the copper foil layer; removing the first dry film and the second dry film.

The application also provides a circuit board, including the circuit base plate, the circuit base plate is including the first conducting wire layer, insulating layer, adhesive layer, basic unit and the second conducting wire layer of folding in proper order and establishing. The first conductive trace layer includes two first pads, and the second conductive trace layer includes two second pads. The circuit substrate further comprises a reinforcing plate arranged on the surface of the base layer far away from the second conductive circuit layer, the adhesive layer coats the reinforcing plate, the reinforcing plate comprises a copper foil layer and an electroplated layer, and the copper foil layer is located between the electroplated layer and the base layer. The first welding pad and the second welding pad correspond to the reinforcing plate in position. The circuit board further comprises a first electronic element and a second electronic element, wherein the first electronic element and the second electronic element are respectively arranged on the first bonding pad and the second bonding pad.

In some possible implementation manners, the circuit substrate further includes a first protection layer and a second protection layer respectively disposed on the first conductive circuit layer and the second conductive circuit layer, a portion of the first conductive circuit layer is exposed to the first protection layer to form the first bonding pad, and a portion of the second conductive circuit layer is exposed to the second protection layer to form the second bonding pad.

In some possible implementations, along the extending direction of the base layer, the difference between the width of the reinforcing plate and the width of the first mounting region is greater than 80 micrometers, and the difference between the width of the reinforcing plate and the width of the second mounting region is greater than 80 micrometers.

Compared with the prior art, the reinforcing plate consisting of the copper foil layer and the electroplated layer is embedded between the base layer and the adhesive layer, so that the flatness and the rigidity of the area of the circuit board corresponding to the reinforcing plate are improved. Moreover, electronic elements can be arranged on the two sides of the same area of the circuit board, the situation that the electronic elements are required to be arranged on the surface of the circuit board in a staggered mode due to the fact that reinforcing plates are arranged on the surface of the circuit board is avoided, and the space utilization rate and the surface mounting density are improved.

Drawings

Fig. 1 is a schematic cross-sectional view of a double-sided copper-clad substrate according to an embodiment of the present disclosure.

Fig. 2 is a schematic cross-sectional view of the double-sided copper-clad substrate shown in fig. 1 after a first dry film and a second dry film are coated thereon.

Fig. 3 is a schematic cross-sectional view illustrating the first copper foil shown in fig. 2 etched to obtain a copper foil layer.

Fig. 4 is a schematic cross-sectional view of the copper foil layer and the second copper foil shown in fig. 3 covered with a third dry film and a fourth dry film, respectively.

Fig. 5 is a schematic cross-sectional view of a reinforcing plate obtained by forming a plating layer on the copper foil layer shown in fig. 4.

Fig. 6 is a schematic cross-sectional view of the reinforcing plate shown in fig. 5 after the adhesive layer, the insulating layer and the third copper foil are laminated thereon.

Fig. 7 is a schematic cross-sectional view of the third copper foil and the second copper foil shown in fig. 6 covered with a fifth dry film and a sixth dry film, respectively.

Fig. 8 is a schematic cross-sectional view of the third copper foil and the second copper foil shown in fig. 7 after etching to obtain the first conductive trace layer and the second conductive trace layer.

Fig. 9 is a schematic cross-sectional view illustrating a first protective layer and a second protective layer formed on the first conductive trace layer and the second conductive trace layer shown in fig. 8, respectively.

Fig. 10 is a schematic cross-sectional view of a wiring board obtained after mounting a first electronic component and a second electronic component on the first conductive wiring layer and the second conductive wiring layer shown in fig. 9, respectively.

Description of the main elements

Double-sided copper-clad substrate 10

Base layer 11

First copper foil 12

Second copper foil 13

Copper foil layer 14

Plating layer 15

Reinforcing plate 16

First dry film 20

Second dry film 21

Third dry film 30

Fourth dry film 31

Adhesive layer 40

Insulating layer 41

Third copper foil 42

First conductive trace layer 50

Second conductive trace layer 51

Fifth dry film 60

Sixth dry film 61

First protective layer 70

Second protective layer 71

First electronic component 80

Second electronic component 81

Conductive layer 82

Wiring board 100

Circuit board 101

Openings

300, 600, 610

First bonding pad 500

First mounting area 501

Second bonding pad 510

Second mounting region 511

First region 1010

Widths W1, W2, W3, W4

Thickness H

The following detailed description will further illustrate the present application in conjunction with the above-described figures.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

To further explain the technical means and effects of the present application for achieving the intended purpose, the following detailed description is given to the present application in conjunction with the accompanying drawings and preferred embodiments.

The application provides a preparation method of a circuit board, which comprises the following steps:

s1, please refer to fig. 1, a double-sided copper-clad substrate 10 is provided. The double-sided copper-clad substrate 10 includes a base layer 11, and a first copper foil 12 and a second copper foil 13 respectively disposed on opposite surfaces of the base layer 11.

In one embodiment, the material of the base layer 11 is an insulating resin, and specifically, the material of the base layer 11 may be one selected from epoxy resin (epoxy resin), polypropylene (PP), BT resin, polyphenylene Oxide (PPO), polypropylene (PP), Polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and the like.

S2, referring to fig. 2 and 3, a portion of the first copper foil 12 is etched to obtain the copper foil layer 14.

In one embodiment, as shown in fig. 2, first, a first dry film 20 and a second dry film 21 are coated on a first copper foil 12 and a second copper foil 13, respectively. The first dry film 20 covers a part of the surface of the first copper foil 12, and the second dry film 21 covers the entire surface of the second copper foil 13.

As shown in fig. 3, the first copper foil 12 not covered by the first dry film 20 is etched by exposure and development using the first dry film 20 as a mask, thereby obtaining the copper foil layer 14. Then, the first dry film 20 and the second dry film 21 are removed.

Specifically, since the first dry film 20 covers a part of the surface of the first copper foil 12 and the second dry film 21 covers the entire surface of the second copper foil 13, the covered part of the first copper foil 12 and the entire second copper foil 13 are left after exposure development. And the remaining first copper foil 12 not covered with the first dry film 20 is removed after exposure and development.

In one embodiment, the number of copper foil layers 14 is one. It is to be understood that the number of copper foil layers 14 is not limited to one, and may be set according to the number of electronic components to be mounted subsequently on the substrate 11 side.

S3, referring to fig. 4 and 5, a plating layer 15 is formed on the copper foil layer 14 by plating, and the copper foil layer 14 and the plating layer 15 together form the reinforcing plate 16.

In one embodiment, as shown in fig. 4, a third dry film 30 is first coated on the base layer 11 having the copper foil layer 14, and a fourth dry film 31 is coated on the second copper foil 13. Wherein the third dry film 30 has an opening 300 for exposing the copper foil, and the fourth dry film 31 covers the entire surface of the second copper foil 13. As shown in fig. 5, copper is then electroplated in the opening 300, thereby forming a plating layer 15. Since the fourth dry film 31 covers the entire surface of the second copper foil 13, the plating layer 15 is not formed on the second copper foil 13. Then, the third dry film 30 and the fourth dry film 31 are removed.

In one embodiment, the width W2 of the plating layer 15 may be equal to or slightly less than the width W1 of the copper foil layer 14 along the extending direction of the base layer 11. As shown in fig. 4, in the present embodiment, the width W2 of the plating layer 15 is slightly smaller than the width W1 of the copper foil layer 14, that is, the width of the opening 300 is slightly smaller than the width W1 of the copper foil layer 14.

The plating layer 15 is provided to increase the total thickness H of the reinforcing plate 16. The cross-sectional shape of the plating layer 15 may be square. However, it is understood that in other embodiments, the cross-sectional shape of the plated layer 15 is not limited to a square shape, and may be correspondingly configured according to the shape of the electronic component to be mounted later.

In another embodiment, the material of the plating layer 15 is not limited to copper, and may be obtained by plating a metal having a higher young's modulus. For example, the material of the plating layer 15 may include one of beryllium, molybdenum, tungsten, and osmium.

S4, referring to fig. 6, the adhesive layer 40, the insulating layer 41 and the third copper foil 42 are laminated on the surface of the base layer 11 with the reinforcing plate 16. The insulating layer 41 is located between the adhesive layer 40 and the third copper foil 42.

In one embodiment, the material of the insulating layer 41 is an insulating resin, and specifically, the material of the insulating layer 41 may be one selected from resins such as epoxy resin, polypropylene, BT resin, polyphenylene ether, polypropylene, polyimide, polyethylene terephthalate, and polyethylene naphthalate. The material of the insulating layer 41 may be the same as that of the base layer 11.

S5, referring to fig. 7 and 8, the third copper foil 42 and the second copper foil 13 are etched by an exposure and development process to obtain the first conductive trace layer 50 and the second conductive trace layer 51.

In one embodiment, as shown in fig. 7, first, a fifth dry film 60 and a sixth dry film 61 are coated on the third copper foil 42 and the second copper foil 13, respectively. The fifth dry film 60 and the sixth dry film 61 have

openings

600, 610 for exposing the third copper foil 42 and the second copper foil 13, respectively. Then, as shown in fig. 8, the third copper foil 42 and the second copper foil 13 are exposed and developed by using the fifth dry film 60 and the sixth dry film 61 as masks, so that the third copper foil 42 exposed to the opening 600 of the fifth dry film 60 and the second copper foil 13 exposed to the opening 610 of the sixth dry film 61 are etched, thereby obtaining the first conductive trace layer 50 and the second conductive trace layer 51. Then, the fifth dry film 60 and the sixth dry film 61 are removed.

S6, referring to fig. 9, a first passivation layer 70 and a second passivation layer 71 are formed on the first conductive trace layer 50 and the second conductive trace layer 51, respectively, to obtain the circuit substrate 101. Wherein, a portion of the first conductive trace layer 50 is exposed to the first passivation layer 70 to form two first bonding pads 500, and a portion of the second conductive trace layer 51 is exposed to the second passivation layer 71 to form two second bonding pads 510. The first pad 500 and the second pad 510 correspond to the stiffener 16. That is, the first and

second pads

500 and 510 are aligned with the reinforcing plate 16 in a direction perpendicular to the extending direction of the base layer 11.

In one embodiment, the first and second

protective layers

70 and 71 may be solder resist layers or coverlay films (CVLs), e.g., the first and second

protective layers

70 and 71 may include solder resist ink. The first protective layer 70 and the second protective layer 71 serve to prevent the first conductive trace layer 50 and the second conductive trace layer 51 from being oxidized or short-circuited by soldering.

S7, referring to fig. 10, the first electronic component 80 and the second electronic component 81 are respectively mounted on the first bonding pad 500 and the second bonding pad 510 of the circuit substrate 101, thereby obtaining the circuit board 100.

The first electronic element 80 and the second electronic element 81 may be passive elements such as resistors and capacitors. Both the first electronic component 80 and the second electronic component 81 can be mounted on the first pad 500 and the second pad 510 through the conductive layer 82. In one embodiment, the first electronic component 80 and the second electronic component 81 are mounted on the first pad 500 and the second pad 510 by soldering, i.e., the conductive layer 82 is solder.

The wiring substrate 101 has a first mounting region 501 for the first electronic component 80 formed in a region corresponding to the two first pads 500, and a second mounting region 511 for the second electronic component 81 formed in a region corresponding to the two second pads 510. As the total thickness H of the reinforcing plate 16 increases, the rigidity of the first and second mounting

regions

501 and 511 increases accordingly. The stiffness required for the first mounting region 501 and the second mounting region 511 is in turn related to the kind or size of the mounted electronic component. Among them, when it is necessary to increase the rigidity of the first mounting region 501 and the second mounting region 511, the plating time can be appropriately extended, thereby increasing the thickness of the plated layer 15. In one embodiment, when the material of the electroplated copper 15 is copper, the thickness of the electroplated layer 156 is greater than or equal to 59 microns. The stiffness of the second mounting region 511 of the first mounting region 501 is greater than or equal to 3.2N/mm.

In another embodiment, when the material of the plating layer 15 includes one of beryllium, molybdenum, tungsten, and osmium, since the young's modulus of these metals is higher, it is advantageous to reduce the thickness of the plating layer 15 under the condition that the rigidity of the first mounting region 501 and the second mounting region 511 is constant. Wherein, when the material of the electroplated layer 15 is beryllium, the thickness of the electroplated layer 15 is greater than or equal to 44 micrometers; when the material of the electroplated layer 15 is molybdenum, the thickness of the electroplated layer 15 is more than or equal to 42 micrometers; when the material of the electroplated layer 15 is tungsten, the thickness of the electroplated layer 15 is more than or equal to 39 micrometers; when the material of the electroplated copper 15 is osmium, the thickness of the electroplated layer 15 is greater than or equal to 35 micrometers.

As shown in fig. 10, in one embodiment, both the perpendicular projection of the first mounting region 501 on the reinforcing plate 16 and the perpendicular projection of the second mounting region 511 on the reinforcing plate 16 are located within the range of the reinforcing plate 16. In this way, the first mounting region 501 and the second mounting region 511 can be ensured to have high rigidity, and the first electronic component 80 and the second electronic component 81 can be ensured not to have problems such as empty soldering and the like during soldering. In the present embodiment, the difference between the width of the reinforcing plate 16 (when the width W2 of the plating layer 15 is smaller than the width W1 of the copper foil layer 14, the width of the reinforcing plate 16 is W1) and the width W3 of the first mounting region 501 is greater than 80 micrometers, and the difference between the width of the reinforcing plate 16 and the width W4 of the second mounting region 511 is greater than 80 micrometers, in the extending direction of the base layer 11.

Referring to fig. 10, the present application further provides a circuit board 100 manufactured by the above manufacturing method, including a circuit substrate 101, and a first electronic component 80 and a second electronic component 81 mounted on the circuit substrate 101. The circuit substrate 101 includes a first protective layer 70, a first conductive trace layer 50, an insulating layer 41, an adhesive layer 40, a base layer 11, a second conductive trace layer 51, and a second protective layer 71, which are sequentially stacked. A portion of the first conductive trace layer 50 is exposed to the first passivation layer 70 to form the first bonding pad 500, and a portion of the second conductive trace layer 51 is exposed to the second passivation layer 71 to form the second bonding pad 510.

The circuit substrate 101 further includes a reinforcing plate 16 disposed on a surface of the base layer 11 away from the second conductive trace layer 51. The adhesive layer 40 covers the reinforcing plate 16. The reinforcing plate 16 includes a copper foil layer 14 and a plating layer 15, and the copper foil layer 14 is located between the plating layer 15 and the base layer 11. The first pad 500 and the second pad 510 correspond to the stiffener 16. The first and second

electronic components

80 and 81 are mounted on the first and

second pads

500 and 510, respectively.

The circuit substrate 101 is divided into a first region 1010 corresponding to the reinforcing plate 16 and a second region (not shown) excluding the first region. Due to the presence of the reinforcing plate 16, the thickness of the first region 1010 is larger than the thickness of the second region in the direction perpendicular to the extending direction of the wiring board 100.

In the present application, since the reinforcing plate 16 composed of the copper foil layer 14 and the plated layer 15 is embedded between the base layer 11 and the adhesive layer 40, the flatness and rigidity of the region of the wiring board 100 corresponding to the reinforcing plate 16 are improved. Moreover, electronic components can be mounted on both sides of the same area of the circuit board 100, so that the situation that the electronic components need to be arranged on the surface of the circuit board 100 in a staggered manner due to the fact that the reinforcing plate 16 is mounted on the surface of the circuit board 100 is avoided, and the space utilization rate and the surface mounting density are improved.

It is understood that various other changes and modifications can be made by those skilled in the art based on the technical idea of the present application, and all such changes and modifications should fall within the protective scope of the claims of the present application.

Claims

1. A method for manufacturing a circuit board is characterized by comprising the following steps:

providing a double-sided copper-clad substrate, wherein the double-sided copper-clad substrate comprises a base layer, a first copper foil and a second copper foil, and the first copper foil and the second copper foil are respectively arranged on two opposite surfaces of the base layer;

etching a portion of the first copper foil to obtain a copper foil layer;

electroplating on the copper foil layer to form an electroplated layer, wherein the copper foil layer and the electroplated layer jointly form a reinforcing plate;

laminating an adhesive layer, an insulating layer and a third copper foil on the surface of the base layer with the reinforcing plate;

etching the third copper foil and the second copper foil to obtain a first conductive circuit layer and a second conductive circuit layer, wherein the first conductive circuit layer comprises two first welding pads, the second conductive circuit layer comprises two second welding pads, and the first welding pads and the second welding pads correspond to the reinforcing plate in position;

and respectively mounting a first electronic element and a second electronic element on the first welding pad and the second welding pad to obtain the circuit board.

2. The method for producing a wiring board according to claim 1, wherein before mounting the first electronic component and the second electronic component, the method further comprises the steps of:

forming a first protective layer and a second protective layer on the first conductive circuit layer and the second conductive circuit layer respectively to obtain a circuit substrate;

part of the first conductive circuit layer is exposed out of the first protective layer to form the first bonding pad, and part of the second conductive circuit layer is exposed out of the second protective layer to form the second bonding pad.

3. The method for manufacturing a wiring board according to claim 2, wherein the wiring substrate is formed with a first mounting region for the first electronic component in a region corresponding to two of the first pads and a second mounting region for the second electronic component in a region corresponding to two of the second pads, and a vertical projection of the first mounting region on the reinforcing plate and a vertical projection of the second mounting region on the reinforcing plate are both located within a range of the reinforcing plate.

4. The method for manufacturing a wiring board according to claim 3, wherein the plating layer is made of one material selected from the group consisting of copper, beryllium, molybdenum, tungsten, and osmium, and the first mounting region and the second mounting region each have a rigidity of 3.2N/mm or more.

5. The method of manufacturing a wiring board according to claim 1, wherein etching a portion of the first copper foil to obtain a copper foil layer specifically comprises the steps of:

covering a first dry film and a second dry film on the first copper foil and the second copper foil respectively, wherein the first dry film covers part of the surface of the first copper foil, and the second dry film covers the whole surface of the second copper foil;

etching the first copper foil which is not covered by the first dry film by using the first dry film as a photomask in an exposure and development mode to obtain the copper foil layer;

removing the first dry film and the second dry film.

6. A circuit board comprises a circuit substrate, wherein the circuit substrate comprises a first conductive circuit layer, an insulating layer, an adhesive layer, a base layer and a second conductive circuit layer which are sequentially stacked, the first conductive circuit layer comprises two first welding pads, the second conductive circuit layer comprises two second welding pads,

the circuit substrate further comprises a reinforcing plate arranged on the surface of the base layer far away from the second conductive circuit layer, the adhesive layer coats the reinforcing plate, the reinforcing plate comprises a copper foil layer and an electroplated layer, the copper foil layer is located between the electroplated layer and the base layer, and the first welding pad and the second welding pad correspond to the reinforcing plate in position;

the circuit board further comprises a first electronic element and a second electronic element, wherein the first electronic element and the second electronic element are respectively arranged on the first bonding pad and the second bonding pad.

7. The circuit board of claim 6, wherein the circuit substrate further comprises a first protective layer and a second protective layer respectively disposed on the first conductive trace layer and the second conductive trace layer, wherein a portion of the first conductive trace layer is exposed to the first protective layer to form the first bonding pad, and a portion of the second conductive trace layer is exposed to the second protective layer to form the second bonding pad.

8. The wiring board according to claim 7, wherein the wiring substrate forms a first mounting region of the first electronic component in a region corresponding to two of the first pads, and forms a second mounting region of the second electronic component in a region corresponding to two of the second pads, and a perpendicular projection of the first mounting region on the reinforcing plate and a perpendicular projection of the second mounting region on the reinforcing plate are both located within a range of the reinforcing plate.

9. The wiring board of claim 8, wherein the plating layer is selected from one of copper, beryllium, molybdenum, tungsten, and osmium, and wherein the first mounting region and the second mounting region each have a stiffness of 3.2N/mm or greater.

10. The wiring board of claim 8, wherein the difference between the width of the stiffener and the width of the first mounting region is greater than 80 microns and the difference between the width of the stiffener and the width of the second mounting region is greater than 80 microns along the extension direction of the base layer.