CN114553223A - MDAC circuit for eliminating kickback noise nonlinearity of pipeline analog-to-digital converter - Google Patents
MDAC circuit for eliminating kickback noise nonlinearity of pipeline analog-to-digital converter Download PDFInfo
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- CN114553223A CN114553223A CN202111551825.9A CN202111551825A CN114553223A CN 114553223 A CN114553223 A CN 114553223A CN 202111551825 A CN202111551825 A CN 202111551825A CN 114553223 A CN114553223 A CN 114553223A
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- AFYCEAFSNDLKSX-UHFFFAOYSA-N coumarin 460 Chemical compound CC1=CC(=O)OC2=CC(N(CC)CC)=CC=C21 AFYCEAFSNDLKSX-UHFFFAOYSA-N 0.000 title claims abstract description 20
- 239000003990 capacitor Substances 0.000 claims abstract description 76
- 238000005070 sampling Methods 0.000 claims abstract description 45
- UDQDXYKYBHKBTI-IZDIIYJESA-N 2-[4-[4-[bis(2-chloroethyl)amino]phenyl]butanoyloxy]ethyl (2e,4e,6e,8e,10e,12e)-docosa-2,4,6,8,10,12-hexaenoate Chemical compound CCCCCCCCC\C=C\C=C\C=C\C=C\C=C\C=C\C(=O)OCCOC(=O)CCCC1=CC=C(N(CCCl)CCCl)C=C1 UDQDXYKYBHKBTI-IZDIIYJESA-N 0.000 claims abstract description 27
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
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Abstract
The invention discloses an MDAC circuit for eliminating the kickback noise nonlinearity of an assembly line analog-to-digital converter, which can respectively and independently work by changing the capacitance value proportion of a sampling capacitor CS and a reference signal capacitor array CDAC and matching with two non-overlapping time sequences on the basis of the traditional MDAC circuit structure, and eliminates the influence of the kickback noise on the circuit performance on the premise of not changing the circuit transfer function.
Description
Technical Field
The invention relates to an MDAC circuit for eliminating kickback noise nonlinearity of a pipeline analog-to-digital converter, and belongs to the technical field of design of integrated circuits.
Background
The MDAC circuit is used as a key circuit module in the pipeline analog-to-digital converter for determining the signal conversion accuracy, and with the continuous development of the pipeline analog-to-digital converter, higher requirements are put forward on the performance of the pipeline analog-to-digital converter. The decreasing size of CMOS technology makes the operating speed of mixed signal circuit higher and higher, and in contrast, due to the decrease of power voltage and the influence of various second-order effects, how to maintain high linearity in high-speed high-precision ADC system becomes a problem that designers should consider and solve. In the analog-to-digital converter structure of the production line without the acquisition and protection, the traditional MDAC structure has difficulty meeting the design requirements.
Disclosure of Invention
The invention provides an MDAC circuit for eliminating kickback noise nonlinearity of a pipeline analog-to-digital converter aiming at kickback noise nonlinearity generated in a traditional MDAC structure.
The technical scheme for solving the technical problems is as follows:
an MDAC circuit for canceling kickback noise nonlinearity of a pipeline analog-to-digital converter, comprising: the FLASH output control circuit comprises a transconductance operational amplifier 100, a FLASH module 101, a sampling capacitor CS, a feedback capacitor CF, a capacitor array CDAC, a switch BSW1, a switch BSW2, a switch SW1, a switch SW2, a switch SW3, a switch SW4 and a FLASH output control switch SWC, wherein:
the left pole plate of the sampling capacitor CS is connected with an input signal VIN through a switch BSW1 and is connected with the ground through a switch SW 2; the right polar plate is connected with the ground through a switch SW1 and is also connected with the negative end of the transconductance operational amplifier 100, the right polar plate of the capacitor array CDAC and the left polar plate of the feedback capacitor CF; the left plate of the capacitor array CDAC is connected with VREF and 0V through a switch SW2 and is connected with the ground through a switch SW 4; the right pole plate of the feedback capacitor CF is connected with the ground through a switch SW3 and is connected with the output end of the transconductance operational amplifier 100 through a switch BSW 2; the positive end of the transconductance operational amplifier is connected with the ground; the input end of the FLASH module 101 is connected to the input signal VIN and the comparison level VCOMP, respectively, and the output end provides a timing sequence for the FLASH output control switch SWC.
The switches BSW1, SW1, SW3 and SW4 are controlled by a sampling phase to work;
the switches BSW2 and SW2 are controlled to work by a holding phase;
the specific time sequence of the switch of the patent is shown in the attached figure 2 of the specification.
An MDAC circuit for eliminating kickback noise nonlinearity of a pipeline analog-to-digital converter comprises the following working steps:
(1) when the circuit timing sequence is in the sampling phase, the switches BSW2 and SW2 are opened, the switches SW1, SW3 and SW4 are closed preferentially, the sampling capacitor CS, the feedback capacitor CF and the capacitor array CDAC are discharged, then the BSW1 is closed, and the sampling capacitor CS samples the input signal VIN; meanwhile, the FLASH module 101 quantizes the input signal VIN and outputs a thermometer code DOUT;
(2) when the circuit timing sequence is in a hold phase, the switches BSW1, SW1, SW3 and SW4 are sequentially opened, the switches SW2, SWC and BSW2 are sequentially closed, the feedback capacitor CF, the sampling capacitor CS, the capacitor array CDAC and the transconductance operational amplifier 100 form a feedback loop, and a residual signal VOUT is output;
compared with the prior art, the invention has the advantages that:
and a single input sampling capacitor CS and a single reference sampling capacitor array CDAC are used, the CS samples an input signal during sampling phase, the sampling capacitor CS is reset during holding phase, and meanwhile, the reference sampling capacitor array CDAC completes the signal reconstruction process of the DAC. Therefore, when the signal is sampled again in the next period, the signal does not have nonlinear kickback noise.
Drawings
Fig. 1 is a schematic diagram of an MDAC circuit structure for eliminating kickback noise nonlinearity of a pipeline analog-to-digital converter according to the present invention;
FIG. 2 is a timing diagram according to the present invention.
Detailed Description
An MDAC circuit for eliminating kickback noise nonlinearity of a pipeline analog-to-digital converter comprises a transconductance operational amplifier 100, a FLASH module 101, a sampling capacitor CS, a feedback capacitor CF, a capacitor array CDAC, a switch BSW1, a switch BSW2, a switch SW1, a switch SW2, a switch SW3, a switch SW4 and a FLASH output control switch SWC, and the specific circuit structure is as follows:
the left pole plate of the sampling capacitor CS is connected with an input signal VIN through a switch BSW1 and is connected with the ground through a switch SW 2; the right polar plate is connected with the ground through a switch SW1 and is also connected with the negative end of the transconductance operational amplifier 100, the right polar plate of the capacitor array CDAC and the left polar plate of the feedback capacitor CF; the left plate of the capacitor array CDAC is connected with VREF and 0V through a switch SW2 and is connected with the ground through a switch SW 4; the right pole plate of the feedback capacitor CF is connected with the ground through a switch SW3 and is connected with the output end of the transconductance operational amplifier 100 through a switch BSW 2; the positive end of the transconductance operational amplifier is connected with the ground; the input end of the FLASH module 101 is connected to the input signal VIN and the comparison level VCOMP, respectively, and the output end provides a timing sequence for the FLASH output control switch SWC.
The switches BSW1, SW1, SW3 and SW4 are controlled by a sampling phase to work, the switches BSW2 and SW2 are controlled by a holding phase to work, and the specific time sequence of the switches is shown in the attached figure 2 of the specification.
By utilizing the built circuit structure, the MDAC circuit for eliminating the kickback noise nonlinearity of the pipeline analog-to-digital converter is provided, and the method specifically comprises the following steps:
(1) when the circuit timing sequence is in the sampling phase, the switches BSW2 and SW2 are opened, the switches SW1, SW3 and SW4 are closed preferentially, the sampling capacitor CS, the feedback capacitor CF and the capacitor array CDAC are discharged, then the BSW1 is closed, and the sampling capacitor CS samples the input signal VIN; meanwhile, the FLASH module 101 quantizes the input signal VIN and outputs a thermometer code DOUT;
(2) when the circuit timing is in the hold phase, the switches BSW1, SW1, SW3 and SW4 are sequentially turned off, the switches SW2, SWC and BSW2 are sequentially turned on, the feedback capacitor CF, the sampling capacitor CS, the capacitor array CDAC and the transconductance operational amplifier 100 form a feedback loop, and the residual signal VOUT is output.
The following is further illustrated with reference to specific examples:
in the conventional MDAC structure, the sampling capacitor CS and the capacitor array CDAC generally use capacitors with the same capacitance value in capacitance value, and sample signals at the same time when sampling phases, and access a reference level for amplifying a residual voltage when maintaining the phases. Such a structure may cause a quantization error, which is a strong non-linearity called kickback noise non-linearity, to be caused by introducing a glitch due to multiplexing of the sampling capacitor CS and the capacitor array CDAC when sampling a phase in the next period in the high-speed pipeline analog-to-digital converter structure.
In this embodiment, on the basis of the conventional MDAC circuit structure, by changing the capacitance value ratio of the sampling capacitor CS and the reference signal capacitor array CDAC and matching with the two non-overlapping time sequences, the two capacitors can respectively and independently operate, and the influence of kickback noise on the circuit performance is eliminated on the premise of not changing the circuit transfer function.
As shown in fig. 1, fig. 1 illustrates the present invention by taking 3-bit mdac as an example, and the present invention includes a transconductance operational amplifier 100, a FLASH module 101, a sampling capacitor CS, a feedback capacitor CF, a capacitor array CDAC, a switch BSW1, a switch BSW2, a switch SW1, a switch SW2, a switch SW3, a switch SW4, and a FLASH output control switch SWC.
As shown in fig. 1, the left plate of the sampling capacitor CS is connected to the input signal VIN through the switch BSW1 and to ground through the switch SW 2; the right polar plate is connected with the ground through a switch SW1 and is also connected with the negative end of the transconductance operational amplifier 100, the right polar plate of the capacitor array CDAC and the left polar plate of the feedback capacitor CF; the left pole plate of the capacitor array CDAC is connected with VREF and 0V through a switch SW2 and is connected with the ground through a switch SW 4; the right pole plate of the feedback capacitor CF is connected with the ground through a switch SW3 and is connected with the output end of the transconductance operational amplifier 100 through a switch BSW 2; the positive end of the transconductance operational amplifier is connected with the ground; the input end of the FLASH module 101 is connected to the input signal VIN and the comparison level VCOMP, respectively, and the output end provides a timing sequence for the FLASH output control switch SWC.
As shown in fig. 2, the timing of the switches in the circuit of the present invention is adjusted based on the non-overlapping timing of the two phases, and during the sampling phase, the switches BSW1, SW1, SW3, SW4 are closed, and are sequentially opened before the holding phase arrives; in the hold phase, the switches BSW2, SW2 are closed and sequentially opened before the next periodic sampling phase.
The circuit of the invention specifically comprises the following working steps:
(1) when the circuit timing sequence is in the sampling phase, the switches BSW2 and SW2 are opened, the switches SW1, SW3 and SW4 are closed preferentially, the sampling capacitor CS, the feedback capacitor CF and the capacitor array CDAC are discharged, then the BSW1 is closed, and the sampling capacitor CS samples the input signal VIN; meanwhile, the FLASH module 101 quantizes the input signal VIN and outputs a thermometer code DOUT;
(2) when the circuit timing is in the hold phase, the switches BSW1, SW1, SW3 and SW4 are sequentially opened, the switches SW2, SWC and BSW2 are sequentially closed, the feedback capacitor CF, the sampling capacitor CS, the capacitor array CDAC and the transconductance operational amplifier 100 form a feedback loop, and output a residual signal VOUT with a transfer function:
wherein CS =8C, CF =2C, CDAC = C, N = -4 to +4, and is determined by a FLASH module outputting a thermometer code DOUT. According to the timing diagram of the switches shown in fig. 2, when the circuit works in the sampling phase, the switch SW1 and the switch SW2 are turned on simultaneously to reset the sampling capacitor, so that the sampling capacitor is not affected by kickback noise in the previous sampling period when sampling the relative signal, thereby improving the linearity of the MDAC circuit.
Those skilled in the art will appreciate that the details of the present invention not described in detail herein are well within the skill of those skilled in the art.
Claims (3)
1. An MDAC circuit for canceling kickback noise nonlinearity of a pipeline analog-to-digital converter, comprising: the FLASH output control circuit comprises a transconductance operational amplifier 100, a FLASH module 101, a sampling capacitor CS, a feedback capacitor CF, a capacitor array CDAC, a switch BSW1, a switch BSW2, a switch SW1, a switch SW2, a switch SW3, a switch SW4 and a FLASH output control switch SWC, wherein:
the left pole plate of the sampling capacitor CS is connected with an input signal VIN through a switch BSW1 and is connected with the ground through a switch SW 2; the right polar plate is connected with the ground through a switch SW1 and is also connected with the negative end of the transconductance operational amplifier 100, the right polar plate of the capacitor array CDAC and the left polar plate of the feedback capacitor CF; the left plate of the capacitor array CDAC is connected with VREF and 0V through a switch SW2 and is connected with the ground through a switch SW 4; the right pole plate of the feedback capacitor CF is connected with the ground through a switch SW3 and is connected with the output end of the transconductance operational amplifier 100 through a switch BSW 2; the positive end of the transconductance operational amplifier is connected with the ground; the input end of the FLASH module 101 is connected to the input signal VIN and the comparison level VCOMP, respectively, and the output end provides a timing sequence for the FLASH output control switch SWC.
2. The MDAC circuit for canceling kickback noise nonlinearity of a pipeline analog-to-digital converter according to claim 1, wherein:
the switches BSW1, SW1, SW3 and SW4 are controlled by a sampling phase to work;
the switches BSW2 and SW2 are controlled to work by a holding phase;
the specific time sequence of the switch of the patent is shown in the attached figure 2 of the specification.
3. The MDAC circuit for eliminating kickback noise nonlinearity of a pipeline adc according to claim 1, comprising the steps of:
(1) when the circuit timing sequence is in the sampling phase, the switches BSW2 and SW2 are opened, the switches SW1, SW3 and SW4 are closed preferentially, the sampling capacitor CS, the feedback capacitor CF and the capacitor array CDAC are discharged, then the BSW1 is closed, and the sampling capacitor CS samples the input signal VIN; meanwhile, the FLASH module 101 quantizes an input signal VIN and outputs a thermometer code DOUT;
(2) when the circuit timing is in the hold phase, the switches BSW1, SW1, SW3 and SW4 are sequentially turned off, the switches SW2, SWC and BSW2 are sequentially turned on, the feedback capacitor CF, the sampling capacitor CS, the capacitor array CDAC and the transconductance operational amplifier 100 form a feedback loop, and the residual signal VOUT is output.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111551825.9A CN114553223A (en) | 2021-12-17 | 2021-12-17 | MDAC circuit for eliminating kickback noise nonlinearity of pipeline analog-to-digital converter |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111551825.9A CN114553223A (en) | 2021-12-17 | 2021-12-17 | MDAC circuit for eliminating kickback noise nonlinearity of pipeline analog-to-digital converter |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040070917A1 (en) * | 2002-06-18 | 2004-04-15 | Analog Devices, Inc. | Switched-capacitor structures with enhanced isolation |
| CN102904573A (en) * | 2011-07-29 | 2013-01-30 | 联发科技（新加坡）私人有限公司 | Analog-to-digital converters and analog-to-digital conversion methods |
| CN106899302A (en) * | 2015-12-17 | 2017-06-27 | 亚德诺半导体集团 | The adaptive digital quantizing noise of MADS ADCS eliminates wave filter |
| CN112511167A (en) * | 2019-09-13 | 2021-03-16 | 亚德诺半导体国际无限责任公司 | Low noise analog-to-digital converter |
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2021
- 2021-12-17 CN CN202111551825.9A patent/CN114553223A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040070917A1 (en) * | 2002-06-18 | 2004-04-15 | Analog Devices, Inc. | Switched-capacitor structures with enhanced isolation |
| CN102904573A (en) * | 2011-07-29 | 2013-01-30 | 联发科技（新加坡）私人有限公司 | Analog-to-digital converters and analog-to-digital conversion methods |
| CN106899302A (en) * | 2015-12-17 | 2017-06-27 | 亚德诺半导体集团 | The adaptive digital quantizing noise of MADS ADCS eliminates wave filter |
| CN112511167A (en) * | 2019-09-13 | 2021-03-16 | 亚德诺半导体国际无限责任公司 | Low noise analog-to-digital converter |
Non-Patent Citations (1)
| Title |
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| MALIANG LIU, JINGYU WANG, ZHANGMING ZHU, WEI GUO, LIANXI LIU & RUIXUE DING: "A low distortion CMOS analogue switch with high-order compensation", MIXED SIGNAL LETTER, 7 January 2015 (2015-01-07) * |
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