CN114551475A - Display panel manufacturing method and display panel - Google Patents

Display panel manufacturing method and display panel Download PDF

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Publication number
CN114551475A
CN114551475A CN202210121788.6A CN202210121788A CN114551475A CN 114551475 A CN114551475 A CN 114551475A CN 202210121788 A CN202210121788 A CN 202210121788A CN 114551475 A CN114551475 A CN 114551475A
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opening
layer
forming
display panel
electrode
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宋志伟
郑帅
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

The application discloses display panel's manufacturing method and display panel, this application forms two first through-holes, first trompil and first opening simultaneously through same light shield, and forms two second through-holes, the second trompil that is located first trompil simultaneously through same light shield to and be located the second opening in the first opening, can reduce the complexity of LTPO display panel's manufacture craft, reduce light shield quantity, reduce cost.

Description

Display panel manufacturing method and display panel
Technical Field
The application relates to the field of display, in particular to a display panel and a manufacturing method thereof.
Background
Display panels of Organic Light Emitting Display (OLED) panels and the like are widely used in human life, such as Display screens of mobile phones, computers and the like. The low temperature poly-silicon oxide (LTPO) display technology combines two thin film transistors, i.e., low temperature poly-silicon (LTPS) and Indium Gallium Zinc Oxide (IGZO), so that the display panel has both strong driving capability and low power consumption, is suitable for both high frequency display and low frequency display, and has become more and more popular in the display panel.
However, the LTPO display panel has the problems of complex structure, complex manufacturing process, large number of masks, and high cost.
Disclosure of Invention
The application provides a manufacturing method of a display panel and the display panel, which can solve the problems of complicated manufacturing process, more light shields and high cost caused by the complicated structure of an LTPO display panel.
The embodiment of the application provides a manufacturing method of a display panel, wherein the display panel comprises a display area and a non-display area, the non-display area comprises a bending area, and the method comprises the following steps:
step S100, providing a substrate, forming a light shielding layer on the substrate, forming a buffer layer on the light shielding layer, forming a P-type semiconductor layer and a first grid electrode of a P-type transistor, and an N-type semiconductor layer and a second grid electrode of an N-type transistor on the buffer layer, and forming an interlayer insulating layer on the second grid electrode;
step S200: simultaneously forming two first through holes, a first opening and a first opening corresponding to the P-type transistor, wherein the first opening is positioned in the bending area;
step S300: forming two second through holes corresponding to the N-type transistors, a second opening in the first opening and a second opening in the first opening;
step S400: forming a source drain metal layer, and patterning the source drain metal layer to form a first source electrode and a first drain electrode of the P-type transistor, a second source electrode and a second drain electrode of the N-type transistor, and a connecting electrode; the first source electrode and the first drain electrode are respectively connected with the P-type semiconductor layer through the two first through holes, the second source electrode and the second drain electrode are respectively connected with the N-type semiconductor layer through the two second through holes, and the connecting electrode is connected with the shading layer through the first opening and the second opening.
Optionally, in some embodiments of the present application, in the step S400, the connection electrode is connected to one of the first source electrode and the first drain electrode, or/and the connection electrode is connected to one of the second source electrode and the second drain electrode.
Optionally, in some embodiments of the present application, the step S100 includes the following steps:
step S110: providing a substrate, forming a light shielding layer on the substrate, and forming a buffer layer on the light shielding layer;
step S120: forming the P-type semiconductor layer on the buffer layer, forming a first gate insulating layer on the P-type semiconductor layer, and forming the first gate on the first gate insulating layer;
step S130: forming a first insulating layer on the first gate, forming a capacitor metal layer on the first insulating layer, and simultaneously patterning the capacitor metal layer to form a capacitor electrode plate of a storage capacitor and a third gate of the N-type transistor;
step S140: forming a second gate insulating layer on the third gate electrode, forming the N-type semiconductor layer on the second gate insulating layer, forming a third gate insulating layer on the N-type semiconductor layer, forming the second gate electrode on the third gate insulating layer, and forming the interlayer insulating layer on the second gate electrode.
Optionally, in some embodiments of the application, in the step S200, the first through hole penetrates through the interlayer insulating layer to a surface of the P-type semiconductor layer away from the substrate, and the first opening penetrate through the interlayer insulating layer to a surface of the buffer layer away from the substrate.
Optionally, in some embodiments of the application, in the step S300, the second through hole penetrates through the interlayer insulating layer to a surface of the N-type semiconductor layer away from the substrate, the second opening penetrates through the buffer layer to a surface of the light shielding layer away from the substrate, and the second opening penetrates through the buffer layer to a surface of the substrate close to the light shielding layer.
Optionally, in some embodiments of the present application, in the step S300, a width of the second opening is smaller than a width of the first opening, and a width of the second opening is smaller than a width of the first opening.
Optionally, in some embodiments of the present application, a center of an orthographic projection of the first aperture on the substrate overlaps a center of an orthographic projection of the second aperture on the substrate;
the center of the orthographic projection of the first opening on the substrate overlaps with the center of the orthographic projection of the second opening on the substrate.
Optionally, in some embodiments of the present application, the P-type semiconductor layer is a polysilicon material, and the N-type semiconductor layer is an oxide semiconductor material.
Optionally, in some embodiments of the present application, between the step S300 and the step S400, further comprising: step S500: filling the first opening and the second opening with organic layers;
after the step S400, the method further includes: step S600: and forming a light-emitting device layer and an encapsulation layer.
Correspondingly, the embodiment of the application also provides a display panel, and the display panel is manufactured by adopting the manufacturing method of any one of the display panels
In an embodiment of the present application, a manufacturing method of a display panel and the display panel are provided, the display panel includes a display area and a non-display area, the non-display area includes a bending area, and the manufacturing method of the display panel at least includes the following steps: step S100, providing a substrate, forming a shading layer on the substrate, forming a buffer layer on the shading layer, forming a P-type semiconductor layer and a first grid electrode of a P-type transistor, an N-type semiconductor layer and a second grid electrode of an N-type transistor on the buffer layer, and forming an interlayer insulating layer on the second grid electrode; step S200: simultaneously forming two first through holes, a first opening and a first opening which correspond to the P-type transistor, wherein the first opening is positioned in the bending area; step S300: forming two second through holes corresponding to the N-type transistors, a second opening in the first opening and a second opening in the first opening; step S400: forming a source and drain metal layer, and patterning the source and drain metal layer to form a first source electrode and a first drain electrode of a P-type transistor, a second source electrode and a second drain electrode of an N-type transistor and a connecting electrode; the first source electrode and the first drain electrode are respectively connected with the P-type semiconductor layer through two first through holes, the second source electrode and the second drain electrode are respectively connected with the N-type semiconductor layer through two second through holes, and the connecting electrode is connected with the shading layer through the first opening and the second opening. According to the application, two first through holes, a first opening and a first opening are formed simultaneously through the same photomask (step S200), two second through holes, a second opening located in the first opening and a second opening located in the first opening are formed simultaneously through the same photomask (step S300), the complexity of the manufacturing process of the LTPO display panel can be reduced, the number of photomasks is reduced, and the cost is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic top view of a display panel according to an embodiment of the present disclosure;
fig. 2 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram illustrating a first flow step of a method for manufacturing a display panel according to an embodiment of the present disclosure;
fig. 4 is a first process diagram of a method for manufacturing a display panel according to an embodiment of the present disclosure;
fig. 5 is a schematic process diagram of a second method for manufacturing a display panel according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram illustrating a third process of a method for manufacturing a display panel according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram illustrating a fourth process of a method for manufacturing a display panel according to an embodiment of the present disclosure;
fig. 8 is a schematic diagram illustrating a second flow step of a method for manufacturing a display panel according to an embodiment of the present application;
fig. 9 is a schematic diagram illustrating a third flow step of a method for manufacturing a display panel according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The application provides a manufacturing method of a display panel, the display panel comprises a display area and a non-display area, the non-display area comprises a bending area, and the manufacturing method of the display panel at least comprises the following steps: step S100, providing a substrate, forming a shading layer on the substrate, forming a buffer layer on the shading layer, forming a P-type semiconductor layer and a first grid electrode of a P-type transistor, an N-type semiconductor layer and a second grid electrode of an N-type transistor on the buffer layer, and forming an interlayer insulating layer on the second grid electrode; step S200: simultaneously forming two first through holes, a first opening and a first opening which correspond to the P-type transistor, wherein the first opening is positioned in the bending area; step S300: forming two second through holes corresponding to the N-type transistors, a second opening in the first opening and a second opening in the first opening; step S400: forming a source and drain metal layer, and patterning the source and drain metal layer to form a first source electrode and a first drain electrode of a P-type transistor, a second source electrode and a second drain electrode of an N-type transistor and a connecting electrode; the first source electrode and the first drain electrode are respectively connected with the P-type semiconductor layer through two first through holes, the second source electrode and the second drain electrode are respectively connected with the N-type semiconductor layer through two second through holes, and the connecting electrode is connected with the shading layer through the first opening and the second opening. The application also provides a display panel manufactured by the manufacturing method of the display panel. Specific examples of the present application are described in detail below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
Example one
Referring to fig. 1 and fig. 2, fig. 1 is a schematic top view of a display panel 100 according to an embodiment of the present disclosure; fig. 2 is a schematic cross-sectional structure diagram of a display panel 100 according to an embodiment of the present disclosure.
Referring to fig. 1 and fig. 2, in order to facilitate understanding of the method for manufacturing a display panel according to the subsequent embodiments of the present application, the present embodiment illustrates a structure of a display panel 100, and the method for manufacturing a display panel according to the present application may further manufacture a display panel other than the structure illustrated in fig. 1 and fig. 2.
Referring to fig. 1, fig. 1 illustrates a display panel 100, the display panel 100 includes a display area AA and a non-display area BB, and the non-display area BB includes a bending area BB 1.
Specifically, in some embodiments, the bending region BB1 may be bent to the non-display side of the display panel 100, which is the side opposite to the light emitting direction of the display panel 100 or away from the human eye for frame reduction.
Referring to fig. 2, fig. 2 is a cross-sectional view of a dotted line H-K in fig. 1, fig. 3 only illustrates a partial structure of the display panel 100, and the display panel 100 may further include a light emitting device layer and an encapsulation layer (not illustrated in fig. 2).
Referring to fig. 2, the layer structure of the display panel 100 sequentially includes: the pixel structure comprises a substrate 11, a shading layer 12, a buffer layer 13, a P-type semiconductor layer 14, a first gate insulating layer 15, a first gate 16, a first insulating layer 17, a capacitor metal layer 18, a second gate insulating layer 19, an N-type semiconductor layer 20, a third gate insulating layer 21, a second gate 22, an interlayer insulating layer 23, a source/drain metal layer 24, a first flat layer 25, a transition metal layer 26, a second flat layer 27, an anode 28 and a pixel defining layer 29.
Specifically, the display panel includes a P-type transistor (P-type thin film transistor) and an N-type transistor (N-type thin film transistor), and the structure of the display panel 100 is not limited to the film layer structure shown in fig. 2, for example, the P-type transistor 101 and the N-type transistor 102 are not limited to a top gate type transistor or a bottom gate type transistor; for example, the display panel 100 may not include the first planarization layer 25; for example, other film layers may be included between buffer layer 13 and substrate 11.
Specifically, the substrate 11 may be a rigid substrate or a flexible substrate, and when the substrate 11 is a rigid substrate, the material of the substrate 11 may be glass; when the substrate 11 is a flexible substrate, the material of the substrate 11 may be a composite structure of multiple film layers, for example, the substrate 11 includes a first flexible film layer, an inorganic layer, and a second flexible film layer.
Specifically, the structure of the display panel 100 may further include a filling layer 30 located in the first opening 71 and the second opening 72 in the bending region BB1, so as to improve the bending performance of the bending region BB 1.
Specifically, the structure of the display panel 100 may be any structure suitable for the manufacturing method of the display panel of the present application.
Example two
Referring to fig. 3 to 9, fig. 3 is a schematic diagram illustrating a first flow step of a method for manufacturing a display panel 100 according to an embodiment of the present disclosure; fig. 4 is a first process diagram of a method for manufacturing a display panel 100 according to an embodiment of the present disclosure; fig. 5 is a second process diagram of a manufacturing method of a display panel 100 according to an embodiment of the present disclosure; fig. 6 is a schematic diagram illustrating a third process of a method for manufacturing a display panel 100 according to an embodiment of the present disclosure; fig. 7 is a schematic diagram illustrating a fourth process of a method for manufacturing a display panel 100 according to an embodiment of the present disclosure; fig. 8 is a schematic diagram illustrating a second flow step of a method for manufacturing a display panel 100 according to an embodiment of the present disclosure; fig. 9 is a schematic diagram illustrating a third flow of a manufacturing method of a display panel 100 according to an embodiment of the present disclosure.
The embodiment of the application provides a manufacturing method of a display panel, which at least comprises the following steps: step S100, step S200, step S300, and step S400.
Step S100, providing a substrate, forming a light-shielding layer on the substrate, forming a buffer layer on the light-shielding layer, forming a P-type semiconductor layer and a first gate of a P-type transistor, and an N-type semiconductor layer and a second gate of an N-type transistor on the buffer layer, and forming an interlayer insulating layer on the second gate.
Specifically, as shown in fig. 4, a substrate 11 is provided, a light-shielding layer 12 is formed on the substrate 11, a buffer layer 13 is formed on the light-shielding layer 12, a P-type semiconductor layer 14 and a first gate electrode 16 of a P-type transistor 101, and an N-type semiconductor layer 20 and a second gate electrode 22 of an N-type transistor 102 are formed on the buffer layer 13, and an interlayer insulating layer 23 is formed on the second gate electrode 22.
Step S200: two first through holes, a first opening and a first opening are formed at the same time, wherein the two first through holes correspond to the P-type transistor, and the first opening is located in the bending area.
Specifically, as shown in fig. 5, two first vias 51 corresponding to the P-type transistor 101, the first opening 61, and the first opening 71 are formed simultaneously, and the first opening 71 is located in the bending region BB 1.
Step S300: and forming two second through holes corresponding to the N-type transistors, a second opening in the first opening and a second opening in the first opening.
Specifically, as shown in fig. 6, two second vias 81 corresponding to the N-type transistors 102, the second opening 62 located in the first opening 61, and the second opening 72 located in the first opening 71 are formed.
Step S400: forming a source and drain metal layer, and patterning the source and drain metal layer to form a first source electrode and a first drain electrode of a P-type transistor, a second source electrode and a second drain electrode of an N-type transistor and a connecting electrode; the first source electrode and the first drain electrode are respectively connected with the P-type semiconductor layer through two first through holes, the second source electrode and the second drain electrode are respectively connected with the N-type semiconductor layer through two second through holes, and the connecting electrode is connected with the shading layer through the first opening and the second opening.
Specifically, as shown in fig. 7, a source-drain metal layer 24 is formed, and the source-drain metal layer 24 is patterned to form a first source 241 and a first drain 242 of the P-type transistor 101, a second source 243 and a second drain 244 of the N-type transistor 102, and a connection electrode 245; the first source electrode 241 and the first drain electrode 242 are respectively connected to the P-type semiconductor layer 14 through two first through holes 51, the second source electrode 243 and the second drain electrode 244 are respectively connected to the N-type semiconductor layer 20 through two second through holes 81, and the connection electrode 245 is connected to the light-shielding layer 12 through the first opening 61 and the second opening 62.
In some embodiments, in step S400, the connection electrode 245 connects one of the first source 241 and the first drain 242, or/and the connection electrode 245 connects one of the second source 243 and the second drain 244.
Specifically, the connection electrode 245 is connected to one of the first source 241 and the first drain 242, or/and the connection electrode 245 is connected to one of the second source 243 and the second drain 244 (not shown in the figure), which can shield the charges polarized on the substrate 11, and improve the performance of the P-type transistor 101 or/and the N-type transistor 102, such as stability.
In some embodiments, as shown in fig. 8. Step S100 includes at least the following steps: step S110, step S120, step S130, and step S140, which describe the detailed process of some manufacturing steps of the display panel illustrated in fig. 1 in detail.
Step S110: providing a substrate, forming a light shielding layer on the substrate, and forming a buffer layer on the light shielding layer.
Specifically, as shown in fig. 4, a substrate 11 is provided, a light-shielding layer 12 is formed on the substrate 11, and a buffer layer 13 is formed on the light-shielding layer 12.
Step S120: a P-type semiconductor layer is formed on the buffer layer, a first gate insulating layer is formed on the P-type semiconductor layer, and a first gate electrode is formed on the first gate insulating layer.
Specifically, as shown in fig. 4, a P-type semiconductor layer 14 is formed on the buffer layer 13, a first gate insulating layer 15 is formed on the P-type semiconductor layer 14, and a first gate electrode 16 is formed on the first gate insulating layer 15.
Step S130: forming a first insulating layer on the first gate, forming a capacitor metal layer on the first insulating layer, and patterning the capacitor metal layer to form a capacitor electrode plate of the storage capacitor and a third gate of the N-type transistor.
Specifically, as shown in fig. 4, a first insulating layer 17 is formed on the first gate electrode 16, a capacitor metal layer 18 is formed on the first insulating layer 17, and the capacitor metal layer 18 is simultaneously patterned to form a capacitor electrode plate 181 of the storage capacitor and a third gate electrode 182 of the N-type transistor 102.
Specifically, in the pixel driving circuit of the display panel 100, the capacitor electrode plate 181 and the first gate 16 form a storage capacitor, and the pixel driving circuit of the organic light emitting display panel may have structures of 2T1C, 7T1C, 8T2C, and the like, which are not described herein again.
Step S140: forming a second gate insulating layer on the third gate electrode, forming an N-type semiconductor layer on the second gate insulating layer, forming a third gate insulating layer on the N-type semiconductor layer, forming a second gate electrode on the third gate insulating layer, and forming an interlayer insulating layer on the second gate electrode.
Specifically, as shown in fig. 4, the second gate insulating layer 19 is formed on the third gate electrode 182, the N-type semiconductor layer 20 is formed on the second gate insulating layer 19, the third gate insulating layer 21 is formed on the N-type semiconductor layer 20, the second gate electrode 22 is formed on the third gate insulating layer 21, and the interlayer insulating layer 23 is formed on the second gate electrode 22.
It should be noted that, the steps S110, S120, S130 and S140 exemplify a manufacturing process of a partial film structure of the array substrate in the display panel 100, and when the array substrate in the display panel 100 is not limited to the structure shown in fig. 1, the manufacturing process of the array substrate in the display panel 100 may further include other processes besides the steps S110, S120, S130 and S140.
In some embodiments, as shown in fig. 5, in step S200, the first via 51 penetrates through the interlayer insulating layer 23 to the surface of the P-type semiconductor layer 14 away from the substrate 11, and the first opening 61 and the first opening 71 penetrate through the interlayer insulating layer 23 to the surface of the buffer layer 13 away from the substrate 11.
In some embodiments, as shown in fig. 6, in step S300, the second via 81 penetrates through the interlayer insulating layer 23 to the surface of the N-type semiconductor layer 20 away from the substrate 11, the second opening 62 penetrates through the buffer layer 13 to the surface of the light-shielding layer 12 away from the substrate 11, and the second opening 72 penetrates through the buffer layer 13 to the surface of the substrate 11 close to the light-shielding layer 12.
Specifically, by the arrangement of the first through hole 51, the second through hole 81, the first and second openings 61 and 62, and the first and second openings 71 and 72 in fig. 5 and 6, as shown in fig. 2 and 7, the first source and drain electrodes 241 and 242 may be connected to the P-type semiconductor layer 14, the second source and drain electrodes 243 and 244 may be connected to the N-type semiconductor layer 20, the connection electrode 245 may be connected to the light-shielding layer 12, and the filling layer 30 may be connected to the substrate 11.
In some embodiments, in step S300, the width of the second opening 62 is smaller than the width of the first opening 61, and the width of the second opening 72 is smaller than the width of the first opening 71.
Specifically, the inner diameter width of the second opening 62 is smaller than the inner diameter width of the first opening 61, and the inner diameter width of the second opening 72 is smaller than the inner diameter width of the first opening 71.
In some embodiments, the center of the orthographic projection of the first aperture 61 on the substrate 11 overlaps the center of the orthographic projection of the second aperture 62 on the substrate 11; the center of the orthographic projection of the first opening 71 on the substrate 11 overlaps the center of the orthographic projection of the second opening 72 on the substrate 11.
In some embodiments, the P-type semiconductor layer is a polysilicon material and the N-type semiconductor layer is an oxide semiconductor material.
In some embodiments, there is further included between step S300 and step S400 the step of: step S500, filling organic layers in the first opening and the second opening; further included after step S400 is: step S600, forming a light emitting device layer and an encapsulation layer.
Specifically, as shown in fig. 9, step S500 is further included between step S300 and step S400, and step S600 is further included after step S400.
Step S500: and filling the first opening and the second opening with organic layers.
Specifically, the first opening 71 and the second opening 72 are filled with the organic layer to form the filling layer 30, and then the manufacturing process of step S400 is performed, the source/drain metal layer 24 may be conveniently formed, so that the source/drain metal layer 24 is not formed and remains in the first opening 71 and the second opening 72.
Step S600: and forming a light-emitting device layer and an encapsulation layer.
Specifically, the structure of the display panel 100 further includes a light emitting device layer and an encapsulation layer (not illustrated in fig. 2), and thus further includes a step S600 after the step S400.
This application is through forming through-hole, trompil, opening simultaneously, forms two first through-holes, first trompil and first opening simultaneously through step S200, forms two second through-holes simultaneously through step S300, is located the second trompil in the first trompil to and be located the second opening in the first opening, can reduce the complexity of LTPO display panel' S manufacture craft, reduce light shield quantity, reduce cost.
According to the application, two first through holes, a first opening and a first opening are formed simultaneously through the same photomask (step S200), two second through holes, a second opening located in the first opening and a second opening located in the first opening are formed simultaneously through the same photomask (step S300), the complexity of the manufacturing process of the LTPO display panel can be reduced, the number of photomasks is reduced, and the cost is reduced.
EXAMPLE III
The embodiment of the present application further provides a display panel 100, and the display panel 100 is manufactured by using the manufacturing method of the display panel in any one of the above embodiments.
Specifically, for example, the display panel 100 includes the film layer structure shown in fig. 2. The film layer structure of the display panel 100 is not limited to the film layer structure shown in fig. 2.
The above detailed description is provided for the manufacturing method of the display panel and the display panel provided in the embodiments of the present application, and the principle and the implementation of the present application are explained by applying specific examples, and the above description of the embodiments is only used to help understanding the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. A manufacturing method of a display panel, the display panel comprises a display area and a non-display area, the non-display area comprises a bending area, and the method is characterized by comprising the following steps:
step S100, providing a substrate, forming a light shielding layer on the substrate, forming a buffer layer on the light shielding layer, forming a P-type semiconductor layer and a first grid electrode of a P-type transistor, and an N-type semiconductor layer and a second grid electrode of an N-type transistor on the buffer layer, and forming an interlayer insulating layer on the second grid electrode;
step S200: simultaneously forming two first through holes, a first opening and a first opening corresponding to the P-type transistor, wherein the first opening is positioned in the bending area;
step S300: forming two second through holes corresponding to the N-type transistors, a second opening in the first opening and a second opening in the first opening;
step S400: forming a source drain metal layer, and patterning the source drain metal layer to form a first source electrode and a first drain electrode of the P-type transistor, a second source electrode and a second drain electrode of the N-type transistor, and a connecting electrode; the first source electrode and the first drain electrode are respectively connected with the P-type semiconductor layer through the two first through holes, the second source electrode and the second drain electrode are respectively connected with the N-type semiconductor layer through the two second through holes, and the connecting electrode is connected with the shading layer through the first opening and the second opening.
2. The method for manufacturing a display panel according to claim 1, wherein in the step S400, the connection electrode is connected to one of the first source electrode and the first drain electrode, or/and the connection electrode is connected to one of the second source electrode and the second drain electrode.
3. The method for manufacturing a display panel according to claim 1, wherein the step S100 includes the steps of:
step S110: providing a substrate, forming a light shielding layer on the substrate, and forming a buffer layer on the light shielding layer;
step S120: forming the P-type semiconductor layer on the buffer layer, forming a first gate insulating layer on the P-type semiconductor layer, and forming the first gate on the first gate insulating layer;
step S130: forming a first insulating layer on the first gate, forming a capacitor metal layer on the first insulating layer, and simultaneously patterning the capacitor metal layer to form a capacitor electrode plate of a storage capacitor and a third gate of the N-type transistor;
step S140: forming a second gate insulating layer on the third gate electrode, forming the N-type semiconductor layer on the second gate insulating layer, forming a third gate insulating layer on the N-type semiconductor layer, forming the second gate electrode on the third gate insulating layer, and forming the interlayer insulating layer on the second gate electrode.
4. The method according to any one of claims 1 to 3, wherein in the step S200, the first via hole penetrates through the interlayer insulating layer to a surface of the P-type semiconductor layer away from the substrate, and the first opening penetrate through the interlayer insulating layer to a surface of the buffer layer away from the substrate.
5. The method of claim 4, wherein in the step S300, the second via hole penetrates through the interlayer insulating layer to a surface of the N-type semiconductor layer away from the substrate, the second opening penetrates through the buffer layer to a surface of the light-shielding layer away from the substrate, and the second opening penetrates through the buffer layer to a surface of the substrate close to the light-shielding layer.
6. The method of manufacturing a display panel according to claim 1, wherein in the step S300, an inner diameter width of the second opening is smaller than an inner diameter width of the first opening, and an inner diameter width of the second opening is smaller than an inner diameter width of the first opening.
7. The method of manufacturing a display panel according to claim 1, wherein a center of an orthographic projection of the first opening on the substrate overlaps a center of an orthographic projection of the second opening on the substrate;
a center of an orthographic projection of the first opening on the substrate overlaps a center of an orthographic projection of the second opening on the substrate.
8. The method for manufacturing a display panel according to claim 1, wherein the P-type semiconductor layer is a polycrystalline silicon material, and the N-type semiconductor layer is an oxide semiconductor material.
9. The method for manufacturing a display panel according to claim 1, further comprising, between the step S300 and the step S400: step S500: filling the first opening and the second opening with organic layers;
after the step S400, the method further includes: step S600: and forming a light-emitting device layer and an encapsulation layer.
10. A display panel manufactured by the method for manufacturing a display panel according to any one of claims 1 to 9.
CN202210121788.6A 2022-02-09 2022-02-09 Display panel manufacturing method and display panel Pending CN114551475A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210121788.6A CN114551475A (en) 2022-02-09 2022-02-09 Display panel manufacturing method and display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210121788.6A CN114551475A (en) 2022-02-09 2022-02-09 Display panel manufacturing method and display panel

Publications (1)

Publication Number Publication Date
CN114551475A true CN114551475A (en) 2022-05-27

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210121788.6A Pending CN114551475A (en) 2022-02-09 2022-02-09 Display panel manufacturing method and display panel

Country Status (1)

Country Link
CN (1) CN114551475A (en)

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