CN114551426A - Trans-impedance amplifier chip with WiFi interference signal capability and packaging method thereof - Google Patents

Trans-impedance amplifier chip with WiFi interference signal capability and packaging method thereof Download PDF

Info

Publication number
CN114551426A
CN114551426A CN202210125116.2A CN202210125116A CN114551426A CN 114551426 A CN114551426 A CN 114551426A CN 202210125116 A CN202210125116 A CN 202210125116A CN 114551426 A CN114551426 A CN 114551426A
Authority
CN
China
Prior art keywords
chip
amplifier
equivalent
amplifier chip
binding wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202210125116.2A
Other languages
Chinese (zh)
Other versions
CN114551426B (en
Inventor
王睿
赵欣
林颖帆
雷春桃
罗程
杨棵
陶蕤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chengdu Mingyi Electronic Technology Co ltd
Original Assignee
Chengdu Mingyi Electronic Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chengdu Mingyi Electronic Technology Co ltd filed Critical Chengdu Mingyi Electronic Technology Co ltd
Priority to CN202210125116.2A priority Critical patent/CN114551426B/en
Publication of CN114551426A publication Critical patent/CN114551426A/en
Application granted granted Critical
Publication of CN114551426B publication Critical patent/CN114551426B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H03F3/08—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
    • H03F3/082—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light with FET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Amplifiers (AREA)

Abstract

The invention provides a trans-impedance amplifier chip with WiFi interference signal capability, which is characterized in that an amplifier chip and a photoelectric conversion module are packaged in a trans-impedance amplifier packaging chip; set up three equivalent anti-interference module on trans-impedance amplifier encapsulation chip, specifically do: the amplifier chip in the trans-impedance amplifier packaging chip is provided with a first equivalent anti-interference module, and the input end of the first equivalent anti-interference module receives power supply required by the photoelectric conversion moduleSource VAPD_exThe output end of the photoelectric conversion module is connected with the input end of the photoelectric conversion module; secondly, setting an equivalent circuit comprising a binding wire equivalent inductor and setting a discrete capacitor; setting five TO pins on a trans-impedance amplifier packaging chip TO form an S parameter equivalent model; the invention improves the chip layout, the internal circuit and the packaging mode of the over-frequency high-speed trans-impedance amplifier, and improves the Wi-Fi signal interference resistance of the over-frequency high-speed trans-impedance amplifier by multilayer improvement.

Description

Trans-impedance amplifier chip with WiFi interference signal capability and packaging method thereof
Technical Field
The invention relates to the field of high-speed optical communication electric chips, in particular to a transimpedance amplifier chip with WiFi (wireless fidelity) interference signal capability and a packaging method thereof.
Background
Currently, mass production of optical modules in the optical communication field is shifting from a passive optical network GPON having a gigabit function to XGPON/XGSPON. Unlike GPON, the transmission rate of the receiving end of the optical network unit ONU in XGPON/XGSPON has increased from 2.5Gbps to 10 Gbps. Although the realization of 10Gbps does not pose a great challenge to the chip design of the receiving end due to the development of CMOS process, even if the avalanche photodiode APD is applied to receive light to improve sensitivity, the receiving end can only realize an error rate of more than 1x10-3 if the sensitivity is-29 dBm. On the other hand, as the function of a Wi-Fi router is integrated in the optical modem currently in the market, the OLT substrate of the XGPON/XGSPON also needs to integrate the function of Wi-Fi, which may cause the ONU receiving end to be interfered by the Wi-Fi signal. Generally, the carrier of the Wi-Fi signal is divided into 2.4GHz and 5GHz, and the two signal frequencies are close to the fundamental frequency and the first harmonic frequency of 10Gbps rate, and if the input of the ONU receiving end is mixed, the Wi-Fi signal cannot be distinguished from the real signal. Due to the high sensitivity requirement of the receiving end, the power of the Wi-Fi signal is very close to that of the real signal, so that the sensitivity of the receiving end is reduced and the requirement cannot be met. In conclusion, the problem that the ONU receiving end is interfered by Wi-Fi signals needs to be solved by the large-scale mass production of the XGPON/XGSPON.
Disclosure of Invention
In order to solve the problem that an ONU receiving end of the XGPON/XGSPON is interfered by Wi-Fi signals in the prior art, the invention provides a trans-impedance amplifier chip with WiFi signal interference capability and a packaging method thereof, which improve the chip layout, the internal circuit and the packaging mode of the over-frequency high-speed trans-impedance amplifier and improve the Wi-Fi signal interference resistance capability of the over-frequency high-speed trans-impedance amplifier by multilayer improvement.
The invention specifically comprises the following contents:
the invention provides a trans-impedance amplifier chip with WiFi interference signal capability, which is characterized in that an amplifier chip and a photoelectric conversion module are packaged in a trans-impedance amplifier packaging chip; set up three equivalent anti-interference module on trans-impedance amplifier encapsulation chip, specifically do:
firstly, a signal processing module and a first equivalent anti-interference module are arranged in an amplifier chip in a trans-impedance amplifier packaging chip, and the input end of the first equivalent anti-interference module receives a power supply V required by a photoelectric conversion moduleAPD_exThe output end of the photoelectric conversion module is connected with the input end of the photoelectric conversion module; the output end of the photoelectric conversion module is connected with the input end of a signal processing module in the amplifier chip;
secondly, arranging an equivalent circuit comprising a binding wire equivalent inductor outside the amplifier chip inside the trans-impedance amplifier packaging chip, and arranging a discrete capacitor on the equivalent circuit connecting the photoelectric conversion module and the amplifier chip;
setting five TO pins on a trans-impedance amplifier packaging chip TO form an S parameter equivalent model; five TO pins are respectively connected with a power supply V of the trans-impedance amplifier packaging chip for supplying power TO a power supplyDD_exTerminal of, power supply source V for supplying power to negative terminal of photoelectric conversion moduleAPD_exThe wiring terminal, two output ends of the trans-impedance amplifier packaging chip for outputting the AC coupling capacitor and the load resistor, and a ground end GND connected with the first equivalent anti-interference modulechipThe terminal of (2).
In order to better implement the present invention,further, the first equivalent anti-jamming module comprises an anti-jamming resistor Ron-chipAnd an anti-interference capacitor Con-chip；
The anti-interference resistor Ron-chipV of the input terminal of the amplifier chipAPD-chipPin connection power supply source VAPD_ex(ii) a Anti-interference resistor Ron-chipOutput terminal of the amplifier chip through a PINKchipThe pin is connected with the input end of the photoelectric conversion module;
the anti-interference capacitor Con-chipOne end of the ground terminal GND is connected with the amplifier chipchipAnd the other end is lapped on the PINK of the amplifier chipchipPin and anti-interference resistor Ron-chipBetween the output terminals of (a).
In order to better implement the invention, further, an equivalent circuit arranged outside the amplifier chip inside the trans-impedance amplifier packaging chip comprises a binding wire equivalent inductor LBW1Equivalent inductance L of binding wireBW2Equivalent inductance L of binding wireBW3Equivalent inductance L of binding wireBW4Equivalent inductance L of binding wireBW5Equivalent inductance L of binding wireBW6Equivalent inductance L of binding wireBW7Equivalent inductance L of binding wireBW8Equivalent inductance L of binding wireBW9Equivalent inductance L of binding wireBW10TO ground terminal GNDTODiscrete capacitor C1Discrete capacitor C2Discrete capacitor C3；
The binding wire equivalent inductance LBW1Is supplied to a power supply VDD_exThe input end is connected with a binding wire equivalent inductor LBW2Equivalent inductance L through binding wireBW2V with amplifier chipAPD-chipConnecting pins; the discrete capacitor C1One end is connected with the TO ground end GNDTOAnd the other end is lapped on the binding wire equivalent inductor LBW1Equivalent inductance L of binding wireBW2To (c) to (d);
the binding wire equivalent inductance LBW6Input end power supply source VDD_exThe input end is connected with a binding wire equivalent inductor LBW7Equivalent inductance L through binding wireBW7V with amplifier chipDD-chipConnecting pins; the discrete capacitor C3One end is connected with the TO ground end GNDTOAnd the other end is lapped on the binding wire equivalent inductor LBW6Equivalent inductance L of binding wireBW7To (c) to (d);
the binding wire equivalent inductance LBW9Equivalent inductance L of binding wireBW10The two output ends of the amplifier chip are respectively connected;
the binding wire equivalent inductance LBW4PINK with one end connected with amplifier chipchipThe other end of the pin is connected with the input end of the photoelectric conversion module;
the binding wire equivalent inductance LBW5PINA with one end connected with amplifier chipchipPins and through PINAchipThe pin is connected with the signal processing module, and the other end of the pin is connected with the output end of the photoelectric conversion module;
the binding wire equivalent inductance LBW3One end of the second connecting line is lapped on the input end of the photoelectric conversion module and the binding wire equivalent inductor LBW4Between the output ends of the two capacitors, the other end is connected with a discrete capacitor C2Rear and TO ground GNDTOConnecting;
the binding wire equivalent inductance LBW8Lap joint at the ground end GND of the amplifier chipchipThe above.
In order TO better implement the invention, further, the five TO pins include a first TO pin, a second TO pin, a third TO pin, a fourth TO pin and a fifth TO pin; the specific setting is as follows: the first TO pin is connected with a power supply VAPD_exEquivalent inductance L of rear and binding wireBW1The input ends of the two-way valve are connected; the second TO pin is connected with a power supply VDD_exEquivalent inductance L of rear and binding wireBW6Is connected with the input end of the power supply; equivalent inductance L of the third TO pin and the binding wire after being groundedBW8Connecting; the fourth TO pin and the fifth TO pin are respectively lapped on the binding wire equivalent inductor LBW9Equivalent inductance L of binding wireBW10On the output terminal of the switch.
In order to better implement the present invention, further, a first load capacitor C is further includedload1A second load capacitor Cload2A first load resistor Rload1A second load resistor Rload2；
The first mentionedA load capacitor Cload1A first load resistor Rload1The second TO pin is connected with the third TO pin after being grounded in series; the second load capacitor Cload2A second load resistor Rload2And the series connection is grounded and then connected with the fourth TO pin.
The invention also provides a trans-impedance amplifier chip with WiFi interference signal capability, which is characterized in that the amplifier chip and the photoelectric conversion module are packaged in the trans-impedance amplifier packaging chip; set up three equivalent anti-interference module on trans-impedance amplifier encapsulation chip, specifically do:
firstly, a signal processing module and a first equivalent anti-interference module are arranged in an amplifier chip in a trans-impedance amplifier packaging chip, and the input end of the first equivalent anti-interference module receives a power supply V required by a photoelectric conversion moduleAPD_exThe output end of the photoelectric conversion module is connected with the input end of the photoelectric conversion module; the output end of the photoelectric conversion module is connected with the input end of a signal processing module in the amplifier chip;
secondly, arranging an equivalent circuit outside the amplifier chip in the trans-impedance amplifier packaging chip, and arranging a discrete capacitor on the equivalent circuit connecting the photoelectric conversion module and the amplifier chip;
setting five TO pins on a trans-impedance amplifier packaging chip TO form an S parameter equivalent model; five TO pins are respectively connected with a power supply V of the trans-impedance amplifier packaging chip for supplying power TO a power supplyDD_exTerminal of, power supply source V for supplying power to negative terminal of photoelectric conversion moduleAPD_exThe wiring terminal, two output ends of the trans-impedance amplifier packaging chip for outputting the AC coupling capacitor and the load resistor, and a ground end GND connected with the first equivalent anti-interference modulechipThe terminal of (1);
the signal processing module comprises a voltage stabilizing module, a preamplifier module and a post-stage circuit module;
the input end of the voltage stabilizing module is connected with a power supply on the amplifier chip, and the output end of the voltage stabilizing module is connected with the preamplifier module and the post-stage circuit module;
the input end of the preamplifier module is connected with a PINA end pin of the amplifier chip; the output end of the output end is connected with the input end of the post-stage circuit module;
the output end of the post-stage circuit module and the OUT of the amplifier chipNEnd connection;
the PINA end and the PINK end of the amplifier chip are connected with a photoelectric conversion module;
v of the amplifier chipAPD_ChipThe end is connected with a first filtering unit; v of the amplifier chipDD_ChipThe end is connected with a second filtering unit; the grounding end of the amplifier chip is connected with a third filtering unit; OUT of the amplifier chipNThe end is connected with a load unit.
In order to better implement the present invention, further, the preamplifier module includes a preamplifier unit, a feedback resistance unit;
the preamplifier unit comprises a current processing unit, an inverter unit and a current mirror unit;
the input end of the current processing unit is connected with a PINA end pin of the amplifier chip, and the output end of the current processing unit is connected with the inverter unit;
the current mirror unit is connected with the inverter unit;
the feedback resistance unit is lapped on the input end and the output end of the phase inverter unit;
and the output end of the reverser unit is connected with the rear-stage circuit module.
In order to better implement the present invention, further, the inverter unit includes three sets of inverters, which are a first inverter, a second inverter, and a third inverter, respectively;
the input end of the first phase inverter is connected with the output end of the current processing unit, and the output end of the first phase inverter is connected with the input end of the second phase inverter;
the input end of the third inverter is connected with the output end of the second inverter, and the output end of the third inverter is connected with the rear-stage circuit module;
the three groups of inverters are sequentially connected in a link manner, the input end of the first inverter is a pole A, the output end of the first inverter and the input end of the second inverter are a pole B, the output end of the second inverter and the input end of the third inverter are a pole C, and the output end of the third inverter is a pole D; the pole C and the pole D are output ends of the pre-transimpedance amplifier connected with the post-stage circuit module;
the feedback resistance unit is a resistor R1Said resistance R1The pole B and the output end of the second inverter are lapped;
and the pole A is a connecting end of the inverter unit and the current processing unit.
The invention also provides a packaging method of the trans-impedance amplifier chip with the WiFi interference signal capability, based on the trans-impedance amplifier chip with the WiFi interference signal capability, the trans-impedance amplifier packaging chip is subjected to anti-WiFi interference packaging treatment based on the following operations:
operation 1: integrating a first equivalent anti-interference module inside the amplifier chip to receive the power supply V required by the photoelectric conversion moduleAPD_exCarrying out anti-interference treatment and then outputting the anti-interference treatment to a photoelectric conversion module;
operation 2: arranging an equivalent circuit comprising a binding wire equivalent inductor outside the amplifier chip inside the trans-impedance amplifier packaging chip, arranging a discrete capacitor on the equivalent circuit connecting the photoelectric conversion module and the amplifier chip, and improving the WiFi interference resistance of the amplifier chip by combining the discrete capacitor with the equivalent circuit through the equivalent circuit;
operation 3: adding five TO pins, and connecting the TO pins and the amplifier chip by using a binding wire equivalent inductor; a more stable path is provided to filter out WiFi interference signals than the ground of the amplifier chip.
The invention also provides a packaging method of the trans-impedance amplifier chip with the WiFi interference signal capability, and based on the trans-impedance amplifier chip with the WiFi interference signal capability, when the trans-impedance amplifier chip is packaged and distributed, the phase inverter units are subjected to layout in a mirror symmetry mode.
The invention also provides a packaging method of the trans-impedance amplifier chip with the WiFi interference signal capability, and based on the trans-impedance amplifier chip with the WiFi interference signal capability, the layout of the amplifier chip is improved, and the specific improvement is as follows: the amplifier chip is provided with a magnetic field shielding layer to be connected with the chip ground end of the transimpedance amplifier, and an induced current generated by a variable magnetic field in the amplifier chip is guided to a ground port outside the amplifier chip through the magnetic field shielding layer.
In order to better implement the present invention, further, pads are uniformly arranged on the ground end of the amplifier chip in each direction, and the magnetic field shielding layer is connected to the pads of the amplifier chip to shield the amplifier chip from the WiFi interference signal in all directions.
In order to better implement the invention, a plurality of metal laminations communicated with the substrate of the amplifier chip are further arranged between the bonding pad of the grounding end of the amplifier chip and the electromagnetic shielding layer.
In order to better implement the invention, further, the magnetic field shielding layer is provided in a hollowed-out form.
The invention has the following beneficial effects:
according to the trans-impedance amplifier chip with the WiFi signal interference capability and the packaging method thereof, the improved amplifier chip improves the inhibition effect of a receiving end system on Wi-Fi signal interference, does not have any influence on the sensitivity and the error rate of the receiving end system, does not have higher requirements on the current chip process and packaging technology, and enhances the universality of the application.
Drawings
FIG. 1 is a circuit schematic of an amplifier chip;
FIG. 2 is a schematic diagram of a mirror-symmetrical layout of some components in the schematic diagram of the transimpedance amplifier circuit of FIG. 1;
FIG. 3 is a chip layout of the amplifier chip of FIGS. 1 and 5;
FIG. 4 is a schematic diagram of a metal stack of the transimpedance amplifier of FIG. 3;
FIG. 5 is a schematic circuit diagram of a transimpedance amplifier package chip according to the present invention;
FIG. 6 is a schematic view of a conventional binding-wire;
FIG. 7 is a schematic diagram of an improved wire binding mode of the chip packaged with the transimpedance amplifier according to the present invention;
FIG. 8 shows a voltage signal PINK at the negative terminal when the avalanche diode APD is used as the photoelectric conversion modulerealAnd GNDTOGraph of frequency response of ground terminal differential signal.
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and therefore should not be considered as a limitation to the scope of protection. All other embodiments, which can be obtained by a worker skilled in the art based on the embodiments of the present invention without making creative efforts, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Example 1:
the embodiment provides a transimpedance amplifier chip with WiFi interference signal capability, which is characterized in that an amplifier chip and a photoelectric conversion module are packaged in the transimpedance amplifier packaging chip; as shown in fig. 5, three equivalent anti-interference modules are disposed on the transimpedance amplifier package chip, specifically:
firstly, a signal processing module and a first equivalent anti-interference module are arranged in an amplifier chip in a trans-impedance amplifier packaging chip, and the input end of the first equivalent anti-interference module receives a power supply V required by a photoelectric conversion moduleAPD_exThe output end of the photoelectric conversion module is connected with the input end of the photoelectric conversion module; the output end of the photoelectric conversion module and the amplifier chipThe input end of the signal processing module is connected;
secondly, arranging an equivalent circuit comprising a binding wire equivalent inductor outside the amplifier chip inside the trans-impedance amplifier packaging chip, and arranging a discrete capacitor on the equivalent circuit connecting the photoelectric conversion module and the amplifier chip;
setting five TO pins on a trans-impedance amplifier packaging chip TO form an S parameter equivalent model; five TO pins are respectively connected with a power supply V of the trans-impedance amplifier packaging chip for supplying power TO a power supplyDD_exTerminal of, power supply source V for supplying power to negative terminal of photoelectric conversion moduleAPD_exThe wiring terminal, two output ends of the trans-impedance amplifier packaging chip for outputting the AC coupling capacitor and the load resistor, and a ground end GND connected with the first equivalent anti-interference modulechipThe terminal of (2).
The working principle is as follows: the improvement mode aiming at the chip layout is mainly used for resisting the influence of current induced after a Wi-Fi interference signal generates a changing magnetic field through spatial coupling on the sensitivity of the chip. Wi-Fi signals can also interfere with the power supply of the chip and the negative side supply of the APD by coupling spatially, which must be countered by packaging modifications. And the design of package improvement requires establishing a completely new equivalent circuit analysis method to see the differences of different packaging modes. Generally, the stability of the chip power supply can be guaranteed by the LDO inside the chip. If conditions permit, a decoupling capacitor can be added to the package to further reduce power supply interference outside the package. And because the voltage of the chip power supply is lower, a decoupling capacitor can be added in the chip, and the capacitance density of the chip is also higher. Therefore, the equivalent circuit analysis method proposed in this patent mainly discusses how to stabilize the negative terminal power supply of the APD to reduce Wi-Fi signal interference.
The equivalent circuit for resisting Wi-Fi signal interference proposed by the patent is shown in figure 5. The equivalent circuit comprises three parts. The first part is a circuit outside the package, which comprises an S parameter equivalent model of five TO pins, and a power supply source V outside the package for supplying power TO a chip power supplyDD_exAnd a power supply V for supplying power to the APD negative terminal outside the packageAPD_exAnd chip transportAn AC coupling capacitor and a load resistor. The second part is an equivalent circuit outside the chip in the package, wherein the equivalent circuit comprises a binding wire equivalent inductance (L)BW1~10) TO Ground (GND)TO) Equivalent capacitance of APD, and discrete capacitance (C) for improving Wi-Fi signal resistance of the patent1~3). The third part is the chip interior, which includes an on-chip integrated resistor (R)on-chip) And a high-voltage capacitor (C)on-chip) Transimpedance amplifier and its post-circuit module, LDO and on-chip power supply and ground (V)APD_Chip，VDD_ChipAnd GNDChip). Since the equivalent circuit is used to analyze how to stabilize the negative side power supply of the APD to reduce Wi-Fi signal interference, this patent is at VAPD_exAnd an alternating current signal is added at the power supply, and the influence of the Wi-Fi signal is judged through alternating current analysis.
The improvement mode aiming at the chip layout is mainly used for resisting the influence of current induced after a Wi-Fi interference signal generates a changing magnetic field through spatial coupling on the sensitivity of the chip. Wi-Fi signals can also interfere with the power supply of the chip and the negative side supply of the APD by coupling spatially, which must be countered by packaging modifications. And the design of package improvement requires establishing a completely new equivalent circuit analysis method to see the differences of different packaging modes. Generally, the stability of the chip power supply can be guaranteed by the LDO inside the chip. If conditions permit, a decoupling capacitor can be added to the package to further reduce power supply interference outside the package. And because the voltage of the chip power supply is lower, a decoupling capacitor can be added in the chip, and the capacitance density of the chip is also higher. Therefore, the equivalent circuit analysis method proposed in this patent mainly discusses how to stabilize the negative terminal power supply of the APD to reduce Wi-Fi signal interference.
Example 2:
in this embodiment, in order to better implement the present invention based on the above embodiment 1, as shown in fig. 5, further, the first equivalent anti-jamming module includes an anti-jamming resistor Ron-chipAnd an anti-interference capacitor Con-chip；
The anti-interference resistor Ron-chipV of the input terminal of the amplifier chipAPD-chipPin connection power supply source VAPD_ex(ii) a Anti-interference resistor Ron-chipOutput terminal of the amplifier chip through a PINKchipThe pin is connected with the input end of the photoelectric conversion module;
the anti-interference capacitor Con-chipOne end of the ground terminal GND is connected with the amplifier chipchipAnd the other end is lapped on the PINK of the amplifier chipchipPin and anti-interference resistor Ron-chipBetween the output terminals of (a).
The working principle is as follows: on the circuit design level, the patent also makes an improvement on the traditional design. In the traditional receiving end chip design, the power supply to the negative end of the APD has no relation with the chip. Therefore, if the power supply of the APD is required to be filtered to reduce the influence of power supply interference outside the package on the APD, the resistance and the capacitance used for filtering are required to be replaced by discrete devices, so that the production cost is greatly improved, and the resistance and the capacitance of the discrete devices are not accurate and have poor high-frequency characteristics. Therefore, in the improved circuit design, a 400 ohm poly resistor (R) is integrated on the chipon-chip) And 20 picofarads of high voltage capacitance (C)on-chip) And a first-order RC low-pass filter is formed between the two, so that power supply for the APD from the outside is firstly connected to a bonding pad of a chip, then passes through the low-pass filter in the chip, and finally comes out from the bonding pad of the chip and is connected to the negative end of the APD. Thus, the first-order filtering of the power supply for supplying the APD can be realized without adding any discrete device.
Other parts of this embodiment are the same as those of embodiment 1, and thus are not described again.
Example 3:
in this embodiment, on the basis of the above embodiments 1-2, in order to better implement the present invention, as shown in fig. 5, fig. 6, fig. 7, and fig. 8, an equivalent circuit disposed outside the amplifier chip inside the transimpedance amplifier package chip includes a bond wire equivalent inductor LBW1Equivalent inductance L of binding wireBW2Equivalent inductance L of binding wireBW3Equivalent inductance L of binding wireBW4Binding wireEquivalent inductance LBW5Equivalent inductance L of binding wireBW6Equivalent inductance L of binding wireBW7Equivalent inductance L of binding wireBW8Equivalent inductance L of binding wireBW9Equivalent inductance L of binding wireBW10TO ground terminal GNDTODiscrete capacitor C1Discrete capacitor C2Discrete capacitor C3；
The binding wire equivalent inductance LBW1Is supplied to a power supply VDD_exThe input end is connected with a binding wire equivalent inductor LBW2Equivalent inductance L through binding wireBW2V with amplifier chipAPD-chipConnecting pins; the discrete capacitor C1One end is connected with the TO ground end GNDTOAnd the other end is lapped on the binding wire equivalent inductor LBW1Equivalent inductance L of binding wireBW2To (c) to (d);
the binding wire equivalent inductance LBW6Input end power supply source VDD_exThe input end is connected with a binding wire equivalent inductor LBW7Equivalent inductance L through binding wireBW7V with amplifier chipDD-chipConnecting pins; the discrete capacitor C3One end is connected with the TO ground end GNDTOThe other end is connected with the binding wire equivalent inductor L in a lap joint modeBW6Equivalent inductance L of binding wireBW7To (c) to (d);
the binding wire equivalent inductance LBW9Equivalent inductance L of binding wireBW10The two output ends of the amplifier chip are respectively connected;
the binding wire equivalent inductance LBW4PINK with one end connected with amplifier chipchipThe other end of the pin is connected with the input end of the photoelectric conversion module;
the binding wire equivalent inductance LBW5PINA with one end connected with amplifier chipchipPins and through PINAchipThe pin is connected with the signal processing module, and the other end of the pin is connected with the output end of the photoelectric conversion module;
the binding wire equivalent inductance LBW3One end of the second connecting line is lapped on the input end of the photoelectric conversion module and the binding wire equivalent inductor LBW4Between the output ends of the two capacitors, the other end is connected with a discrete capacitor C2Rear and TO ground GNDTOConnecting;
the binding wire equivalent inductance LBW8Lap joint is at the ground end GND of the amplifier chipchipThe above.
Furthermore, the five TO pins comprise a first TO pin, a second TO pin, a third TO pin, a fourth TO pin and a first five TO pin; the specific setting is as follows: the first TO pin is connected with a power supply VAPD_exEquivalent inductance L of rear and binding wireBW1The input ends of the two-way valve are connected; the second TO pin is connected with a power supply VDD_exEquivalent inductance L of rear and binding wireBW6The input ends of the two-way valve are connected; the third TO pin is grounded and then is equivalent TO the binding wire TO form an inductor LBW8Connecting; the fourth TO pin and the fifth TO pin are respectively lapped on the binding wire equivalent inductor LBW9Equivalent inductance L of binding wireBW10On the output terminal of the switch.
The working principle is as follows: in this patent, an external power supply V is packagedAPD_exThe APD is powered from outside the package through the chip interior through a series of wirebonding schemes and finally to the negative terminal of the APD. So if VAPD_exUnder the interference of Wi-Fi signals, the Wi-Fi signals directly interfere the power supply of the negative terminal of the APD under the condition that no filtering decoupling exists, and as a result, the output current of the APD is modulated by the Wi-Fi signals, so that the current entering the trans-impedance amplifier also comprises the Wi-Fi interference signals, and the sensitivity of a receiving terminal is influenced. In another aspect, V is for the positive terminal of the APDAPD_exIndirectly coupled through the equivalent capacitance of the APD itself; as long as the decoupling of the negative terminal of the APD is well done, the interference of Wi-Fi signals on the positive terminal of the APD is also reduced, so in an equivalent circuit, the problem that the negative terminal of the APD is subjected to V is mainly considered in the patentAPD_exThe influence of (c). Theoretically, since the ground of the package is larger than that of the chip, and the ground of the chip is tied TO the ground of the TO through the wire-tying inductor, and the TO ground provides a path for filtering the interference signal more stably and effectively than the chip ground, the wire-tying scheme proposed by the present patent is expected TO enable the voltage signal (PINK) finally reaching the negative terminal of the APD (avalanche photo diode)real) More stable with respect TO. In summary, the patent refers to the PINK and the accompanying drawings, which are incorporated herein by reference, and which show equivalent circuit diagrams for resisting Wi-Fi signal interferencerealAnd GNDTOThe frequency response of the differential signals is used for judging the capability of different wire binding schemes for resisting Wi-Fi interference signals.
As shown in fig. 6 and 7, the binding-wire proposed in the present patent is shown in fig. 7, while the conventional binding-wire is shown in fig. 6. Direct binding V of traditional binding wire diagramDD_exAnd VAPD_exAnd V of chipDD_ChipAnd VAPD_ChipDirectly connected by binding wires, so that the voltage signal (PINK) of the negative terminal of the APDreal) Only first-order filtering exists relative TO the TO ground, and the filtering frequency is relatively high, so that the filtering effect at high frequency is not good, specifically, comparison can be carried out through a graph 8, wherein a line 1 in the graph 8 is PINK in a traditional moderealAnd GNDTOFrequency response curve of differential signal, line 2 is PINK under improved moderealAnd GNDTOA frequency response curve of the differential signal; as can be seen from line 1 of fig. 8: if the Wi-Fi signal passes through VAPD_exCoupled to PINKrealAnd the traditional wire binding mode only provides 42dB of isolation for 2.4GHz Wi-Fi signals and provides 47dB of isolation for 5GHz Wi-Fi signals.
The brand new binding wire proposal proposed by the patent is improved as follows: at VDD_exAnd VDD_ChipA capacitor with 1nF is connected in parallel between the two capacitors; at VAPD_exAnd VAPD_ChipA high-voltage capacitor of 470pF is connected in parallel between the two capacitors; another 470pF high voltage capacitor is placed directly at the bottom of the APD, and the negative terminal of the APD is connected to the capacitor directly through a very short binding wire; the PINK of the chip is connected to the capacitor at the bottom of the APD through two binding wires. As can be seen from line 2 of FIG. 8, the proposed wire binding scheme of this patent is applied to the voltage signal (PINK) at the negative terminal of the APDreal) Two-order filtering is provided relative TO the TO ground, and the frequency of the first-order filtering is less than 1MHz, so that the wire binding scheme provided by the patent provides 69dB of isolation for 2.4GHz Wi-Fi signals, 62dB of isolation for 5GHz Wi-Fi signals, and the isolation is respectively improved by 27dB and 15dB compared with the traditional wire binding. The binding-wire proposed by this patent is proposed for APDs with PINK on the front side. If PINK is on the back of APD, the capacitor at the bottom of APD can be directly connected without binding wires, and the ability of the binding wire scheme provided by the patent to resist Wi-Fi signals is stronger.
The other parts of this embodiment are the same as those of the above embodiments 1-2, and thus are not described again.
Example 4:
in this embodiment, on the basis of any one of the above embodiments 1 to 3, in order to better implement the present invention, as shown in fig. 5, a first load capacitor C is further includedload1A second load capacitor Cload2A first load resistor Rload1A second load resistor Rload2；
The first load capacitor Cload1A first load resistor Rload1The second TO pin is connected with the third TO pin after being grounded in series; the second load capacitor Cload2A second load resistor Rload2And the series connection is grounded and then connected with the fourth TO pin.
Other parts of this embodiment are the same as any of embodiments 1 to 3, and thus are not described again.
Example 5:
the embodiment further provides a method for packaging a transimpedance amplifier chip with WiFi interference signal capability, where based on the transimpedance amplifier chip with WiFi interference signal capability described in the above embodiments 1 to 4, the transimpedance amplifier chip is subjected to WiFi interference resistant packaging processing based on the following operations:
operation 1: integrating a first equivalent anti-interference module inside the amplifier chip to receive the power supply V required by the photoelectric conversion moduleAPD_exCarrying out anti-interference treatment and then outputting the anti-interference treatment to a photoelectric conversion module;
operation 2: arranging an equivalent circuit comprising a binding wire equivalent inductor outside the amplifier chip inside the trans-impedance amplifier packaging chip, arranging a discrete capacitor on the equivalent circuit connecting the photoelectric conversion module and the amplifier chip, and improving the WiFi interference resistance of the amplifier chip by combining the discrete capacitor with the equivalent circuit through the equivalent circuit;
operation 3: adding five TO pins, and connecting the TO pins with the amplifier chip by using binding wire equivalent inductors; a more stable path is provided to filter out WiFi interference signals than the ground of the amplifier chip.
Other parts of this embodiment are the same as any of embodiments 1 to 4, and thus are not described again.
Example 6:
the embodiment also provides a transimpedance amplifier chip with WiFi interference signal capability, as shown in fig. 1 and 5, an amplifier chip and a photoelectric conversion module are packaged in the transimpedance amplifier package chip; set up three equivalent anti-interference module on trans-impedance amplifier encapsulation chip, specifically do:
firstly, a signal processing module and a first equivalent anti-interference module are arranged in an amplifier chip in a trans-impedance amplifier packaging chip, and the input end of the first equivalent anti-interference module receives a power supply V required by a photoelectric conversion moduleAPD_exThe output end of the photoelectric conversion module is connected with the input end of the photoelectric conversion module; the output end of the photoelectric conversion module is connected with the input end of a signal processing module in the amplifier chip;
secondly, arranging an equivalent circuit outside the amplifier chip inside the trans-impedance amplifier packaging chip, and arranging a discrete capacitor on the equivalent circuit connecting the photoelectric conversion module and the amplifier chip;
setting five TO pins on a trans-impedance amplifier packaging chip TO form an S parameter equivalent model; five TO pins are respectively connected with a power supply V of the trans-impedance amplifier packaging chip for supplying power TO a power supplyDD_exTerminal of, power supply source V for supplying power to negative terminal of photoelectric conversion moduleAPD_exThe wiring terminal, two output ends of the trans-impedance amplifier packaging chip for outputting the AC coupling capacitor and the load resistor, and a ground end GND connected with the first equivalent anti-interference modulechipThe terminal of (1);
the signal processing module comprises a voltage stabilizing module, a preamplifier module and a post-stage circuit module;
the input end of the voltage stabilizing module is connected with a power supply on the amplifier chip, and the output end of the voltage stabilizing module is connected with the preamplifier module and the post-stage circuit module;
the input end of the preamplifier module is connected with a PINA end pin of the amplifier chip; the output end is connected with the input end of the rear-stage circuit module;
the output end of the post-stage circuit module and the OUT of the amplifier chipNEnd connection;
the PINA end and the PINK end of the amplifier chip are connected with a photoelectric conversion module;
v of the amplifier chipAPD_ChipThe end is connected with a first filtering unit; v of the amplifier chipDD_ChipThe end is connected with a second filtering unit; the grounding end of the amplifier chip is connected with a third filtering unit; OUT of the amplifier chipNThe end is connected with a load unit.
The specific amplifier chip described in the present application is also designed with a series of related chips, and is described in patent document 2021113519420 and patent document 2021113518362, which were previously filed by the applicant, for reference.
Example 7:
in this embodiment, on the basis of the above embodiment 6, in order to better implement the present invention, as shown in fig. 1, the preamplifier module includes a preamplifier unit and a feedback resistor unit;
the preamplifier unit comprises a current processing unit, an inverter unit and a current mirror unit;
the input end of the current processing unit is connected with a PINA end pin of the amplifier chip, and the output end of the current processing unit is connected with the inverter unit;
the current mirror unit is connected with the inverter unit;
the feedback resistance unit is lapped on the input end and the output end of the phase inverter unit;
and the output end of the reverser unit is connected with the rear-stage circuit module.
In order to better implement the present invention, further, the inverter unit includes three sets of inverters, which are a first inverter, a second inverter, and a third inverter, respectively;
the input end of the first phase inverter is connected with the output end of the current processing unit, and the output end of the first phase inverter is connected with the input end of the second phase inverter;
the input end of the third inverter is connected with the output end of the second inverter, and the output end of the third inverter is connected with the rear-stage circuit module;
the three groups of inverters are sequentially connected in a link manner, the input end of the first inverter is a pole A, the output end of the first inverter and the input end of the second inverter are a pole B, the output end of the second inverter and the input end of the third inverter are a pole C, and the output end of the third inverter is a pole D; the pole C and the pole D are output ends of the pre-transimpedance amplifier connected with the post-stage circuit module;
the feedback resistance unit is a resistor R1Said resistance R1The pole B and the output end of the second inverter are lapped;
and the pole A is a connecting end of the inverter unit and the current processing unit.
The working principle is as follows: as shown in fig. 1, the inverter unit includes three sets of inverter combinations, which are a first inverter, a second inverter, and a third inverter;
the first phase inverter comprises a first PMOS tube and a first NMOS tube; the grid electrodes of the first PMOS tube and the first NMOS tube are used as the input end of the first phase inverter; the drain electrodes of the first PMOS tube and the first NMOS tube are used as the output end of the first phase inverter; the source electrode of the first PMOS tube is connected with the current mirror unit, and the source electrode of the first NMOS tube is grounded;
the second phase inverter comprises a second PMOS tube and a second NMOS tube; the grid electrodes of the second PMOS tube and the second NMOS tube are used as the input end of the second phase inverter; the drain electrodes of the second PMOS tube and the second NMOS tube are used as the output end of the second phase inverter; the source electrode of the second PMOS tube is connected with the current mirror unit, and the source electrode of the second NMOS tube is grounded;
the third phase inverter comprises a third PMOS tube and a third NMOS tube; the grid electrodes of the third PMOS tube and the third NMOS tube are used as the input end of the third phase inverter; the drain electrodes of the third PMOS tube and the third NMOS tube are used as the output end of the third phase inverter; the source electrode of the third PMOS tube is connected with the current mirror unit, and the source electrode of the third NMOS tube is grounded;
the three groups of inverters are sequentially connected in a link manner, the input end of the first inverter is a pole A, the output end of the first inverter and the input end of the second inverter are a pole B, the output end of the second inverter and the input end of the third inverter are a pole C, and the output end of the third inverter is a pole D; the pole C and the pole D are output ends of the pre-transimpedance amplifier and the continuous time equalizer;
the feedback resistance unit is lapped on the pole A and the pole D;
and the pole A is a connecting end of the inverter unit and the current processing unit.
As shown in fig. 1, the input signal is a current signal Iin photoelectrically converted by a photodiode, and has dc and ac components. The pre-transimpedance amplifier has the main function of bypassing the direct-current component of the current signal and amplifying the alternating-current component into a voltage signal output without distortion as much as possible.
Three groups of inverters of a feed-forward amplifier in the trans-impedance amplifier are respectively combined by PM1 and NM 1; PM2, NM2 combination; PM3, NM3 in combination, provide an open loop gain of sufficient magnitude to help reduce the input impedance of the transimpedance amplifier and increase bandwidth. When all the inverters are the same in size, the four-point direct-current voltages of A, B, C and D are basically consistent, so that the current can be evenly distributed into three groups of inverters in a dynamic range, and each group of inverters can achieve the optimal gain-bandwidth product. Therefore, the gain bandwidth product of the feedforward amplifier formed by cascading three inverters is far larger than that of the feedforward amplifier formed by only one inverter in the traditional scheme, the bandwidth of a closed-loop system after trans-impedance feedback can be greatly expanded, the problem of intersymbol interference caused by insufficient bandwidth is solved, and main help is provided for the over-frequency success of the whole system. When the gain of the feedforward amplifier is increased, the transimpedance gain can be properly increased on the premise of ensuring the bandwidth so as to reduce the size of the input equivalent noise and improve the sensitivity of the system. Finally, because the direct-current voltage of the point C is consistent with that of the point D, and the signals at the two positions are in differential complementation, the signals at the two positions C and D can be directly connected to the differential input of the next-stage high-speed circuit, compared with the traditional design, one path of reference circuit can be saved, and the capability of the circuit for resisting common-mode interference can be improved when the differential signals enter the next stage.
Except that the direct current component of the signal is removed through the direct current offset eliminator, in order to avoid distortion of an output signal of the pre-transimpedance amplifier caused by overlarge input alternating current component, the transimpedance, namely, the transimpedance gain of the pre-transimpedance amplifier needs to be reduced through the automatic gain controller after the condition is met. In addition, when the transimpedance is reduced, the direct-current gain of a feed-forward amplifier consisting of the three phase inverters is ensured to be unchanged, the input impedance of the preposed transimpedance amplifier at the point A can be correspondingly reduced, and the condition that the input voltage at the point A of the preposed transimpedance amplifier is too large and enters the states of amplitude limiting and distortion when large current is input is avoided. However, the dc gain of the three-inverter combination is not changed, which results in the input impedance at the a point position becoming smaller in the low transimpedance mode under the automatic gain control. This may shift the dominant pole of the a-point location towards high frequencies close to the second pole of the D-point location, causing the phase margin of the feedback system to become smaller, affecting stability and increasing jitter in the amplitude and phase of the eye diagram. Therefore, the feedback voltage Vagc of the automatic gain control is used for controlling and increasing the capacitance of the dominant pole of the input A point position of the pre-transimpedance amplifier, and the problem of stability can be effectively solved after the transimpedance is reduced. The automatic gain controller is NM6 in the access part of the pre-transimpedance amplifier.
The inverter unit further comprises a resistor R1, one end of the resistor R1 is lapped between the grid electrodes of the second PMOS tube and the second NMOS tube, and the other end of the resistor R1 is lapped between the drain electrodes of the second PMOS tube and the second NMOS tube.
The working principle is as follows: resistor R1 may help to substantially reduce the impedance at output point B of the PM1, NM1 inverter and reduce the impedance at output point C of the PM2, NM2 inverter, shifting the poles B, C to higher frequencies. This leaves the dominant poles in the loop at only a, D, thus allowing the loop to be close to a two pole system. During design, only the point A is ensured to be a main pole with lower frequency all the time under all conditions, and meanwhile, the parasitic capacitance of a secondary pole of the position of the point D is reduced as much as possible, so that the difficulty of loop stability compensation can be greatly reduced.
The current processing unit comprises an inductor L1, a fifth NMOS tube and a sixth NMOS tube;
the input end of the inductor L1 is connected with a current signal Iin sent by the photodiode, and the output end of the inductor L1 is connected with the input end of the first inverter;
the fifth NMOS tube is grounded and then lapped at the output end of the inductor L1, and the sixth NMOS tube is grounded and then lapped at the input end of the first inverter.
The input part of the signal transmission link of the pre-transimpedance amplifier is a series inductor L1, and after the series inductor is added, the parasitic capacitance of the photodiode and the input parasitic capacitance of the pre-transimpedance amplifier can be isolated to a certain degree, and partial bandwidth can be improved in advance through resonance with the two capacitors.
The feedback voltage Vagc of the automatic gain control is used for controlling and increasing the capacitance of the dominant pole of the input A point position of the pre-transimpedance amplifier, so that the problem of stability can be effectively solved after the transimpedance is reduced. The automatic gain controller is NM6 in the access part of the pre-transimpedance amplifier. When NM6 is turned on, a parallel compensation capacitor C4 is introduced to the main pole of the a position to ensure that the position of the main pole is unchanged. In addition, the series resistor R5 of the C4 can finely adjust the phase of the point A, so that the large change of group delay at a high frequency position is avoided when the transimpedance is reduced, and the quality is ensured.
In order to ensure that the working point of the pre-transimpedance amplifier is still normal when the intensity of the input optical signal is increased and avoid signal distortion caused by the change of the working point, a direct current offset canceller is generally required to be adopted to remove a direct current component of the input signal. The gate voltage Vdcoc of the input NM5 transistor is the feedback voltage of the dc offset canceller. When the direct current component of the current signal flowing into the pre-transimpedance amplifier is increased, the voltage of the Vdcoc is increased along with the adjustment of the loop, all input direct current is enabled to be completely bypassed through the NM5, the working point voltage of the pre-transimpedance amplifier cannot be influenced, and therefore distortion of the input and output signals caused by the change of the working point is avoided.
Other parts of this embodiment are the same as any of embodiment 6 described above, and therefore are not described again.
Example 8:
the embodiment also provides a method for packaging the transimpedance amplifier chip with the WiFi interference signal capability, based on the transimpedance amplifier chip with the WiFi interference signal capability of embodiment 7, as shown in fig. 1 and 2, when the transimpedance amplifier package chip is subjected to package layout, the layout is performed on the inverter unit in a mirror symmetry manner.
The working principle is as follows: the design of the selected ultra-frequency high-speed trans-impedance amplifier is shown in fig. 1, and the specific circuit analysis shows the embodiment. Unlike conventional high speed transimpedance amplifiers, the output C/D of this design is very close to a fully differential output (the amplitude of the output of C is relatively small); the output of the conventional design is a signal only at one end and a static voltage at the other end. Therefore, the selected high-speed trans-impedance amplifier has stronger capacity of resisting common-mode interference, and Wi-Fi signals are presented as common-mode signals after entering the amplifier, so that the selected circuit structure also has certain capacity of resisting the Wi-Fi interference. In order to better improve the common mode rejection capability, an improvement is also made on the layout, as shown in fig. 2. In the improved layout, the three cascaded inverters on the high-speed main path are in mirror symmetry with the red horizontal axis. Since the PMOS and the NMOS of the inverter are asymmetrical in layout, in the layout, the NMOS needs to be mirror-symmetrical, and then the PMOS is split into two identical parts which are respectively arranged on the NMOS and are symmetrical up and down. The resistor between B and C is split into two resistors with twice resistance value and is also respectively symmetrical with the red horizontal axis. The outputs C and D are also symmetrical about the horizontal axis. Therefore, the high-speed main path of the trans-impedance amplifier can be completely symmetrical on the layout. The horizontal axis of symmetry should also be the central horizontal axis of the whole chip, so that the transimpedance amplifier is also symmetrical about the horizontal axis of the chip.
The rest of this embodiment is the same as embodiment 7, and thus, the description thereof is omitted.
Example 9:
the embodiment further provides a method for packaging a transimpedance amplifier chip with a WiFi interference signal capability, and based on the transimpedance amplifier chip with the WiFi interference signal capability of embodiment 7, as shown in fig. 3 and 4, a layout of the amplifier chip is improved, and the specific improvement is as follows: the amplifier chip is provided with a magnetic field shielding layer to be connected with the chip ground end of the transimpedance amplifier, and an induced current generated by a variable magnetic field in the amplifier chip is guided to a ground port outside the amplifier chip through the magnetic field shielding layer. Via in fig. 4 denotes a connected via or solder joint.
Furthermore, bonding pads are uniformly arranged on the ground end of the amplifier chip in each direction, and the magnetic field shielding layer is connected with the bonding pads of the amplifier chip to shield the WiFi interference signals of the amplifier chip in all directions.
Furthermore, a plurality of metal laminated layers communicated with the amplifier chip substrate are arranged between the bonding pad of the grounding end of the amplifier chip and the electromagnetic shielding layer.
Further, the magnetic field shielding layer is provided in a hollowed-out form.
The working principle is as follows: as described in examples 7 and 8; unlike a conventional voltage amplifier, where the input is a voltage signal, the input to the transimpedance amplifier is a current signal. Although the post-stage amplifiers of the transimpedance amplifier are all voltage amplification, the post-stage amplifiers are not sensitive to voltage interference because the gain of the transimpedance amplifier is large and the amplitude of the voltage output by the transimpedance amplifier is large. From the above analysis, it can be seen that the receiving end system is more sensitive to current interference. Due to the high bandwidth requirement of the transimpedance amplifier, the input impedance of the transimpedance amplifier is also low, so that a current interference signal can flow into the node more easily, and the sensitivity is affected as a part of noise. Different from the interference voltage, the interference current is generated by a changing magnetic field, so in order to prevent the current induced by the changing magnetic field generated by the Wi-Fi signal from influencing the sensitivity, the magnetic field shielding capability of the receiving-end chip needs to be improved. Based on the above analysis, we improve the layout shown in fig. 2 to improve the magnetic field shielding capability of the chip. The specific improvements are shown in fig. 3 and 4:
as can be seen from fig. 3 and 4, the improved layout is a magnetic field shielding layer made of a metal aluminum layer AP with extremely low resistance above the conventional receiving-end chip layout. Unlike the electric field shielding layer, the magnetic field shielding layer needs to provide a low resistance path to guide the induced current generated by the changing magnetic field to the ground outside the chip, so the magnetic field shielding layer is connected to the pads connected to the chip ground, and the more pads are connected, the lower the impedance of the low resistance path along which the induced current flows, and the stronger the ability of shielding the magnetic field. The shielding layer designed by the method is connected with 12 grounded bonding pads, and the bonding pads guarantee that the whole chip can shield Wi-Fi signals from all directions. However, in our design, the shielding layer on the high-speed circuit of the transimpedance amplifier which determines the bandwidth is hollowed out, so that the bandwidth of the circuit is not reduced due to the introduction of the shielding layer. Meanwhile, the shielding layer is not arranged near the inductor in the circuit, so that the inductance value of the circuit is not influenced.
As can also be seen in fig. 4, our design also superimposes a continuous metal stack on the grounded pad from the AP layer all the way to the substrate, thus allowing the grounded pad to be connected directly to the substrate through a very low resistance. Because the power supply pad is not designed, parasitic capacitance exists between the power supply pad and the substrate, and the equivalent capacitance of the power supply and the substrate reaches about 6pF by adding a dummy capacitor of the power supply to the substrate on the chip. Therefore, after the above process, the equivalent capacitance of 6pF is equivalent to the capacitance between the power supply and the ground, so that the coupling capacitance between the power supply and the ground can be increased without increasing the area.
On the circuit design level, the patent also makes an improvement on the traditional design. In the traditional receiving end chip design, the power supply to the negative end of the APD has no relation with the chip. Therefore, if the power supply of the APD is required to be filtered to reduce the influence of power supply interference outside the package on the APD, the resistance and the capacitance used for filtering are required to be replaced by discrete devices, so that the production cost is greatly improved, and the resistance and the capacitance of the discrete devices are not accurate and have poor high-frequency characteristics. Therefore, in the improved circuit design, a 400 ohm poly resistor (R) is integrated on the chipon-chip) And 20 picofarads of high voltage capacitance (C)on-chip) And a first-order RC low-pass filter is formed between the two, so that power supply for the APD from the outside is firstly connected to a bonding pad of a chip, then passes through the low-pass filter in the chip, and finally comes out from the bonding pad of the chip and is connected to the negative end of the APD. This can be achieved without adding any discrete deviceFirst order filtering of the power supply supplying the APD is achieved.
The rest of this embodiment is the same as embodiments 7 and 8, and thus the description thereof is omitted.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and all simple modifications and equivalent variations of the above embodiments according to the technical spirit of the present invention are included in the scope of the present invention.

Claims (14)

1. A trans-impedance amplifier chip with WiFi interference signal capability is characterized in that an amplifier chip and a photoelectric conversion module are packaged in the trans-impedance amplifier packaging chip; the anti-interference amplifier is characterized in that three equivalent anti-interference modules are arranged on a trans-impedance amplifier packaging chip, and the anti-interference amplifier is specifically characterized in that:
firstly, a signal processing module and a first equivalent anti-interference module are arranged in an amplifier chip in a trans-impedance amplifier packaging chip, and the input end of the first equivalent anti-interference module receives a power supply V required by a photoelectric conversion moduleAPD_exThe output end of the photoelectric conversion module is connected with the input end of the photoelectric conversion module; the output end of the photoelectric conversion module is connected with the input end of a signal processing module in the amplifier chip;
secondly, arranging an equivalent circuit comprising a binding wire equivalent inductor outside the amplifier chip inside the trans-impedance amplifier packaging chip, and arranging a discrete capacitor on the equivalent circuit connecting the photoelectric conversion module and the amplifier chip;
setting five TO pins on a trans-impedance amplifier packaging chip TO form an S parameter equivalent model; five TO pins are respectively connected with a power supply V of the trans-impedance amplifier packaging chip for supplying power TO a power supplyDD_exTerminal of, power supply source V for supplying power to negative terminal of photoelectric conversion moduleAPD_exThe wiring terminal, two output ends of the trans-impedance amplifier packaging chip for outputting the AC coupling capacitor and the load resistor, and a ground end GND connected with the first equivalent anti-interference modulechipThe terminal of (2).
2. The method of claim 1, wherein the WiFi interference is providedA transimpedance amplifier chip for signal capability, wherein said first equivalent antijam module comprises an antijam resistor Ron-chipAnd an anti-interference capacitor Con-chip；
The anti-interference resistor Ron-chipV of the input terminal of the amplifier chipAPD-chipPin connection power supply source VAPD_ex(ii) a Anti-interference resistor Ron-chipOutput terminal of the amplifier chip through a PINKchipThe pin is connected with the input end of the photoelectric conversion module;
the anti-interference capacitor Con-chipOne end of the ground terminal GND is connected with the amplifier chipchipAnd the other end is lapped on the PINK of the amplifier chipchipPin and anti-interference resistor Ron-chipBetween the output terminals of (a).
3. The transimpedance amplifier chip according to claim 2, wherein the equivalent circuit disposed outside the amplifier chip inside the transimpedance amplifier package chip comprises a bond wire equivalent inductor LBW1Equivalent inductance L of binding wireBW2Equivalent inductance L of binding wireBW3Equivalent inductance L of binding wireBW4Equivalent inductance L of binding wireBW5Equivalent inductance L of binding wireBW6Equivalent inductance L of binding wireBW7Equivalent inductance L of binding wireBW8Equivalent inductance L of binding wireBW9Equivalent inductance L of binding wireBW10TO ground terminal GNDTODiscrete capacitor C1Discrete capacitor C2Discrete capacitor C3；
The binding wire equivalent inductance LBW1Is supplied to a power supply VDD_exThe input end is connected with a binding wire equivalent inductor LBW2Equivalent inductance L through binding wireBW2V with amplifier chipAPD-chipConnecting pins; the discrete capacitor C1One end is connected with the TO ground end GNDTOAnd the other end is lapped on the binding wire equivalent inductor LBW1Equivalent inductance L of binding wireBW2To (c) to (d);
the binding wire equivalent inductance LBW6Input end power supply source VDD_exInput end is connected toEquivalent inductance L of binding wireBW7Equivalent inductance L through binding wireBW7V with amplifier chipDD-chipConnecting pins; the discrete capacitor C3One end is connected with the TO ground end GNDTOAnd the other end is lapped on the binding wire equivalent inductor LBW6Equivalent inductance L of binding wireBW7To (c) to (d);
the binding wire equivalent inductance LBW9Equivalent inductance L of binding wireBW10The two output ends of the amplifier chip are respectively connected;
the binding wire equivalent inductance LBW4PINK with one end connected with amplifier chipchipThe other end of the pin is connected with the input end of the photoelectric conversion module;
the binding wire equivalent inductance LBW5PINA with one end connected with amplifier chipchipPins and through PINAchipThe pin is connected with the signal processing module, and the other end of the pin is connected with the output end of the photoelectric conversion module;
the binding wire equivalent inductance LBW3One end of the second connecting line is lapped on the input end of the photoelectric conversion module and the binding wire equivalent inductor LBW4Between the output ends of the two capacitors, the other end is connected with a discrete capacitor C2Rear and TO ground GNDTOConnecting;
the binding wire equivalent inductance LBW8Lap joint at the ground end GND of the amplifier chipchipThe above.
4. The transimpedance amplifier chip according TO claim 3, wherein the five TO pins include a first TO pin, a second TO pin, a third TO pin, a fourth TO pin, and a first five TO pin; the specific setting is as follows: the first TO pin is connected with a power supply VAPD_exEquivalent inductance L of rear and binding wireBW1The input ends of the two-way valve are connected; the second TO pin is connected with a power supply VDD_exEquivalent inductance L of rear and binding wireBW6The input ends of the two-way valve are connected; equivalent inductance L of the third TO pin and the binding wire after being groundedBW8Connecting; the fourth TO pin and the fifth TO pin are respectively lapped on the binding wire equivalent inductor LBW9Equivalent inductance L of binding wireBW10On the output terminal of the switch.
5. The transimpedance amplifier chip according to claim 4, further comprising a first load capacitor Cload1A second load capacitor Cload2A first load resistor Rload1A second load resistor Rload2；
The first load capacitor Cload1A first load resistor Rload1The second TO pin is connected with the third TO pin after being grounded in series; the second load capacitor Cload2A second load resistor Rload2And the series connection is grounded and then connected with the fourth TO pin.
6. A trans-impedance amplifier chip with WiFi interference signal capability is characterized in that an amplifier chip and a photoelectric conversion module are packaged in a trans-impedance amplifier packaging chip; the anti-interference device is characterized in that three equivalent anti-interference modules are arranged on a trans-impedance amplifier packaging chip, and the anti-interference device specifically comprises:
firstly, a signal processing module and a first equivalent anti-interference module are arranged in an amplifier chip in a trans-impedance amplifier packaging chip, and the input end of the first equivalent anti-interference module receives a power supply V required by a photoelectric conversion moduleAPD_exThe output end of the photoelectric conversion module is connected with the input end of the photoelectric conversion module; the output end of the photoelectric conversion module is connected with the input end of a signal processing module in the amplifier chip;
secondly, arranging an equivalent circuit outside the amplifier chip inside the trans-impedance amplifier packaging chip, and arranging a discrete capacitor on the equivalent circuit connecting the photoelectric conversion module and the amplifier chip;
setting five TO pins on a trans-impedance amplifier packaging chip TO form an S parameter equivalent model; five TO pins are respectively connected with a power supply V of the trans-impedance amplifier packaging chip for supplying power TO a power supplyDD_exTerminal of, power supply source V for supplying power to negative terminal of photoelectric conversion moduleAPD_exThe wiring terminal, two output ends of the trans-impedance amplifier packaging chip for outputting the AC coupling capacitor and the load resistor, and a ground end GND connected with the first equivalent anti-interference modulechipThe terminal of (1);
the signal processing module comprises a voltage stabilizing module, a preamplifier module and a post-stage circuit module;
the input end of the voltage stabilizing module is connected with a power supply on the amplifier chip, and the output end of the voltage stabilizing module is connected with the preamplifier module and the post-stage circuit module;
the input end of the preamplifier module is connected with a PINA end pin of the amplifier chip; the output end is connected with the input end of the rear-stage circuit module;
the output end of the post-stage circuit module and the OUT of the amplifier chipNEnd connection;
the PINA end and the PINK end of the amplifier chip are connected with a photoelectric conversion module;
v of the amplifier chipAPD_ChipThe end is connected with a first filtering unit; v of the amplifier chipDD_ChipThe end is connected with a second filtering unit; the grounding end of the amplifier chip is connected with a third filtering unit; OUT of the amplifier chipNThe end is connected with a load unit.
7. The transimpedance amplifier chip according to claim 6, wherein the preamplifier module comprises a preamplifier unit, a feedback resistance unit;
the preamplifier unit comprises a current processing unit, an inverter unit and a current mirror unit;
the input end of the current processing unit is connected with a PINA end pin of the amplifier chip, and the output end of the current processing unit is connected with the inverter unit;
the current mirror unit is connected with the inverter unit;
the feedback resistance unit is lapped on the input end and the output end of the phase inverter unit;
and the output end of the reverser unit is connected with the rear-stage circuit module.
8. The transimpedance amplifier chip according to claim 7, wherein the inverter unit comprises three sets of inverters, each of the three sets of inverters being a first inverter, a second inverter, and a third inverter;
the input end of the first phase inverter is connected with the output end of the current processing unit, and the output end of the first phase inverter is connected with the input end of the second phase inverter;
the input end of the third inverter is connected with the output end of the second inverter, and the output end of the third inverter is connected with the rear-stage circuit module;
the three groups of inverters are sequentially connected in a link manner, the input end of the first inverter is a pole A, the output end of the first inverter and the input end of the second inverter are a pole B, the output end of the second inverter and the input end of the third inverter are a pole C, and the output end of the third inverter is a pole D; the pole C and the pole D are output ends of the pre-transimpedance amplifier connected with the post-stage circuit module;
the feedback resistance unit is a resistor R1The resistance R1The pole B and the output end of the second inverter are lapped;
and the pole A is a connecting end of the inverter unit and the current processing unit.
9. A packaging method of a transimpedance amplifier chip with WiFi interference signal capability is based on the transimpedance amplifier chip with WiFi interference signal capability of any one of claims 1-5, and is characterized in that the packaging processing of anti-WiFi interference is carried out based on the following steps:
operation 1: integrating a first equivalent anti-interference module inside the amplifier chip to receive the power supply V required by the photoelectric conversion moduleAPD_exCarrying out anti-interference treatment and then outputting the anti-interference treatment to a photoelectric conversion module;
operation 2: arranging an equivalent circuit comprising a binding wire equivalent inductor outside the amplifier chip inside the trans-impedance amplifier packaging chip, arranging a discrete capacitor on the equivalent circuit connecting the photoelectric conversion module and the amplifier chip, and improving the WiFi interference resistance of the amplifier chip by combining the discrete capacitor with the equivalent circuit through the equivalent circuit;
operation 3: adding five TO pins, and connecting the TO pins with the amplifier chip by using binding wire equivalent inductors; a more stable path is provided to filter out WiFi interference signals than the ground of the amplifier chip.
10. A packaging method of a transimpedance amplifier chip with WiFi interference signal capability is based on the transimpedance amplifier chip with WiFi interference signal capability of claim 7 or 8, and is characterized in that layout is performed on an inverter unit in a mirror symmetry mode when the transimpedance amplifier packaging chip is subjected to packaging layout.
11. A packaging method of a transimpedance amplifier chip with WiFi interference signal capability is based on the transimpedance amplifier chip with WiFi interference signal capability of any one of claims 1-8, and is characterized in that the layout of the amplifier chip is improved, and the specific improvement is as follows: the amplifier chip is provided with a magnetic field shielding layer to be connected with the chip ground end of the transimpedance amplifier, and an induced current generated by a variable magnetic field in the amplifier chip is guided to a ground port outside the amplifier chip through the magnetic field shielding layer.
12. The method for packaging a transimpedance amplifier chip with WiFi interference signal capability according to claim 11, wherein pads are uniformly disposed on ground terminals of the amplifier chip in all directions, and the magnetic field shielding layer is connected to the pads of the amplifier chip to shield the amplifier chip from WiFi interference signals in all directions.
13. The method for packaging the transimpedance amplifier chip with the WiFi interference signal capability according to claim 11 or 12, wherein a plurality of metal stacks in communication with the amplifier chip substrate are disposed between the pad of the amplifier chip ground and the electromagnetic shielding layer.
14. The method for packaging the transimpedance amplifier chip with WiFi interference signal capability according to claim 11 or 12, wherein the magnetic field shielding layer is provided in a hollowed-out form.
CN202210125116.2A 2022-02-10 2022-02-10 Trans-impedance amplifier chip with WiFi interference signal capability and packaging method thereof Active CN114551426B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210125116.2A CN114551426B (en) 2022-02-10 2022-02-10 Trans-impedance amplifier chip with WiFi interference signal capability and packaging method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210125116.2A CN114551426B (en) 2022-02-10 2022-02-10 Trans-impedance amplifier chip with WiFi interference signal capability and packaging method thereof

Publications (2)

Publication Number Publication Date
CN114551426A true CN114551426A (en) 2022-05-27
CN114551426B CN114551426B (en) 2022-11-04

Family

ID=81672786

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210125116.2A Active CN114551426B (en) 2022-02-10 2022-02-10 Trans-impedance amplifier chip with WiFi interference signal capability and packaging method thereof

Country Status (1)

Country Link
CN (1) CN114551426B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115811283A (en) * 2022-11-25 2023-03-17 厦门优迅高速芯片有限公司 Anti-wifi signal interference circuit of trans-impedance amplifier
CN115844390A (en) * 2022-12-24 2023-03-28 北京津发科技股份有限公司 Near-infrared light acquisition circuit, method, system and device

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050047801A1 (en) * 2003-08-27 2005-03-03 Karl Schrodinger Optical receiver circuit
US20060034621A1 (en) * 2004-08-12 2006-02-16 Finisar Corporation Transimpedance amplifier with integrated filtering and reduced parasitic capacitance
CN201533301U (en) * 2009-12-01 2010-07-21 苏州优达光电子有限公司 Photosensitive receiving circuit for optoelectronic coupler
US20140126622A1 (en) * 2012-11-06 2014-05-08 Fujitsu Limited Transimpedance Amplifier with Equalization
CN203596347U (en) * 2013-11-07 2014-05-14 武汉电信器件有限公司 High-speed coaxial photoelectric detection component
US20170026011A1 (en) * 2015-07-20 2017-01-26 Mindspeed Technologies, Inc. Transimpedance Amplifier with Bandwidth Extender
CN206004626U (en) * 2016-06-30 2017-03-08 惠州市德赛西威汽车电子股份有限公司 A kind of anti-interference differential amplifier circuit for vehicle-mounted analog video
CN106656061A (en) * 2016-12-30 2017-05-10 光梓信息科技（上海）有限公司 Transimpedance amplifier
CN206585531U (en) * 2017-03-15 2017-10-24 北京中科远恒科技有限公司 Isolated form amplifying circuit
CN108923754A (en) * 2018-04-08 2018-11-30 安徽师范大学 A kind of photo detector signal amplifying device
WO2018228772A1 (en) * 2017-06-13 2018-12-20 Firecomms Limited A low-noise transimpedance amplifier incorporating a regulator
CN110212875A (en) * 2019-05-20 2019-09-06 西安交通大学 A kind of linear trans-impedance amplifier and its design method and application
CN111404494A (en) * 2020-06-04 2020-07-10 微龛(广州)半导体有限公司 Transimpedance amplifier chip and optical receiving module
CN112118052A (en) * 2019-06-21 2020-12-22 华为技术有限公司 Optical receiving module, optical transmitting and receiving module, optical module and optical network equipment
CN212435708U (en) * 2020-08-13 2021-01-29 芯河半导体科技(无锡)有限公司 XPON BOSA packaging structure
CN113572434A (en) * 2021-09-24 2021-10-29 微龛(广州)半导体有限公司 Transimpedance amplifier and optical receiving module

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050047801A1 (en) * 2003-08-27 2005-03-03 Karl Schrodinger Optical receiver circuit
US20060034621A1 (en) * 2004-08-12 2006-02-16 Finisar Corporation Transimpedance amplifier with integrated filtering and reduced parasitic capacitance
CN201533301U (en) * 2009-12-01 2010-07-21 苏州优达光电子有限公司 Photosensitive receiving circuit for optoelectronic coupler
US20140126622A1 (en) * 2012-11-06 2014-05-08 Fujitsu Limited Transimpedance Amplifier with Equalization
CN203596347U (en) * 2013-11-07 2014-05-14 武汉电信器件有限公司 High-speed coaxial photoelectric detection component
US20170026011A1 (en) * 2015-07-20 2017-01-26 Mindspeed Technologies, Inc. Transimpedance Amplifier with Bandwidth Extender
CN206004626U (en) * 2016-06-30 2017-03-08 惠州市德赛西威汽车电子股份有限公司 A kind of anti-interference differential amplifier circuit for vehicle-mounted analog video
CN106656061A (en) * 2016-12-30 2017-05-10 光梓信息科技（上海）有限公司 Transimpedance amplifier
CN206585531U (en) * 2017-03-15 2017-10-24 北京中科远恒科技有限公司 Isolated form amplifying circuit
WO2018228772A1 (en) * 2017-06-13 2018-12-20 Firecomms Limited A low-noise transimpedance amplifier incorporating a regulator
CN108923754A (en) * 2018-04-08 2018-11-30 安徽师范大学 A kind of photo detector signal amplifying device
CN110212875A (en) * 2019-05-20 2019-09-06 西安交通大学 A kind of linear trans-impedance amplifier and its design method and application
CN112118052A (en) * 2019-06-21 2020-12-22 华为技术有限公司 Optical receiving module, optical transmitting and receiving module, optical module and optical network equipment
CN111404494A (en) * 2020-06-04 2020-07-10 微龛(广州)半导体有限公司 Transimpedance amplifier chip and optical receiving module
CN212435708U (en) * 2020-08-13 2021-01-29 芯河半导体科技(无锡)有限公司 XPON BOSA packaging structure
CN113572434A (en) * 2021-09-24 2021-10-29 微龛(广州)半导体有限公司 Transimpedance amplifier and optical receiving module

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115811283A (en) * 2022-11-25 2023-03-17 厦门优迅高速芯片有限公司 Anti-wifi signal interference circuit of trans-impedance amplifier
CN115844390A (en) * 2022-12-24 2023-03-28 北京津发科技股份有限公司 Near-infrared light acquisition circuit, method, system and device
CN115844390B (en) * 2022-12-24 2023-09-29 北京津发科技股份有限公司 Near infrared light acquisition circuit, method, system and device

Also Published As

Publication number Publication date
CN114551426B (en) 2022-11-04

Similar Documents

Publication Publication Date Title
CN114551426B (en) Trans-impedance amplifier chip with WiFi interference signal capability and packaging method thereof
US20180351519A1 (en) Transimpedance amplifier with bandwidth extender
Wu et al. A 1V 4.2 mW fully integrated 2.5 Gb/s CMOS limiting amplifier using folded active inductors
Kucharski et al. 10Gb/s 15mW optical receiver with integrated Germanium photodetector and hybrid inductor peaking in 0.13 µm SOI CMOS technology
Chen et al. Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-/spl mu/m digital CMOS technology
WO2006020612A1 (en) Transimpedance amplifier with integrated filtering and reduced parasitic capacitance
Pan et al. An 18-Gb/s fully integrated optical receiver with adaptive cascaded equalizer
JP6425271B2 (en) Optical receiver circuit
CN114039562B (en) Low-cost over-frequency high-speed trans-impedance amplifier
US8993952B2 (en) Transimpedance amplifier, semiconductor device, and optical module to include an adding circuit for adding first and second current variation
CN110098814A (en) A kind of automatic gain method and circuit of trans-impedance amplifier
CN114050793B (en) Amplification method adopting low-cost over-frequency high-speed transimpedance amplifier
CN110535534A (en) Optical receiver front end and the method for receiving optical signal
CN109039473A (en) The front-end circuit and its low noise acoustic processing method of high-speed light receiver
Choi Ultra-low-power SiGe Driver-IC for High-speed electro-absorption modulated DFB Lasers
CN108599866A (en) A kind of transmission rate 25Gbps high-speed light receivers
KR100848360B1 (en) Transimpedance Amplifier With Integrated Filtering And Reduced Parasitic Capacitance
Park et al. A 10-Gb/s optical receiver front-end with 5-mW transimpedance amplifier
CA2480603A1 (en) Improved power supply rejection for high bandwidth transimpedance amplifier circuits (tias)
CN209692778U (en) A kind of infrared receiver module group controlling circuit and infrared receiver mould group
US7502565B2 (en) Circuit for filtering a laser signal
Chen et al. A single-chip 2.5-Gb/s CMOS burst-mode optical receiver
Luo et al. A 112-Gb/s Single-Ended PAM-4 Transceiver Front-End for Reach Extension in Long-Reach Link
Yan et al. CMOS transceiver circuits for energy efficient silicon photonic interconnects
Yan et al. A 25 Gb/s 3D Direct Bond Silicon Photonic Receiver in 12nm FinFET

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CP03 Change of name, title or address

Address after: Floor 9, block a, Xiewei center, No. 333 Dehua Road, hi tech Zone, Chengdu, Sichuan 610000

Patentee after: Chengdu Mingyi Electronic Technology Co.,Ltd.

Country or region after: China

Address before: Floor 9, block a, Xiewei center, No. 333 Dehua Road, hi tech Zone, Chengdu, Sichuan 610000

Patentee before: Chengdu Mingyi Electronic Technology Co.,Ltd.

Country or region before: China

CP03 Change of name, title or address