CN114551339A - Forming method of semiconductor structure, memory and electronic device - Google Patents

Forming method of semiconductor structure, memory and electronic device Download PDF

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Publication number
CN114551339A
CN114551339A CN202210042337.3A CN202210042337A CN114551339A CN 114551339 A CN114551339 A CN 114551339A CN 202210042337 A CN202210042337 A CN 202210042337A CN 114551339 A CN114551339 A CN 114551339A
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layer
insulating layer
sacrificial layer
sacrificial
conductive layer
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徐玲
张中
王迪
周文犀
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN202210042337.3A priority Critical patent/CN114551339A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
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  • Non-Volatile Memory (AREA)
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Abstract

The application discloses a forming method of a semiconductor structure, the semiconductor structure, a memory and an electronic device, wherein the method comprises the following steps: providing a substrate structure; the base structure comprises a substrate and a stacked structure positioned on the substrate; the stacked structure includes a plurality of steps, each step including a first insulating layer and a first sacrificial layer; forming a second insulating layer covering the top surface of the step and the side surface of the first sacrificial layer; a groove for exposing the surface of the first sacrificial layer part is formed on the second insulating layer; forming a second sacrificial layer covering the second insulating layer and exposing the side surface of the second insulating layer, wherein the second sacrificial layer on the step of each level is in contact with the first sacrificial layer through the groove; and removing the first sacrificial layer and the second sacrificial layer of each step to form a cavity, and filling a conductive material in the cavity to form a double-layer contact structure in each step.

Description

Forming method of semiconductor structure, memory and electronic device
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for forming a semiconductor structure, a memory, and an electronic device.
Background
To overcome the limitations of the two-dimensional memory devices, memory devices having a three-dimensional (3D) structure have been developed to increase integration density by arranging memory cells three-dimensionally over a substrate. In a three-dimensional memory device of a 3DNAND flash memory, a memory array may include a core (core) region and a stepped portion. The core region comprises a memory array used for storing data, and the stepped portion is used for leading out a gate layer in the memory array. The gate layer is used as a word line of the memory array to perform programming, erasing, reading and the like.
However, as the number of layers of the 3D NAND increases, the difficulty of leading out the gate layer Through the step portion increases, and a Punch-Through (Punch Through) condition occurs in the step contact hole forming process, resulting in gate layer breakdown. In this case, after the step contact hole is filled with the conductive material for forming the step contact structure, a short between different gate layers, i.e., a word line bridge between different layers, may be caused, thereby causing a failure of the three-dimensional memory.
Disclosure of Invention
Embodiments of the present application are intended to provide a method of forming a semiconductor structure, a memory, and an electronic device.
The technical scheme of the application is realized as follows:
a first aspect of embodiments of the present application provides a method for forming a semiconductor structure, where the method includes:
providing a substrate structure; the base structure comprises a substrate and a stacked structure positioned on the substrate; the stacked structure includes a plurality of steps, each step including a first insulating layer and a first sacrificial layer;
forming a second insulating layer covering the top surface of the step and the side surface of the first sacrificial layer; a groove for exposing the surface of the first sacrificial layer part is formed on the second insulating layer;
forming a second sacrificial layer covering the second insulating layer and exposing the side surface of the second insulating layer, wherein the second sacrificial layer on the step of each level is in contact with the first sacrificial layer through the groove;
and removing the first sacrificial layer and the second sacrificial layer of each step to form a cavity, and filling a conductive material in the cavity to form a double-layer contact structure in each step.
Optionally, the cavities include a first cavity formed by removing the first sacrificial layer and a second cavity formed by removing the second sacrificial layer, and the dual-layer contact structure includes a first conductive layer formed in the first cavity and a second conductive layer formed in the second cavity.
Optionally, the dual layer contact structure further comprises a second insulating layer between the first conductive layer and the second conductive layer.
Optionally, the method further comprises:
etching to form a step contact hole communicated with the double-layer contact structure of each step;
and filling a conductive material in the step contact hole to form a step contact structure.
Optionally, the step contact structure is in contact with at least one conductive layer in the double-layer contact structure.
Optionally, the removing the first sacrificial layer and the second sacrificial layer of each level of the step to form a cavity includes:
forming a dielectric layer covering the stacked structure;
etching the dielectric layer and the stacked structure to form a grid line separation groove penetrating through the stacked structure;
and removing the first sacrificial layer and the second sacrificial layer of each step through the grid line separation groove to form a cavity.
Optionally, when the top surface of the step of each level is the first sacrificial layer, before forming the second insulating layer, the method further includes:
and etching the first insulating layer to form a concave seam which enables the first insulating layer to be concave in the first sacrificial layer.
Optionally, the forming a second insulating layer covering the step top surface and the first sacrificial layer side surface includes:
forming a second insulating layer covering the semiconductor structure;
and etching the second insulating layer along the side wall of the step to form a groove exposing the surface of the first sacrificial layer part on each step.
Optionally, when the top surface of the step at each level is the first insulating layer, the etching the second insulating layer along the sidewall of the step includes:
etching the second insulating layer and the first insulating layer along the side wall of the step, wherein the etching is stopped at the first sacrificial layer on each step; and reserving a second insulating layer on the side face of the first sacrificial layer on each step.
A second aspect of the embodiments of the present application provides a semiconductor structure, including:
a substrate and a stacked structure on the substrate; the stacked structure includes a plurality of steps, each step including an insulating layer, a first conductive layer, and a second conductive layer;
each step has a double-layer contact structure including the first conductive layer, the second conductive layer, and an insulating layer between the first conductive layer and the second conductive layer; the second conductive layer is in contact with the first conductive layer through a groove located on the insulating layer.
Optionally, the semiconductor structure further includes a dielectric layer covering the stacked structure and a gate line isolation structure penetrating through the dielectric layer and the stacked structure.
Optionally, the semiconductor structure further includes a step contact structure located in the dielectric layer and contacting the double-layer contact structure of each step.
Optionally, the step contact structure is in contact with at least one conductive layer in the double-layer contact structure.
Optionally, the first conductive layer and the second conductive layer constitute a gate layer in the stack structure.
Optionally, the method further comprises: a virtual channel structure extending through the multilevel step.
A third aspect of the embodiments of the present application provides a memory, including the semiconductor structure according to the second aspect.
A fourth aspect of the embodiments of the present application provides a memory system, including a controller and the memory of the third aspect; the controller is coupled to the memory and is used for controlling the memory to store data.
A fifth aspect of embodiments of the present application provides an electronic device, which includes the memory system described in the fourth aspect.
Optionally, the electronic device comprises at least one of: the mobile phone, the desktop computer, the tablet computer, the notebook computer, the server, the vehicle-mounted equipment, the wearable equipment and the mobile power supply.
The application discloses a forming method of a semiconductor structure, the semiconductor structure, a memory and an electronic device, wherein the forming method of the semiconductor structure comprises the following steps: providing a substrate structure; the base structure comprises a substrate and a stacked structure positioned on the substrate; the stacked structure includes a plurality of steps, each step including a first insulating layer and a first sacrificial layer; forming a second insulating layer covering the top surface of the step and the side surface of the first sacrificial layer; a groove for exposing the surface of the first sacrificial layer part is formed on the second insulating layer; forming a second sacrificial layer covering the second insulating layer and exposing the side surface of the second insulating layer, wherein the second sacrificial layer on the step of each level is in contact with the first sacrificial layer through the groove; and removing the first sacrificial layer and the second sacrificial layer of each step to form a cavity, and filling a conductive material in the cavity to form a double-layer contact structure in each step. This application is through forming double-deck contact structure at the step top, has reduced the degree of difficulty of drawing forth the gate layer through the step portion, only needs can realize drawing forth of gate layer through the one deck contact structure among the double-deck contact structure, consequently controls the sculpture degree of depth of drawing forth the in-process more easily, has avoided the condition of gate layer breakdown to a great extent, has improved the product yield.
Drawings
Fig. 1 is a schematic structural diagram of a common step provided in this embodiment of the present application after etching;
FIG. 2 is a schematic flow chart illustrating a method of forming a semiconductor structure according to the present disclosure;
fig. 3a to 3i are a first flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the present disclosure;
fig. 4a to 4h are flowcharts illustrating an embodiment of a method for forming a semiconductor structure according to the present application, and fig. 5a to 5c are schematic connection diagrams illustrating a step contact structure according to the present application;
fig. 6 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present disclosure;
FIG. 7a is a first block diagram illustrating a memory system according to an embodiment of the present disclosure;
fig. 7b is a structural schematic diagram of a memory system according to an embodiment of the present application.
Detailed Description
Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
The flow charts shown in the drawings are merely illustrative and do not necessarily include all of the steps. For example, some steps may be decomposed, and some steps may be combined or partially combined, so that the actual execution sequence may be changed according to the actual situation.
It will be appreciated that spatial relationship terms, such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Currently, for etching a step, as shown in fig. 1, fig. 1 is a schematic structural diagram of a common step provided in this embodiment of the present application after etching. Currently, for the extraction of a gate layer in a semiconductor structure, the step region 101 needs to be etched to form a step contact hole, so as to form a step contact structure based on the step contact hole. However, in the structure based on the common step region 101, since the etching depth is difficult to control, an etching through condition is easily generated, and the etching depth is too large instantly, so that the gate layer is broken down, the isolation region 102 is formed, and after the step contact hole is filled with a conductive material for forming the step contact structure, short circuits between different gate layers, namely word line bridging between different layers, are caused, so that the failure of the three-dimensional memory is caused.
Based on this, the present application proposes the following embodiments.
Referring to fig. 2, fig. 2 is a schematic flow chart illustrating a method for forming a semiconductor structure according to the present application. The method comprises the following steps:
s201, providing a substrate structure; the base structure comprises a substrate and a stacked structure positioned on the substrate; the stacked structure includes a plurality of steps, each step including a first insulating layer and a first sacrificial layer;
s202, forming a second insulating layer covering the top surface of the step and the side surface of the first sacrificial layer; a groove for exposing the surface of the first sacrificial layer part is formed on the second insulating layer;
s203, forming a second sacrificial layer which covers the second insulating layer and exposes the side face of the second insulating layer, wherein the second sacrificial layer on each step is in contact with the first sacrificial layer through the groove;
s204, removing the first sacrificial layer and the second sacrificial layer of each step to form a cavity, and filling a conductive material in the cavity to form a double-layer contact structure in each step.
A substrate is understood in the semiconductor art as a base for forming transistors or other semiconductor devices thereon. In the embodiment of the present application, the substrate is a semiconductor substrate, and may be, for example, a Si substrate, a Ge substrate, a SiGe substrate, an SOi (Silicon On Insulator) or a GOI (Silicon On Insulator) or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as GaAs, TnP, SiC, or the like, may also be a stacked structure, such as Si/SiGe, or the like, and may also be another epitaxial structure, such as SGOI (silicon germanium on insulator) or the like.
In the embodiment, the stacked structure in the substrate structure includes a plurality of first insulating layers and a plurality of first sacrificial layers, and the first insulating layers and the first sacrificial layers are distributed at intervals. In practical applications, the number of stacked layers of the stacked structure may be determined according to the number of memory cells required to be formed in the vertical direction, and the number of stacked layers may be, for example, 8 layers, 32 layers, 64 layers, and the like. The stacked structure may be formed by alternately depositing the first insulating layer and the first sacrificial layer in sequence by chemical vapor deposition, atomic layer deposition, or other suitable deposition method. Here, the first insulating layer may be silicon oxide (SiOx), and the first sacrificial layer may be silicon nitride (SiNx).
The stack structure may be divided into a Core portion (Core) and a stepped portion (stable Step, SS) according to differences in position and function, wherein the Core portion is located at least one side of the stepped portion, and the Core portion is used for storage of data; the stepped portion is used for leading out a gate layer in the memory array.
In one embodiment, as shown in fig. 3a to 3i, fig. 3a to 3i are a first flowchart of an embodiment of a method for forming a semiconductor structure provided in the present application. The base structure includes a substrate 300 at the bottom and a stacked structure 310 above the substrate. Note that only a part of the core portion 302 and the step portion 301 is illustrated in fig. 3a to 3 i. In practical applications, both sides of the stacked structure 310 may be formed with step portions, and even the step portions may be formed around the core portion.
Fig. 3a to 3i illustrate an example in which the top surface of each step exposes the first sacrificial layer.
As shown in fig. 3a, the first insulating layer 3012 in each step is located below the first sacrificial layer 3011, the lengths of the first insulating layer 3012 and the first sacrificial layer 3011 in the same level in the direction parallel to the substrate are substantially equal, and the lengths of the first insulating layer 3012 and the first sacrificial layer 3011 in different levels in the direction parallel to the substrate increase in sequence in the direction approaching the substrate 300.
As shown in fig. 3b, the first insulating layer 3012 in each step is etched, so that the first insulating layer 3012 is recessed in the recessed slot 3013 of the first sacrificial layer 3011, that is, after the etching is finished, the length of the first insulating layer 3012 at the same level along the direction parallel to the substrate is smaller than the length of the first sacrificial layer 3011 along the direction parallel to the substrate. In some embodiments, the etching process for etching the first insulating layer in each step to form the concave gap may be a wet etching process, for example, a wet etching process is used to remove a part of the structure of the first insulating layer.
As shown in fig. 3c, a second insulating layer 3014 is formed to cover the surface and side surfaces of the first sacrificial layer 3011 based on the above-described etched stack structure. In this way, when the second insulating layer 3014 is formed, the contact surface between the first insulating layer 3012 and the second insulating layer 3014 is more complete. Here, the first insulating layer may be a non-metal oxide, such as silicon oxide.
As shown in fig. 3d, after the second insulating layer 3014 is formed, the second insulating layer 3014 is etched along the step sidewalls to form a recess 3015 exposing a portion of the surface of the first sacrificial layer 3011 at each step. The second insulating layer 3014 in the step of this level is disconnected from the second insulating layer 3014 of the next level at the groove 3015. Here, the etching operation leaves the side of the second insulating layer 3014 on each step, i.e., after the etching is finished, the side of the first sacrificial layer 3011 is still covered by the second insulating layer 3014. Here, the second insulating layer 3014 may be etched along the step sidewalls using a dry etching process to form a groove 3015 exposing a portion of the surface of the first sacrificial layer 3011 at each step.
As shown in fig. 3e, after the groove 3015 is formed, a second sacrificial layer 3016 is formed based on the groove 3015. The second sacrificial layer 3016 covers the surface and the side of the second insulating layer 3014 and fills the groove 3015, and the second sacrificial layer 3016 and the first sacrificial layer 3011 communicate. Here, the second sacrificial layer 3016 may be implemented by depositing silicon nitride.
In one example, the first sacrificial layer 3011 can be silicon nitride with a low hydrogen content and the second sacrificial layer 3016 can be silicon nitride with a high hydrogen content to account for the removal of the first and second sacrificial layers through the gate line isolation trenches located in the core portion of the semiconductor structure. The less the hydrogen bonds, the better the etching resistance of the silicon nitride, and in the process of removing the first sacrificial layer and the second sacrificial layer through the gate line separation groove, because the end part of the second sacrificial layer 3016 is farther from the gate line separation groove than the first sacrificial layer 3011, the material of the second sacrificial layer 3016 is adjusted to silicon nitride with higher hydrogen content, so that the etching speed of the second sacrificial layer can be improved, the removal of the second sacrificial layer is accelerated, and meanwhile, the problem of residue of the second sacrificial layer caused by the fact that the second sacrificial layer is more difficult to remove from the gate line separation groove can be solved.
After the deposition of the second sacrificial layer 3016 is completed, the stacked structure is etched to remove the second sacrificial layer 3016 on the side of the step portion, as shown in fig. 3 f. That is, only the surface of the second insulating layer 3014 on each step is covered with the second sacrificial layer 3016, and the side surface of the second insulating layer 3014 is exposed, whereby the connection between the sacrificial layers on the adjacent steps is broken.
In this embodiment, after the above steps, the stacked structure is stepped, each step includes two sacrificial layers and two insulating layers, and a second sacrificial layer 3016, a second insulating layer 3014, a first sacrificial layer 3011, and a first insulating layer 3012 are sequentially arranged from top to bottom, where the first sacrificial layer 3011 is communicated with the second sacrificial layer 3016, the first insulating layer 3012 is communicated with the second insulating layer 3014, the second insulating layer 3014 is separated between the first sacrificial layer 3011 and the second sacrificial layer 3016, and the first insulating layer 3012 is separated between the step and the next step. Of course, the number of the sacrificial layer and the insulating layer in each step may not be limited to two, but may also be three, four or more, which is not limited thereto.
As shown in fig. 3g, a dielectric layer 330 covering the stacked structure is formed, gate line isolation grooves 340 penetrating through the stacked structure are formed by etching the dielectric layer 330 and the stacked structure, and the first sacrificial layer 3011 and the second sacrificial layer 3016 of each step are removed based on the gate line isolation grooves 340 to form a cavity, where the cavity 320 includes a first cavity 321 formed by removing the first sacrificial layer 3011 and a second cavity 322 formed by removing the second sacrificial layer 3016, and the two cavities are through.
In one example, after forming the dielectric layer 330 covering the stacked structure, a dummy channel hole 370 penetrating the stacked structure is formed by etching the dielectric layer 330 and the stacked structure, and the dummy channel hole 370 is filled with an insulating material or a conductive material. The dielectric layer 330 is an insulating material layer, such as silicon oxide. The height of the dielectric layer 330 is greater than the height of the highest step of the step portion. It should be noted that the dummy channel hole and the channel hole of the core region may be formed in the same process, and the dummy channel hole and the channel hole of the core region may be formed in the same process or in different processes. It should be noted that, in the case of filling the dummy trench hole with the conductive material, an isolation layer needs to be formed in the dummy trench hole first, and then the conductive material needs to be filled, so as to avoid the electrical influence of the dummy trench hole on the semiconductor structure.
In one example, the dielectric layer 330 and the stacked structure are divided into a plurality of block regions by the gate line isolation grooves 340, so that the first sacrificial layer 3011 and the second sacrificial layer 3016 of each step have exposed end faces, and the first sacrificial layer 3011 and the second sacrificial layer 3016 of each step can be wet-etched by using an etching solution from the exposed end faces, so that the first sacrificial layer 3011 and the second sacrificial layer 3016 of each step are removed, and a cavity is formed at a corresponding position.
After the formation of the cavity, a conductive material is deposited using the cavity as a deposition channel, thereby obtaining a corresponding bi-layer contact structure, as shown in fig. 3 h. The cavities include a first cavity 321 formed by removing the first sacrificial layer and a second cavity 322 formed by removing the second sacrificial layer, the dual layer contact structure includes a first conductive layer 351 formed in the first cavity 321 and a second conductive layer 352 formed in the second cavity 322, and the first conductive layer 351 and the second conductive layer 352 are in communication. Here, the material of the first conductive layer 351 and the second conductive layer 352 includes tungsten W, and may further include polysilicon or a metal silicide material such as a silicide material of a metal selected from tungsten (W) and titanium (Ti). The materials of the first conductive layer 351 and the second conductive layer 352 may be the same or different. In this embodiment, the first conductive layer 351 and the second conductive layer 352 are made of the same material, and are preferably made of tungsten. Note that the first conductive layer 351 and the second conductive layer 352 together form a gate layer in a stacked structure.
The dual layer contact structure further includes a second insulating layer 3014 between the first conductive layer 351 and the second conductive layer 352. Here, the first conductive layer 351, the second insulating layer 3014, and the second conductive layer 352 constitute a sandwich structure.
After the semiconductor structure is formed, a step contact hole communicating with the double-layer contact structure of each step is formed by etching, and a conductive material is filled in the step contact hole to form a step contact structure 360, thereby leading out the gate layer in the stacked structure, as shown in fig. 3 i.
In the present embodiment, the step contact structure 360 is in contact with at least one conductive layer in the dual-layer contact structure. Specifically, the step contact structure 360 may be connected to only the second conductive layer 352, may extend to the second insulating layer 3014 through the second conductive layer 352, and may be connected to both the first conductive layer 351 and the second conductive layer 352.
In this embodiment, an insulating material may be filled in the gate line isolation groove 340 to form a gate line isolation structure 341.
This application is through forming double-deck contact structure at the step top, has reduced the degree of difficulty of drawing forth the gate layer through the step portion, only needs can realize drawing forth of gate layer through the one deck conducting layer in the double-deck contact structure, consequently controls the sculpture degree of depth of drawing forth the in-process more easily, has avoided the condition of gate layer breakdown to a great extent, has improved the product yield.
In some embodiments, as shown in fig. 4a to 4h, fig. 4a to 4h are a second flowchart of an embodiment of a method for forming a semiconductor structure provided in the present application. The base structure includes a substrate 400 at the bottom and a stack structure 410 above the substrate. It should be noted that only a part of the core portion 402 and the step portion 401 is illustrated in fig. 4a to 4 h. In practical applications, both sides of the stacked structure 410 may be formed with step portions, and even the step portions may be formed around the core portion.
Fig. 4a to 4h illustrate an example in which the first insulating layer is exposed on the top surface of each step.
As shown in fig. 4a, the first insulating layer 4012 in each step is located above the first sacrificial layer 4011, the first insulating layer 4012 and the first sacrificial layer 4011 in the same level have substantially equal lengths in a direction parallel to the substrate, and the first insulating layer 4012 and the first sacrificial layer 4011 in different levels have sequentially increasing lengths in a direction close to the substrate 400 in the direction parallel to the substrate.
As shown in fig. 4b, a second insulating layer 4013 covering the surface of the first insulating layer 4012 and the side surface of the first sacrificial layer 4011 is formed on the basis of the base structure. Here, the second insulating layer 4013 can be formed by dielectric deposition, where the materials of the first insulating layer 4012 and the second insulating layer 4013 can be the same or different, and for example, both can be a non-metal oxide such as silicon oxide. In this embodiment, the same material as that of the first insulating layer 4012 and that of the second insulating layer 4013 are used as an example. The first insulating layer 4012 of the step, the second insulating layer 4013 of the step, and the first insulating layer 4012 of the next step cover the first sacrificial layer 4011 of the step, so that the upper and lower surfaces of the first sacrificial layer 4011 and the side surface of the step portion are not exposed to the outside.
As shown in fig. 4c, after forming the second insulating layer 4013, the second insulating layer 4013 and the first insulating layer 4012 are etched along the step sidewalls to form a groove 4014 exposing a portion of the surface of the first sacrificial layer 4011 at each step. Here, the side surface of the second insulating layer 4013 on each step is remained during the etching, that is, after the etching is finished, the side surface of the first sacrificial layer 4011 is still covered with the second insulating layer 4013.
As shown in fig. 4d, a second sacrificial layer 4015 is formed covering the second insulating layer 4013, and the second sacrificial layer 4015 on each step is in contact with the first sacrificial layer 4011 through a groove 4014. Here, the second sacrificial layer 4015 may be implemented by depositing silicon nitride.
In one example, the first sacrificial layer 4011 may be a high-cost silicon nitride with a low hydrogen content, and the second sacrificial layer 4015 may be a low-cost silicon nitride with a high hydrogen content, considering material properties and cost. The less hydrogen bonds, the better the etching resistance of silicon nitride, and the less the requirement for the second sacrificial layer 4015 is in the process of forming a semiconductor structure, so that the cost can be reduced by adjusting the material of the second sacrificial layer 4015 to low-cost silicon nitride. Here, the high and low hydrogen content, and the low cost and high cost are relative concepts, that is, they are obtained by comparing the first sacrificial layer 4011 and the second sacrificial layer 4015.
As shown in fig. 4e, after the deposition of the second sacrificial layer 4015 is completed, an etching operation is performed to remove the second sacrificial layer 4015 on the side surface of the step. That is, only the surface of the second insulating layer 4013 on each step is covered with the second sacrificial layer 4015, and the side surface of the second insulating layer 4013 is exposed, whereby the connection between the second sacrificial layers 4015 on the adjacent steps is broken. In some embodiments, the second sacrificial layer 4015 may be subjected to an anisotropic treatment, so that the etching selectivity of the second sacrificial layer 4015 located on the side surface of the step and the etching selectivity of the second sacrificial layer 4015 located on the surface of the step are different, and therefore, the second sacrificial layer 4015 located on the side surface of the step may be etched and removed, so as to obtain the second sacrificial layer 4015 located on the step surface of the step structure. For example, the anisotropic treatment on the second sacrificial layer 4015 may be plasma treatment on the second sacrificial layer 4015, and the second sacrificial layer 4015 is bombarded by plasma in the longitudinal direction, so that the second sacrificial layer 4015 located on the surface of the step becomes denser, and thus a high selectivity ratio of the second sacrificial layer 4015 on the surface of the step and the second sacrificial layer 4015 on the side surface of the step under wet etching conditions can be achieved, and the second sacrificial layer 4015 located on the side surface of the step can be removed.
In this embodiment, after the above steps, the stacked structure is stepped, and each step is sequentially formed by the second sacrificial layer 4015, the second insulating layer 4013, the first sacrificial layer 4011, and the first insulating layer 4012 from top to bottom, where the first sacrificial layer 4011 is communicated with the second sacrificial layer 4015, the first insulating layer 4012 is communicated with the second insulating layer 4013, and the second insulating layer 4013 is separated between the first sacrificial layer 4011 and the second sacrificial layer 4015. Note that the second insulating layer 4013 in this embodiment completely or partially covers the original first insulating layer 4012 in this step, and the bottom first insulating layer 4012 is the first insulating layer 4012 in the next step sectioned through the groove 4014. Of course, the number of the sacrificial layer and the insulating layer in each step may not be limited to two, but may also be three, four or more, which is not limited thereto.
As shown in fig. 4f, a dielectric layer 430 covering the stacked structure is formed, a gate line isolation groove 440 penetrating through the stacked structure is formed by etching the dielectric layer 430 and the stacked structure, and the first sacrificial layer 4011 and the second sacrificial layer 4015 of each step are removed based on the gate line isolation groove 440 to form a cavity, where the cavity includes a first cavity 421 formed by removing the first sacrificial layer 4011 and a second cavity 422 formed by removing the second sacrificial layer 4015, and the first cavity and the second cavity of each step are through.
In one example, a dielectric layer 430 is formed overlying the stacked structure, and a dummy channel hole 470 is formed through the stacked structure by etching the dielectric layer 430 and the stacked structure, the dummy channel hole being filled with an insulating material or a conductive material. The dielectric layer 430 is an insulating material layer, such as silicon oxide. The height of the dielectric layer 430 is greater than the height of the highest step of the step portion.
In one example, the dielectric layer 430 and the stacked structure are divided into a plurality of block regions by the gate line separating grooves 440, so that the first sacrificial layer 4011 and the second sacrificial layer 4015 of each step have exposed end faces, and thus the first sacrificial layer 4011 and the second sacrificial layer 4015 of each step can be wet-etched by using an etching solution from the exposed end faces, so that the first sacrificial layer 4011 and the second sacrificial layer 4015 of each step are removed, and a cavity is formed at a corresponding position.
After the formation of the cavity, a conductive material is deposited using the cavity as a deposition channel, thereby obtaining a corresponding bi-layer contact structure, as shown in fig. 4 g. The double-layered contact structure includes a first conductive layer 451 formed in the first cavity 421 and a second conductive layer 452 formed in the second cavity 422, and the first conductive layer 451 and the second conductive layer 452 are in communication. Here, the material of the first conductive layer and the second conductive layer includes tungsten (W), and may further include polysilicon or a metal silicide material such as a silicide material of a metal selected from tungsten (W) and titanium (Ti). The materials of the first conductive layer and the second conductive layer may be the same or different. In this embodiment, the first conductive layer and the second conductive layer are made of the same material, and are preferably tungsten.
After the semiconductor structure is formed, a step contact hole communicating with the double-layer contact structure of each step is etched, and a conductive material is filled in the step contact hole to form a step contact structure 460, thereby leading out the gate layer in the stacked structure, as shown in fig. 4 h. Note that the first conductive layer 451 and the second conductive layer 452 constitute a gate layer in a stacked structure.
The dual layer contact structure further includes a second insulating layer 4013 between the first conductive layer 451 and the second conductive layer 452. Here, the first conductive layer 451, the second insulating layer 4013, and the second conductive layer 452 constitute a sandwich structure.
In the present embodiment, the step contact structure 460 is in contact with at least one conductive layer of the dual-layer contact structure. Specifically, the step contact structure 460 may be connected to only the second conductive layer 452, may extend to the second insulating layer 4013 through the second conductive layer 452, or may be connected to both the first conductive layer 451 and the second conductive layer 452.
In the present embodiment, an insulating material may be filled in the gate line isolation groove 440 to form the gate line isolation structure 441.
This application is through forming double-deck contact structure at the step top, has reduced the degree of difficulty of drawing forth the gate layer through the step portion, only needs can realize drawing forth of gate layer through the one deck conducting layer in the double-deck contact structure, consequently controls the sculpture degree of depth of drawing forth the in-process more easily, has avoided the condition of gate layer breakdown to a great extent, has improved the product yield.
In some embodiments, as shown in fig. 5a to 5c, fig. 5a to 5c are schematic connection diagrams of the step contact structure provided in the embodiments of the present application. After the semiconductor structure is formed, a step contact hole communicated with the double-layer contact structure of each step is formed through etching, a conductive material is filled in the step contact hole to form a step contact structure, and the step contact structure is contacted with at least one conductive layer in the double-layer contact structure, so that a grid layer in the stack structure is led out.
As shown in fig. 5a, the stepped contact structure 501 may be connected only with the second conductive layer 502 in the double-layer contact structure, whereby the stepped contact structure 501 leads out the gate layer in the stack structure through the second conductive layer 502.
As shown in fig. 5b, the step contact structure 501 may be connected to the second conductive layer 502 in the double-layer contact structure and to the second insulating layer 504 between the second conductive layer 502 and the first conductive layer 503. At this time, the step contact structure 501 leads out the gate layer in the stack structure through the second conductive layer 502.
As shown in fig. 5c, the step contact structure 501 may penetrate through the second conductive layer 502 and the second insulating layer 504 and be simultaneously connected to the first conductive layer 503 and the second conductive layer 502 in the dual-layer contact structure, and at this time, the step contact structure 501 leads out the gate layer in the stacked structure through the first conductive layer 503 and the second conductive layer 502.
In the three examples, the etching depth of the step contact structure is sequentially increased, namely, as long as the etching of the step contact hole is stopped within the thickness range of the double-layer contact structure, the normal lead-out of the gate layer in the stacked structure can be ensured, meanwhile, the over-etching condition can be avoided, and the etching difficulty is reduced.
This embodiment has reduced the degree of difficulty of drawing forth the gate layer through the stepped portion through setting up double-deck contact structure, only needs can realize drawing forth of gate layer through the one deck conducting layer among the double-deck contact structure, consequently controls the sculpture degree of depth of drawing forth the in-process more easily, has avoided the condition of gate layer breakdown to a great extent, has improved the product yield.
An embodiment of the present application further provides a semiconductor structure, as shown in fig. 6, where fig. 6 is a schematic structural diagram of the semiconductor structure provided in the embodiment of the present application, and the semiconductor structure includes:
a substrate 600 and a stacked structure 610 on the substrate; the stack structure 610 includes a plurality of steps, each of which includes an insulating layer 620, a first conductive layer 621, and a second conductive layer 622;
each step has a double-layer contact structure including a first conductive layer 621, a second conductive layer 622, and an insulating layer 620 between the first conductive layer 621 and the second conductive layer 622; the second conductive layer 622 is in contact with the first conductive layer 621 through a groove on the insulating layer 620.
In this embodiment, each step includes two conductive layers and two insulating layers, and the second conductive layer 622, the insulating layer 620, the first conductive layer 621 and the insulating layer 620 are sequentially disposed from top to bottom, wherein the first conductive layer 621 is connected to the second conductive layer 622, and the insulating layer 620 is disposed between the first conductive layer 621 and the second conductive layer 622. It should be noted that the number of the conductive layers and the insulating layers in each step may not be limited to two, but may also be three, four or more, which is not limited to this. The material of the first conductive layer and the second conductive layer includes tungsten (W), and may further include polysilicon or a metal silicide material such as a silicide material of a metal selected from tungsten (W) and titanium (Ti). The materials of the first conductive layer and the second conductive layer may be the same or different. In this embodiment, the first conductive layer and the second conductive layer are made of the same material, and are preferably tungsten. The material of the insulating layer may be a non-metal oxide such as silicon oxide.
In some embodiments, the semiconductor structure further includes a dielectric layer 630 covering the stacked structure 610, and a gate line isolation structure 640 penetrating the dielectric layer 630 and the stacked structure 610. The dielectric layer 403 is an insulating material layer, such as silicon oxide. The height of the dielectric layer 603 is greater than the height of the highest step of the stepped portion. Specific examples are described in the above method examples, and are not described in detail herein.
In some embodiments, the semiconductor structure further comprises a step contact structure 650 for extracting the gate layer, the step contact structure 650 being in contact with at least one conductive layer in the double-layer contact structure. Specifically, the step contact structure 650 may be connected to the second conductive layer 622 in the dual-layer contact structure only, or may be connected to the second conductive layer 622 in the dual-layer contact structure and connected to the insulating layer between the second conductive layer 622 and the first conductive layer 621, or may penetrate through the second conductive layer 622 and the insulating layer 620 between the first conductive layer 621 and the second conductive layer 622 and be connected to both the first conductive layer 621 and the second conductive layer 622 in the dual-layer contact structure, and at this time, the step contact structure leads out the gate layer in the stacked structure through the first conductive layer 621 and the second conductive layer 622. Note that the first conductive layer 621 and the second conductive layer 622 constitute a gate layer in a stacked structure.
This embodiment is through setting up double-deck contact structure, thereby control the etching depth of grid layer extraction in-process to the step more easily, make step contact structure can only be connected with the second conducting layer in the double-deck contact structure, also can pass the second conducting layer and extend to the second insulating layer, can also be connected with the first conducting layer and the second conducting layer in the double-deck contact structure simultaneously, the degree of difficulty of extracting the grid layer through the stepped portion has been reduced, control the etching depth of extraction in-process more easily, the condition that the grid layer punctures has been avoided to very big degree, the product yield has been improved.
In some embodiments, the first conductive layer and the second conductive layer constitute a gate layer in the stacked structure. The first conducting layer and the second conducting layer are arranged in an upper-lower double-layer mode in the direction perpendicular to the substrate, and the first conducting layer and the second conducting layer are in an electric connection state. The step contact structure may be in contact with any or all of the first and second conductive layers.
In some embodiments, further comprising: and a virtual channel structure penetrating through the multi-stage steps.
Here, the dummy trench structure may be filled with an insulating material as an isolation structure disposed between the double-layer contact structures of the adjacent steps.
Embodiments of the present application also provide a memory including a memory cell and the semiconductor device described above, wherein the semiconductor device is configured to control the memory cell to store data based on a command, an address, or a control signal received from the outside. Specific examples are described in the above semiconductor device examples, and are not described in detail herein.
The embodiment of the application also provides a memory system, which comprises a controller and the memory; the controller is coupled to the memory and is used for controlling the memory to store data.
In one example, as shown in FIG. 7a, a memory system 700 may include only one memory 701, and one corresponding controller 702.
In another example, as shown in FIG. 7b, a memory system 700 may include a plurality of memories 701, and a corresponding controller 702.
Of course, in other examples, the memory system may also include multiple memories and corresponding multiple controllers, which are not enumerated.
In some embodiments, the memory system may be implemented as a memory device such as a Universal Flash Storage (UFS) device, a multi-media card in the form of a Solid State Disk (SSD), MMC, eMMC, RS-MMC, and micro MMC, a secure digital card in the form of SD, mini SD, and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type memory device, a foreign component interconnect (PCI) type memory device, a PCI express (PCI-E) type memory device, a Compact Flash (CF) card, a smart media card, or a memory stick, and the like.
An embodiment of the present application further provides an electronic device including the memory system described above.
In one embodiment, an electronic device includes at least one of: the mobile phone, the desktop computer, the tablet computer, the notebook computer, the server, the vehicle-mounted equipment, the wearable equipment, the portable power source.
The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments.
Features disclosed in several of the product embodiments provided in the present application may be combined in any combination to yield new product embodiments without conflict.
The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.
In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the modules is only one logical functional division, and other division manners may be implemented in practice, such as: multiple modules or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or modules may be electrical, mechanical or other forms.
The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network modules; some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, all functional modules in the embodiments of the present application may be integrated into one processing module, or each module may be separately used as one module, or two or more modules may be integrated into one module; the integrated module can be realized in a hardware form, and can also be realized in a form of hardware and a software functional module.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (19)

1. A method of forming a semiconductor structure, the method comprising:
providing a substrate structure; the base structure comprises a substrate and a stacked structure positioned on the substrate; the stacked structure includes a plurality of steps, each step including a first insulating layer and a first sacrificial layer;
forming a second insulating layer covering the top surface of the step and the side surface of the first sacrificial layer; a groove for exposing the surface of the first sacrificial layer part is formed on the second insulating layer;
forming a second sacrificial layer covering the second insulating layer and exposing the side surface of the second insulating layer, wherein the second sacrificial layer on the step of each level is in contact with the first sacrificial layer through the groove;
and removing the first sacrificial layer and the second sacrificial layer of each step to form a cavity, and filling a conductive material in the cavity to form a double-layer contact structure in each step.
2. The method of claim 1, wherein the cavity comprises a first cavity formed by removing the first sacrificial layer and a second cavity formed by removing the second sacrificial layer, and wherein the bi-layer contact structure comprises a first conductive layer formed in the first cavity and a second conductive layer formed in the second cavity.
3. The method of claim 2, wherein the bi-layer contact structure further comprises a second insulating layer between the first conductive layer and the second conductive layer.
4. The method of claim 2, further comprising:
etching to form a step contact hole communicated with the double-layer contact structure of each step;
and filling a conductive material in the step contact hole to form a step contact structure.
5. The method of claim 4, wherein the step contact structure is in contact with at least one conductive layer in the bilayer contact structure.
6. The method of claim 1, wherein the removing the first sacrificial layer and the second sacrificial layer of the step of each level to form a cavity comprises:
forming a dielectric layer covering the stacked structure;
etching the dielectric layer and the stacked structure to form a grid line separation groove penetrating through the stacked structure;
and removing the first sacrificial layer and the second sacrificial layer of each step through the grid line separation groove to form a cavity.
7. The method of claim 1, wherein before forming the second insulating layer when the top surface of the step of each level is the first sacrificial layer, the method further comprises:
and etching the first insulating layer to form a concave seam which enables the first insulating layer to be concave in the first sacrificial layer.
8. The method of claim 1, wherein forming a second insulating layer covering the step top surface and the first sacrificial layer side surface comprises:
forming a second insulating layer covering the semiconductor structure;
and etching the second insulating layer along the side wall of the step to form a groove exposing the surface of the first sacrificial layer part on each step.
9. The method of claim 8, wherein etching the second insulating layer along the step sidewalls when the top surface of the step of each level is the first insulating layer comprises:
etching the second insulating layer and the first insulating layer along the side wall of the step, wherein the etching is stopped at the first sacrificial layer on each step; and reserving a second insulating layer on the side face of the first sacrificial layer on each step.
10. A semiconductor structure, comprising:
a substrate and a stacked structure on the substrate; the stacked structure includes a plurality of steps, each step including an insulating layer, a first conductive layer, and a second conductive layer;
each step has a double-layer contact structure including the first conductive layer, the second conductive layer, and an insulating layer between the first conductive layer and the second conductive layer; the second conductive layer is in contact with the first conductive layer through a groove located on the insulating layer.
11. The semiconductor structure of claim 10, further comprising a dielectric layer overlying the stacked structure and a gate line isolation structure extending through the dielectric layer and the stacked structure.
12. The semiconductor structure of claim 11, further comprising a step contact structure in the dielectric layer and contacting the bilayer contact structure of each level of the step.
13. The semiconductor structure of claim 12, wherein the step contact structure is in contact with at least one conductive layer in the bi-layer contact structure.
14. The semiconductor structure of claim 10,
the first conductive layer and the second conductive layer constitute a gate layer in the stack structure.
15. The semiconductor structure of claim 10, further comprising:
a virtual channel structure extending through the multilevel step.
16. A memory comprising the semiconductor structure of any one of claims 10-15.
17. A memory system comprising a controller and the memory of claim 16; the controller is coupled to the memory and is used for controlling the memory to store data.
18. An electronic device comprising the memory system of claim 17.
19. The electronic device of claim 18, wherein the electronic device comprises at least one of: the mobile phone, the desktop computer, the tablet computer, the notebook computer, the server, the vehicle-mounted equipment, the wearable equipment, the portable power source.
CN202210042337.3A 2022-01-14 2022-01-14 Forming method of semiconductor structure, memory and electronic device Pending CN114551339A (en)

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