CN114551156B - Relay contact protection circuit for controlling capacitive load - Google Patents
Relay contact protection circuit for controlling capacitive load Download PDFInfo
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- CN114551156B CN114551156B CN202210190293.9A CN202210190293A CN114551156B CN 114551156 B CN114551156 B CN 114551156B CN 202210190293 A CN202210190293 A CN 202210190293A CN 114551156 B CN114551156 B CN 114551156B
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- resistor
- relay
- circuit
- current suppression
- surge current
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H47/00—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
- H01H47/02—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for modifying the operation of the relay
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
Abstract
The invention discloses a relay contact protection circuit for controlling capacitive load, comprising: the power input anode of the surge current suppression circuit is externally connected with the anode of the power input, and the power input cathode of the surge current suppression circuit is externally connected with the cathode of the power input; the power output positive electrode of the surge current suppression circuit is connected with a relay control circuit, and the relay control circuit is connected with a capacitive load; the power output cathode of the surge current suppression circuit is connected with a capacitive load; the time sequence controller is respectively connected with the surge current suppression circuit and the relay control circuit. The invention uses the surge current suppression circuit with the enable and the relay control circuit to control the capacitive load to supply power in series, and the time sequence controller ensures that the relay contact is firstly connected when the load is electrified and then the surge current suppression circuit is enabled, so that the relay contact is prevented from bearing the impact of surge energy. The relay can select the small-capacity type of the contact to reduce the size, weight and cost of the product and prolong the service life of the relay.
Description
Technical Field
The invention belongs to the technical field of power electronics, and relates to a relay contact protection circuit for controlling capacitive load.
Background
In a circuit, when a relay is used for controlling a capacitive load, high surge current can be generated at the moment of relay contact attraction, the surge energy is in direct proportion to the load capacitance, and the relay contact adhesion and ablation are caused by the excessive surge energy, so that the reliability and the service life of electronic equipment are deadly affected. The current capacity of the relay to switch capacitive loads is much smaller than the current capacity to switch purely resistive loads. In actual operation, to avoid this problem, a choke inductance or a parallel combination of a choke inductance and a resistance is typically connected in series between the relay contacts and the capacitive load, or a relay of greater capacitive load capacity is selected. However, when the load capacitance is relatively large, the size and cost of the choke inductance will increase significantly and even the proper choke inductance cannot be selected, and the same problem is faced with the relay option for larger capacitive load switching capability.
Disclosure of Invention
The invention aims to solve the problems in the prior art and provides a relay contact protection circuit for controlling a capacitive load, wherein the topology of the relay contact protection circuit is composed of a surge current suppression circuit with enabling control, a relay control circuit, a time sequence controller and the capacitive load. Through adjusting time sequence control, the surge current suppression circuit absorbs surge energy, and the relay contact is prevented from bearing surge impact.
In order to achieve the purpose, the invention is realized by adopting the following technical scheme:
a relay contact protection circuit for controlling capacitive loading, comprising: the device comprises an inrush current suppression circuit, a relay control circuit, a time sequence controller and a capacitive load;
the power input anode of the surge current suppression circuit is externally connected with the anode of the power input, and the power input cathode of the surge current suppression circuit is externally connected with the cathode of the power input; the power output anode of the surge current suppression circuit is connected with a relay control circuit, and the relay control circuit is connected with a capacitive load; the power output cathode of the surge current suppression circuit is connected with a capacitive load; the time sequence controller is respectively connected with the surge current suppression circuit and the relay control circuit.
The invention further improves that:
the time sequence controller comprises an inrush current suppression circuit enabling control end and a relay on-off control end; the surge current suppression circuit enabling control end of the time sequence controller is connected with the surge current suppression circuit;
and a relay on-off control end of the time sequence controller is connected with a relay control circuit.
The relay control circuit includes: diode D1, relay LS1, transistor Q1 and resistor R1; the relay comprises a control coil, a common contact and a load normally-open contact;
the relay public contact is connected with a power output positive electrode of the surge current suppression circuit; the normally open contact of the relay load is connected with a capacitive load;
one end of the resistor R1 is connected with a relay on-off control end of the time sequence controller; the other end of the resistor R1 is connected with the base electrode of the triode Q1, the emitter electrode of the triode Q1 is grounded, the collector electrode of the triode Q1 is connected with the anode of the diode D1 and one end of a control coil of the relay LS1, and the other end of the control coil of the relay LS1 is connected with the cathode of the diode D1 and the power supply VCC of the control circuit.
The capacitive load comprises a capacitor CL and a resistor RL; the positive electrode of the capacitor CL is connected with one end of the resistor RL and a normally open contact of the relay load; the negative electrode of the capacitor CL is connected with the other end of the resistor RL and the power output negative electrode of the surge current suppression circuit.
The circuit also comprises an isolation circuit, wherein the isolation circuit comprises an optocoupler OPT1, a resistor R10, a triode Q3, a resistor R11 and a diode D3;
the optocoupler OPT1 comprises a light emitting diode and a phototriode, wherein the light emitting diode is used as an input end, and the phototriode is used as an output end;
the positive electrode of the diode D3 is connected with the base electrode of the triode Q3 and one end of the resistor R11; the negative electrode of the diode D3 is connected with an inrush current suppression circuit enabling control end of the time schedule controller; the emitter of the triode Q3 is grounded; the other end of the resistor R11 is connected with one end of the resistor R10 and the circuit power supply VCC;
the collector electrode of the triode Q3 is connected with the cathode of the light-emitting diode in the optocoupler OPT1, and the resistor R10 is connected with the anode of the light-emitting diode in the optocoupler OPT 1;
the collector electrode of the phototriode in the optocoupler OPT1 is connected with a surge current suppression circuit; an emitter of a phototriode in the optocoupler OPT1 is connected with a cathode of a power supply input.
The isolation circuit further comprises a resistor R12, one end of the resistor R12 is connected with the cathode of the diode D3, and the resistor R12 is connected with the circuit power supply VCC.
The surge current suppression circuit includes: the integrated circuit U1, the MOS tube Q1, the resistor R9, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6, the diode D2, the triode Q2 and the capacitor C2;
the positive electrode of the power supply input is connected with one end of a resistor R9, one end of a resistor R2, one end of a resistor R4 and the VIN pin of the integrated circuit U1;
the other end of the resistor R9 is connected with a SENSE pin of the integrated circuit U1 and a drain electrode of the MOS tube Q1; the grid electrode of the MOS tube Q1 is connected with the CATE pin of the integrated circuit U1, one end of the resistor R6 and the anode of the diode D2, and the source electrode of the MOS tube Q1 is connected with the OUT pin of the integrated circuit U1, the PGD pin and the relay control circuit;
the base electrode of the triode Q2 is connected with the other end of the resistor R6, the cathode of the diode D2 is connected with the emitter of the triode Q2 and one end of the capacitor C2, and the other end of the capacitor C2 is connected with the collector of the triode Q2 and the ground;
the other end of the resistor R2 is connected with a UVLO pin of the integrated circuit U1 and one end of the resistor R3;
the other end of the resistor R4 is connected with an OVLO pin of the integrated circuit U1, one end of the resistor R5 and a collector electrode of the optocoupler OPT1 phototriode;
the negative electrode of the power supply input is connected with the other end of the resistor R5, the other end of the resistor R3, the TIMER pin, the PWR pin and the GND pin of the integrated circuit U1.
The inrush current suppression circuit further includes: a capacitor C3, a resistor R8, a resistor R7 and a capacitor C1;
the capacitor C3 is positioned between the TIMER pin of the integrated circuit U1 and the negative electrode of the power supply input; the resistor R8 is positioned between the PWR pin of the integrated circuit U1 and the negative electrode of the power supply input; the resistor R7 is located between the PGD pin of the integrated circuit U1 and the source electrode of the MOS tube Q1, one end of the capacitor C1 is connected with the positive electrode of the power input, and the other end of the capacitor C1 is grounded.
The model of the integrated circuit U1 is LM5069; the MOS transistor Q1 is an NMOS transistor.
Compared with the prior art, the invention has the following beneficial effects:
the invention uses the surge current suppression circuit with the enable and the relay control circuit to control the capacitive load to supply power in series, and the time sequence controller ensures that the relay contact is firstly connected when the load is electrified and then the surge current suppression circuit is enabled, so that the relay contact is prevented from bearing the impact of surge energy. Because the relay contacts do not bear the energy impact when being switched on and off, the relay can select the model with smaller contact capacity so as to reduce the size, weight and cost of the product and prolong the service life of the relay.
Drawings
For a clearer description of the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a topology of a relay contact protection circuit for controlling capacitive loading in accordance with an embodiment of the invention;
FIG. 2 is a control timing diagram of a relay contact protection circuit controlling capacitive loading in accordance with an embodiment of the present invention;
fig. 3 is another topology diagram of a relay contact protection circuit for controlling capacitive loading in accordance with an embodiment of the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the embodiments of the present invention, it should be noted that, if the terms "upper," "lower," "horizontal," "inner," and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and does not indicate or imply that the apparatus or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
Furthermore, the term "horizontal" if present does not mean that the component is required to be absolutely horizontal, but may be slightly inclined. As "horizontal" merely means that its direction is more horizontal than "vertical", and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.
In the description of the embodiments of the present invention, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "mounted," "connected," and "connected" should be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
The invention is described in further detail below with reference to the attached drawing figures:
referring to fig. 1, the invention discloses a relay contact protection circuit for controlling capacitive load, comprising: an inrush current suppression circuit, a relay control circuit, a timing controller, and a capacitive load. The surge current suppression circuit is provided with an enable control end EN_Inrush and is used for controlling on-off of a circuit and suppressing surge current; the relay control circuit consists of a relay LS1, a diode D1, a triode Q1 and a resistor R1; the on-off control of the Relay contacts is realized through a control end EN_Relay; the relay LS1 is used for isolating load power supply and control circuit power supply; the time sequence controller realizes the control of the power-on sequence and the power-off sequence of the load through control signals EN_Inrush and EN_Relay, and the Relay contacts are prevented from being damaged by surge energy.
The relay contact protection circuit structure for controlling capacitive load can be as follows: the power supply input, the surge current suppression circuit, the relay and the capacitive load are sequentially connected, and the method can also be used for: power input-relay-surge current suppression circuit-capacitive load sequence connection. The sequence of the relay and the surge current suppression circuit does not influence the protection result.
According to the following steps: when the power input, the surge current suppression circuit, the relay control circuit and the capacitive load are sequentially connected with the circuits, the positive electrode of the power input of the surge current suppression circuit is externally connected with the positive electrode of the power input, and the negative electrode of the power input of the surge current suppression circuit is externally connected with the negative electrode of the power input; the power output positive electrode of the surge current suppression circuit is connected with a relay control circuit, and the relay control circuit is connected with a capacitive load; the power output cathode of the surge current suppression circuit is connected with a capacitive load; the time sequence controller is respectively connected with the surge current suppression circuit and the relay control circuit.
The inrush current suppression circuit topology includes using an integrated circuit control chip to control a MOSFET, discrete devices to implement an NMOS or PMOS inrush current suppression circuit with enable control.
The time schedule controller comprises an Inrush current suppression circuit enabling control end (EN_Inrush) and a Relay on-off control end (EN_Relay); an enable control end (EN_Inrush) of the surge current suppression circuit of the time sequence controller is connected with the surge current suppression circuit; the Relay on-off control end (EN_Relay) of the time sequence controller is connected with the Relay control circuit.
The logic of the enable control terminal (en_inrush) and the Relay control terminal signal (en_relay) level of the Inrush current suppression circuit is not limited to the high level, and a low level or a combination logic is also possible. Taking high level enable control logic as an example, the controller output timing satisfies that shown in fig. 2. The enabling time of the surge current suppression circuit in the power-on process is required to lag the time t1 of the relay on time, and t1 is required to be longer than the action time of the relay.
The time sequence controller is used for controlling the on-off sequence of the surge suppression circuit and the relay contact, so that the relay contact is ensured not to bear surge energy impact. The timing controller may be any type of hardware delay circuit, single chip microcomputer, microprocessor, DSP, FPGA, etc., and is not limited thereto.
The relay control circuit includes: diode D1, relay LS1, transistor Q1 and resistor R1; the relay comprises a control coil, a common contact and a load normally-open contact;
the relay common contact is connected with a power output positive electrode of the surge current suppression circuit; the normally open contact of the relay load is connected with a capacitive load;
one end of the resistor R1 is connected with a relay on-off control end of the time sequence controller; the other end of the resistor R1 is connected with the base electrode of the triode Q1, the emitter electrode of the triode Q1 is grounded, the collector electrode of the triode Q1 is connected with the anode of the diode D1 and one end of a control coil of the relay LS1, and the other end of the control coil of the relay LS1 is connected with the cathode of the diode D1 and the power supply VCC of the control circuit.
The Relay control signal (en_relay) and the surge current suppression circuit enable signal (en_inrush) can adopt non-isolated structures, and can also adopt optical isolation, magnetic isolation and capacitive isolation measures.
The relay can be single-set contacts or multiple sets of contacts in the forms of single-pole single-throw, single-pole double-throw, double-pole double-throw and the like which are connected in parallel, and is not limited to a common electromagnetic relay, a magnetic latching relay, a sealed relay and the like.
The capacitive load comprises a capacitor CL and a resistor RL; the positive electrode of the capacitor CL is connected with one end of the resistor RL and a normally open contact of the relay load; the negative electrode of the capacitor CL is connected to the other end of the resistor RL and the negative electrode of the power output of the surge current suppression circuit.
The capacitive load is an equivalent circuit and may be a circuit unit, a circuit module, a circuit system or a subsystem.
As shown in fig. 3, the relay contact protection circuit for controlling capacitive load further includes an isolation circuit, where the isolation circuit includes an optocoupler OPT1, a resistor R10, a triode Q3, a resistor R11, and a diode D3;
the optocoupler OPT1 comprises a light emitting diode and a phototriode, wherein the light emitting diode is used as an input end, and the phototriode is used as an output end;
the positive electrode of the diode D3 is connected with the base electrode of the triode Q3 and one end of the resistor R11; the negative electrode of the diode D3 is connected with the surge current suppression circuit enabling control end of the time schedule controller; the emitter of the triode Q3 is grounded; the other end of the resistor R11 is connected with one end of the resistor R10 and the circuit power supply VCC;
the collector electrode of the triode Q3 is connected with the cathode of the light emitting diode in the optocoupler OPT1, and the resistor R10 is connected with the anode of the light emitting diode in the optocoupler OPT 1;
the collector electrode of the phototriode in the optocoupler OPT1 is connected with a surge current suppression circuit; an emitter of a phototriode in the optocoupler OPT1 is connected with a cathode of a power supply input.
The isolation circuit further comprises a resistor R12, one end of the resistor R12 is connected with the cathode of the diode D3, and the resistor R12 is connected with the circuit power supply VCC.
The optocoupler OPT1, the resistor R10, the triode Q3, the resistor R11, the resistor R12 and the diode D3 form an inrush current suppression circuit enabling control isolation circuit. The isolation circuit may use a non-isolated form.
The surge current suppression circuit includes: the integrated circuit U1, the MOS tube Q1, the resistor R9, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6, the diode D2, the triode Q2 and the capacitor C2;
the surge current suppression circuit is realized by driving the MOS transistor Q1 by the integrated circuit U1. The resistor R2 and the resistor R3 realize overvoltage sampling; the resistor R4 and the resistor R5 realize undervoltage sampling; the resistor R6, the diode D2, the triode Q2 and the capacitor C2 realize the adjustment of the grid voltage slope of the MOS tube and the power-down discharge.
The positive electrode of the power supply input is connected with one end of a resistor R9, one end of a resistor R2, one end of a resistor R4 and the VIN pin of the integrated circuit U1;
the other end of the resistor R9 is connected with a SENSE pin of the integrated circuit U1 and a drain electrode of the MOS tube Q1; the grid electrode of the MOS tube Q1 is connected with the CATE pin of the integrated circuit U1, one end of the resistor R6 and the anode of the diode D2, and the source electrode of the MOS tube Q1 is connected with the OUT pin, the PGD pin and the relay control circuit of the integrated circuit U1;
the base electrode of the triode Q2 is connected with the other end of the resistor R6, the cathode of the diode D2 is connected with the emitter of the triode Q2 and one end of the capacitor C2, and the other end of the capacitor C2 is connected with the collector of the triode Q2 and the ground;
the other end of the resistor R2 is connected with a UVLO pin of the integrated circuit U1 and one end of the resistor R3;
the other end of the resistor R4 is connected with an OVLO pin of the integrated circuit U1, one end of the resistor R5 and a collector electrode of the optocoupler OPT1 phototriode;
the negative electrode of the power supply input is connected with the other end of the resistor R5, the other end of the resistor R3, the TIMER pin, the PWR pin and the GND pin of the integrated circuit U1.
The inrush current suppression circuit further includes: a capacitor C3, a resistor R8, a resistor R7 and a capacitor C1;
the capacitor C3 is positioned between the TIMER pin of the integrated circuit U1 and the negative electrode of the power supply input; resistor R8 is located between PWR pin of integrated circuit U1 and the negative pole of the power input; resistor R7 is located between PGD pin of integrated circuit U1 and MOS pipe Q1's source, and the positive pole of power input is connected to capacitor C1's one end, and the other end ground connection of capacitor C1.
The model of the integrated circuit U1 is LM5069; the MOS transistor Q1 is an NMOS transistor.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A relay contact protection circuit for controlling capacitive loading, comprising: the device comprises an inrush current suppression circuit, a relay control circuit, a time sequence controller and a capacitive load;
the power input anode of the surge current suppression circuit is externally connected with the anode of the power input, and the power input cathode of the surge current suppression circuit is externally connected with the cathode of the power input; the power output anode of the surge current suppression circuit is connected with a relay control circuit, and the relay control circuit is connected with a capacitive load; the power output cathode of the surge current suppression circuit is connected with a capacitive load; the time sequence controller is respectively connected with the surge current suppression circuit and the relay control circuit; the time sequence controller comprises an inrush current suppression circuit enabling control end and a relay on-off control end; the surge current suppression circuit enabling control end of the time sequence controller is connected with the surge current suppression circuit; the relay on-off control end of the time sequence controller is connected with a relay control circuit;
the enabling time of the surge current suppression circuit in the power-on process is required to lag the relay on time t1, and t1 is required to be longer than the relay action time.
2. The relay contact protection circuit for controlling a capacitive load of claim 1, wherein the relay control circuit comprises: diode D1, relay LS1, transistor Q1 and resistor R1; the relay comprises a control coil, a common contact and a load normally-open contact;
the relay public contact is connected with a power output positive electrode of the surge current suppression circuit; the normally open contact of the relay load is connected with a capacitive load;
one end of the resistor R1 is connected with a relay on-off control end of the time sequence controller; the other end of the resistor R1 is connected with the base electrode of the triode Q1, the emitter electrode of the triode Q1 is grounded, the collector electrode of the triode Q1 is connected with the anode of the diode D1 and one end of a control coil of the relay LS1, and the other end of the control coil of the relay LS1 is connected with the cathode of the diode D1 and the power supply VCC of the control circuit.
3. The relay contact protection circuit for controlling a capacitive load according to claim 2, wherein the capacitive load includes a capacitor CL and a resistor RL; the positive electrode of the capacitor CL is connected with one end of the resistor RL and a normally open contact of the relay load; the negative electrode of the capacitor CL is connected with the other end of the resistor RL and the power output negative electrode of the surge current suppression circuit.
4. The relay contact protection circuit for controlling capacitive loads according to claim 3, further comprising an isolation circuit comprising an optocoupler OPT1, a resistor R10, a transistor Q3, a resistor R11, and a diode D3;
the optocoupler OPT1 comprises a light emitting diode and a phototriode, wherein the light emitting diode is used as an input end, and the phototriode is used as an output end;
the positive electrode of the diode D3 is connected with the base electrode of the triode Q3 and one end of the resistor R11; the negative electrode of the diode D3 is connected with an inrush current suppression circuit enabling control end of the time schedule controller; the emitter of the triode Q3 is grounded; the other end of the resistor R11 is connected with one end of the resistor R10 and the circuit power supply VCC;
the collector electrode of the triode Q3 is connected with the cathode of the light-emitting diode in the optocoupler OPT1, and the resistor R10 is connected with the anode of the light-emitting diode in the optocoupler OPT 1;
the collector electrode of the phototriode in the optocoupler OPT1 is connected with a surge current suppression circuit; an emitter of a phototriode in the optocoupler OPT1 is connected with a cathode of a power supply input.
5. The capacitive load control relay contact protection circuit of claim 4, wherein the isolation circuit further comprises a resistor R12, wherein one end of the resistor R12 is connected to the cathode of the diode D3, and wherein the resistor R12 is connected to the circuit power supply VCC.
6. The relay contact protection circuit for controlling a capacitive load according to claim 5, wherein the inrush current suppression circuit comprises: the integrated circuit U1, the MOS tube Q1, the resistor R9, the resistor R2, the resistor R3, the resistor R4, the resistor R5, the resistor R6, the diode D2, the triode Q2 and the capacitor C2;
the positive electrode of the power supply input is connected with one end of a resistor R9, one end of a resistor R2, one end of a resistor R4 and the VIN pin of the integrated circuit U1;
the other end of the resistor R9 is connected with a SENSE pin of the integrated circuit U1 and a drain electrode of the MOS tube Q1; the grid electrode of the MOS tube Q1 is connected with the CATE pin of the integrated circuit U1, one end of the resistor R6 and the anode of the diode D2, and the source electrode of the MOS tube Q1 is connected with the OUT pin of the integrated circuit U1, the PGD pin and the relay control circuit;
the base electrode of the triode Q2 is connected with the other end of the resistor R6, the cathode of the diode D2 is connected with the emitter of the triode Q2 and one end of the capacitor C2, and the other end of the capacitor C2 is connected with the collector of the triode Q2 and the ground;
the other end of the resistor R2 is connected with a UVLO pin of the integrated circuit U1 and one end of the resistor R3;
the other end of the resistor R4 is connected with an OVLO pin of the integrated circuit U1, one end of the resistor R5 and a collector electrode of the optocoupler OPT1 phototriode;
the negative electrode of the power supply input is connected with the other end of the resistor R5, the other end of the resistor R3, the TIMER pin, the PWR pin and the GND pin of the integrated circuit U1.
7. The relay contact protection circuit for controlling a capacitive load of claim 6, wherein the inrush current suppression circuit further comprises: a capacitor C3, a resistor R8, a resistor R7 and a capacitor C1;
the capacitor C3 is positioned between the TIMER pin of the integrated circuit U1 and the negative electrode of the power supply input; the resistor R8 is positioned between the PWR pin of the integrated circuit U1 and the negative electrode of the power supply input; the resistor R7 is located between the PGD pin of the integrated circuit U1 and the source electrode of the MOS tube Q1, one end of the capacitor C1 is connected with the positive electrode of the power input, and the other end of the capacitor C1 is grounded.
8. The capacitive load control relay contact protection circuit of claim 7, wherein the integrated circuit U1 is model LM5069; the MOS transistor Q1 is an NMOS transistor.
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| CN202210190293.9A CN114551156B (en) | 2022-02-28 | 2022-02-28 | Relay contact protection circuit for controlling capacitive load |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210190293.9A CN114551156B (en) | 2022-02-28 | 2022-02-28 | Relay contact protection circuit for controlling capacitive load |
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| CN114551156B true CN114551156B (en) | 2023-08-29 |
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| CN114551156A (en) | 2022-05-27 |
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