CN114548021B - Test point identification method, device and application - Google Patents
Test point identification method, device and application Download PDFInfo
- Publication number
- CN114548021B CN114548021B CN202210448582.4A CN202210448582A CN114548021B CN 114548021 B CN114548021 B CN 114548021B CN 202210448582 A CN202210448582 A CN 202210448582A CN 114548021 B CN114548021 B CN 114548021B
- Authority
- CN
- China
- Prior art keywords
- network
- node
- traveled
- segment
- nodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/10—Geometric CAD
- G06F30/18—Network design, e.g. design based on topological or interconnect aspects of utility systems, piping, heating ventilation air conditioning [HVAC] or cabling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Geometry (AREA)
- Evolutionary Computation (AREA)
- General Engineering & Computer Science (AREA)
- Architecture (AREA)
- Computer Networks & Wireless Communication (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The application provides a test point identification method, a test point identification device and application, and the method comprises the following steps: the method comprises the steps of obtaining a PCB basic primitive, constructing a network connected graph based on the PCB basic primitive, selecting any network node in the network connected graph as an execution node, traversing the network connected graph by taking the execution node as a starting point, marking the traversed network node as a traversed node in the traversing process, marking the traversed network line segment as a traversed line segment, collecting the network line segments connected with the traversed node as a subset of the traversed node, counting the number of the network line segments in the subset of the traversed node, identifying the traversed node as a test point if the number of the line segments is 1, judging whether the network node is a network node which needs to be tested by using the number of the network line segments, screening necessary test points in a plurality of network nodes, reducing the testing of unnecessary test points and improving the testing efficiency of the PCB.
Description
Technical Field
The present application relates to the field of printed circuit boards, and in particular, to a test point identification method, apparatus, and application.
Background
Parts on the PCB are complex and various, and can not be manufactured in a trade if the parts do not meet the process requirements, so the parts need to be tested before the PCB is manufactured, and test points need to be arranged on the PCB for testing the PCB. In other words, the purpose of the test points on the PCB is to test whether the components on the circuit board meet the specification and solderability.
In the prior art, test points are selected on a PCB manually, and the selected test points are sent to corresponding test equipment, so that the test equipment can perform connectivity test on the PCB according to the selected test points. However, the accuracy of the test point identification in this way completely depends on the technical level of the technician, problems of missed detection, multiple detection and the like easily exist, and the identification way also needs to consume too much energy of the technician. Certainly, some PCB engineering file test point analysis tools can automatically analyze test points, but the test points analyzed by the analysis tools often have many unnecessary test points, and the unnecessary test points cause low PCB test efficiency, thereby affecting the overall production efficiency.
Disclosure of Invention
The embodiment of the application provides a test point identification method, a test point identification device and application, which can accurately identify necessary test points on a printed circuit and improve the test efficiency of a printed circuit board.
In a first aspect, an embodiment of the present application provides a test point identification method, where the method includes:
acquiring a PCB basic primitive, wherein the PCB basic primitive comprises a network node and a network line segment connected with the network node;
constructing a network connected graph based on the PCB basic primitives, wherein any two PCB basic primitives in each network connected graph are conducted;
selecting any network node in a network connection graph as an execution node, traveling the network connection graph by taking the execution node as a starting point, marking a network node which has traveled as a traveled node in the traveling process, marking a network line segment which has traveled as a traveled line segment, and collecting the network line segments which are communicated with the traveled node as a subset of the traveled node;
and counting the number of network line segments in each subset of the visited nodes, and if the number of the line segments is 1, identifying the visited nodes as test points.
In a second aspect, an embodiment of the present application provides a test point identification apparatus, including:
the device comprises a primitive obtaining unit, a primitive obtaining unit and a primitive processing unit, wherein the primitive obtaining unit is used for obtaining a PCB basic primitive which comprises a network node and a network line segment connected with the network node;
the network connected graph acquisition unit is used for constructing a network connected graph based on the PCB basic primitives, wherein any two PCB basic primitives in each network connected graph are conducted;
the tour unit is used for selecting any network node in the network connected graph as an execution node, tour the network connected graph by taking the execution node as a starting point, marking the network node which has walked as a tour node in the tour process, marking the network line segment which has walked as a tour line segment, and collecting the network line segments which are communicated with the tour node as a subset of the tour node;
and the statistical unit is used for counting the number of the network line segments in the subset of each traversed node, and if the number of the line segments is 1, identifying the traversed node as a test point.
In a third aspect, an embodiment of the present application provides an electronic apparatus, including a memory and a processor, where the memory stores a computer program, and the processor is configured to execute the computer program to perform the test point identification method.
In a fourth aspect, the present application provides a readable storage medium, in which a computer program is stored, where the computer program includes program code for controlling a process to execute a process, and the process includes the test point identification method.
The main contributions and innovation points of the invention are as follows:
according to the method and the device, the pads of the PCB are used as network nodes, the connecting lines between the pads are used as network line segments to form the network connection graph, the network connection graph is traversed, the number of the network line segments of each network node in the traversing process is counted, whether the network nodes are the network nodes which need to be tested or not is judged according to the number of the network line segments, then necessary test points are screened from a plurality of network nodes, tests of unnecessary test points are reduced, and PCB test efficiency is improved.
It is worth mentioning that the concept of "path" is originally introduced in the test point identification technical scheme, if a certain network node has two or more paths, it indicates that the network node is located between the paths of other network nodes, at this time, only the other two network nodes including the path of the network node need to be measured, and then the network node does not need to be further tested; if a certain network node can only have one path, it means that the network node is located at a path end point, and the network node located at the path end point can be used to determine whether the path is connected, so that the node located at the path end point can be used as a test point. In addition, for the network node in the closed-loop structure, although the network node in the closed-loop structure has at least two paths, because the network node is located in the closed-loop structure, two adjacent paths of the network node need to be merged to obtain a merged path, and whether the network node is a test point which needs to be tested can be quickly judged by counting the number of the paths.
The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the application.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a flowchart of a test point identification method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of primitive clustering according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a closed loop path according to one embodiment of the present application;
FIG. 4 is a schematic diagram of a network connectivity graph according to one embodiment of the present application;
fig. 5 is a schematic diagram of a trial-and-actual operation of a test point identification method according to an embodiment of the present application;
FIG. 6 is a schematic logic flow diagram of a test point identification method according to an embodiment of the present application;
fig. 7 is a block diagram of a test point identification apparatus according to an embodiment of the present application;
fig. 8 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with one or more embodiments of the present specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of one or more embodiments of the specification, as detailed in the claims which follow.
It should be noted that: in other embodiments, the steps of the corresponding methods are not necessarily performed in the order shown and described herein. In some other embodiments, the method may include more or fewer steps than those described herein. Moreover, a single step described in this specification may be broken down into multiple steps for description in other embodiments; multiple steps described in this specification may be combined into a single step in other embodiments.
Example one
The embodiment of the application provides a test point identification method, which can accurately identify necessary test points on a printed circuit board, reduce the test of unnecessary test points and further improve the test efficiency of the printed circuit board. Specifically, with reference to fig. 1, the method comprises:
acquiring a PCB basic primitive, wherein the PCB basic primitive comprises a network node and a network line segment connected with the network node;
constructing a network connected graph based on the PCB basic primitives, wherein any two PCB basic primitives in each network connected graph are conducted;
selecting any network node in a network connection graph as an execution node, traveling the network connection graph by taking the execution node as a starting point, marking a network node which has traveled as a traveled node in the traveling process, marking a network line segment which has traveled as a traveled line segment, and collecting the network line segments which are communicated with the traveled node as a subset of the traveled node;
and counting the number of network line segments in each subset of the visited nodes, and if the number of the line segments is 1, identifying the visited nodes as test points.
In the step of obtaining basic graphic elements of the PCB, a jigsaw file of the PCB is obtained, and the basic graphic elements in the jigsaw file are identified. In this scheme, the makeup files may be read according to the Gerber protocol.
Specifically, the scheme defines that the welding pads on the PCB are identified as network nodes, and the connecting lines between the welding pads are identified as network line segments. That is to say, the network node corresponds to a pad on the PCB, and the network line segment corresponds to a connection line between the pad and the pad on the PCB.
Of course, all the pads on the PCB can be used as test points, but in this case, there is a problem that the test points are too redundant, which results in low test efficiency. In the scheme, the network end points are selected from a plurality of bonding pads to be used as test points to be tested, and the rest network intermediate points are used as unnecessary test points. This is because, in the same network line, if the network endpoints of the network line are connected, it means that the entire network line is connected, and the corresponding middle segment of the network line is necessarily connected, so it is not necessary to test the network middle point of the network line.
For clarity of illustration: the concept of "network endpoints" and "network intermediate points". This is illustrated below:
the scheme creatively introduces the concepts of 'access' and 'merged access':
according to the scheme, the network line segment which can be conducted by the corresponding network node is defined as a path, and a plurality of paths can be formed by corresponding to the same network node. Assuming that there are three network nodes a/B/C, B, C for which a must pass through network node a, a is the network intermediate point between B and C, when the path between two a and B for a, and the path between a and C is already covered by the path between B and C, when the path of a does not need to be tested after the path between B and C is tested. However, if a via is not covered by other vias, that is, a is the starting point or the ending point of the via. In other words, if a network node is located on a path between two other network nodes, the path of the network node is already covered by the paths of the two other network nodes, and no additional measurement for the path of the node is required.
If a closed-loop structure is formed among a plurality of network nodes, at this time, the path of each network node in the closed-loop structure is necessarily overlapped with the path of an adjacent network node, and at this time, two adjacent paths of each network node need to be combined to form a combined path.
In the step of constructing the network connection graph based on the PCB basic primitives, the PCB basic primitives which can be communicated with each other are clustered into the same cluster group, and the network connection graph is constructed according to the position relation of the PCB basic primitives in each cluster group.
That is to say, in the scheme, a network connected graph can be constructed by using a primitive clustering method, and the PCB basic primitives which cannot be connected are grouped, so that any two PCB basic primitives in each group can be connected, and the PCB basic primitives in different groups cannot be connected.
It should be noted that any two PCB basic primitives are connected through other PCB basic primitives, and it may also be defined that the two PCB basic primitives may be connected.
For example, as shown in fig. 2, if a PCB basic primitive includes A, B, C, D four network nodes, two network line segments AB and AD, the two PCB basic primitives B and D may be connected through the two PCB basic primitives AB and AD, and the two PCB basic primitives B and D may be clustered into the same cluster group. A, C, the PCB primitives A and C are clustered into different clusters.
Certainly, a plurality of independent network connection graphs can be constructed based on the PCB basic primitive, and in the scheme, the test point identification calculation is performed for each network connection graph. In order to improve the efficiency of identifying the test points of the whole scheme, the scheme adopts a parallel operation mode to identify the test points of a plurality of network connection graphs simultaneously.
In a specific example, a test point calculation thread pool may be created, and the number of threads in the test point calculation thread pool is the number of CPUs, so that an independent test point calculation task may be created for each network connectivity graph, and the threads in the calculation thread pool may perform parallel operations.
In the step of selecting any network node of the network connectivity graph as an executing node, the executing node is also marked as a walked node. In some embodiments, the bottom-left most network node in the network connectivity graph may be selected as the originating node.
In the present solution, the network segments between two network nodes are bi-directionally connected, that is, the network segments may traverse in a forward direction or in a reverse direction. In order to reduce the amount of calculation, the scheme does not traverse the traversed network segments.
In the scheme, the network line segments directly connected with the traveled line segments are collected into the subset of the traveled nodes. It is worth noting that a network segment may serve as a subset of the plurality of traversed nodes. In addition, if a loop exists in the tour process, the network segment of each network node in the loop needs to be adjusted, and the adjustment mode is as follows: network segments in the loop that communicate with the network nodes are merged.
Specifically, in the step of "traveling the network connectivity graph starting from the execution node", it is determined whether there is a network segment that is not marked as a traveled segment and is in communication with the execution node, and if there is a network segment that is not marked as a traveled segment and is in communication with the execution node, the network connectivity graph is traveled along the network segment to reach a next network node, and the network node is used as a new execution node to continue traveling the network connectivity graph.
In addition, if the next network node that arrives is a visited node, a visited path that takes the visited node as a starting point and an ending point is selected as a closed-loop path, and a subset of all visited nodes in the closed-loop path is adjusted according to a closed-loop adjustment rule, where the closed-loop adjustment rule is: and combining two network line segments which are communicated with each other in front and back of each traversed node. It should be noted that each traversed node in the closed-loop path needs to merge with the path associated with the closed-loop path.
For example, as shown in fig. 3, when travelling along the line of C-D-E-G-F-D, the travelling path surrounded by D-E-G-F-D is used as a closed-loop path, and D, E, G, F two network line segments connected back and forth between the four travelling nodes are merged, specifically, DE and EG are merged into one network line segment which is collected into a subset corresponding to E, and there is only one network line segment in the subset corresponding to E. And combining the DE and the FD into the same network line segment and collecting the network line segment into a subset corresponding to the D, wherein the subset corresponding to the D contains the CD and the new network line segment after combination.
According to the scheme, all network nodes of the network connection graph are taken as traveled nodes, and all network line segments are taken as traveled line segments and taken as signals for stopping traveling.
Specifically, in the step of "determining whether there is a network segment which is not marked as a traveled segment and is communicated with the execution node", if there is no network segment which is not marked as a traveled segment and is communicated with the execution node, the remaining traveled nodes in the travel path where the execution node is located are selected as the execution nodes.
It is worth mentioning that the other traversed nodes in the traversal path where the execution node is located are traced back as the execution nodes according to the far and near sequence until all the execution nodes do not have network segments which are not marked as traversed segments and are communicated with the execution nodes.
For example, as shown in fig. 4, when traversing the network connectivity graph from point a along the manner shown by the arrow, the network connectivity graph will eventually return to point a, at this time, there is no network segment which is not marked as a traveled segment and is connected to point a, but there is still a network segment which is not marked as a traveled segment in the network connectivity graph, so that point B in the traveled path where point a is located is traced back, and if it is found that there is a network segment which is not marked as a traveled segment and is taken as an execution node, the node B is taken as an execution node to continue the travel.
Fig. 5 is a schematic diagram of actual operation of the test point identification method, and 5 test points can be calculated from fig. 5, where a network node corresponding to a white dot on a line shown in the diagram is a test point, a network node marked by a white "x" symbol is a network intermediate point, and is not selected as an actual test point. It can be seen that the line includes a closed loop structure, although the white dots in the closed loop structure have two paths, because the white dots are located in the closed loop structure, the test point identification method in the present scheme merges two adjacent network line segments before and after the white dots, and finally, the subset corresponding to the white dots only contains one network line segment, which can be used as the test point of the line.
As shown in fig. 6, fig. 6 is a specific application example of the present solution, in which a network node at the leftmost lower corner in the network connectivity graph is selected as a starting execution node, and a network segment that is not marked as a traveled segment is found for traveling. The tour path can be subdivided into the following cases according to circumstances:
1. and when the network line segment which is not marked as the traveled line segment does not exist, and other traveled nodes or other traveled nodes in the traveled path do not exist or the network line segment which is not marked as the traveled line segment does not exist, ending the travel.
2. If the network line segment which is not marked as the traveled line segment does not exist, but other traveled nodes in the travel path have the network line segment which is not marked as the traveled line segment, the other traveled nodes continue to travel;
3. if the network segment which is not marked as the tour segment exists, continuing the tour along the network segment;
in this case, if a traveled node exists in the travel route to be traveled, the closed-loop route formed by the traveled node is adjusted.
Example two
Based on the same concept, referring to fig. 7, the present application further provides a test point identification apparatus, including:
a primitive obtaining unit 301, configured to obtain a PCB basic primitive, where the PCB basic primitive includes a network node and a network line segment connecting the network node;
a network connectivity graph obtaining unit 302, configured to construct a network connectivity graph based on the PCB basic primitives, where any two PCB basic primitives in each network connectivity graph are connected;
a tour unit 303, configured to select any network node in a network connectivity graph as an execution node, tour the network connectivity graph using the execution node as a starting point, mark a network node that has walked as a tour node in a tour process, mark a network line segment that has walked as a tour line segment, and collect the network line segments that connect the tour nodes into a subset of the tour nodes;
a counting unit 304, configured to count the number of network line segments in each subset of the traversed nodes, and if the number of line segments is 1, identify the traversed node as a test point.
The technical features of the test point identification device are the same as the technical features of the test point identification method, and repeated contents are not redundantly described here.
EXAMPLE III
The present embodiment further provides an electronic apparatus, referring to fig. 8, including a memory 404 and a processor 402, where the memory 404 stores a computer program, and the processor 402 is configured to execute the computer program to perform the steps in any of the test point identification method embodiments.
Specifically, the processor 402 may include a Central Processing Unit (CPU), or A Specific Integrated Circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.
The processor 402 may implement any of the test point identification methods in the above embodiments by reading and executing computer program instructions stored in the memory 404.
Optionally, the electronic apparatus may further include a transmission device 406 and an input/output device 408, where the transmission device 406 is connected to the processor 402, and the input/output device 408 is connected to the processor 402.
The transmitting device 406 may be used to receive or transmit data via a network. Specific examples of the network described above may include wired or wireless networks provided by communication providers of the electronic devices. In one example, the transmission device includes a Network adapter (NIC) that can be connected to other Network devices through a base station to communicate with the internet. In one example, the transmitting device 406 may be a Radio Frequency (RF) module, which is used to communicate with the internet in a wireless manner.
The input and output devices 408 are used to input or output information. In this embodiment, the input information may be a PCB panel text, and the output information may be a test point.
Optionally, in this embodiment, the processor 402 may be configured to execute the following steps by a computer program:
s101, obtaining a PCB basic primitive, wherein the PCB basic primitive comprises a network node and a network line segment connected with the network node;
s102, constructing a network connected graph based on the PCB basic graphic elements, wherein any two PCB basic graphic elements in each network connected graph are conducted;
s103, selecting any network node in the network connected graph as an execution node, traveling the network connected graph by taking the execution node as a starting point, marking the network node which has traveled as a traveled node in the traveling process, marking the network line segment which has traveled as a traveled line segment, and collecting the network line segments which are connected with the traveled node as a subset of the traveled node;
and S104, counting the number of network line segments in each sub-set of the visited nodes, and if the number of the line segments is 1, identifying the visited nodes as test points.
It should be noted that, for specific examples in this embodiment, reference may be made to examples described in the foregoing embodiments and optional implementations, and details of this embodiment are not described herein again.
In general, the various embodiments may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. Some aspects of the invention may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the invention is not limited thereto. While various aspects of the invention may be illustrated and described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that these blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.
Embodiments of the invention may be implemented by computer software executable by a data processor of the mobile device, such as in a processor entity, or by hardware, or by a combination of software and hardware. Computer software or programs (also referred to as program products) including software routines, applets and/or macros can be stored in any device-readable data storage medium and they include program instructions for performing particular tasks. The computer program product may comprise one or more computer-executable components configured to perform embodiments when the program is run. The one or more computer-executable components may be at least one software code or a portion thereof. Further in this regard it should be noted that any block of the logic flow as in the figures may represent a program step, or an interconnected logic circuit, block and function, or a combination of a program step and a logic circuit, block and function. The software may be stored on physical media such as memory chips or memory blocks implemented within the processor, magnetic media such as hard or floppy disks, and optical media such as, for example, DVDs and data variants thereof, CDs. The physical medium is a non-transitory medium.
It should be understood by those skilled in the art that various features of the above embodiments can be combined arbitrarily, and for the sake of brevity, all possible combinations of the features in the above embodiments are not described, but should be considered as within the scope of the present disclosure as long as there is no contradiction between the combinations of the features.
The above examples are merely illustrative of several embodiments of the present application, and the description is more specific and detailed, but not to be construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.
Claims (8)
1. A test point identification method is characterized by comprising the following steps:
acquiring a PCB basic primitive, wherein the PCB basic primitive comprises a network node and a network line segment connected with the network node;
constructing a network connected graph based on the PCB basic primitives, wherein any two PCB basic primitives in each network connected graph are conducted;
selecting any network node in the network connection graph as an execution node, judging whether a network segment which is not marked as a traveled segment and is communicated with the execution node exists, if so, traveling the network connection graph along the network segment to reach the next network node, and taking the network node as a new execution node to continue traveling the network connection graph, marking the network node which has traveled as the node which has traveled in the process of traveling, marking the network line segment which has traveled as the line segment which has traveled, and collecting network line segments communicating the traveled nodes as a subset of the traveled nodes, if the next network node is the traveled node, selecting a traveled path with the traveled node as a starting point and an end point as a closed-loop path, and adjusting the subset of all the traveled nodes in the closed-loop path according to a closed-loop adjustment rule, wherein the closed-loop adjustment rule is as follows: merging two network line segments which are communicated with each other in front and at the back of each tour node;
and counting the number of network line segments in the subset of each traversed node, and if the number of the line segments is 1, identifying the traversed node as a test point.
2. The test point identification method of claim 1, wherein in the step of determining whether there is a network segment which is not marked as a traveled segment and is communicated with the execution node, if there is no network segment which is not marked as a traveled segment and is communicated with the execution node, the rest traveled nodes in the traveled path where the execution node is located are selected as the execution nodes.
3. The test point identification method of claim 2, wherein the other traversed nodes in the traversal path where the execution node is located are traced back as the execution nodes according to the far and near order until all the execution nodes do not have network line segments which are not marked as traversed line segments and are communicated with the execution nodes.
4. The test point identification method of claim 1, wherein in the step of constructing the network connectivity graph based on the PCB base primitives, the PCB base primitives that can be connected to each other are clustered into the same cluster group, and the network connectivity graph is constructed according to the position relationship of the PCB base primitives within each cluster group.
5. The test point identification method of claim 1, wherein pads on the PCB are identified as network nodes and the connections between the pads are identified as network line segments.
6. A test point identification apparatus, comprising:
the device comprises a primitive obtaining unit, a primitive obtaining unit and a primitive processing unit, wherein the primitive obtaining unit is used for obtaining a PCB basic primitive which comprises a network node and a network line segment connected with the network node;
the network connected graph acquisition unit is used for constructing a network connected graph based on the PCB basic primitives, wherein any two PCB basic primitives in each network connected graph are conducted;
a tour unit, configured to select any network node in a network connectivity graph as an execution node, determine whether there is a network segment that is not marked as a tour segment and is communicated with the execution node, if so, tour the network connectivity graph along the network segment to a next network node, continue to tour the network connectivity graph with the network node as a new execution node, mark the network node that has walked during the tour as a tour node, mark the network segment that has walked as a tour segment, and collect the network segments that are communicated with the tour node into a subset of the tour node, if the next network node that arrives as a tour node, select a tour path that has the tour node as a start point and an end point as a closed-loop path, and adjust the subset of all the tour nodes in the closed-loop path according to a closed-loop adjustment rule, the closed-loop regulation rule is as follows: merging two network line segments which are communicated with each other in front and at the back of each tour node;
and the counting unit is used for counting the number of network line segments in each sub-set of the visited nodes, and if the number of the line segments is 1, identifying the visited nodes as test points.
7. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and the processor is configured to execute the computer program to perform the test point identification method of any of claims 1 to 5.
8. A readable storage medium, characterized in that a computer program is stored in the readable storage medium, the computer program comprising program code for controlling a process to execute a process, the process comprising the test point identification method according to any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210448582.4A CN114548021B (en) | 2022-04-27 | 2022-04-27 | Test point identification method, device and application |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210448582.4A CN114548021B (en) | 2022-04-27 | 2022-04-27 | Test point identification method, device and application |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114548021A CN114548021A (en) | 2022-05-27 |
| CN114548021B true CN114548021B (en) | 2022-07-29 |
Family
ID=81667124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210448582.4A Active CN114548021B (en) | 2022-04-27 | 2022-04-27 | Test point identification method, device and application |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114548021B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105043400A (en) * | 2015-06-30 | 2015-11-11 | 百度在线网络技术（北京）有限公司 | Route planning method and device |
| CN108009061A (en) * | 2017-12-04 | 2018-05-08 | 东北大学 | A kind of method for changing Node Contraction in Complex Networks control category |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10116547B2 (en) * | 2015-05-19 | 2018-10-30 | Ca, Inc. | Coverage policy-based testing in computer networks |
| CN109768883A (en) * | 2018-12-21 | 2019-05-17 | 华为技术服务有限公司 | A kind of the determination method, apparatus and terminal device in network topology path |
| CN109918779B (en) * | 2019-03-06 | 2023-05-16 | 深圳市百能信息技术有限公司 | Method and device for selecting vector diagram test points, storage medium and terminal |
| CN113597119B (en) * | 2021-09-30 | 2021-12-10 | 杭州捷配信息科技有限公司 | Waste treatment method and device suitable for PCB production process |
-
2022
- 2022-04-27 CN CN202210448582.4A patent/CN114548021B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105043400A (en) * | 2015-06-30 | 2015-11-11 | 百度在线网络技术（北京）有限公司 | Route planning method and device |
| CN108009061A (en) * | 2017-12-04 | 2018-05-08 | 东北大学 | A kind of method for changing Node Contraction in Complex Networks control category |
Non-Patent Citations (1)
| Title |
|---|
| 基于最小集合覆盖的网络连通性自动化测试;张馨等;《计算机工程》;20121220(第24期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114548021A (en) | 2022-05-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110413506A (en) | Test case recommended method, device, equipment and storage medium | |
| CN108733540B (en) | Method and system for testing computational power and power consumption of mining machine | |
| CN103377105B (en) | A kind of serial bus testing method | |
| CN108919083A (en) | A method of improving Serdes IP wafer test efficiency | |
| CN103246602A (en) | Code coverage rate confirming method, code coverage rate confirming system, code coverage rate detecting method and code coverage rate detecting system | |
| CN104422878A (en) | Integrated circuit (IC), method of operating the IC, and device having the IC | |
| CN112543470B (en) | Terminal positioning method and system based on machine learning | |
| CN115809203B (en) | Dynamic nesting method and device for software test cases and application of dynamic nesting method and device | |
| US20130166976A1 (en) | Diagnosis-Aware Scan Chain Stitching | |
| CN113190220A (en) | JSON file differentiation comparison method and device | |
| CN115982053A (en) | Method, device and application for detecting software source code defects | |
| CN109408309A (en) | The test method and device of multiple terminals | |
| CN114286383B (en) | Network quality determining method, device and storage medium | |
| CN114339603B (en) | Method, device, equipment and storage medium for switching positioning area | |
| CN114548021B (en) | Test point identification method, device and application | |
| CN112464609B (en) | Integrated circuit relative position layout optimization method, device and storage medium | |
| CN112462245B (en) | Method and device for generating boundary scanning interconnection line | |
| CN107844515B (en) | Data compliance checking method and device | |
| CN202404912U (en) | Neural network test module and test system of smart card chip memory | |
| CN112822700A (en) | Method and device for determining category | |
| CN115470108A (en) | Gateway route testing method and device for vehicle, electronic equipment and storage medium | |
| WO2023184732A1 (en) | Genome assembly method and apparatus, and device and storage medium | |
| CN105679690B (en) | The method for improving test wafer service life | |
| CN113227965B (en) | Distributed processing support device, distributed processing support method, and storage medium | |
| CN113779925B (en) | Minimum line width calculation method and device suitable for PCB engineering file and application |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |