CN114531135B - A packaging structure for SAW filter CSP form - Google Patents

A packaging structure for SAW filter CSP form Download PDF

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CN114531135B
CN114531135B CN202210436197.8A CN202210436197A CN114531135B CN 114531135 B CN114531135 B CN 114531135B CN 202210436197 A CN202210436197 A CN 202210436197A CN 114531135 B CN114531135 B CN 114531135B
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copper
substrate
copper strip
chip
metal
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CN114531135A (en
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不公告发明人
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Shenzhen Newsonic Technologies Co Ltd
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Shenzhen Newsonic Technologies Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/08—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/46—Filters
    • H03H9/64—Filters using surface acoustic waves

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Toxicology (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

The invention provides a packaging structure for an SAW filter CSP form, which comprises a chip set; a part of the chips in the chipset is embedded in the substrate of the packaging structure, and another part of the chips in the chipset is embedded in the cover plate of the packaging structure; a plurality of metal copper layers are arranged in the substrate; the metal copper layer is used for performing signal connection and electromagnetic shielding on a chip embedded in the substrate of the packaging structure and a chip embedded in the cover plate of the packaging structure.

Description

A packaging structure for SAW filter CSP form
Technical Field
The invention provides a packaging structure for an SAW filter CSP form, and belongs to the technical field of chip packaging.
Background
In the continuous industrial field that is applied to of film filter, with the wide range of film filter application and the continuous requirement of present industrial technology application index, need film filter volume to do little gradually, however, because the setting of the wafer chip of film filter, apron and base plate three layer construction, lead to film filter thickness to continue to do not to do little all the time, lead to the too big problem of encapsulation thickness to exist always.
Disclosure of Invention
The invention provides a packaging structure for SAW filter CSP form, which is used for solving the problems of strong electromagnetic interference and overlarge packaging thickness of the existing chip packaging, and adopts the following technical scheme:
a package structure for SAW filter CSP form, said package structure comprising a chipset; a part of the plurality of chips in the chipset is embedded in the substrate 10 of the package structure, and another part of the plurality of chips in the chipset is embedded in the cover plate 11 of the package structure; a plurality of metal copper layers are arranged in the substrate 10; the metal copper layer is used for performing signal connection and electromagnetic shielding on a chip embedded in the substrate 10 of the packaging structure and a chip embedded in the cover plate 11 of the packaging structure.
Further, a passivation layer is disposed between the substrate 10 and the cover plate 11; moreover, the passivation layer is provided with welding spot hole positions; a metal welding spot 8 is arranged in the welding spot hole; the metal welding points are used for establishing electric signal connection between the chip embedded in the cover plate 11 of the packaging structure and the metal copper layer.
Further, the chip set includes a first chip 1, a second chip 2, and a third chip 3; the first chip 1 is embedded in the substrate 10; the second chip 2 and the third chip 3 are embedded in the cover plate 11.
Further, the metallic copper layers include a first substrate metallic copper layer 4, a second substrate metallic copper layer 5, a third substrate metallic copper layer 6 and a fourth substrate metallic copper layer 7; the first substrate metal copper layer 4 is arranged on the periphery of a first chip 1 in the chip set, and is used for electrically connecting the first chip 1 with a welding spot signal end of a second chip 2; the second substrate copper metal layer 5 is arranged in the substrate space between the first substrate copper metal layer 4 and the fourth substrate copper metal layer 7; the third substrate metal copper layer 6 is arranged in the substrate 10 and is positioned on the bottom surface of the substrate on the side where the cover plate is not arranged; the fourth substrate copper layer 7 is disposed below the third chip 3, and connects the third chip 3 and the third substrate copper layer 6.
Further, the first substrate metallic copper layer 4 includes a first sub copper layer 41 and a second sub copper layer 42; the first sub copper layer 41 and the second sub copper layer 42 are respectively located below the two metal pads 8 of the second chip 2 and connected to the two metal pads 8.
Further, the first sub copper layer 41 includes an upper connection copper strip, a peripheral portion, and a lower connection copper strip; the peripheral part comprises two longitudinal copper strips and two transverse copper strips; the two longitudinal copper strips and the two transverse copper strips are enclosed to form a rectangular structure; the first chip 1 is arranged in a substrate in the rectangular structure; the transverse copper strip on one side of the peripheral part close to the cover plate is connected with the metal welding spot 8 of the second chip 2 corresponding to the first sub copper layer 41 through an upper connecting copper strip; a lower connecting copper strip is arranged on the transverse copper strip on one side, close to the non-arranged cover plate, of the peripheral part; and the lower connecting copper strip is electrically connected with the first chip 1.
Further, the second substrate metallic copper layer 5 comprises an upper transverse copper strip, a longitudinal copper strip and a lower transverse copper strip; the longitudinal copper strip is vertically arranged between the upper transverse copper strip and the lower transverse copper strip.
Further, the height of the upper transverse copper strip and the height of the second substrate copper metal layer 5 are the same as the height of the transverse copper strip on the side close to the cover plate in the second substrate copper metal layer 5, and the height range of the lower transverse copper meets the following condition:
0.35H≤H 1 ≤0.60H
wherein H 1 Represents the vertical distance between the lower transverse copper of the second substrate metallic copper layer 5 and the bottom surface of the substrate on the side where the cover plate is not arranged; h denotes the vertical distance between the transverse copper strip near the cover plate side in the first sub-copper layer 41 of the first substrate copper layer 4 and the bottom surface of the substrate on the side where the cover plate is not provided.
Further, the fourth substrate copper metal layer 7 comprises a first sub copper strip 71 and a second sub copper strip 72; the first sub copper strip 71 and the second sub copper strip 72 are respectively positioned below the two metal welding points 8 of the third chip 3 and are connected with the two metal welding points 8; and the first copper strip 71 connects one metal pad 8 of the third chip 3 with the third substrate metallic copper layer 6.
Further, the sub copper strip one 71 comprises an upper connecting copper strip, a first transverse copper strip, a second transverse copper strip, a first longitudinal copper strip and a second longitudinal copper strip; one end of the upper connecting copper strip is connected with one metal welding spot 8 corresponding to the third chip 3; the other end of the upper connecting copper strip is connected with the first transverse copper strip; the first transverse copper strip is connected with one end of the first longitudinal copper strip; the other end of the first longitudinal copper strip is connected with the second transverse copper strip; the second transverse copper strip is connected with one end of the second longitudinal copper strip; the other end of the second longitudinal copper strip is connected with the third substrate metal copper layer 6;
the first longitudinal copper strip and the second longitudinal copper strip are arranged in a staggered mode and are not on the same longitudinal straight line any more, and when the first longitudinal copper strip and the second longitudinal copper strip are arranged in a staggered mode, the distance between the first longitudinal copper strip and the second longitudinal copper strip meets the following conditions:
0.30L 2 ≤D≤0.61L 2
wherein D represents the distance between the first and second longitudinal copper strips, L 2 Representing the length of the second transverse copper strip;
meanwhile, the length ratio between the first transverse copper strip and the second transverse copper strip meets the following conditions:
0.50L 1 ≤L 2 ≤0.82L 1
wherein L is 1 And L 2 The lengths of the first and second transverse copper strips are indicated, respectively.
The invention has the beneficial effects that:
the SAW filter CSP type packaging structure provided by the invention removes the independent space occupied by the chip during packaging by the structural form that the chip is embedded in the cover plate and the substrate, thereby effectively reducing the thickness size of the thin film filter in thickness. Simultaneously, because the structure of chip embedded in apron and base plate leads to the chip all to set up in the entity structure, lead to the chip easily to produce the high conductibility of physical vibration and electromagnetism in the entity structure when carrying out high-frequency oscillation, and then influence the running performance of film filter, consequently, through set up the metal copper layer of horizontal and vertical extension and the structural shape and the size proportion of metal copper layer in the base plate, effectively improve electromagnetic interference's shielding performance and block the vibration wave conduction who decomposes physical vibration, and then improve film filter's operating stability.
Drawings
FIG. 1 is a schematic diagram of a cover plate structure of the package structure according to the present invention;
FIG. 2 is a schematic diagram of a substrate structure of the package structure according to the present invention;
FIG. 3 is a schematic diagram of the overall structure of the package structure according to the present invention;
(1, first chip; 2, second chip; 3, third chip; 4, first substrate copper metal layer; 5, second substrate copper metal layer; 6, third substrate copper metal layer; 7, fourth substrate copper metal layer; 8, metal pad; 9, passivation layer; 10, substrate; 11, cover plate; 41, first sub-copper layer; 42, second sub-copper layer; 71, first sub-copper strip; 72, second sub-copper strip).
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
An embodiment of the present invention provides a package structure for SAW filter CSP, as shown in fig. 1 to 3, the package structure includes a chipset; a part of the plurality of chips in the chipset is embedded in the substrate 10 of the package structure, and another part of the plurality of chips in the chipset is embedded in the cover plate 11 of the package structure; a plurality of metal copper layers are arranged in the substrate 10; the metal copper layer is used for performing signal connection and electromagnetic shielding on a chip embedded in the substrate 10 of the packaging structure and a chip embedded in the cover plate 11 of the packaging structure.
Meanwhile, a passivation layer is arranged between the substrate 10 and the cover plate 11; moreover, the passivation layer 9 is provided with a welding spot hole position; a metal welding spot 8 is arranged in the welding spot hole; the metal welding points are used for establishing electric signal connection between the chip embedded in the cover plate 11 of the packaging structure and the metal copper layer.
The working principle and the effect of the technical scheme are as follows: the packaging structure for the SAW filter CSP type provided by the embodiment removes the independent space occupied by the chip during packaging through the structural form of embedding the chip in the cover plate and the substrate, thereby effectively reducing the thickness of the thin film filter in thickness. Simultaneously, because the structure of chip embedded in apron and base plate leads to the chip all to set up in the entity structure, lead to the chip easily to produce the high conductibility of physical vibration and electromagnetism in the entity structure when carrying out high-frequency oscillation, and then influence the running performance of film filter, consequently, through set up the metal copper layer of horizontal and vertical extension and the structural shape and the size proportion of metal copper layer in the base plate, effectively improve electromagnetic interference's shielding performance and block the vibration wave conduction who decomposes physical vibration, and then improve film filter's operating stability.
In one embodiment of the present invention, the chipset includes a first chip 1, a second chip 2, and a third chip 3; the first chip 1 is embedded in the substrate 10; the second chip 2 and the third chip 3 are embedded in the cover plate 11.
The metal copper layers comprise a first substrate metal copper layer 4, a second substrate metal copper layer 5, a third substrate metal copper layer 6 and a fourth substrate metal copper layer 7; the first substrate metal copper layer 4 is arranged on the periphery of a first chip 1 in the chip set, and is used for electrically connecting the first chip 1 with a welding spot signal end of a second chip 2; the second substrate copper metal layer 5 is arranged in the substrate space between the first substrate copper metal layer 4 and the fourth substrate copper metal layer 7; the third substrate metal copper layer 6 is arranged in the substrate 10 and is positioned on the bottom surface of the substrate on the side where the cover plate is not arranged; the fourth substrate copper layer 7 is disposed below the third chip 3, and connects the third chip 3 and the third substrate copper layer 6.
The working principle and the effect of the technical scheme are as follows: under the condition that the filter chip with multi-stage connection is arranged, the independent space occupied by the chip during packaging is removed through the structural form that the chip is embedded in the cover plate and the substrate, and the thickness size of the thin film filter is effectively reduced in thickness. Meanwhile, the structure that the chip is embedded in the cover plate and the substrate leads the chip to be arranged in the solid structure, the chip is easy to generate physical vibration and high conductivity of electromagnetism in the solid structure when high-frequency vibration is carried out, and the running performance of the thin film filter is further influenced.
In one embodiment of the present invention, the first substrate metallic copper layer 4 includes a first sub copper layer 41 and a second sub copper layer 42; the first sub copper layer 41 and the second sub copper layer 42 are respectively located below the two metal pads 8 of the second chip 2 and connected to the two metal pads 8.
Wherein the first sub copper layer 41 comprises an upper connecting copper strip, a peripheral part and a lower connecting copper strip; the peripheral part comprises two longitudinal copper strips and two transverse copper strips; the two longitudinal copper strips and the two transverse copper strips are enclosed to form a rectangular structure; the first chip 1 is arranged in a substrate in the rectangular structure; the transverse copper strip on one side of the peripheral part close to the cover plate is connected with the metal welding spot 8 of the second chip 2 corresponding to the first sub copper layer 41 through an upper connecting copper strip; a lower connecting copper strip is arranged on the transverse copper strip on one side, close to the non-arranged cover plate, of the peripheral part; and the lower connecting copper strip is electrically connected with the first chip 1.
The working principle and the effect of the technical scheme are as follows: through the structural part of the first substrate metal copper layer, the chip can be subjected to signal cascade and external conduction, the structural shapes of the metal copper layer and the metal copper layer which are transversely and longitudinally extended are arranged in the substrate, the shielding performance of signal transmission electromagnetic interference is effectively improved when a signal of the chip arranged in the cover plate is transmitted into the substrate, and the electromagnetic interference generated by the signal transmission on the chip in the substrate is avoided.
In one embodiment of the present invention, the second substrate metallic copper layer 5 comprises an upper transverse copper strip, a longitudinal copper strip and a lower transverse copper strip; the longitudinal copper strip is vertically arranged between the upper transverse copper strip and the lower transverse copper strip.
The height of the upper transverse copper strip and the height of the second substrate copper metal layer 5 are the same as the height of the transverse copper strip on one side, close to the cover plate, in the second substrate copper metal layer 5, and the height range of the lower transverse copper meets the following conditions:
0.35H≤H 1 ≤0.60H
wherein H 1 Represents the vertical distance between the lower transverse copper of the second substrate metallic copper layer 5 and the bottom surface of the substrate on the side where the cover plate is not arranged; h denotes the vertical distance between the transverse copper strip near the cover plate side in the first sub-copper layer 41 of the first substrate copper layer 4 and the bottom surface of the substrate on the side where the cover plate is not provided.
The working principle and the effect of the technical scheme are as follows: through the structure setting of second base plate metal copper layer 5, size setting and position setting combine other metal copper layer structures and positions can effectively improve second base plate metal copper layer 5 and form effectual electromagnetic signal shielding efficiency to between the signal cascade structure that second chip and first chip formed and the signal of third chip leads the structure, and simultaneously, can be under the condition that effectively improves electromagnetic signal shielding efficiency through the position setting, reduce the coverage area and the coverage rate on metal copper layer, and then effectively reduce manufacturing cost and the manufacturing difficulty, improve manufacturing efficiency and reduce cost consumption.
In an embodiment of the present invention, the fourth substrate metallic copper layer 7 includes a first sub copper strip 71 and a second sub copper strip 72; the first sub copper strip 71 and the second sub copper strip 72 are respectively positioned below the two metal welding points 8 of the third chip 3 and are connected with the two metal welding points 8; and the first copper strip 71 connects one metal pad 8 of the third chip 3 with the third substrate metallic copper layer 6.
The sub copper strip I71 comprises an upper connecting copper strip, a first transverse copper strip, a second transverse copper strip, a first longitudinal copper strip and a second longitudinal copper strip; one end of the upper connecting copper strip is connected with one metal welding spot 8 corresponding to the third chip 3; the other end of the upper connecting copper strip is connected with the first transverse copper strip; the first transverse copper strip is connected with one end of the first longitudinal copper strip; the other end of the first longitudinal copper strip is connected with the second transverse copper strip; the second transverse copper strip is connected with one end of the second longitudinal copper strip; the other end of the second longitudinal copper strip is connected with the third substrate metal copper layer 6; meanwhile, the height of the first transverse copper strip is the same as that of the upper transverse copper strip of the second substrate metal copper layer. The height of the second transverse copper strip is the same as the height of the lower transverse copper strip of the second substrate copper metal layer.
The first longitudinal copper strip and the second longitudinal copper strip are arranged in a staggered mode and are not on the same longitudinal straight line any more, and when the first longitudinal copper strip and the second longitudinal copper strip are arranged in a staggered mode, the distance between the first longitudinal copper strip and the second longitudinal copper strip meets the following conditions:
0.30L 2 ≤D≤0.61L 2
wherein D represents the distance between the first and second longitudinal copper strips, L 2 Representing the length of the second transverse copper strip;
meanwhile, the length ratio between the first transverse copper strip and the second transverse copper strip meets the following conditions:
0.50L 1 ≤L 2 ≤0.82L 1
wherein L is 1 And L 2 The lengths of the first and second transverse copper strips are indicated, respectively.
The working principle and the effect of the technical scheme are as follows: through the structure setting of fourth base plate metal copper layer 7, size setting and position setting combine other metal copper layer structures and positions can effectively improve fourth base plate metal copper layer 7 and lead the anti-electromagnetic interference performance of structure outside the signal of third chip, simultaneously, can effectively eliminate and decompose third chip vibration conductivity through the position setting under the condition of effective anti-battery interference performance, and then improve the stability of third chip operation, and reduce the mutual interference nature that causes other chip operations in its operation.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (9)

1. A package structure for SAW filter CSP, characterized in that it comprises a chipset; a part of the plurality of chips in the chip group is embedded in a substrate (10) of the packaging structure, and the other part of the plurality of chips in the chip group is embedded in a cover plate (11) of the packaging structure; a plurality of metal copper layers are arranged in the substrate (10); the metal copper layer is used for performing signal connection and electromagnetic shielding on a chip embedded in a substrate (10) of the packaging structure and a chip embedded in a cover plate (11) of the packaging structure;
wherein the metal copper layers comprise a first substrate metal copper layer (4), a second substrate metal copper layer (5), a third substrate metal copper layer (6) and a fourth substrate metal copper layer (7); the first substrate metal copper layer (4) is arranged on the periphery of a first chip (1) in the chip set, and a welding spot signal end of the first chip (1) is electrically connected with a welding spot signal end of a second chip (2); the second substrate copper metal layer (5) is arranged in a substrate space between the first substrate copper metal layer (4) and a fourth substrate copper metal layer (7); the third substrate metal copper layer (6) is arranged in the substrate (10) and is positioned on the bottom surface of the substrate on the side where the cover plate is not arranged; the fourth substrate metal copper layer (7) is arranged below the third chip (3), and the third chip (3) is connected with the third substrate metal copper layer (6).
2. The encapsulation structure according to claim 1, characterized in that a passivation layer is arranged between the substrate (10) and the cover plate (11); moreover, the passivation layer is provided with welding spot hole positions; metal welding spots (8) are arranged in the welding spot hole positions; the metal welding points are used for establishing electric signal connection between the chip embedded in the cover plate (11) of the packaging structure and the metal copper layer.
3. The package structure according to claim 1, wherein the chipset comprises a first chip (1), a second chip (2) and a third chip (3); the first chip (1) is embedded in the substrate (10); the second chip (2) and the third chip (3) are embedded in the cover plate (11).
4. The package structure according to claim 1, wherein the first substrate metallic copper layer (4) comprises a first sub-copper layer (41) and a second sub-copper layer (42); the first sub copper layer (41) and the second sub copper layer (42) are respectively positioned below the two metal welding points (8) of the second chip (2) and are connected with the two metal welding points (8).
5. The package structure according to claim 4, wherein the first sub-copper layer (41) comprises an upper connecting copper strip, a peripheral portion and a lower connecting copper strip; the peripheral part comprises two longitudinal copper strips and two transverse copper strips; the two longitudinal copper strips and the two transverse copper strips are enclosed to form a rectangular structure; the first chip (1) is arranged in a substrate in the rectangular structure; the transverse copper strip on one side, close to the cover plate, of the peripheral part is connected with a metal welding point (8) of the second chip (2) corresponding to the first sub copper layer (41) through an upper connecting copper strip; a lower connecting copper strip is arranged on the transverse copper strip on one side, close to the non-arranged cover plate, of the peripheral part; and the lower connecting copper strip is electrically connected with the first chip (1).
6. The encapsulation structure according to claim 1, wherein the second substrate metallic copper layer (5) comprises an upper transverse copper strip, a longitudinal copper strip and a lower transverse copper strip; the longitudinal copper strip is vertically arranged between the upper transverse copper strip and the lower transverse copper strip.
7. The package structure according to claim 6, wherein the height of the upper lateral copper strip and the second substrate copper metal layer (5) is the same as the height of the lateral copper strip of the second substrate copper metal layer (5) on the side close to the cover plate, and the height range of the lower lateral copper satisfies the following condition:
0.35H≤H 1 ≤0.60H
wherein H 1 Represents the vertical distance between the lower transverse copper of the second substrate metallic copper layer (5) and the bottom surface of the substrate on the side not provided with the cover plate; h represents the vertical distance between the transverse copper strip close to the cover plate side in the first sub copper layer (41) of the first substrate metal copper layer (4) and the bottom surface of the substrate on the side where the cover plate is not arranged.
8. The encapsulation structure according to claim 1, wherein the fourth substrate metallic copper layer (7) comprises a first sub-copper strip (71) and a second sub-copper strip (72); the first sub copper strip (71) and the second sub copper strip (72) are respectively positioned below the two metal welding points (8) of the third chip (3) and are connected with the two metal welding points (8); and the first copper strip (71) connects one metal pad (8) of the third chip (3) with the third substrate copper layer (6).
9. The package structure according to claim 8, wherein the first sub-copper strip (71) comprises an upper connection copper strip, a first transverse copper strip, a second transverse copper strip, a first longitudinal copper strip, and a second longitudinal copper strip; one end of the upper connecting copper strip is connected with one metal welding spot (8) corresponding to the third chip (3); the other end of the upper connecting copper strip is connected with the first transverse copper strip; the first transverse copper strip is connected with one end of the first longitudinal copper strip; the other end of the first longitudinal copper strip is connected with the second transverse copper strip; the second transverse copper strip is connected with one end of the second longitudinal copper strip; the other end of the second longitudinal copper strip is connected with the third substrate metal copper layer (6);
the first longitudinal copper strip and the second longitudinal copper strip are arranged in a staggered mode and are not on the same longitudinal straight line any more, and when the first longitudinal copper strip and the second longitudinal copper strip are arranged in a staggered mode, the distance between the first longitudinal copper strip and the second longitudinal copper strip meets the following conditions:
0.30L 2 ≤D≤0.61L 2
wherein D represents the distance between the first and second longitudinal copper strips, L 2 Representing the length of the second transverse copper strip;
meanwhile, the length ratio between the first transverse copper strip and the second transverse copper strip meets the following conditions:
0.50L 1 ≤L 2 ≤0.82L 1
wherein L is 1 And L 2 The lengths of the first and second transverse copper strips are indicated, respectively.
CN202210436197.8A 2022-04-25 2022-04-25 A packaging structure for SAW filter CSP form Active CN114531135B (en)

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Publication number Priority date Publication date Assignee Title
TW200810035A (en) * 2006-08-03 2008-02-16 Unimicron Technology Corp Embedded chip package process and circuit board with embedded chip
CN112820694A (en) * 2021-01-15 2021-05-18 上海航天电子通讯设备研究所 Chip shielding and airtight packaging method and packaging structure

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