CN114528803A - Matching method and device of circuit schematic diagram, electronic equipment and storage medium - Google Patents
Matching method and device of circuit schematic diagram, electronic equipment and storage medium Download PDFInfo
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Abstract
The application discloses a matching method of a circuit schematic diagram, which comprises the following steps: determining an IC chip, and inquiring an alternative CBB circuit corresponding to the IC chip in a standard CBB model library; obtaining a circuit schematic diagram of a circuit where the IC chip is located, and determining pin connection information of the IC chip according to the circuit schematic diagram; determining a target circuit corresponding to the alternative CBB circuit in the circuit schematic diagram according to the circuit connection relation in the circuit schematic diagram; and determining the difference information of the alternative CBB circuit and the target circuit according to the pin connection information. The difference between the circuit of actual design and the common circuit module can be confirmed to this application, and the circuit designer of being convenient for carries out the exactness check to the circuit. The application also discloses a matching device of the circuit schematic diagram, an electronic device and a storage medium, and the matching device has the beneficial effects.
Description
Technical Field
The present disclosure relates to the field of circuit design technologies, and in particular, to a method and an apparatus for matching a schematic diagram of a circuit, an electronic device, and a storage medium.
Background
CBB (Common Building Block) circuit refers to a circuit module shared between different design platforms and projects. At present, in the design process of the circuit schematic diagram, the designed schematic diagram is usually directly referred to, and the required CBB module is copied from the schematic diagram. However, since the application functions of each product form to the same chip are different, each chip may correspond to multiple versions of CBB circuits, and the correctness of the circuit schematic diagram cannot be guaranteed without actual project verification by directly using the designed CBB circuit.
Therefore, how to determine the difference between the actually designed circuit and the common circuit module to facilitate the circuit designer to check the correctness of the circuit is a technical problem that needs to be solved by those skilled in the art at present.
Disclosure of Invention
The application aims to provide a matching method and device of a circuit schematic diagram, an electronic device and a storage medium, which can determine the difference between an actually designed circuit and a common circuit module and facilitate the circuit designer to carry out correctness verification on the circuit.
In order to solve the above technical problem, the present application provides a matching method of a circuit schematic diagram, including:
determining an IC chip, and inquiring an alternative CBB circuit corresponding to the IC chip in a standard CBB model library;
obtaining a circuit schematic diagram of a circuit where the IC chip is located, and determining pin connection information of the IC chip according to the circuit schematic diagram;
determining a target circuit corresponding to the alternative CBB circuit in the circuit schematic diagram according to the circuit connection relation in the circuit schematic diagram;
and determining the difference information of the alternative CBB circuit and the target circuit according to the pin connection information.
Optionally, determining pin connection information of the IC chip according to the schematic circuit diagram includes:
generating a first tree diagram by traversing the connection condition of pins in the IC chip; the first tree diagram comprises a network name, a device bit number, a material code of the device and a packaging name;
generating a second tree graph by traversing the connection condition of pins in other circuit modules; wherein the other circuit modules include circuit modules not connected to the IC chip in the schematic circuit diagram; the second tree diagram comprises a network name, a device bit number, a material code of the device and a packaging name;
and obtaining a total tree diagram taking the IC chip as a root node according to all the first tree diagrams and all the second tree diagrams, and taking the total tree diagram as pin connection information of the IC chip.
Optionally, the generating a total tree diagram with the IC chip as a root node according to all the first tree diagrams and all the second tree diagrams includes:
adding a state mark for a topological end point in the first tree diagram and the second tree diagram; the state mark comprises a network name, a device name and a pin number;
merging the topological end points with the same state labels in the first tree diagram and the second tree diagram into the same node so as to connect the first tree diagram and the second tree diagram to obtain a total tree diagram taking the IC chip as a root node.
Optionally, determining difference information between the candidate CBB circuit and the target circuit according to the pin connection information includes:
determining a target tree diagram corresponding to the alternative CBB circuit in the total tree diagram;
and comparing the network and the device in the alternative CBB circuit with the target dendrogram to obtain difference information.
Optionally, comparing the network and the device in the alternative CBB circuit with the target tree diagram to obtain difference information, including:
determining a current hierarchy element in the alternative CBB circuit;
judging whether the current level element is the same as the same level element in the target tree diagram;
if not, generating difference information corresponding to the current level element;
if the current hierarchy element is the same as the current hierarchy element, setting the next hierarchy as a new current hierarchy element, and executing the operation of judging whether the current hierarchy element is the same as the element of the same hierarchy in the target tree diagram.
Optionally, if the current hierarchical element is a network, the determining whether the current hierarchical element is the same as the same hierarchical element in the target tree diagram includes:
judging whether the current level element and the same level element in the target tree diagram are distributed with non-default network names or not; the network names comprise default network names and non-default network names, and the default network names are network names automatically distributed to the elements by the system;
if the current level element and/or the same level element in the target tree diagram is/are distributed with a non-default network name, judging whether the network name of the current level element is the same as the network name of the same level element in the target tree diagram; if the current hierarchical element is the same as the current hierarchical element, marking the state of the current hierarchical element as successful matching; if not, marking the state of the current level element as matching failure;
if the current hierarchical element and the same hierarchical element in the target tree map are not distributed with the non-default network name, marking the state of the current hierarchical element as pending;
if the states of all elements under the elements marked as undetermined are marked as matching success, modifying the state of the elements marked as undetermined into matching success;
if the state of any element under the element marked as undetermined is marked as matching failure, modifying the state of the element marked as undetermined into matching failure;
adding an element of which the state is marked as matching failure to an information difference list; wherein the difference information includes information in the information difference list.
Optionally, if the current level element is a device, the determining whether the current level element is the same as the same level element in the target tree diagram includes:
judging whether the material codes of the current level elements are the same as the material codes of the same level elements in the target dendrogram or not;
if the material codes are the same, judging that the current level elements are the same as the same level elements in the target tree diagram;
if the material codes are different, judging whether the packaging name of the current level element is the same as the packaging name of the same level element in the target tree diagram;
if the packaging names are the same, adding the current level element to a device attribute difference list;
if the packaging names are different, judging whether the pin parameters of the current level elements are the same as the administrative parameters of the same level elements in the target tree diagram; the pin parameters comprise the number of pins and the serial number of the pins;
if the pin parameters are the same, adding the current level element to the device attribute difference list;
if the pin parameters are different, adding the current level element and other elements under the current level element into an information difference list; wherein the difference information includes information in the device attribute difference list and/or the information difference list.
Optionally, after determining the difference information between the candidate CBB circuit and the target circuit according to the pin connection information, the method further includes:
determining the matching degree of the alternative CBB circuit and the circuit schematic diagram and elements with differences in the alternative CBB circuit and the circuit schematic diagram according to the difference information;
and displaying the alternative CBB circuit to a circuit schematic diagram editing interface, and displaying the matching degree and improving the display brightness of the elements with the difference in the circuit schematic diagram editing interface.
The present application also provides a matching device of a schematic diagram of a circuit, the correcting device including:
the CBB circuit query module is used for determining the IC chip and querying an alternative CBB circuit corresponding to the IC chip in a standard CBB model library;
the connection information determining module is used for acquiring a circuit schematic diagram of a circuit where the IC chip is located and determining pin connection information of the IC chip according to the circuit schematic diagram;
the circuit determining module is used for determining a target circuit corresponding to the alternative CBB circuit in the circuit schematic diagram according to the circuit connection relation in the circuit schematic diagram;
and the difference determining module is used for determining the difference information between the candidate CBB circuit and the target circuit according to the pin connection information.
The present application also provides a storage medium having stored thereon a computer program which, when executed, implements the steps performed by the matching method of the above-described circuit schematic.
The application also provides an electronic device, which comprises a memory and a processor, wherein the memory is stored with a computer program, and the processor realizes the steps executed by the matching method of the circuit schematic diagram when calling the computer program in the memory.
The invention provides a matching method of a circuit schematic diagram, which comprises the following steps: determining an IC chip, and inquiring an alternative CBB circuit corresponding to the IC chip in a standard CBB model library; obtaining a circuit schematic diagram of a circuit where the IC chip is located, and determining pin connection information of the IC chip according to the circuit schematic diagram; determining a target circuit corresponding to the alternative CBB circuit in the circuit schematic diagram according to the circuit connection relation in the circuit schematic diagram; and determining the difference information of the alternative CBB circuit and the target circuit according to the pin connection information.
The candidate CBB circuit corresponding to the IC chip is inquired in a CBB model base, and the candidate CBB circuit is a CBB circuit pre-stored in a standard CBB model base so as to be compared with the CBB circuit in a circuit schematic diagram of the circuit where the IC chip is located. The method comprises the steps of determining pin connection information of an IC chip according to a circuit schematic diagram of a circuit where the IC chip is located, determining a target circuit corresponding to an alternative CBB circuit in the circuit schematic diagram according to an actual circuit connection relation in the circuit schematic diagram if the alternative CBB circuit is applied to the circuit schematic diagram, determining difference information of the alternative CBB circuit and the target circuit based on the pin connection information, using the difference information as a difference between the actually used circuit in the circuit schematic diagram and a CBB circuit prestored in a standard CBB model base, and verifying correctness of the circuit schematic diagram according to the difference information by a circuit designer. The difference between the circuit of actual design and the common circuit module can be confirmed to this application, and the circuit designer of being convenient for carries out the exactness check to the circuit. The application also provides a matching device of the circuit schematic diagram, an electronic device and a storage medium, which have the beneficial effects and are not repeated herein.
Drawings
In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a flowchart of a matching method of a schematic circuit diagram according to an embodiment of the present disclosure;
fig. 2 is a flowchart of a method for determining pin connection information according to an embodiment of the present disclosure;
fig. 3 is a tree diagram of a pin connection relationship provided in the embodiment of the present application;
FIG. 4 is a schematic diagram illustrating an automatic matching principle of a CBB circuit in practical application according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a matching apparatus of a circuit schematic diagram according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a flowchart of a matching method of a circuit schematic diagram according to an embodiment of the present disclosure.
The specific steps may include:
s101: determining an IC chip, and inquiring an alternative CBB circuit corresponding to the IC chip in a standard CBB model library;
in this embodiment, the circuit used in the schematic circuit diagram is compared with the CBB circuit in the standard CBB model library, and the IC (integrated circuit) chip determined in this step is the chip in the schematic circuit diagram. The standard CBB model library may store a plurality of pre-stored CBB circuits and a correspondence between the IC chip and each pre-stored CBB circuit, and in this step, the candidate CBB circuit corresponding to the IC chip may be queried in the standard CBB model library based on the correspondence.
As a possible implementation, each IC chip may have its corresponding material code, which is a unique identifier for each device in the circuit. After the code of the IC chip is determined, the corresponding candidate CBB circuit may be queried in a standard CBB model library. The standard CBB model library stores a plurality of pre-stored CBB circuits and a correspondence between the material code of each CBB circuit and the material code of the IC chip, and this embodiment may determine an alternative CBB circuit corresponding to the IC chip according to the correspondence. The alternative CBB circuit refers to the CBB circuit that the IC chip is required to use.
Before the step, an operation of constructing a standard CBB model library can also exist, and after the designed CBB circuit is completed, the circuit schematic diagram of the CBB circuit, the material code of the CBB circuit and the material code of the IC chip contained in the circuit schematic diagram of the CBB circuit can be stored in the standard CBB model library.
S102: obtaining a circuit schematic diagram of a circuit where an IC chip is located, and determining pin connection information of the IC chip according to the circuit schematic diagram;
wherein the operation of the circuit schematic of the circuit in which the IC chip is designed by the user may be present before this step. As a possible implementation manner, in the process of designing the schematic diagram of the circuit, the selected IC chip may be determined first, and the material CODE (i.e., CODE) of the IC chip may be obtained. The material code based on the IC chip is matched with the standard CBB model library, the candidate CBB circuits corresponding to the IC chip are inquired, the candidate CBB circuits are copied into the schematic diagram in a module mode, and a designer manually inspects whether the CBB circuits are directly available or can modify based on a certain CBB circuit, so that the designer can be quickly assisted to match the required CBB circuits. Because the number of the CBB circuit filing libraries is huge, the alternative CBB circuits are matched in the embodiment through a mode of automatically inquiring material codes, and each follow-up CBB filing person carries out filing based on the actual application design of the module. By the method, the multiplexing accuracy of the CBB circuit can be improved, and the borrowing rate is improved. The mode solves the problem of information intercommunication among the cross-department, and all CBB circuits can become public available resources. The requirements of the CBB circuit filing of the embodiment can be changed to be based on practical application and higher in usability.
Specifically, the generation process of the circuit schematic diagram includes: displaying the alternative CBB circuit to a circuit schematic diagram editing interface; if an editing instruction is received, executing corresponding editing operation on the alternative CBB circuit according to the editing instruction; and if a displacement instruction is received, moving the alternative CBB circuit to a corresponding position according to the displacement instruction. The IC chip may include a plurality of pins, and the present embodiment may acquire pin connection information of all the pins. The pin can be connected with a network and a device, and the pin connection information is information for describing a pin connection state.
S103: determining a target circuit corresponding to the alternative CBB circuit in the circuit schematic diagram according to the circuit connection relation in the circuit schematic diagram;
s104: and determining the difference information of the alternative CBB circuit and the target circuit according to the pin connection information.
In this embodiment, the candidate CBB circuits pre-stored in the standard CBB model library are queried through the material codes of the IC chip, and if there is difference information between the target circuit and the candidate CBB circuit corresponding to the same circuit module, it may be shown that there is a design difference between the actually designed circuit and the pre-stored CBB circuit. By obtaining the difference information, the circuit designer can be helped to check the correctness of the circuit schematic diagram, the difference points between the target circuit in the newly designed circuit schematic diagram and the CBB circuit in the standard CBB model library can be reflected, and the reference can be provided for other people to use the CBB circuit in the standard CBB model library for reference.
Specifically, in this embodiment, the pin connection information of the IC chip may be used to match the candidate CBB circuit, and the difference information between the candidate CBB circuit and the target circuit in the circuit schematic diagram is determined according to the matching result. And if the difference information is null, the target circuit in the circuit schematic diagram is consistent with the alternative CBB circuit design in the standard CBB model library. If the difference information is not null, the difference indicates that the target circuit is different from the alternative CBB circuit design in the standard CBB model base, and at the moment, a design error may exist in the circuit schematic diagram, and the circuit schematic diagram can be corrected according to the difference information.
In this embodiment, the candidate CBB circuit corresponding to the IC chip is searched in the CBB model library, and the candidate CBB circuit is a CBB circuit pre-stored in the standard CBB model library, so as to compare with the CBB circuit in the circuit schematic diagram of the circuit where the IC chip is located. In this embodiment, pin connection information of the IC chip is determined according to a circuit schematic diagram of a circuit in which the IC chip is located, if the candidate CBB circuit is applied to the circuit schematic diagram, a certain circuit connection relationship exists between the candidate CBB circuit and the IC chip, the embodiment determines a target circuit corresponding to the candidate CBB circuit in the circuit schematic diagram according to an actual circuit connection relationship in the circuit schematic diagram, further determines difference information between the candidate CBB circuit and the target circuit based on the pin connection information, and uses the difference information as a difference between a circuit actually used in the circuit schematic diagram and a CBB circuit pre-stored in a standard CBB model library, and a circuit designer can check the correctness of the circuit schematic diagram according to the difference information. The embodiment can determine the difference between the actually designed circuit and the common circuit module, and is convenient for circuit designers to carry out correctness verification on the circuit.
As a further description of the corresponding embodiment of fig. 1, this embodiment may determine, according to the difference information, a matching degree between the candidate CBB circuit and the circuit schematic diagram, and an element of the candidate CBB circuit and the circuit schematic diagram, where there is a difference; and displaying the alternative CBB circuit to a circuit schematic diagram editing interface, and displaying the matching degree and improving the display brightness of the elements with the difference in the circuit schematic diagram editing interface. The method for calculating the matching degree of the candidate CBB circuit and the circuit schematic diagram may be: taking the ratio of the number of the matched elements to the number of the total matched elements as the matching degree; the number of matched elements is the number of networks matched with the circuit schematic diagram in the alternative CBB circuit, and the total number of matched elements is the sum of the number of devices in the CBB circuit and the number of networks. The embodiment can automatically lead the CBB into schematic diagram software and highlight the difference points, and can quickly compare the difference points between the design module and the CBB circuit, thereby quickly confirming the difference points and mainly checking the difference.
Referring to fig. 2, fig. 2 is a flowchart of a method for determining pin connection information according to an embodiment of the present application, where this embodiment is further described with respect to S102 in the embodiment corresponding to fig. 1, and a further implementation may be obtained by combining this embodiment with the embodiment corresponding to fig. 1, where this embodiment may include the following steps:
s201: generating a first tree diagram by traversing the connection condition of pins in the IC chip;
the first tree graph comprises a network name, a device position number, a material code and a packaging name of the device;
s202: generating a second tree graph by traversing the connection condition of pins in other circuit modules;
wherein the other circuit modules include circuit modules not connected to the IC chip in the schematic circuit diagram; the second tree diagram comprises a network name, a device bit number, a material code of the device and a packaging name;
s203: and obtaining a total tree diagram taking the IC chip as a root node according to all the first tree diagrams and all the second tree diagrams, and taking the total tree diagram as pin connection information of the IC chip.
In the embodiment, a map page (such as pages 1 to 5) of a circuit module circuit designed in a circuit schematic diagram can be selected, and the candidate CBB circuit is obtained by matching the designated IC chip in the designed CBB circuit with the CBB circuit. Specifically, the present embodiment may cycle through the pin topology to obtain the connection condition of the pins in the IC chip in the actual circuit. The other circuit modules are circuit modules except the IC chip in the circuit schematic diagram, and the embodiment can cycle through the pin topology to obtain the connection condition of the pins in the other circuit modules. Referring to fig. 3, fig. 3 is a tree diagram of a pin connection relationship provided in the present embodiment, where the present embodiment can generate a first tree diagram and a second tree diagram according to a pin connection condition.
Further, the extraction and topology expansion method of other circuit modules not directly connected to the IC chip and circuit modules of other pages is as follows: the other modules are not directly connected with the IC module, so that an external connection network of a certain module is obtained, the network meets the requirement that one end is suspended or is a ground network, the extracted external network is marked, and the marking format is as follows: network and network name label (namely non-default network name), device name, extracted device bit number, material code and packaging name value. The tags are extracted into a list and sorted, and the list is compared with the network tag list of the IC module. The network label list of the IC module comprises a network of the IC chip and a name label (namely a non-default network name) of the network, a device name, an extracted device bit number, a material code and a package name value. And finding a mark with successful first matching in the comparison process, wherein the mark is used as a network reference extracted by the module, and the network is used as the module to start topology expansion.
The generation idea of the tree diagram is as follows: traversing from the base pin, and judging whether a branch exists at the position or not by searching for one step forwards; when the branch exists, each branch is taken as a subroot value of the tree diagram, and then each branch is respectively circulated, so that the pin connection information is extracted. The pin connection information includes: the method comprises the steps that a network and a network name label (namely a non-default network name), a device name, an extracted device bit number, a material code and an encapsulation name value are stored in a child root of a father root, and all IC pins and corresponding topologies are extracted into a tree diagram by the same method. In the process of extracting the pin connection information, if there is no name label of the network, the UID of the network (i.e., default network name) is extracted.
The external connection of the IC chip pins is a topology which comprises a network, a resistor, a capacitor, an inductor or other functional chips and network connections extending outwards from the chips and the like until the topological end point of the first tree diagram or the second tree diagram. Topological end points include the following two cases: the first is that topology expansion extends to the pin of the IC chip, and the topology is the end point of the path topology; another is that the end point is a network, one end of the network is suspended or grounded, and this is a topology end point, and this end point is also an end point connected with other modules, so that a status flag is added at each such end point, and the format is: network name + DEVICE name (i.e., DEVICE) + pin number, and extracts all state labels for external connections into a list.
As a further introduction to the corresponding embodiment of fig. 2, the operation of generating the total tree diagram in S203 may include the following processes: adding a state mark for a topological end point in the first tree diagram and the second tree diagram; the state mark comprises a network name, a device name and a pin number; merging the topological end points with the same state labels in the first tree diagram and the second tree diagram into the same node so as to connect the first tree diagram and the second tree diagram to obtain a total tree diagram taking the IC chip as a root node.
Then, the expanded module topology is placed at a mark point matched in the IC module as the topology extension of the IC module, and so on, all the dispersed modules in the circuit are expanded and hung under the IC module, the modules can be expanded and hung at an external network of the IC module under the normal condition that the modules exist, if the external network of the module is not matched with the external network of the IC module, the module is compared with the external network of the expanded module, if the matching is successful, the module is hung under the module, and if all the expanded modules are not matched successfully, the module is placed in a temporary list firstly, and the other modules are generated and then are matched.
If the embodiments corresponding to fig. 1 and fig. 2 are combined, the process of determining the difference information in S103 includes: determining a target tree diagram corresponding to the alternative CBB circuit in the total tree diagram; and comparing the network and the device in the alternative CBB circuit with the target tree diagram to obtain difference information.
Specifically, comparing the network and the device in the alternative CBB circuit with the target tree diagram to obtain difference information includes:
step A1: determining a current hierarchy element in the alternative CBB circuit;
step A2: judging whether the current level element is the same as the same level element in the target tree diagram; if yes, go to step A4; if not, go to step A3;
step A3: generating difference information corresponding to the current level element;
step A4: and setting the next hierarchy as a new current hierarchy element, and entering an operation flow corresponding to the step A2.
In the above embodiment, the process of comparing the tree graphs step by step is described, and after the elements of the current hierarchy are the same, whether the elements of the next hierarchy are the same is judged; if the elements of the current hierarchy are detected to be different, corresponding difference information can be directly generated. The embodiment matches all the extracted candidate CBB circuits which meet the conditions in the standard CBB model library. The specific process is as follows: and circulating all CBB circuits meeting the conditions, circulating the IC pins in each CBB, selecting any IC pin in the CBB to perform traversal matching with the tree diagram generated in the design module circuit, and recording the number of layers of the CBB module and the number of layers of the CBB module in the tree diagram when the matching is successful, wherein the two numbers are required to be matched, namely the information of the integral comparison is on the same position of the two modules. For example, if a location in the CBB circuit is at a level of 3, then the number graph traversed in the module is also all branches of the third level. When a certain layer is compared, the algorithm is that if the current layer number is the same, information is matched with the layer, the information continues to advance to the lower layer successfully, the advance mark is recorded as the success of matching, if the matching is unsuccessful, the position is increased and marked as the failure of matching, and the advancing direction is upward return and is compared with other information of the layer and marked. If the matching cannot be determined, when the network is compared, the network does not have the name label of the network, and the UIDs of the networks are randomly generated, so the UIDs of the networks are possibly different, at this time, the state of the position needs to be recorded as pending, the next layer of matching is continued, if the matching is successful, the pending mark of the position is changed into the matching success, otherwise, the matching is failed, and until all information is compared.
Because the elements to be compared in the circuit schematic diagram comprise networks and devices, the elements to be compared at each time are divided into two types, namely networks and devices, if the elements to be compared are the networks, and the elements to be compared are also the networks, the names of the networks, namely the names of the networks, are distinguished, if the elements to be compared are the networks, the step is marked to be undetermined, and the downward comparison is continued to determine the correctness of the network path. If the names of the networks are all available, or one of the names of the networks is available, and the other of the names of the networks is not available, the path is terminated when the matching values are different, all the information on the path behind the position is extracted into a corresponding array, and the array is added to the information difference list.
Specifically, if the current level element is a network, the determining whether the current level element is the same as the same level element in the target tree diagram includes the following steps: judging whether the current level element and the same level element in the target tree diagram are distributed with non-default network names or not; the network names comprise default network names and non-default network names, and the default network names are network names automatically allocated to the elements by the system; if the current level element and/or the same level element in the target tree diagram is/are distributed with a non-default network name, judging whether the network name of the current level element is the same as the network name of the same level element in the target tree diagram; if the current hierarchical element is the same as the current hierarchical element, marking the state of the current hierarchical element as successful matching; if not, marking the state of the current level element as matching failure; if the current level element and the same level element in the target tree graph are not distributed with non-default network names, marking the state of the current level element as pending; if the states of all elements under the elements marked as undetermined are marked as matching success, modifying the state of the elements marked as undetermined into matching success; if the state of any element under the element marked as undetermined is marked as matching failure, modifying the state of the element marked as undetermined into matching failure; adding an element of which the state is marked as matching failure to an information difference list; wherein the difference information includes information in the information difference list.
If the comparison element and the compared element are devices, comparing whether the material codes of the two devices are the same, and if so, continuously traversing the connectivity of the pins on the devices and the corresponding pins of the compared devices. If the material codes are different and the package names are the same, recording the device information into an array independent record as a different list of device attribute information. If the packaging names are different, whether the number of the pins and the serial numbers of the pins are the same or not is continuously matched, and if the packaging names are different, the position device information and all elements on the following paths of the two modules are respectively put into arrays to be used as device and following information difference lists. If the pins are the same, the device is put into a device attribute information different list, whether the information behind the corresponding pin of the matching device is the same or not is continuously matched, finally, the difference points of the two modules are all found and put into the corresponding array, and finally, the matching degree check and the record of all matched CBB circuits and the designed module circuits are respectively carried out according to the method.
Specifically, if the current level element is a device, the determining whether the current level element is the same as the same level element in the target dendrogram includes the following steps: judging whether the material codes of the current level elements are the same as the material codes of the same level elements in the target tree diagram or not; if the material codes are the same, judging that the current level elements are the same as the same level elements in the target tree diagram; if the material codes are different, judging whether the packaging name of the current level element is the same as the packaging name of the same level element in the target dendrogram or not; if the packaging names are the same, adding the current level element to a device attribute difference list; if the packaging names are different, judging whether the pin parameters of the current level elements are the same as the administrative parameters of the same level elements in the target tree diagram; the pin parameters comprise pin numbers and pin serial numbers; if the pin parameters are the same, adding the current level element to the device attribute difference list; if the pin parameters are different, adding the current level element and other elements under the current level element into an information difference list; wherein the difference information includes information in the device attribute difference list and/or the information difference list. By the method, the circuit schematic diagram can be quickly matched with the alternative CBB circuit in the standard CBB model library, so that the problems existing in the design of the circuit schematic diagram can be found, and the design correctness of the circuit schematic diagram is ensured.
The flow described in the above embodiment is explained below by an embodiment in practical use. Referring to fig. 4, fig. 4 is a schematic diagram illustrating an automatic CBB matching principle in practical applications according to an embodiment of the present disclosure.
In the process of designing the circuit schematic diagram, the CBB circuit corresponding to the IC chip may be queried. Because a plurality of circuit modules can exist in the circuit schematic diagram, after the circuit module selected by a user is detected, whether the circuit module selected by the user is an IC device or not can be judged, and if the selected CBB circuit is the IC device, the standard CBB model library is inquired according to IC information (namely material codes). After all the CBB circuits meeting the requirements are extracted from the standard CBB model library, all the CBB circuits extracted from the standard CBB model library can be opened in the circuit schematic diagram so as to select the CBB circuits meeting the design requirements for use and delete the redundant CBB circuits.
In the process of matching the circuit schematic diagram, information of a design module in the circuit schematic diagram can be extracted firstly, and a CBB circuit in a standard CBB model base can be inquired based on material coding of an IC chip. Copying the CBB circuits extracted from the standard CBB model library into a circuit schematic diagram, respectively extracting relevant information of each CBB circuit, carrying out information matching on the relevant information and modules in the circuit schematic diagram to obtain difference points and matching degrees of corresponding CBB circuits in the circuit schematic diagram and the standard CBB model library, and further outputting a difference comparison result.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a matching device of a circuit schematic diagram according to an embodiment of the present disclosure;
the apparatus may include:
a CBB circuit query module 100, configured to determine an IC chip, and query a standard CBB model library for a candidate CBB circuit corresponding to the IC chip;
a connection information determining module 200, configured to obtain a schematic circuit diagram of a circuit where the IC chip is located, and determine pin connection information of the IC chip according to the schematic circuit diagram;
a circuit determining module 300, configured to determine, according to a circuit connection relationship in a circuit schematic diagram, a target circuit in the circuit schematic diagram corresponding to the candidate CBB circuit;
a difference determining module 400, configured to determine difference information between the candidate CBB circuit and the target circuit according to the pin connection information.
In this embodiment, the candidate CBB circuit corresponding to the IC chip is searched in the CBB model library, and the candidate CBB circuit is a CBB circuit pre-stored in the standard CBB model library, so as to compare with the CBB circuit in the circuit schematic diagram of the circuit where the IC chip is located. In this embodiment, pin connection information of the IC chip is determined according to a circuit schematic diagram of a circuit in which the IC chip is located, if the candidate CBB circuit is applied to the circuit schematic diagram, a certain circuit connection relationship exists between the candidate CBB circuit and the IC chip, the embodiment determines a target circuit in the circuit schematic diagram corresponding to the candidate CBB circuit according to an actual circuit connection relationship in the circuit schematic diagram, further determines difference information between the candidate CBB circuit and the target circuit based on the pin connection information, uses the difference information as a difference between a circuit actually used in the circuit schematic diagram and a CBB circuit pre-stored in a standard CBB model library, and a circuit designer can check the correctness of the circuit schematic diagram according to the difference information. The embodiment can determine the difference between the actually designed circuit and the common circuit module, and is convenient for circuit designers to carry out correctness verification on the circuit.
Further, the connection information determining module 200 includes:
the first tree diagram generating unit is used for generating a first tree diagram by traversing the connection condition of pins in the IC chip; the first tree diagram comprises a network name, a device bit number, a material code of the device and a packaging name;
the second tree diagram generating unit is used for generating a second tree diagram by traversing the connection condition of pins in other circuit modules; wherein the other circuit modules include a circuit module not connected to the IC chip in the schematic circuit diagram; the second tree diagram comprises a network name, a device bit number, a material code of the device and a packaging name;
and the total tree-like graph generating unit is used for obtaining a total tree-like graph taking the IC chip as a root node according to all the first tree-like graphs and all the second tree-like graphs, and taking the total tree-like graph as pin connection information of the IC chip.
Further, the total tree-like graph generating unit is configured to add a status flag to a topology end point in the first tree-like graph and the second tree-like graph; the state mark comprises a network name, a device name and a pin number; and merging the topological end points with the same state labels in the first tree diagram and the second tree diagram into the same node so as to connect the first tree diagram and the second tree diagram to obtain a total tree diagram taking the IC chip as a root node.
Further, the difference determining module 400 includes:
the target tree-shaped graph determining unit is used for determining a target tree-shaped graph corresponding to a target circuit in the total tree-shaped graph;
and the difference comparison unit is used for comparing the network and the device in the alternative CBB circuit with the target tree diagram to obtain difference information.
Further, the difference comparing unit includes:
a hierarchy determination subunit for determining a current hierarchy element in the alternative CBB circuit;
a judging subunit, configured to judge whether a current hierarchical element is the same as an element of the same hierarchy in the target dendrogram; if not, generating difference information corresponding to the current level element; and if the current hierarchy element is the same as the current hierarchy element, setting the next hierarchy as a new current hierarchy element, and starting a workflow corresponding to the hierarchy determining subunit.
Further, if the current level element is a network, the determining subunit is configured to determine whether the current level element and the same level element in the target dendrogram are assigned a non-default network name; the network names comprise default network names and non-default network names, and the default network names are network names automatically allocated to the elements by the system; the network name judging module is used for judging whether the network name of the current level element is the same as the network name of the same level element in the target tree diagram or not if the current level element and/or the same level element in the target tree diagram is distributed with a non-default network name; if the current hierarchical element is the same as the current hierarchical element, marking the state of the current hierarchical element as successful matching; if not, marking the state of the current level element as matching failure; means for marking the state of the current hierarchical element pending if neither the current hierarchical element nor the same hierarchical element in the target tree is assigned a non-default network name; if the states of all the elements marked as the elements to be determined are marked as matching success, modifying the state of the elements marked as the elements to be determined into matching success; if the state of any element under the element marked as pending is marked as matching failure, modifying the state of the element marked as pending into matching failure; adding an element for marking the state as matching failure to the information difference list; wherein the difference information includes information in the information difference list.
Further, if the current level element is a device, the judging subunit is used for judging whether the material code of the current level element is the same as the material code of the same level element in the target tree diagram; if the material codes are the same, judging that the current level elements are the same as the same level elements in the target tree diagram; if the material codes are different, judging whether the packaging name of the current level element is the same as the packaging name of the same level element in the target dendrogram or not; the device attribute difference list is used for adding the current level element to the device attribute difference list if the packaging names are the same; if the packaging names are different, judging whether the pin parameter of the current level element is the same as the instructive parameter of the same level element in the target tree diagram; the pin parameters comprise the number of pins and the serial number of the pins; the device attribute difference list is used for adding the current level element to the device attribute difference list if the pin parameters are the same; the method comprises the steps of adding a current level element and other elements under the current level element to an information difference list if pin parameters are different; wherein the difference information includes information in the device attribute difference list and/or the information difference list.
Further, the method also comprises the following steps:
the difference information processing module is used for determining the matching degree of the alternative CBB circuit and the circuit schematic diagram and the elements with differences in the alternative CBB circuit and the circuit schematic diagram according to the difference information after determining the difference information of the alternative CBB circuit and the corresponding module in the circuit schematic diagram according to the pin connection information;
and the difference marking module is used for displaying the alternative CBB circuit to a circuit schematic diagram editing interface, displaying the matching degree in the circuit schematic diagram editing interface and improving the display brightness of the elements with the difference.
Since the embodiments of the apparatus portion and the method portion correspond to each other, please refer to the description of the embodiments of the method portion for the embodiments of the apparatus portion, which is not repeated here.
The present application also provides a storage medium having a computer program stored thereon, which when executed, may implement the steps provided by the above-described embodiments. The storage medium may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The application further provides an electronic device, which may include a memory and a processor, where the memory stores a computer program, and the processor may implement the steps provided by the foregoing embodiments when calling the computer program in the memory. Of course, the electronic device may also include various network interfaces, power supplies, and the like.
The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (11)
1. A method for matching a schematic diagram of a circuit, comprising:
determining an IC chip, and inquiring an alternative CBB circuit corresponding to the IC chip in a standard CBB model library;
obtaining a circuit schematic diagram of a circuit where the IC chip is located, and determining pin connection information of the IC chip according to the circuit schematic diagram;
determining a target circuit corresponding to the alternative CBB circuit in the circuit schematic diagram according to the circuit connection relation in the circuit schematic diagram;
and determining the difference information of the alternative CBB circuit and the target circuit according to the pin connection information.
2. The method for matching circuit schematics of claim 1, wherein determining pin connection information of the IC chip according to the circuit schematic comprises:
generating a first tree diagram by traversing the connection condition of pins in the IC chip; the first tree diagram comprises a network name, a device bit number, a material code of the device and a packaging name;
generating a second tree graph by traversing the connection condition of pins in other circuit modules; wherein the other circuit modules include circuit modules not connected to the IC chip in the schematic circuit diagram; the second tree diagram comprises a network name, a device bit number, a material code of the device and a packaging name;
and obtaining a total tree diagram taking the IC chip as a root node according to all the first tree diagrams and all the second tree diagrams, and taking the total tree diagram as pin connection information of the IC chip.
3. The method for matching circuit schematics according to claim 2, wherein said generating a total dendrogram having said IC chip as a root node according to all of said first dendrograms and all of said second dendrograms comprises:
adding a state mark for a topological terminal point in the first tree diagram and the second tree diagram; the state mark comprises a network name, a device name and a pin number;
merging the topological end points with the same state labels in the first tree diagram and the second tree diagram into the same node so as to connect the first tree diagram and the second tree diagram to obtain a total tree diagram taking the IC chip as a root node.
4. The method of matching a circuit schematic of claim 2, wherein determining difference information between the candidate CBB circuit and the target circuit based on the pin connection information comprises:
determining a target tree diagram corresponding to the target circuit in the total tree diagram;
and comparing the network and the device in the alternative CBB circuit with the target dendrogram to obtain difference information.
5. The method for matching circuit schematics of claim 4, wherein comparing networks and devices in the alternative CBB circuit with the target dendrogram to obtain difference information comprises:
determining a current hierarchy element in the alternative CBB circuit;
judging whether the current level element is the same as the same level element in the target tree diagram;
if not, generating difference information corresponding to the current level element;
if the current hierarchy element is the same as the current hierarchy element, setting the next hierarchy as a new current hierarchy element, and executing the operation of judging whether the current hierarchy element is the same as the element of the same hierarchy in the target tree diagram.
6. The method as claimed in claim 5, wherein if the current level element is a net, said determining whether the current level element is the same as the same level element in the target tree, comprises:
judging whether the current level element and the same level element in the target tree diagram are distributed with non-default network names or not; the network names comprise default network names and non-default network names, and the default network names are network names automatically allocated to the elements by the system;
if the current level element and/or the same level element in the target tree diagram is/are distributed with a non-default network name, judging whether the network name of the current level element is the same as the network name of the same level element in the target tree diagram; if the current hierarchical element is the same as the current hierarchical element, marking the state of the current hierarchical element as successful matching; if not, marking the state of the current level element as matching failure;
if the current level element and the same level element in the target tree graph are not distributed with non-default network names, marking the state of the current level element as pending;
if the states of all elements under the elements marked as undetermined are marked as matching success, modifying the state of the elements marked as undetermined into matching success;
if the state of any element under the element marked as undetermined is marked as matching failure, modifying the state of the element marked as undetermined into matching failure;
adding an element of which the state is marked as matching failure to an information difference list; wherein the difference information includes information in the information difference list.
7. The method of claim 5, wherein if the current level element is a device, said determining whether the current level element is the same as the same level element in the target tree, comprises:
judging whether the material codes of the current level elements are the same as the material codes of the same level elements in the target tree diagram or not;
if the material codes are the same, judging that the current level elements are the same as the same level elements in the target tree diagram;
if the material codes are different, judging whether the packaging name of the current level element is the same as the packaging name of the same level element in the target tree diagram;
if the packaging names are the same, adding the current level element to a device attribute difference list;
if the packaging names are different, judging whether the pin parameters of the current level elements are the same as the administrative parameters of the same level elements in the target tree diagram; the pin parameters comprise pin numbers and pin serial numbers;
if the pin parameters are the same, adding the current level element to the device attribute difference list;
if the pin parameters are different, adding the current level element and other elements under the current level element into an information difference list; wherein the difference information comprises information in the device attribute difference list and/or the information difference list.
8. The method for matching a circuit schematic of any of claims 1 to 7, wherein after determining the difference information between the candidate CBB circuit and the target circuit according to the pin connection information, the method further comprises:
determining the matching degree of the alternative CBB circuit and the circuit schematic diagram and elements with differences in the alternative CBB circuit and the circuit schematic diagram according to the difference information;
and displaying the alternative CBB circuit to a circuit schematic diagram editing interface, and displaying the matching degree and improving the display brightness of the elements with the difference in the circuit schematic diagram editing interface.
9. An apparatus for matching circuit schematics, comprising:
the CBB circuit query module is used for determining the IC chip and querying an alternative CBB circuit corresponding to the IC chip in a standard CBB model library;
the connection information determining module is used for acquiring a circuit schematic diagram of a circuit where the IC chip is located and determining pin connection information of the IC chip according to the circuit schematic diagram;
the circuit determining module is used for determining a target circuit corresponding to the alternative CBB circuit in the circuit schematic diagram according to the circuit connection relation in the circuit schematic diagram;
and the difference determining module is used for determining the difference information between the candidate CBB circuit and the target circuit according to the pin connection information.
10. An electronic device, characterized in that it comprises a memory in which a computer program is stored and a processor which, when it calls the computer program in the memory, implements the steps of the matching method of the schematic circuit diagram according to any of claims 1 to 8.
11. A storage medium having stored thereon computer-executable instructions which, when loaded and executed by a processor, carry out the steps of a method of matching circuit schematics as claimed in any one of the preceding claims 1 to 8.
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