CN114520927A - Video processing method, device and equipment and display system - Google Patents
Video processing method, device and equipment and display system Download PDFInfo
- Publication number
- CN114520927A CN114520927A CN202011297939.0A CN202011297939A CN114520927A CN 114520927 A CN114520927 A CN 114520927A CN 202011297939 A CN202011297939 A CN 202011297939A CN 114520927 A CN114520927 A CN 114520927A
- Authority
- CN
- China
- Prior art keywords
- field
- count value
- synchronization
- signal
- sync
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000003672 processing method Methods 0.000 title claims abstract description 31
- 230000001360 synchronised effect Effects 0.000 claims abstract description 10
- 230000000630 rising effect Effects 0.000 claims description 42
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 230000015654 memory Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000007493 shaping process Methods 0.000 description 6
- 238000004590 computer program Methods 0.000 description 4
- 238000004364 calculation method Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 101000885321 Homo sapiens Serine/threonine-protein kinase DCLK1 Proteins 0.000 description 2
- 102100039758 Serine/threonine-protein kinase DCLK1 Human genes 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003750 conditioning effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
- H04N21/4307—Synchronising the rendering of multiple content streams or additional data on devices, e.g. synchronisation of audio on a mobile phone with the video output on the TV screen
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
- H04N21/4342—Demultiplexing isochronously with video sync, e.g. according to bit-parallel or bit-serial interface formats, as SDI
Abstract
The embodiment of the invention discloses a video processing method, a video processing device, video processing equipment and a display system. The video processing method includes, for example: acquiring a DP format video source decoded by software and a DP format video source decoded by hardware; generating a field synchronization adjusting parameter based on a first line synchronization signal, a first field synchronization signal and a first enabling signal in the DP format video source after software decoding; and adjusting the first field synchronizing signal based on the field synchronizing adjusting parameter to obtain a target field synchronizing signal, wherein the target field synchronizing signal is the same as a second field synchronizing signal in the DP format video source after the hardware decoding. The invention can realize the synchronous display of the DP format video source decoded by hardware and the DP format video source decoded by software.
Description
Technical Field
The embodiment of the invention relates to the technical field of video processing, in particular to a video processing method, a video processing device, video processing equipment and a display system.
Background
At present, when a video processing device performs mosaic display on a plurality of DP format video sources, if decoding schemes of the plurality of DP format video sources are different, for example, software decoding and hardware decoding are respectively performed, a situation that the plurality of DP format video sources cannot be synchronously displayed occurs. For example, as shown in fig. 1, Video1 and Video2 are two synchronized DP format Video sources with identical Video timing. The video processing device receives two DP format video sources through two different input interfaces, wherein one interface is DP1.2, the input DP format video source needs to be subjected to software decoding through a DP soft core, the other interface is DP1.1, and the input DP format video source needs to be subjected to hardware decoding through a hardware chip, such as an IT6506E chip. However, after the DP soft core performs software decoding, the time sequence of a field synchronization signal (VS) of an original video is destroyed, and the VS of the video after hardware decoding by the hardware chip is consistent with the original video, which results in that the VS signals obtained after two DP format video sources pass through different decoding schemes are not aligned any more and the time sequence difference is large, so that when the FPGA applies the VS signals after two DP format video decoding to perform video synchronization processing on the two videos, the time sequence difference of the two VS signals is large, which causes the two processed videos to be displayed asynchronously, thereby seriously affecting the display effect.
Disclosure of Invention
Therefore, to overcome the aforementioned drawbacks and deficiencies in the related art, embodiments of the present invention disclose a video processing method, a video processing apparatus, a video processing device, a display system, and a computer-readable storage medium, which can implement synchronous display of a hardware-decoded DP format video source and a software-decoded DP format video source and ensure display effect.
In a first aspect, an embodiment of the present invention discloses a video processing method, including: acquiring a DP format video source decoded by software and a DP format video source decoded by hardware; generating a field synchronization adjusting parameter based on a first line synchronization signal, a first field synchronization signal and a first enabling signal in the DP format video source after software decoding; and adjusting the first field synchronizing signal based on the field synchronizing adjusting parameter to obtain a target field synchronizing signal, wherein the target field synchronizing signal is the same as a second field synchronizing signal in the DP format video source after the hardware decoding.
The above field synchronization adjustment parameter is generated based on the first line synchronization signal, the first field synchronization signal and the first enable signal in the DP format video source after software decoding, so as to adjust the first field synchronization signal based on the field synchronization adjustment parameter to obtain the target field synchronization signal, which is the same as the second field synchronization signal in the DP format video source after hardware decoding, that is, the present embodiment adjusts the field synchronization signal in the DP format video source after software decoding to be the same as the field synchronization signal in the DP format video source after hardware decoding, so as to avoid the disadvantages that the field synchronization signals obtained after decoding the DP format video source by using the software decoding scheme and the hardware decoding scheme in the prior art are not aligned any more and the timing difference is large, and realize real-time dynamic adjustment of the field synchronization signal in the DP format video source after software decoding, the DP format video source after hardware decoding and the DP format video source after software decoding are synchronously displayed, and the display effect is ensured.
In an embodiment of the present invention, the generating a field sync adjustment parameter based on a first line sync signal, a first field sync signal and a first enable signal in the DP format video source after software decoding includes: obtaining line synchronization information, field synchronization information, and enable information based on the first line synchronization signal, the first field synchronization signal, and the first enable signal; generating the field sync adjustment parameter based on the line sync information, the field sync information, and the enable information.
The corresponding line synchronization information, field synchronization information and enable information are obtained based on the line synchronization signal, the field synchronization signal and the enable signal in the DP format video source decoded by the software, so that the field synchronization adjustment parameter is generated based on the line synchronization information, the field synchronization information and the enable information, real-time dynamic adjustment of the field synchronization signal, namely the first field synchronization signal, in the DP format video source decoded by the software can be realized, and the splicing display synchronism of the DP format video source decoded by the software and the DP format video source decoded by the hardware is ensured.
In one embodiment of the present invention, the line synchronization information includes: a line synchronization period count value, the field synchronization information including: a field sync period count value and a field sync valid count value, the enable information including: a field synchronization enable count value and a line synchronization enable count value; the generating the field synchronization adjustment parameter based on the line synchronization information, the field synchronization information, and the enable information includes: generating a field sync falling edge count value based on the line sync period count value, the line sync enable count value, and the field sync period count value and the field sync enable count value; and generating a field synchronization rising edge count value based on the field synchronization falling edge count value, the field synchronization effective count value and the line synchronization period count value, wherein the field synchronization falling edge count value and the field synchronization rising edge count value form the field synchronization adjusting parameter.
The field synchronization adjustment parameters are obtained by generating the field synchronization falling edge count value and the field synchronization rising edge count value, so that the adjustment accuracy of the field synchronization signals in the DP format video source after software decoding is ensured.
In an embodiment of the present invention, the generating a field synchronization falling edge count value based on the line synchronization period count value, the line synchronization enable count value, and the field synchronization period count value and the field synchronization enable count value includes: subtracting the field synchronization period count value and the field synchronization enabling count value to obtain a first operation result; multiplying the first operation result and the line synchronization period count value to obtain a second operation result; performing subtraction on the line synchronization period count value and the line synchronization enable count value to obtain a third operation result; and adding the second operation result and the third operation result to obtain the field synchronization falling edge count value.
In an embodiment of the present invention, the generating a field synchronization rising edge count value based on the field synchronization falling edge count value, the field synchronization valid count value, and the line synchronization period count value includes: multiplying the field synchronization effective count value and the line synchronization period count value to obtain a fourth operation result; and adding the fourth operation result and the field synchronization falling edge count value to obtain the field synchronization rising edge count value.
In an embodiment of the present invention, the adjusting the first field sync signal based on the field sync adjustment parameter to obtain a target field sync signal includes: and starting to count the input clock signals by taking the falling edge of the last first enable signal of each frame as a reference starting point until the first count value is the same as the field synchronization falling edge count value to generate the falling edge of the target field synchronization signal, and until the second count value is the same as the field synchronization rising edge count value to generate the rising edge of the target field synchronization signal, thereby obtaining the target field synchronization signal.
The method starts to count the input clock signal by taking the falling edge of the last first enable signal of each frame as a reference starting point until the first count value is the same as the field synchronization falling edge count value to generate the falling edge of the target field synchronization signal and until the second count value is the same as the field synchronization rising edge count value to generate the rising edge of the target field synchronization signal, thereby generating the target field synchronization signal, ensuring the consistency of the target field synchronization signal and the field synchronization signal in the DP format video after hardware decoding, and realizing the splicing display synchronization of the DP format video source after software decoding and the DP format video source after hardware decoding.
In an embodiment of the present invention, after the adjusting the first field sync signal based on the field sync adjustment parameter to obtain a target field sync signal, the method further includes: and performing video processing on the DP format video source decoded by the software based on the target field synchronizing signal, performing video processing on the DP format video source decoded by the hardware based on the second field synchronizing signal, and outputting synchronous display.
The DP-format video source after software decoding and the DP-format video source after hardware decoding are respectively subjected to video processing and then output synchronous display based on the target field synchronizing signal and the second field synchronizing signal, so that the splicing display synchronism of the DP-format video source after software decoding and the DP-format video source after hardware decoding is ensured.
In a second aspect, an embodiment of the present invention discloses a video processing apparatus, configured to perform any one of the foregoing video processing methods, where the video processing apparatus includes: the video acquisition module is used for acquiring the DP format video source after software decoding and the DP format video source after hardware decoding; the parameter generating module is used for generating a field synchronization adjusting parameter based on a first line synchronizing signal, a first field synchronizing signal and a first enabling signal in the DP format video source after software decoding; and the signal adjusting module is used for adjusting the first field synchronizing signal based on the field synchronizing adjusting parameter to obtain a target field synchronizing signal, wherein the target field synchronizing signal is the same as a second field synchronizing signal in the DP format video source after the hardware decoding.
In a third aspect, a video processing apparatus disclosed in an embodiment of the present invention includes: a microprocessor; the programmable logic device is connected with the microprocessor; wherein the microprocessor and the programmable logic device cooperate to implement any of the video processing methods described above.
In a fourth aspect, a display system disclosed in an embodiment of the present invention includes: a video processing device, wherein the video processing device is configured to perform any one of the video processing methods; and the target display screen is connected with the video processing equipment and is used for synchronously displaying the DP format video source after the software decoding and the DP format video source after the hardware decoding.
In a fifth aspect, a computer-readable storage medium is disclosed in the embodiments of the present invention, in which a computer program is stored, and the stored computer program, when executed by a processor, can implement any one of the video processing methods described above.
One or more of the above technical solutions may have the following advantages or beneficial effects: by adjusting the field synchronizing signal in the DP format video source after software decoding to be the same as the field synchronizing signal in the DP format video source after hardware decoding, the defects that the field synchronizing signals obtained after the DP format video source is decoded respectively by using a software decoding scheme and a hardware decoding scheme in the prior art are not aligned any more and the time sequence difference is large can be avoided, real-time dynamic adjustment of the field synchronizing signal in the DP format video source after software decoding can be realized, synchronous display of the DP format video source after hardware decoding and the DP format video source after software decoding is realized, and the display effect is ensured.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow diagram illustrating a video processing apparatus receiving a DP format video source according to the related art.
Fig. 2 is a flowchart illustrating a video processing method according to an embodiment of the present invention.
Fig. 3 is a flowchart illustrating step S13 in the video processing method shown in fig. 2.
Fig. 4 is a schematic structural diagram of a display system according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a video processing device according to an embodiment of the present invention.
Fig. 6 is a signal diagram of field sync signals and enable signals corresponding to a DP format video source after software decoding and a DP format video source after hardware decoding according to a specific implementation of a video processing method disclosed in an embodiment of the present invention.
Fig. 7 is a signal diagram illustrating a first field sync signal, a first line sync signal and a first enable signal of a DP format video source after software decoding according to an embodiment of the present invention.
Fig. 8 is a schematic structural diagram of a video processing apparatus according to an embodiment of the present invention.
Fig. 9 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 2, a video processing method according to an embodiment of the present invention includes steps S11 to S15.
S11: acquiring a DP format video source decoded by software and a DP format video source decoded by hardware;
s13: generating a field synchronization adjusting parameter based on a first line synchronization signal, a first field synchronization signal and a first enabling signal in the DP format video source after software decoding;
s15: and adjusting the first field synchronizing signal based on the field synchronizing adjusting parameter to obtain a target field synchronizing signal, wherein the target field synchronizing signal is the same as a second field synchronizing signal in the DP format video source after the hardware decoding.
The DP format video source after software decoding mentioned in step S11 may be understood as a DP format video source after software decoding obtained by decoding the DP format video source through a DP software core, and the DP format video source after hardware decoding mentioned may be understood as a DP format video source after hardware decoding obtained by decoding the DP format video source through a DP video source hardware decoding chip, where the DP video source hardware decoding chip is, for example, an IT6506E chip.
The first line synchronization signal, i.e., the HS signal, the first field synchronization signal, i.e., the VS signal, and the first enable signal, i.e., the DE signal, mentioned in step S13, the field synchronization adjustment parameters include, for example: a field sync rising edge count value and a field sync falling edge count value.
The adjustment of the first field sync signal mentioned in step S15 can also be understood as performing VS shaping on the first field sync signal, and the reference of the target field sync signal being the same as the second field sync signal can be understood as being completely aligned with the rising edge and the falling edge and having the same timing.
The above field synchronization adjustment parameter is generated based on the first line synchronization signal, the first field synchronization signal and the first enable signal in the DP format video source after software decoding, so as to adjust the first field synchronization signal based on the field synchronization adjustment parameter to obtain the target field synchronization signal, which is the same as the second field synchronization signal in the DP format video source after hardware decoding, that is, the present embodiment adjusts the field synchronization signal in the DP format video source after software decoding to be the same as the field synchronization signal in the DP format video source after hardware decoding, so as to avoid the disadvantages that the field synchronization signals obtained after decoding the DP format video source by using the software decoding scheme and the hardware decoding scheme in the prior art are not aligned any more and the timing difference is large, and realize real-time dynamic adjustment of the field synchronization signal in the DP format video source after software decoding, the DP format video source after hardware decoding and the DP format video source after software decoding are synchronously displayed, and the display effect is ensured.
Further, as shown in fig. 3, step S13 includes, for example, step S131 and step S132.
Step S131: obtaining line synchronization information, field synchronization information, and enable information based on the first line synchronization signal, the first field synchronization signal, and the first enable signal;
step S132: generating the field sync adjustment parameter based on the line sync information, the field sync information, and the enable information.
The line synchronization information mentioned in step S131 includes, for example: line sync period count values, and the mentioned field sync information includes, for example: a field sync period count value and a field sync valid count value, and the mentioned enable information includes, for example: the field sync enable count value and the line sync enable count value.
The corresponding line synchronization information, field synchronization information and enabling information are obtained based on the line synchronization signal, the field synchronization signal and the enabling signal in the DP format video source after software decoding, so that the field synchronization adjusting parameter is generated based on the line synchronization information, the field synchronization information and the enabling information, real-time dynamic adjustment of the field synchronization signal, namely the first field synchronization signal, in the DP format video source after software decoding can be realized, and the splicing display synchronism of the DP format video source after software decoding and the DP format video source after hardware decoding is ensured.
Further, the aforementioned step S132 includes, for example:
generating a field synchronization falling edge count value based on the line synchronization period count value, the line synchronization enable count value, and the field synchronization period count value and the field synchronization enable count value; and
and generating a field synchronization rising edge count value based on the field synchronization falling edge count value, the field synchronization effective count value and the line synchronization period count value, wherein the field synchronization falling edge count value and the field synchronization rising edge count value form the field synchronization adjusting parameter.
The field synchronization adjustment parameters are obtained by generating the field synchronization falling edge count value and the field synchronization rising edge count value, so that the adjustment accuracy of the field synchronization signals in the DP format video source after software decoding is ensured.
Further, the aforementioned generating a field sync falling edge count value based on the line sync period count value, the line sync enable count value, and the field sync period count value and the field sync enable count value includes, for example:
subtracting the field synchronization period count value and the field synchronization enabling count value to obtain a first operation result;
multiplying the first operation result and the line synchronization period count value to obtain a second operation result;
performing subtraction operation on the line synchronization period count value and the line synchronization enabling count value to obtain a third operation result; and
and adding the second operation result and the third operation result to obtain the field synchronization falling edge count value.
That is, the calculation formula for calculating and generating the field synchronization falling edge count value based on the line synchronization period count value, the line synchronization enable count value, the field synchronization period count value, and the field synchronization enable count value is as follows: the DelayFall is H _ Total (V _ Total-V _ de) + (H _ Total-H _ de), where DelayFall is a field sync falling edge count value, H _ Total is a line sync period count value, V _ Total is a field sync period count value, V _ de is a field sync enable count value, and H _ de is a line sync enable count value.
Further, the aforementioned generating a field sync rising edge count value based on the field sync falling edge count value, the field sync valid count value, and the line sync period count value includes, for example:
multiplying the field synchronization effective count value and the line synchronization period count value to obtain a fourth operation result; and
and adding the fourth operation result and the field synchronization falling edge count value to obtain the field synchronization rising edge count value.
That is, the calculation formula for generating the field synchronization rising edge count value based on the field synchronization falling edge count value, the field synchronization valid count value, and the line synchronization period count value is as follows:
DelayRaise is V _ SyncStart H _ Total + DelayFall, where DelayRaise is a field sync rising edge count value, V _ SyncStart is a field sync valid count value, H _ Total is a line sync period count value, and DelayFall is a field sync falling edge count value.
Further, the aforementioned step S15 includes, for example: and starting to count the input clock signals by taking the falling edge of the last first enable signal of each frame as a reference starting point until the first count value is the same as the field synchronization falling edge count value to generate the falling edge of the target field synchronization signal, and until the second count value is the same as the field synchronization rising edge count value to generate the rising edge of the target field synchronization signal, thereby obtaining the target field synchronization signal.
The method starts to count the input clock signal by taking the falling edge of the last first enable signal of each frame as a reference starting point until the first count value is the same as the field synchronization falling edge count value to generate the falling edge of the target field synchronization signal and until the second count value is the same as the field synchronization signal rising edge count value to generate the rising edge of the target field synchronization signal, thereby generating the target field synchronization signal, ensuring the consistency of the field synchronization signal in the DP format video after the target field synchronization signal and the hardware decoding, and realizing the splicing display synchronization of the DP format video source after the software decoding and the DP format video source after the hardware decoding.
Further, after step S15, the video processing method disclosed in this embodiment further includes, for example: and performing video processing on the DP format video source decoded by the software based on the target field synchronizing signal, performing video processing on the DP format video source decoded by the hardware based on the second field synchronizing signal, and outputting synchronous display.
The video processing mentioned therein includes, for example, video processing operations such as layer processing.
The DP format video source after software decoding and the DP format video source after hardware decoding are respectively subjected to video processing based on the target field synchronizing signal and the second field synchronizing signal and then output and synchronously displayed, so that the synchronization of splicing display of the DP format video source after software decoding and the DP format video source after hardware decoding is ensured.
For better understanding of the present embodiment, a specific implementation of the video processing method disclosed in the present embodiment is illustrated below with reference to fig. 4 to 7.
Referring to fig. 4, the present embodiment discloses a display system 200 comprising a video processing device 100 and a target display screen 210. The video processing device 100 is, for example, configured to execute the video processing method disclosed in the foregoing, and the target display screen 210 is connected to the video processing device 100 and configured to synchronously display the DP format video source after software decoding and the DP format video source after hardware decoding.
As shown in fig. 5, the video processing apparatus 100 includes, for example: a microprocessor 110 and a programmable logic device 130 coupled to the microprocessor 110, wherein the microprocessor 110 and the programmable logic device 130 cooperate to implement the video processing method disclosed previously. The microprocessor 110 is, for example, an MCU (micro controller Unit), which is also called a Single Chip Microcomputer (Single Chip Microcomputer) or a Single Chip Microcomputer, or other microprocessors with certain data processing and computing capabilities, such as an ARM processor. The Programmable logic device 130 is, for example, an FPGA (Field-Programmable Gate Array) or other similar logic device.
In addition, the video processing apparatus 100 is further provided with a plurality of DP input interfaces connected to the programmable logic device 130, for example, for receiving the input DP format video sources, for example, the video processing apparatus 100 is provided with two DP input interfaces, for receiving two input DP format video sources, and the video timings of the two DP format video sources are completely consistent. One of the DP input interfaces is, for example, a DP1.2 interface, and the other DP input interface is, for example, a DP1.1 interface, where the DP1.1 interface needs to be connected to a DP format video source decoding chip, such as IT6506E decoding chip, for hardware decoding, and the DP1.2 interface needs to be connected to a DP soft core for software decoding, where the DP soft core is, for example, disposed inside the programmable logic device 130, and the microprocessor 110 configures the DP soft core to start working through an AXI bus, for software decoding, and in addition, a DP159 chip may be disposed between the programmable logic device and the DP1.2 interface, and before the DP soft core performs software decoding, the microprocessor 110 configures the DP159 chip through an IIC bus to recover a clock of the DP format video source to complete initialization of decoding, and then performs software decoding. Based on the foregoing steps, the programmable logic device 130 can obtain one path of DP format video source after software decoding and one path of DP format video source after hardware decoding.
The DP format video source after software decoding includes: the first RGB data signals, the first field sync signal VS1, the first row sync signal HS1, and the first enable signal DE1, and further include a first pixel clock signal DCLK 1. The hardware-decoded DP format video source includes: the second RGB data signals, the second field sync signal VS2, the second line sync signal HS2, and the second enable signal DE2, and further include a second pixel clock signal DCLK 2. Wherein the first line sync signal HS1 and the first enable signal DE1 are the same as the second line sync signal HS2 and the second enable signal DE2, respectively, wherein the timing of the first field sync signal VS1 of the DP format video source after software decoding can be destroyed, resulting in a difference from the second field sync signal VS2 of the DP format video source after hardware decoding, see fig. 6.
The programmable logic device 130 obtains field sync information, line sync information, and enable information based on the first field sync signal VS1, the first line sync signal HS1, and the first enable signal DE1, and then sends the field sync information, the line sync information, and the enable information to the microprocessor 110, and the microprocessor 110 generates field sync adjustment parameters based on the field sync information, the line sync information, and the enable information.
For example, as shown in fig. 7, the mentioned row synchronization information includes, for example: the line synchronization period count value H _ Total, and the mentioned field synchronization information includes, for example: the field sync period count value V _ Total and the field sync valid count value V _ SyncStart, and the mentioned enabling information includes, for example: a field sync enable count value V _ de end and a line sync enable count value H _ de end. The microprocessor 110 generates a field sync falling edge count value DelayFall based on the line sync period count value H _ Total, the line sync enable count value H _ de, the field sync period count value V _ Total, and the field sync enable count value V _ de _ end, and generates a field sync rising edge count value DelayRaise based on the field sync falling edge count value DelayFall, the field sync valid count value V _ SyncStart, and the line sync period count value H _ Total, wherein the field sync falling edge count value DelayFall and the field sync rising edge count value DelayRaise constitute the aforementioned field sync adjustment parameter.
Specifically, the calculation formula for the microprocessor 110 to generate the field sync falling edge count value DelayFall and the field sync rising edge count value DelayRaise is as follows:
DelayFall＝H_Total*(V_Total-V_DeEnd)+(H_Total-H_DeEnd)；
DelayRaise＝V_SyncStart*H_Total+DelayFall。
the microprocessor 110 calculates the field sync falling edge count value DelayFall and the field sync rising edge count value DelayRaise, and then issues the field sync falling edge count value DelayFall and the field sync rising edge count value DelayRaise to the programmable logic device 130, for example, through the FSMC bus. The programmable logic device 130 adjusts a first field synchronizing signal VS1 in the DP format video source after software decoding according to the field synchronization adjusting parameter to obtain a target field synchronizing signal, the target field synchronizing signal is the same as a second field synchronizing signal VS2 in the DP format video source after hardware decoding, and the programmable logic device 130 shapes the first field synchronizing signal VS1 based on the field synchronization falling edge count value DelayFall and the field synchronization rising edge count value DelayRaise to make the first field synchronizing signal VS1 be the same as the second field synchronizing signal VS 2.
Specifically, the programmable logic device 130 is provided therein with, for example, a VS shaping module connected to the DP soft core, the VS shaping module starts counting an input clock signal with a falling edge of the last first enable signal DE1 of each frame as a reference starting point, where the clock signal may be generated by an external clock or, of course, an internal clock, the VS shaping module counts the clock signal until the first count value is the same as the field sync falling edge count value DelayFall, generates a falling edge of the target field sync signal, and until the second count value is the same as the field sync rising edge count value DelayRaise, generates a rising edge of the target field sync signal, thereby obtaining the target field sync signal, and in short, the VS shaping module detects the falling edge of the last DE1 of each frame, and generates the falling edge of the target field sync signal after delaying the falling edge until the count value of DelayFall, the count value delayed to DelayRaise generates the rising edge of the target field sync signal, thereby completing the shaping of the first field sync signal VS 1.
The video processing module inside the programmable logic device 130 can perform video processing on the DP format video source decoded by the software and the DP format video source decoded by the hardware based on the target field sync signal and the second field sync signal, and then output the processed video to the target display screen 210 for synchronous display. Video processing here may be understood as layer processing or the like.
The target display screen 210 is, for example, an LED display screen, and is formed by a plurality of LED display boxes, each of which includes, for example, a receiving card and at least one LED lamp panel connected to the receiving card, where the receiving card includes, for example, a network interface, a programmable logic device electrically connected to the network interface, and a memory. The video processing apparatus 100 is connected to a receiving card of the target display screen 210, for example.
Further, as shown in fig. 8, an embodiment of the present invention discloses a video processing apparatus 300 including: a video acquisition module 310, a parameter generation module 330, and a signal conditioning module 350.
The video obtaining module 310 is configured to obtain a DP format video source after software decoding and a DP format video source after hardware decoding. The parameter generating module 330 is configured to generate a field sync adjustment parameter based on the first line sync signal, the first field sync signal and the first enable signal in the DP format video source after software decoding. The signal adjusting module 350 is configured to adjust the first field sync signal based on the field sync adjustment parameter to obtain a field sync target signal, where the field sync target signal is the same as a second field sync signal in the DP format video source after the hardware decoding.
Further, the parameter generation module 330 includes: the device comprises an information acquisition unit and a parameter generation unit, wherein the information acquisition unit is used for obtaining line synchronization information, field synchronization information and enabling information based on the first line synchronization signal, the first field synchronization signal and the first enabling signal, and the parameter generation unit is used for generating the field synchronization adjustment parameter based on the line synchronization information, the field synchronization information and the enabling information.
The line synchronization information includes, for example: line sync period count values, and the mentioned field sync information includes, for example: a field sync period count value and a field sync valid count value, and the mentioned enable information includes: the field sync enable count value and the line sync enable count value. The parameter generation unit includes, for example: the first count value generation subunit is configured to generate a field synchronization falling edge count value based on the line synchronization period count value, the line synchronization enable count value, the field synchronization period count value, and the field synchronization enable count value. The second count value generation subunit is configured to generate a field synchronization rising edge count value based on the field synchronization falling edge count value, the field synchronization valid count value, and the line synchronization period count value, where the field synchronization falling edge count value and the field synchronization rising edge count value constitute the field synchronization adjustment parameter.
Further, the first count value generation subunit is specifically configured to: subtracting the field synchronization period count value and the field synchronization enabling count value to obtain a first operation result; multiplying the first operation result and the line synchronization period count value to obtain a second operation result; performing subtraction operation on the line synchronization period count value and the line synchronization enabling count value to obtain a third operation result; and adding the second operation result and the third operation result to obtain the field synchronization falling edge count value.
Further, the second count value generation subunit is specifically configured to: multiplying the field synchronization effective count value and the line synchronization period count value to obtain a fourth operation result; and adding the fourth operation result and the field synchronization falling edge count value to obtain the field synchronization rising edge count value.
Further, the signal adjusting module 350 is specifically configured to start counting the input clock signal with a falling edge of the last first enable signal in each frame as a reference starting point, generate a falling edge of the target field synchronizing signal until the first count value is the same as the field synchronization falling edge count value, and generate a rising edge of the target field synchronizing signal until the second count value is the same as the field synchronization rising edge count value, so as to obtain the target field synchronizing signal.
Further, the video processing apparatus disclosed in this embodiment further includes: and the video processing module is used for carrying out video processing on the DP format video source after the software decoding based on the target field synchronizing signal, carrying out video processing on the DP format video source after the hardware decoding based on the second field synchronizing signal, and outputting synchronous display.
It should be noted that the video processing method implemented by the video processing apparatus 300 disclosed in the present embodiment is as described in the foregoing embodiments, and therefore, detailed description thereof is omitted here. Alternatively, each module, unit and other operations or functions described above in this embodiment are respectively for realizing the method in the foregoing embodiment.
Further, as shown in FIG. 9, one embodiment of the present invention discloses a computer-readable storage medium 400. The computer-readable storage medium 400 is, for example, a non-volatile memory, such as: magnetic media (e.g., hard disks, floppy disks, and magnetic tape), optical media (e.g., CDROM disks and DVDs), magneto-optical media (e.g., optical disks), and hardware devices specially constructed for storing and executing computer-executable instructions (e.g., Read Only Memories (ROMs), Random Access Memories (RAMs), flash memories, etc.). The computer-readable storage medium 400 has stored thereon a computer program 410. The computer-readable storage medium 400 may be executed by one or more processors or processing devices to execute the computer program 410 to implement the video processing method in the foregoing embodiments.
In summary, in the above embodiments, the field synchronization adjustment parameter is generated based on the first line synchronization signal, the first field synchronization signal and the first enable signal in the DP format video source after software decoding, so as to adjust the first field synchronization signal based on the field synchronization adjustment parameter to obtain the target field synchronization signal, which is the same as the second field synchronization signal in the DP format video source after hardware decoding, that is, by adjusting the field synchronization signal in the DP format video source after software decoding to be the same as the field synchronization signal in the DP format video source after hardware decoding, disadvantages caused by that field synchronization signals obtained after DP format video sources are decoded respectively by using a software decoding scheme and a hardware decoding scheme in the prior art are not aligned any more and timing differences are large can be avoided, and real-time dynamic adjustment of the field synchronization signal in the DP format video source after software decoding can be realized, the DP format video source after hardware decoding and the DP format video source after software decoding are synchronously displayed, and the display effect is ensured.
In addition, it should be understood that the foregoing embodiments are merely exemplary of the present invention, and the technical solutions of the embodiments may be arbitrarily combined and used without conflict and contradiction in technical features and without departing from the purpose of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, a division of a unit is merely a division of one logic function, and an actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may also be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, each functional unit/module in the embodiments of the present invention may be integrated into one processing unit/module, or each unit/module may exist alone physically, or two or more units/modules may be integrated into one unit/module. The integrated units/modules may be implemented in the form of hardware, or may be implemented in the form of hardware plus software functional units/modules.
The integrated units/modules, which are implemented in the form of software functional units/modules, may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions for causing one or more processors of a computer device (which may be a personal computer, a server, or a network device) to execute some steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A video processing method, comprising:
acquiring a DP format video source decoded by software and a DP format video source decoded by hardware;
generating a field synchronization adjusting parameter based on a first line synchronization signal, a first field synchronization signal and a first enabling signal in the DP format video source after software decoding;
and adjusting the first field synchronizing signal based on the field synchronizing adjusting parameter to obtain a target field synchronizing signal, wherein the target field synchronizing signal is the same as a second field synchronizing signal in the DP format video source after the hardware decoding.
2. The video processing method according to claim 1, wherein generating the field sync adjustment parameter based on the first line sync signal, the first field sync signal, and the first enable signal in the software decoded DP format video source comprises:
obtaining line synchronization information, field synchronization information, and enable information based on the first line synchronization signal, the first field synchronization signal, and the first enable signal;
generating the field sync adjustment parameter based on the line sync information, the field sync information, and the enable information.
3. The video processing method of claim 2, wherein the line synchronization information comprises: a line synchronization period count value, the field synchronization information including: a field sync period count value and a field sync valid count value, the enable information including: a field synchronization enable count value and a line synchronization enable count value;
the generating the field synchronization adjustment parameter based on the line synchronization information, the field synchronization information, and the enable information includes:
generating a field sync falling edge count value based on the line sync period count value, the line sync enable count value, and the field sync period count value and the field sync enable count value;
and generating a field synchronization rising edge count value based on the field synchronization falling edge count value, the field synchronization effective count value and the line synchronization period count value, wherein the field synchronization falling edge count value and the field synchronization rising edge count value form the field synchronization adjusting parameter.
4. The video processing method of claim 3, wherein generating a field sync falling edge count value based on the line sync period count value, the line sync enable count value, and the field sync period count value and the field sync enable count value comprises:
subtracting the field synchronization period count value and the field synchronization enabling count value to obtain a first operation result;
multiplying the first operation result and the line synchronization period count value to obtain a second operation result;
performing subtraction operation on the line synchronization period count value and the line synchronization enabling count value to obtain a third operation result;
and adding the second operation result and the third operation result to obtain the field synchronization falling edge count value.
5. The video processing method of claim 4, wherein generating a field sync rising edge count value based on the field sync falling edge count value, the field sync valid count value, and the line sync period count value comprises:
multiplying the field synchronization effective count value and the line synchronization period count value to obtain a fourth operation result;
and adding the fourth operation result and the field synchronization falling edge count value to obtain the field synchronization rising edge count value.
6. The video processing method according to claim 3, wherein said adjusting the first field sync signal based on the field sync adjustment parameter to obtain a target field sync signal comprises:
and starting to count the input clock signals by taking the falling edge of the last first enable signal of each frame as a reference starting point until the first count value is the same as the field synchronization falling edge count value to generate the falling edge of the target field synchronization signal, and until the second count value is the same as the field synchronization rising edge count value to generate the rising edge of the target field synchronization signal, thereby obtaining the target field synchronization signal.
7. The video processing method according to claim 1, further comprising, after said adjusting the first field sync signal based on the field sync adjustment parameter to obtain a target field sync signal:
and performing video processing on the DP format video source decoded by the software based on the target field synchronizing signal, performing video processing on the DP format video source decoded by the hardware based on the second field synchronizing signal, and outputting synchronous display.
8. A video processing apparatus for performing the video processing method of any one of claims 1 to 7, comprising:
the video acquisition module is used for acquiring the DP format video source after software decoding and the DP format video source after hardware decoding;
the parameter generating module is used for generating a field synchronization adjusting parameter based on a first line synchronizing signal, a first field synchronizing signal and a first enabling signal in the DP format video source after software decoding;
and the signal adjusting module is used for adjusting the first field synchronizing signal based on the field synchronizing adjusting parameter to obtain a target field synchronizing signal, wherein the target field synchronizing signal is the same as a second field synchronizing signal in the DP format video source after the hardware decoding.
9. A video processing apparatus, comprising:
a microprocessor;
the programmable logic device is connected with the microprocessor;
wherein the microprocessor and the programmable logic device cooperate to implement the video processing method of any of claims 1-7.
10. A display system, comprising:
a video processing device, wherein the video processing device is configured to perform the video processing method of any one of claims 1-7;
and the target display screen is connected with the video processing equipment and is used for synchronously displaying the DP format video source after the software decoding and the DP format video source after the hardware decoding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011297939.0A CN114520927B (en) | 2020-11-18 | 2020-11-18 | Video processing method, device and equipment and display system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011297939.0A CN114520927B (en) | 2020-11-18 | 2020-11-18 | Video processing method, device and equipment and display system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114520927A true CN114520927A (en) | 2022-05-20 |
| CN114520927B CN114520927B (en) | 2024-04-05 |
Family
ID=81594590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011297939.0A Active CN114520927B (en) | 2020-11-18 | 2020-11-18 | Video processing method, device and equipment and display system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114520927B (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102006426A (en) * | 2010-11-30 | 2011-04-06 | 广东威创视讯科技股份有限公司 | Synchronization method and device for splicing system |
| WO2011068494A1 (en) * | 2009-12-03 | 2011-06-09 | Thomson Licensing | Synchronization correction in a mobile dtv receiver |
| CN102361469A (en) * | 2011-06-21 | 2012-02-22 | 北京交大思诺科技有限公司 | Device and method for parallel decoding of software and hardware |
| US20130083843A1 (en) * | 2011-07-20 | 2013-04-04 | Broadcom Corporation | Adaptable media processing architectures |
| CN109120988A (en) * | 2018-08-23 | 2019-01-01 | Oppo广东移动通信有限公司 | Coding/decoding method, device, electronic equipment and storage medium |
| CN110572622A (en) * | 2019-09-30 | 2019-12-13 | 威创集团股份有限公司 | Video decoding method and device |
| CN111083311A (en) * | 2019-12-31 | 2020-04-28 | 航天图景（北京）科技有限公司 | Synchronization system and method for airborne multi-channel video and POS data of unmanned aerial vehicle |
| CN111405276A (en) * | 2020-04-26 | 2020-07-10 | 北京淳中科技股份有限公司 | Video signal synchronous detection method and device |
| CN111711842A (en) * | 2020-05-18 | 2020-09-25 | 深圳市东微智能科技股份有限公司 | Synchronous display control method, device and computer readable storage medium |
-
2020
- 2020-11-18 CN CN202011297939.0A patent/CN114520927B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011068494A1 (en) * | 2009-12-03 | 2011-06-09 | Thomson Licensing | Synchronization correction in a mobile dtv receiver |
| CN102006426A (en) * | 2010-11-30 | 2011-04-06 | 广东威创视讯科技股份有限公司 | Synchronization method and device for splicing system |
| CN102361469A (en) * | 2011-06-21 | 2012-02-22 | 北京交大思诺科技有限公司 | Device and method for parallel decoding of software and hardware |
| US20130083843A1 (en) * | 2011-07-20 | 2013-04-04 | Broadcom Corporation | Adaptable media processing architectures |
| CN109120988A (en) * | 2018-08-23 | 2019-01-01 | Oppo广东移动通信有限公司 | Coding/decoding method, device, electronic equipment and storage medium |
| CN110572622A (en) * | 2019-09-30 | 2019-12-13 | 威创集团股份有限公司 | Video decoding method and device |
| CN111083311A (en) * | 2019-12-31 | 2020-04-28 | 航天图景（北京）科技有限公司 | Synchronization system and method for airborne multi-channel video and POS data of unmanned aerial vehicle |
| CN111405276A (en) * | 2020-04-26 | 2020-07-10 | 北京淳中科技股份有限公司 | Video signal synchronous detection method and device |
| CN111711842A (en) * | 2020-05-18 | 2020-09-25 | 深圳市东微智能科技股份有限公司 | Synchronous display control method, device and computer readable storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114520927B (en) | 2024-04-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112995735B (en) | Distributed video display system, control device and control method | |
| US20180277054A1 (en) | Video frame rate compensation through adjustment of vertical blanking | |
| CN103021378B (en) | A kind of device for multi-screen mosaic display and method | |
| US10798334B2 (en) | Image processing system, image display method, display device and storage medium | |
| US20180174551A1 (en) | Sending frames using adjustable vertical blanking intervals | |
| US9607542B2 (en) | Display panel driving method, driving device and display device | |
| US9160895B2 (en) | Method and apparatus for quickly responding to signal | |
| TW201428675A (en) | Video generating system and related method thereof | |
| EP3057315A1 (en) | Digital movie projection system and method | |
| WO2023029936A1 (en) | Audio and video synchronization method and apparatus based on different reference clocks, and computer device | |
| CN110225316B (en) | Software and hardware cooperative multi-channel video processing device and system | |
| CN101383913B (en) | Display overlapping control system and control method thereof | |
| JP5998579B2 (en) | Video display apparatus, method and program for multi-display system | |
| CN112040284B (en) | Synchronous display control method and device of multiple display screens and storage medium | |
| CN114520927A (en) | Video processing method, device and equipment and display system | |
| CN105472203A (en) | Genlock system and method | |
| CN112995559B (en) | Video processing method, device and system, display controller and display control system | |
| TWI765293B (en) | Receiving device, video recording system and method for reducing video latency in video recording system | |
| TWI605717B (en) | Display control apparatus and corresponding method | |
| CN114500767A (en) | Input video source adjusting method and device, video input card and video processing equipment | |
| US20220301468A1 (en) | Control method of display apparatus, display apparatus, and computer-readable storage medium | |
| CN115842893A (en) | Picture synchronous output method, device and equipment | |
| CN115842940A (en) | Data processing method, device, equipment, system and medium for display device | |
| WO2021143717A1 (en) | Video timing conversion method and apparatus, and computer readable medium | |
| CN112752129A (en) | Video source synchronous output method, device, system and computer readable storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |