CN114520010A - DDR DFE receiving circuit structure for reducing delay unit - Google Patents
DDR DFE receiving circuit structure for reducing delay unit Download PDFInfo
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- CN114520010A CN114520010A CN202210412885.0A CN202210412885A CN114520010A CN 114520010 A CN114520010 A CN 114520010A CN 202210412885 A CN202210412885 A CN 202210412885A CN 114520010 A CN114520010 A CN 114520010A
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Abstract
The invention discloses a DDR DFE receiving circuit structure for reducing delay units, which comprises: a first DFE sense amplifier, a second DFE sense amplifier, a first delay unit, a second delay unit, and a trigger circuit, the first DFE sense amplifier receiving an internal clock through the first delay unit; the second DFE sense amplifier receives an internal clock through the second delay cell; the first DFE sense amplifier and the second DFE sense amplifier respectively generate clock domain signals elp and olp according to external data and are connected with the trigger circuit; the trigger circuit receives an internal clock through the first delay unit and the second delay unit. The invention effectively reduces the number and area of the delay units and realizes the purpose of saving cost.
Description
Technical Field
The invention relates to the technical field of DDR (double data rate), in particular to a DDR DFE (double data rate) receiving circuit structure.
Background
With the increasing speed, the existing DDR, especially DDR5, etc. circuits need to add a Decision Feedback Equalization (DFE) structure, which is limited by its operating speed, and the DFE generally needs to divide the incoming data DQ into parity two paths [ DFE sense amplifier (DFE sense latch high) and DFE sense amplifier (DFE sense latch low) in fig. 1 ] for processing separately. Here, each path needs to have a delay unit (256 step delay line) 1, 2 to adjust the timing relationship between DQS and DQS. On the other hand, DDR itself has the characteristics that the clock signal DQS from the difference unit (DIO) is required to sample the data DQ to generate the data e1p and o1p, and then the signals e1p and o1p in the clock domain are required to be converted into signals in the internal clock (phy _ clk) domain, so that the central processing unit (cpu) and the like can directly process the data, where two delay units 3 and 4 are required to sample e1p/o1p, and the clock frequency division flip-flop (DFF _ CLKDIV) is used to generate parallel four-way data by the flip-flop (DFF) 9/7/6/8 after being further slowed down by the clock frequency division flip-flop (DFF _ CLKDIV).
Namely, two delay units are needed to process the timing relationship between the data DQ and the DQs, and two delay units (delay lines) are needed to process the data into a signal of the internal clock (phy _ clk), and four delay units occupy a huge area.
Disclosure of Invention
The invention aims to provide a DDR DFE receiving circuit structure for reducing delay units, effectively reduce the number and area of the delay units and achieve the purpose of saving cost.
The technical scheme for realizing the purpose is as follows:
a reduced delay unit DDR DFE receive circuit configuration, comprising: a first DFE sense amplifier, a second DFE sense amplifier, a first delay unit, a second delay unit, and a trigger circuit, wherein,
the first DFE sense amplifier receives an internal clock through the first delay cell;
the second DFE sense amplifier receives an internal clock through the second delay cell;
the first DFE sensitive amplifier and the second DFE sensitive amplifier respectively generate clock domain signals elp and olp according to external data and are connected with the trigger circuit;
the trigger circuit receives an internal clock through the first delay unit and the second delay unit.
Preferably, the trigger circuit includes: a clock division flip-flop and first to ninth flip-flops,
the first DFE sensitive amplifier, the first trigger, the third trigger, the fifth trigger and the ninth trigger are sequentially connected in series;
the second DFE sensitive amplifier, the second trigger, the fourth trigger and the eighth trigger are sequentially connected in series;
the seventh trigger is connected with the connection ends of the third trigger and the fifth trigger;
the sixth trigger is connected with the connection end of the second trigger and the fourth trigger;
the first delay unit is connected with the first trigger;
the second delay unit is connected with the second trigger, the third trigger, the fourth trigger, the fifth trigger and the clock frequency division trigger;
the clock frequency division trigger is connected with the sixth trigger, the seventh trigger, the eighth trigger and the ninth trigger.
A reduced delay unit DDR DFE receive circuit configuration, comprising: a first DFE sense amplifier, a second DFE sense amplifier, a first delay unit, an inverter, and a trigger circuit, wherein,
the first DFE sense amplifier receives an internal clock through the first delay cell;
the first delay unit is connected with the second DFE sensitive amplifier through the inverter;
the first DFE sense amplifier and the second DFE sense amplifier respectively generate clock domain signals elp and olp according to external data and are connected with the trigger circuit;
the trigger circuit is respectively connected with the first delay unit and the inverter.
Preferably, the trigger circuit includes: a clock division flip-flop and first to ninth flip-flops,
the first DFE sensitive amplifier, the first trigger, the third trigger, the fifth trigger and the ninth trigger are sequentially connected in series;
the second DFE sensitive amplifier, the second trigger, the fourth trigger and the eighth trigger are sequentially connected in series;
the seventh trigger is connected with the connection ends of the third trigger and the fifth trigger;
the sixth trigger is connected with the connection end of the second trigger and the fourth trigger;
the first delay unit is connected with the first trigger;
the inverter is connected with the second trigger, the third trigger, the fourth trigger, the fifth trigger and the clock frequency division trigger;
the clock frequency division trigger is connected with the sixth trigger, the seventh trigger, the eighth trigger and the ninth trigger.
The invention has the beneficial effects that: the invention directly uses the internal clock (phy _ clk) to replace the data sampling clock (DQS) to sample the data, adopts fixed four-phase sampling, adopts measures such as an inverter and the like to reduce the number of delay units, greatly reduces the area and saves the cost.
Drawings
FIG. 1 is a schematic diagram of a prior art DDR DFE receiver circuit;
FIG. 2 is a block diagram of one embodiment of a reduced delay DDR DFE receive circuit configuration of the present invention;
FIG. 3 is a block diagram of another embodiment of a reduced delay unit DDR DFE receive circuit configuration of the present invention;
fig. 4 is a timing diagram of the internal clock and the multiphase divided clock generated by DFE _ CLKDIV in relation to the phase timing of DFFs 6, 7, 8, 9.
Detailed Description
The invention will be further explained with reference to the drawings.
Example one
As shown in fig. 2, the architecture of the DDR DFE receiver circuit with reduced delay units of the present invention includes: a first DFE sense amplifier, a second DFE sense amplifier, a first delay unit, a second delay unit, and a trigger circuit, wherein,
the differential signal unit outputs an internal clock. The first DFE sense amplifier receives the internal clock through the first delay unit; a second DFE sense amplifier receives an internal clock through the second delay cell.
The first DFE sense amplifier and the second DFE sense amplifier generate clock domain signals elp and olp, respectively, according to external data DQ, and are connected in parallel to the power generation circuit; the external data DQ is processed by the DFE gain adjustment and adder module and then is simultaneously sent to the first DFE sensitive amplifier and the second DFE sensitive amplifier, and the level and the amplitude of the external data DQ are adjusted to be proper and proper in the DFE gain adjustment link, so that the signal can be conveniently received by the first DFE sensitive amplifier and the second DFE sensitive amplifier after passing through the adder. The adder is as follows: and a unit for adding the external data to feedback signals of DFF1, 2, 3, 4 stages in DFE.
The trigger circuit receives an internal clock through a first delay unit and a second delay unit.
The trigger circuit includes: the clock division flip-flop DFF _ CLKDIV and the first to ninth flip-flops DFF1-DFF9,
the first DFE sense amplifier, the first flip-flop DFF1, the third flip-flop DFF3, the fifth flip-flop DFF5 and the ninth flip-flop DFF9 are sequentially connected in series. The second DFE sense amplifier, the second flip-flop DFF2, the fourth flip-flop DFF4 and the eighth flip-flop DFF8 are connected in series in sequence. The seventh flip-flop DFF7 connects the meeting ends of the third and fifth flip-flops DFF3 and DFF 5. The sixth flip-flop DFF6 connects the meeting ends of the second and fourth flip-flops DFF2 and DFF 4. The first delay unit is connected with a first trigger DFF 1; the second delay unit is connected to the second flip-flop DFF2, the third flip-flop DFF3, the fourth flip-flop DFF4, the fifth flip-flop DFF5, and the clock division flip-flop DFF _ CLKDIV.
The clock division flip-flop DFF _ CLKDIV is connected to the sixth flip-flop DFF6, the seventh flip-flop DFF7, the eighth flip-flop DFF8, and the ninth flip-flop DFF 9.
In the invention, the first-stage sampling clock DQS is replaced by the internal clock (phy _ clk) on the original basis, so that the delay unit 3 and the delay unit 4 which are used for processing the clock domain timing relation of DQS and phy _ clk in FIG. 1 can be omitted. Meanwhile, the DFF1/DFF2 changes from the original rising edge sampling to the falling edge sampling, and sufficient stable and set-up time is reserved for the e1p/o1p signal, so that the time delay of the delay units 3 and 4 is replaced.
Example two
As shown in fig. 3, a DDR DFE receiving circuit structure with reduced delay units includes: the DFE sense amplifier circuit comprises a first DFE sense amplifier, a second DFE sense amplifier, a first delay unit, an inverter inv and a trigger circuit.
The first DFE sense amplifier receives the internal clock through the first delay unit; the first delay cell is connected to the second DFE sense amplifier through an inverter inv.
The first DFE sense amplifier and the second DFE sense amplifier generate clock domain signals elp and olp, respectively, according to external data, and are connected in parallel to the power generation circuit; the flip-flop circuits are connected to the first delay unit and the inverter inv, respectively.
The trigger circuit includes: the clock division flip-flop DFF _ CLKDIV and the first to ninth flip-flops DFF1-DFF 9.
The first DFE sense amplifier, the first flip-flop DFF1, the third flip-flop DFF3, the fifth flip-flop DFF5 and the ninth flip-flop DFF9 are sequentially connected in series. The second DFE sense amplifier, the second flip-flop DFF2, the fourth flip-flop DFF4 and the eighth flip-flop DFF8 are connected in series in sequence. The seventh flip-flop DFF7 connects the meeting ends of the third and fifth flip-flops DFF3 and DFF 5. The sixth flip-flop DFF6 connects the connected ends of the second and fourth flip-flops DFF2 and DFF 4. The first delay cell is connected to a first flip-flop DFF 1. The inverter inv is connected with the second flip-flop DFF2, the third flip-flop DFF3, the fourth flip-flop DFF4, the fifth flip-flop DFF5 and the clock division flip-flop DFF _ CLKDIV; the clock division flip-flop DFF _ CLKDIV is connected to the sixth flip-flop DFF6, the seventh flip-flop DFF7, the eighth flip-flop DFF8, and the ninth flip-flop DFF 9.
Further, the second delay unit in the first embodiment is replaced by an inverter, so that the number of delay units is reduced to 1, and the area is greatly reduced.
As shown in fig. 4, the data (e.g., Y0) after the last serial parallel operation is sampled by the positive and negative 4-phase internal clock (PHY _ CLK), wherein at least two sets of values are correct, and which way is selected according to the delay values of the delay units 1 and 2, so as to find out the correct value. The DFF6, the DFF7, the DFF8 and the DFF9 can simultaneously generate a plurality of data, and the data are collected successively through an internal clock, and the data are in sequence. In fig. 4, 0, 1, 2, and 3 represent the sequence of a set of data; 4. 5, 6, 7 represent the sequence of another set of data.
The above embodiments are provided only for illustrating the present invention and not for limiting the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, and therefore all equivalent technical solutions should also fall within the scope of the present invention, and should be defined by the claims.
Claims (4)
1. A reduced delay unit DDR DFE receiver circuit configuration, comprising: a first DFE sense amplifier, a second DFE sense amplifier, a first delay unit, a second delay unit, and a trigger circuit, wherein,
the first DFE sense amplifier receives an internal clock through the first delay cell;
the second DFE sense amplifier receives an internal clock through the second delay cell;
the first DFE sense amplifier and the second DFE sense amplifier respectively generate clock domain signals elp and olp according to external data and are connected with the trigger circuit;
the trigger circuit receives an internal clock through the first delay unit and the second delay unit.
2. The reduced delay unit DDR DFE receive circuit architecture of claim 1, wherein the trigger circuit comprises: a clock division flip-flop and first to ninth flip-flops,
the first DFE sensitive amplifier, the first trigger, the third trigger, the fifth trigger and the ninth trigger are sequentially connected in series;
the second DFE sensitive amplifier, the second trigger, the fourth trigger and the eighth trigger are sequentially connected in series;
the seventh trigger is connected with the connection ends of the third trigger and the fifth trigger;
the sixth trigger is connected with the connection end of the second trigger and the fourth trigger;
the first delay unit is connected with the first trigger;
the second delay unit is connected with the second trigger, the third trigger, the fourth trigger, the fifth trigger and the clock frequency division trigger;
the clock frequency division trigger is connected with the sixth trigger, the seventh trigger, the eighth trigger and the ninth trigger.
3. A reduced delay unit DDR DFE receiver circuit configuration, comprising: a first DFE sense amplifier, a second DFE sense amplifier, a first delay unit, an inverter, and a trigger circuit, wherein,
the first DFE sense amplifier receives an internal clock through the first delay cell;
the first delay unit is connected with the second DFE sensitive amplifier through the inverter;
the first DFE sense amplifier and the second DFE sense amplifier respectively generate clock domain signals elp and olp according to external data and are connected with the trigger circuit;
the trigger circuit is respectively connected with the first delay unit and the inverter.
4. The reduced delay unit DDR DFE receive circuit architecture of claim 3, wherein the trigger circuit comprises: a clock division flip-flop and first to ninth flip-flops,
the first DFE sensitive amplifier, the first trigger, the third trigger, the fifth trigger and the ninth trigger are sequentially connected in series;
the second DFE sensitive amplifier, the second trigger, the fourth trigger and the eighth trigger are sequentially connected in series;
the seventh trigger is connected with the connection ends of the third trigger and the fifth trigger;
the sixth trigger is connected with the connection end of the second trigger and the fourth trigger;
the first delay unit is connected with the first trigger;
the inverter is connected with the second trigger, the third trigger, the fourth trigger, the fifth trigger and the clock frequency division trigger;
the clock frequency division trigger is connected with the sixth trigger, the seventh trigger, the eighth trigger and the ninth trigger.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210412885.0A CN114520010A (en) | 2022-04-20 | 2022-04-20 | DDR DFE receiving circuit structure for reducing delay unit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210412885.0A CN114520010A (en) | 2022-04-20 | 2022-04-20 | DDR DFE receiving circuit structure for reducing delay unit |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090010320A1 (en) * | 2007-07-02 | 2009-01-08 | Micron Technology, Inc. | Fractional-Rate Decision Feedback Equalization Useful in a Data Transmission System |
| CN101527555A (en) * | 2008-03-07 | 2009-09-09 | 瑞昱半导体股份有限公司 | Sampling circuit and sampling method |
| CN106982182A (en) * | 2017-04-18 | 2017-07-25 | 南京邮电大学 | A kind of high-speed adaptive DFF |
| CN113114229A (en) * | 2020-01-13 | 2021-07-13 | 达尔科技股份有限公司 | Combined decision feedback equalizer and phase detector for clock data recovery |
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2022
- 2022-04-20 CN CN202210412885.0A patent/CN114520010A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090010320A1 (en) * | 2007-07-02 | 2009-01-08 | Micron Technology, Inc. | Fractional-Rate Decision Feedback Equalization Useful in a Data Transmission System |
| CN101527555A (en) * | 2008-03-07 | 2009-09-09 | 瑞昱半导体股份有限公司 | Sampling circuit and sampling method |
| CN106982182A (en) * | 2017-04-18 | 2017-07-25 | 南京邮电大学 | A kind of high-speed adaptive DFF |
| CN113114229A (en) * | 2020-01-13 | 2021-07-13 | 达尔科技股份有限公司 | Combined decision feedback equalizer and phase detector for clock data recovery |
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Application publication date: 20220520 |