CN114513281B

CN114513281B - Multi-carrier data processing method, device and storage medium

Info

Publication number: CN114513281B
Application number: CN202011291501.1A
Authority: CN
Inventors: 郑向秀; 常静
Original assignee: Datang Mobile Communications Equipment Co Ltd
Current assignee: Datang Mobile Communications Equipment Co Ltd
Priority date: 2020-11-17
Filing date: 2020-11-17
Publication date: 2023-06-23
Anticipated expiration: 2040-11-17
Also published as: CN114513281A

Abstract

The invention provides a multi-carrier data processing method, a device and a storage medium, and relates to the technical field of communication. The method comprises the following steps: acquiring a data format of an interleaved signal, wherein the interleaved signal comprises at least two antenna signals and at least two carrier data, and sampling frequencies of the at least two carrier data are consistent; determining a direct digital frequency signal and a complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency; carrying out frequency carrying processing on the interweaved signals according to the direct digital frequency signals and the complex frequency domain signals to obtain interweaved signals after frequency carrying; combining the interleaved signals after frequency carrying according to a preset rule to obtain combined interleaved signals; and carrying out peak clipping treatment on the combined interleaving signals according to a preset hard peak clipping threshold. The invention can directly carry out peak clipping treatment on the interweaved signals containing the multi-carrier data, reduces the resource occupancy rate and improves the treatment efficiency.

Description

Multi-carrier data processing method, device and storage medium

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a method and an apparatus for processing multicarrier data, and a storage medium.

Background

Currently, most AAUs (Active Antenna Unit, active antenna processing units) employ an operating mode that supports multi-carrier data, which requires the capability of the AAU internal components to process the multi-carrier data.

In the prior art, a multi-carrier NCO (Numerically Controlled Oscillator, digitally controlled oscillator) model is used to process multi-carrier data, and as an example, the downlink three-carrier two-antenna interleaved data is shown in fig. 1, which is a schematic implementation structure of a conventional NCO model, including dds _config (carrier frequency offset selection module), dds _core (direct digital frequency synthesis module), data_delay (data delay module), mixer (complex modulation module), add (combining module), and mag_protect (hard-cut module). The carrier frequency offset selection module is used for realizing the offset selection function of carrier signals, and different carrier offsets are different; the direct digital frequency synthesis module is a DDS module based on LUT and is used for generating a frequency-variable and time-discrete sine wave and cosine wave data sample; the data delay module delays input data and aligns the input data with generated sine waves and cosine waves; the complex modulation module is used for carrying out complex multiplication on the real part and the imaginary part of the input data after delay and the corresponding sine value and cosine value in the LUT table so as to realize frequency shifting of the input data; the combining module is used for carrying out addition operation on the carrier data after frequency moving; the main function of the hard peak clipping module is to calculate the peak value of each sampling point of the combined carrier data, find out the sampling point which is larger than the threshold value and replace the sampling point with the threshold value, thereby reducing the peak-to-average ratio to a certain extent.

As can be seen from the implementation structure of the NCO model shown in fig. 1, in the prior art, when processing multi-carrier data, one carrier data corresponds to a group of carrier frequency offset selection module, direct digital frequency synthesis module, data delay module and complex modulation module, processes input data of one three-carrier interleaving, which is equivalent to an NCO model that needs three processing single-carrier data, which increases the resource occupancy rate undoubtedly, and for the multi-carrier interleaving data, according to the processing method in the prior art, the interleaving data needs to be split according to carriers, and each split carrier data needs to be processed and then output in a combined way, thereby increasing the data processing amount and reducing the processing efficiency.

Disclosure of Invention

The invention provides a multi-carrier data processing method, a device and a storage medium, which are used for solving the problems of high resource occupancy rate and low processing efficiency of multi-carrier data in the prior art.

According to a first aspect of the present invention, there is provided a multi-carrier data processing method, the method comprising:

acquiring a data format of an interleaved signal, wherein the interleaved signal comprises at least two antenna signals and at least two carrier data, and sampling frequencies of the at least two carrier data are consistent;

Determining a direct digital frequency signal and a complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency;

carrying out frequency carrying processing on the interweaved signals according to the direct digital frequency signals and the complex frequency domain signals to obtain interweaved signals after frequency carrying;

combining the interleaved signals after frequency carrying according to a preset rule to obtain combined interleaved signals;

and carrying out peak clipping treatment on the combined interleaving signals according to a preset hard peak clipping threshold.

According to a second aspect of the present invention there is provided an apparatus comprising a memory, a transceiver, a processor: a memory for storing a computer program; a transceiver for transceiving data under control of the processor; a processor for reading the computer program in the memory and performing the following operations:

According to a third aspect of the present invention, there is provided a multi-carrier data processing apparatus, the apparatus comprising:

the device comprises a data format acquisition module, a data transmission module and a data transmission module, wherein the data format acquisition module is used for acquiring the data format of an interleaved signal, the interleaved signal comprises at least two antenna signals and at least two carrier data, and the sampling frequencies of the at least two carrier data are consistent;

a modulation signal determining module, configured to determine a direct digital frequency signal and a complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency;

the frequency-carrying processing module is used for carrying out frequency-carrying processing on the interleaving signals according to the direct digital frequency signals and the complex frequency domain signals to obtain interleaving signals after frequency carrying;

the combining processing module is used for combining the interleaved signals after frequency carrying according to a preset rule to obtain combined interleaved signals;

And the peak clipping processing module is used for clipping the peak of the combined interleaving signals according to a preset hard peak clipping threshold.

According to a fourth aspect of the present invention, there is provided a processor readable storage medium storing a computer program for causing a processor to perform the aforementioned method.

The invention provides a multi-carrier data processing method, a device and a storage medium, wherein the method comprises the following steps: acquiring a data format of an interleaved signal, wherein the interleaved signal comprises at least two antenna signals and at least two carrier data, and sampling frequencies of the at least two carrier data are consistent; determining a direct digital frequency signal and a complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency; carrying out frequency carrying processing on the interweaved signals according to the direct digital frequency signals and the complex frequency domain signals to obtain interweaved signals after frequency carrying; combining the interleaved signals after frequency carrying according to a preset rule to obtain combined interleaved signals; and carrying out peak clipping treatment on the combined interleaving signals according to a preset hard peak clipping threshold. The invention can directly carry out peak clipping treatment on the interweaved signals containing the multi-carrier data, reduces the resource occupancy rate and improves the treatment efficiency.

The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an implementation structure of an NCO model in the prior art;

fig. 2 is a flowchart illustrating steps of a method for processing multicarrier data according to a first embodiment of the present invention;

FIG. 3 is a schematic diagram of a prior art data entry format for an NCO model;

FIG. 4 is a schematic diagram of an NCO model implementation structure according to a first embodiment of the present invention;

FIG. 5 is a schematic diagram of a data input format of an NCO model according to a first embodiment of the present invention;

FIG. 6 is a timing diagram of a direct digital frequency signal and a complex frequency domain signal of a complex modulated signal according to a first embodiment of the present invention;

fig. 7 is a flowchart of specific steps of a multi-carrier data processing method according to a second embodiment of the present invention;

fig. 8 is a schematic diagram of spectrum shifting of a carrier signal according to a second embodiment of the present invention;

fig. 9 is a timing diagram of a carrier frequency offset signal according to a second embodiment of the present invention;

fig. 10 is a schematic structural diagram of a DDS module based on LUT according to a second embodiment of the present invention;

fig. 11 is a timing chart of a three-carrier interleaved signal according to the second embodiment of the present invention;

fig. 12 is a schematic structural diagram of a mag_detect module according to a second embodiment of the present invention;

FIG. 13 is a block diagram of an apparatus according to a third embodiment of the present invention;

fig. 14 is a block diagram of a multi-carrier data processing apparatus according to a fourth embodiment of the present invention.

Detailed Description

In the embodiment of the invention, the term "and/or" describes the association relation of the association objects, which means that three relations can exist, for example, a and/or B can be expressed as follows: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

The term "plurality" in embodiments of the present invention means two or more, and other adjectives are similar.

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Example 1

Referring to fig. 2, a flowchart illustrating specific steps of a multi-carrier data processing method according to a first embodiment of the present invention is shown.

Step 101, obtaining a data format of an interleaved signal, wherein the interleaved signal comprises at least two antenna signals and at least two carrier data, and sampling frequencies of the at least two carrier data are consistent.

In the embodiment of the present invention, when the preset clock frequency is a multiple of the sampling frequency of the carrier data, at least two carrier data are interleaved to obtain interleaved signals, for example, there are three single-carrier two-antenna signals c0a0c 1, c1a0c1a1, c2a0c2a1, where c0, c1, c2 are three carriers respectively, the antenna a0 and the antenna a1 correspond to one carrier respectively, the sampling frequencies of the three carriers c0, c1 and c2 are identical, and the preset clock frequency is a multiple of the sampling frequency, and then the three single-carrier two-antenna signals are interleaved to three-carrier two-antenna signals to obtain interleaved signals.

The preset clock frequency is a working frequency of a device for executing the multi-carrier data processing method provided by the embodiment of the invention.

When the preset clock frequency is a multiple of the carrier data, if the multi-carrier data processing method provided by the prior art is adopted, the interleaving signals of the multi-carrier data need to be deinterleaved according to the carriers to obtain single carrier data, the single carrier data are processed respectively, and then the output data corresponding to the single carrier data are re-interleaved to obtain the final output signals. Taking the implementation structure of the existing NCO model as shown in fig. 1 as an example, when the existing NCO model is used to process the interleaved signals corresponding to the three carriers c0, c1 and c2, the interleaved signals need to be split into single carrier signals respectively, and the three split single carrier signals are respectively input into and output from the NCO model to perform data processing.

Referring to fig. 3, a schematic diagram of a data input format of a conventional NCO model is shown, in which the sampling frequencies of carrier c0, carrier c1 and carrier c2 are identical, and the Clock frequency of the Clock signal Clock is 8 times the sampling frequencies of the three carriers. In fig. 3, the signal frequency of the signal x8_hd is identical to the sampling frequency of three carriers, and the signal processing is generally performed by adopting an FPGA, and the clock frequency of the FPGA is 491.52MHZ, and the sampling frequency of the three carriers is 61.44 MHZ. In the single-carrier two-antenna signals data_c0, data_c1, and data_c2 corresponding to the carrier c0, carrier c1, and carrier c2 shown in fig. 3, only two paths of effective data exist in one signal period, and in the single-carrier two-antenna signal data_c0 as an example, the signal data_c0 only has two paths of effective data, namely, c0a0 and c0a1, in one signal period. The signals freq_c0, freq_c1, freq_c2 in fig. 3 are frequency offset signals corresponding to the carrier c0, the carrier c1, and the carrier c2, respectively. The signal freq_c0 in fig. 3 is the input signal dds _fre (c 0) of the dds _config module in fig. 1, and similarly, the signal freq_c1 is the input signal dds _fre (c 1), and the signal freq_c2 is the input signal dds _fre (c 2).

As can be seen from fig. 1 and 3, for the interleaved signals of the three carriers and the two antennas, the processing method in the prior art is adopted, the interleaved signals are required to be split into single carrier signals according to carriers, then each single carrier signal is processed respectively and then combined and output, one single carrier signal requires a group of carrier frequency offset selection module, a direct digital frequency synthesis module, a data delay module and a complex modulation module, and the processing of the interleaved signals of the three carriers and the two antennas is equivalent to that of an NCO model which requires three processing single carrier data, which clearly increases the resource occupancy rate. Thus, embodiments of the present invention improve upon existing NCO models.

Referring to fig. 4, a schematic diagram of an NCO model implementation structure according to an embodiment of the present invention is shown. Unlike the existing NCO model shown in fig. 1, in the NCO model provided in the embodiment of the present invention, the input signal of dds _config (carrier frequency offset selection module) is an interleaved signal of multi-carrier data, rather than a single carrier signal. Taking three-carrier two-antenna signals as an example, referring to fig. 5, a schematic diagram of a data input format of an NCO model provided by an embodiment of the present invention is shown, where Signal data in fig. 5 is a complex frequency domain Signal corresponding to the interleaved three-carrier two-antenna signals, that is, an input Signal in of the data_delay module in fig. 4; the freq signal is a frequency offset signal corresponding to the interleaved signal of the three-carrier two-antenna, and the freq signal in fig. 5 is the input signal dds _fre of the dds _config module in fig. 4.

As can be seen from fig. 4 and fig. 5, in the embodiment of the present invention, the interleaved signal may be directly processed, taking three-carrier two-antenna signals as an example, and only one group of carrier frequency offset selection module, direct digital frequency synthesis module, data delay module and complex modulation module is needed to reduce the resource occupancy rate by adopting the NCO model provided in the embodiment of the present invention.

In the embodiment of the present invention, the product of the number of antenna signals of at least two antenna signals and the number of carriers of at least two carrier data contained in the interleaved signal is smaller than or equal to a preset number of signals, where the preset number of signals is equal to a ratio of a preset clock frequency to the sampling frequency.

The product of the number of antenna signals of at least two antenna signals and the number of carriers of at least two carrier data contained in the interleaved signal is the number of signals contained in the interleaved signal, for example, the interleaved signal of three carrier two antenna signals contains 6 signals. The preset number of signals is the maximum number of signals that the interleaved signal can contain. In order to ensure that the interleaved signal can contain the sampling point of one signal period of each interleaved signal in each signal period, the number of signals in the interleaved signal cannot be larger than the ratio of the preset clock frequency to the sampling frequency.

In the embodiment of the invention, the dds _config module, the dds _core module and the data_delay module are all interleaved signals, but when signals are processed in the module, data processing is respectively carried out on each carrier according to the data format of the interleaved signals, so that the data format of the interleaved signals needs to be determined in advance in the embodiment of the invention, and the data processing rule of each module and the data format of output data of each module can be determined. Taking an example of an interleaved signal of three carriers and two antennas, referring to fig. 5, in one signal period, data of the interleaved signal data are arranged according to a preset sequence of a carrier c0, a carrier c1 and a carrier c2, antenna signals corresponding to the respective carriers are arranged according to a preset sequence of an antenna a0 and an antenna a1, and a frequency offset signal freq corresponding to the interleaved signal is obtained according to a data format of the interleaved signal data, and as can be seen from fig. 5, data of the freq signal are arranged according to a preset sequence of the carrier c0, the carrier c1 and the carrier c2, so that when the freq signal shown in fig. 5 is input to the dds _config module shown in fig. 4, the dds _config module can determine which carrier corresponds to the frequency offset to be generated according to the data format and clock frequency of the freq signal.

Step 102, determining a direct digital frequency signal and a complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency.

Specifically, after the data format of the interleaved signal is obtained, the direct digital frequency synthesis module and the complex modulation module in the NCO model may determine which carrier the data to be processed belongs to according to the multiple relationship between the clock frequency and the sampling frequency of the carrier in the embodiment of the present invention, and generate an output signal according to the data format of the interleaved signal. Wherein the direct digital frequency signal comprises a sine wave signal and a cosine wave signal, and the complex frequency domain signal comprises a real part signal and an imaginary part signal of the interleaved signal in the complex frequency domain.

Taking three-carrier two-antenna signals as an example, referring to fig. 6, a timing diagram of a direct digital frequency signal and a complex frequency domain signal provided by an embodiment of the present invention is shown. When the frequency offset signal freq shown in fig. 5 is input to the dds _config module shown in fig. 4, the dds _config module outputs the frequency offset corresponding to each carrier according to the input freq data format. The essence of the dds _config module is that the input frequency offset signal is converted into a digital pulse signal according to the multiple relation between the clock frequency and the sampling frequency, so that the dds _core module generates a sine wave signal and a cosine wave signal corresponding to each carrier according to the input digital pulse signal, and the sin signal shown in fig. 6 is a sine wave signal generated according to the digital pulse signal output by the dds _config module shown in fig. 4. The sine wave signal generated by the dds _core module is only related to the carrier wave, and is irrelevant to the antenna, and the sine wave signal and the cosine wave signal corresponding to the same carrier wave are different in phase by 90 degrees, so in order to avoid redundancy, the embodiment of the invention is exemplified by the sine wave signal.

It should be noted that, in the embodiment of the present invention, the Signal data in fig. 5 and fig. 6 is a complex frequency domain Signal of the three-carrier two-antenna Signal in the complex frequency domain, that is, the input Signal in of the data_delay module in fig. 4. The data_delay module is used for performing delay processing on the input complex frequency domain signal, so that the output delayed complex frequency domain signal is consistent with the phase of each sampling point of the direct digital frequency signal output by the dds _core module in fig. 4, and complex multiplication is facilitated. The complex frequency domain signal data comprises a real part signal data_i and an imaginary part signal data_q corresponding to the interleaved signal, and the complex frequency domain signal is divided into two paths of data of the real part signal data_i and the imaginary part signal data_q and is input to the data_delay module. The data format of the real signal data_i and the imaginary signal data_q is the same as the data format of the interleaved signal. As can be seen from fig. 6, the data format of the sine wave signal generated by the dds _core module corresponds to the data format of the complex frequency domain signal data.

And 103, carrying out frequency-carrying processing on the interleaving signals according to the direct digital frequency signals and the complex frequency domain signals to obtain interleaved signals after frequency carrying.

The frequency shift processing is performed on the interleaved signal, namely, the frequency spectrum of the interleaved signal is shifted. Specifically, the direct frequency signal obtained in step 102 and the complex frequency domain signal are complex multiplied, so that the frequency of the interleaved signal can be shifted. The signal data_in shown in fig. 6 is an interleaved signal after frequency shifting.

And 104, combining the interleaved signals after frequency moving according to a preset rule to obtain combined interleaved signals.

As can be seen from the timing chart of the interleaved signal data_in after frequency shifting shown in fig. 6, the data format of the interleaved signal after frequency shifting is the same as the data format of the interleaved signal originally input to the NCO module, and the interleaved data of the antenna signal is subjected to peak clipping processing by the mag_protect module shown in fig. 4, that is, the antenna signal is subjected to peak clipping processing by the preset sequence of the antenna signal, so that the interleaved signal after frequency shifting needs to be subjected to a combining process before the peak clipping processing is performed, specifically, the interleaved signal after frequency shifting is split by the diff_car_data_delay module in fig. 4 to obtain a single carrier signal, and the obtained single carrier signal is synthesized by the add module to obtain the interleaved signal of the antenna signal.

And 105, carrying out peak clipping treatment on the combined interleaving signals according to a preset hard peak clipping threshold.

Specifically, calculating the amplitude value of each sampling point of the interleaved signal after combining, comparing the amplitude value of each sampling point with a preset hard peak clipping threshold, and taking the amplitude value as the amplitude value corresponding to at least one sampling point in the output signal if the amplitude value of at least one sampling point is smaller than or equal to the preset hard peak clipping threshold; if the amplitude value of at least one sampling point is larger than a preset hard peak clipping threshold, taking the preset hard peak clipping threshold as the amplitude value corresponding to the at least one sampling point in the output signal.

In summary, in the embodiment of the present invention, by directly inputting the interleaved signal including the multi-carrier data into the NCO model, and generating the corresponding modulation signal according to the data format of the interleaved signal, the peak clipping processing is performed on the multi-carrier data by using a group of carrier frequency offset selection module, direct digital frequency synthesis module, complex modulation module and hard peak clipping module, thereby reducing the resource occupancy rate and improving the processing efficiency.

Example two

Referring to fig. 7, a flowchart of specific steps of a multi-carrier data processing method according to a second embodiment of the present invention is shown.

Step 201, acquiring at least two carrier data, wherein the sampling frequencies of the at least two carrier data are consistent, and the sampling frequency is a factor of a preset clock frequency.

The preset clock frequency is a working frequency of a device for executing the multi-carrier data processing method provided by the embodiment of the invention, for example, a clock frequency of an FPGA (Field Programmable Gate Array ). Taking the NCO model shown in fig. 4 as an example, the preset clock frequency is the working frequency of the NCO model, and in the NCO model shown in fig. 4, the working frequencies of the modules are consistent and can be represented by the clock frequency.

In the embodiment of the invention, when the sampling frequencies of at least two carriers are consistent and the sampling frequency is a factor of the preset clock frequency, that is, the preset clock frequency is a multiple of the sampling frequency, the at least two carriers can be interleaved to obtain the multi-carrier interleaved signal, and then the multi-carrier data processing method provided by the invention is directly adopted to process the multi-carrier interleaved signal without separately processing each carrier data, thereby reducing the resource occupation rate and improving the data processing efficiency.

Step 202, determining a preset sequence of the at least two carrier data.

And 203, interleaving the at least two antenna signals according to the preset sequence of the at least two carrier data to obtain interleaved signals.

After at least two carrier wave data meeting the preset conditions are obtained, the preset sequence of the carrier wave data can be set, and at least two antenna signals corresponding to the carrier waves are subjected to interleaving treatment according to the preset sequence of the carrier waves to obtain interleaved signals, so that the data formats of the interleaved signals are the same in each signal period, and the interleaved signals are convenient to further process. For example, there are three single-carrier two-antenna signals c0a1, c1a0c1, c2a0c2a1, where c0, c1, c2 are three carriers respectively, the antenna a0, the antenna a1 correspond to one carrier respectively, the sampling frequencies of the carrier c0, the carrier c1 and the carrier c2 are consistent, and the preset clock frequency is a multiple of the sampling frequency, and then the three single-carrier two-antenna signals may be interleaved into three-carrier two-antenna signals according to the preset sequence of the carrier c0, the carrier c1, the carrier c2 to obtain an interleaved signal, or the three single-carrier two-antenna signals may be interleaved according to other preset sequences, for example: carrier c0, carrier c2, carrier c1, or carrier c1, carrier c2, carrier c0, to which embodiments of the present invention are not particularly limited. In the embodiment of the present invention, the preset sequence of the carrier c0, the carrier c1, and the carrier c2 is illustrated, as shown in fig. 5, the signal data is a timing chart of three-carrier two-antenna signals obtained by interleaving according to the preset sequence of the carrier c0, the carrier c1, and the carrier c2, where c0a0, c0a1, c1a0, c1a1, c2a0, and c2a1 are sampling points listed, and as can be seen from fig. 5, in each signal period, the data of the interleaved signals are arranged according to the preset sequence.

The product of the number of antenna signals of at least two antenna signals and the number of carriers of at least two carrier data contained in the interleaved signal is the number of signals contained in the interleaved signal, for example, the interleaved signal of three carrier two antenna signals contains 6 paths of signals. The preset number of signals is the maximum number of signals that the interleaved signal can contain. In order to ensure that the interleaved signal can contain the sampling point of one signal period of each interleaved signal in each signal period, the number of signals in the interleaved signal cannot be larger than the ratio of the preset clock frequency to the sampling frequency.

Taking the three-carrier two-antenna signal as an example, referring to fig. 5, the signal data is a complex frequency domain signal corresponding to the interleaved three-carrier two-antenna signal, the signal frequency of the Clock signal Clock is the preset Clock frequency in the embodiment of the present invention, the signal frequency of the signal x8_hd is consistent with the sampling frequency of the three carriers, as can be seen from fig. 5, the preset Clock frequency of the Clock signal Clock is 8 times the sampling frequency of the interleaved signal data, that is, the signal period of the interleaved signal data is 8 times the signal period of the Clock signal Clock, and at most 8 paths of data can be contained in one signal period of the interleaved signal.

Step 204, a data format of the interleaved signal is obtained.

As can be seen from combining steps 201 to 203, in the embodiment of the present invention, the interleaved signal includes at least two antenna signals and at least two carrier data, and sampling frequencies of the at least two carrier data are consistent.

The step may specifically refer to step 101, and further description of this embodiment of the present invention is omitted herein.

Step 205, determining a direct digital frequency signal and a complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency.

The step may specifically refer to step 102, and further description of the embodiment of the present invention is omitted here.

In an alternative embodiment of the present invention, the determining, in step 205, the direct digital frequency signal and the complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency includes:

and S11, determining a frequency offset signal of the interleaving signal according to the data format and the sampling frequency.

And step S12, generating a direct digital frequency signal of the interleaving signal according to the frequency offset signal.

And step S13, mapping the interleaved signal to a complex frequency domain, and acquiring real part data and imaginary part data of the interleaved signal.

Step S14, generating a complex frequency domain signal of the interleaved signal according to the data format of the interleaved signal, the sampling frequency, the real part data, and the imaginary part data.

In combination with the foregoing, in the embodiment of the present invention, each path of data is arranged according to the preset sequence of at least two carriers included in the interleaved signal in each signal period of the interleaved signal, and in each signal period, the arrangement mode of the data is the data format of the interleaved signal in the embodiment of the present invention. The frequency offset is a value that the spectrum of each carrier needs to be shifted. The NCO model shown in fig. 4 provided by the embodiment of the present invention essentially shifts the frequency spectrum of different carrier signals according to the requirement, and then performs peak clipping processing on the interleaved signals after frequency shift combining. Therefore, in the embodiment of the present invention, it is first necessary to determine the frequency offset of each carrier in the interleaved signal. Referring to fig. 8, a schematic diagram of spectrum shifting of a carrier signal according to an embodiment of the present invention is shown. As can be seen from fig. 8, the shift amounts of the frequency spectrums corresponding to the different carriers are different, and therefore, the frequency offsets corresponding to the different carriers are also different. The frequency offset is carrier-only and antenna-independent. In the embodiment of the present invention, in the NCO model shown in fig. 4, the dds _fre signal input by the dds _config module is the frequency offset signal freq of the interleaved signal, as can be seen from fig. 5, the frequency offset signal freq is arranged according to the preset sequence of the carrier c0, the carrier c1 and the carrier c2, the dds _config module needs to generate a corresponding digital pulse signal according to the input frequency offset signal freq, so that the dds _core module identifies the frequency offset according to the received digital pulse signal and generates a corresponding sine wave signal and a cosine wave signal, and therefore, in order to identify the data corresponding to each carrier in the interleaved frequency offset signal freq, the embodiment of the present invention improves the dds _config module, and the dds _config module can select the data of the corresponding carrier for processing by using the sel25_config signal.

Taking three carrier two antenna signals as an example, referring to fig. 9, a carrier frequency offset signal timing diagram provided by an embodiment of the present invention is shown. The frequency offset signal freq according to carrier interleaving is input to a dds _config module in fig. 4, and digital pulse signals of the frequency offset corresponding to each carrier are generated according to the count value corresponding to the sel signal, so as to obtain pulse signals freq_in of the frequency offset corresponding to the interleaving signal. The sel signal is a digital signal corresponding to a counter value generated by a counter, and the count value of the counter is 0 to (N-1), wherein N is a ratio of a preset clock frequency to a sampling frequency. Taking n=8 as shown in fig. 9 as an example, the preset sequence of three carriers is carrier c0, carrier c1, and one carrier corresponds to two antenna signals, so one carrier corresponds to two count values, therefore, when the count value is 0 or 1, the dds _config module outputs a digital pulse signal (freq_c0) corresponding to a frequency offset corresponding to carrier c0, and so on, when the count value is 2 or 3, the dds _config module outputs a digital pulse signal (freq_c1) corresponding to a frequency offset corresponding to carrier c1, and when the count value is 4 or 5, the dds _config module outputs a digital pulse signal (freq_c2) corresponding to a frequency offset corresponding to carrier 2. Because of the current three-carrier two-antenna data, when the count value is 6 or 7, there is no corresponding data input, and the dds _config module can output 0. In practical application, the dds _config module outputs an interleaved digital pulse signal freq_in, and in order to explain the working principle of the dds _config module, the embodiment of the present invention introduces a digital pulse signal freq_c0, a digital pulse signal freq_c1 and a digital pulse signal freq_c2 for explanation, and actually, the dds _config module only needs to directly output the interleaved digital pulse signal freq_in according to the input frequency offset signals freq and sel signals.

The output signal freq_in of the dds _config module in fig. 4 is input to the dds _core module, and the dds _core module generates corresponding sine wave signals and cosine wave signals according to the input digital pulse signals of the frequency offset. The DDS _core module in the NCO model provided by the embodiment of the present invention is actually a DDS (Direct Digital Synthesis, direct digital frequency synthesis) module based on LUT (Look-Up-Table), and is composed of a phase accumulator and a waveform memory. Referring to fig. 10, a schematic structural diagram of a DDS module based on LUT according to an embodiment of the present invention is shown, where a phase accumulator converts a received digital pulse signal with a frequency offset into a phase, and adds a phase increment on the basis of a phase value corresponding to the digital pulse when receiving one digital pulse. The waveform memory is an LUT in the FPGA, and the LUT stores waveform data of one period according to the phase, in practical application, matlab may be used to generate sine wave data or cosine wave data to be stored, and taking sine wave data as an example, sine wave data stored in the sin LUT shown in fig. 10 may be expressed as:

where N is the depth of the look-up table LUT, and assuming that the bit width of the phase accumulator is N bits, the depth of the LUT n=2 ⁿ . In practical application, sine values corresponding to each phase value of the sine wave generated by the DDS module can be calculated in advance according to the formula (1), the phase value corresponding to each sine value is used as a storage address, the calculated sine value is stored in the LUT, and in view of symmetry of the sine wave in practical engineering application, only 1/2 period sine value needs to be stored in the LUT in order to save storage resources. When the DDS module receives a sampling point of a carrier signal, a phase value is generated, a sine value corresponding to the phase value is searched in the LUT according to the generated phase value, and the searched sine value is used as an amplitude value of a sine wave signal corresponding to the sampling point.

Assuming that the step value of the phase accumulator bit in fig. 10 is μ, the sampling frequency of the interleaved signal is f _s Center frequencies f of sine wave and cosine wave output by DDS _c Expressed as:

the step value μ of the phase accumulator bit is a carrier frequency control word, where the carrier frequency control word is used to represent a carrier frequency offset when the carrier frequency spectrum is shifted, and as can be seen from equation (2), the center frequencies of the sine wave and the cosine wave output by the DDS module are related to the value that the carrier frequency spectrum needs to be shifted.

And (3) calculating the amplitude value corresponding to the sampling point of the carrier signal in the sine wave signal according to the formula (1), and calculating the center frequency of the sine wave signal corresponding to the carrier signal according to the formula (2), so as to generate the sine wave signal corresponding to the carrier signal according to the amplitude value and the center frequency of each sampling point. The sine wave signal and the cosine wave signal corresponding to the same carrier wave are different in phase by 90 degrees, so in order to avoid redundancy, the embodiment of the invention is illustrated by the sine wave signal. As shown in fig. 6, the signal sin is a sine wave signal corresponding to the three-carrier two-antenna signal generated by the NCO model according to the embodiment of the present invention.

In the embodiment of the invention, because the carrier signal is required to be subjected to frequency spectrum shifting, in order to facilitate data processing, the interleaved signal in the time domain is required to be mapped onto the complex frequency domain through Fourier transformation, so as to obtain the complex frequency domain signal of the interleaved signal. Specifically, real part data and imaginary part data of each sampling point of the interleaved signal are calculated, and a complex frequency domain signal of the interleaved signal is generated according to a data format and sampling frequency of the interleaved signal. In the NCO model shown in fig. 4, the input Signal in of the data_delay module is the complex frequency domain Signal of the interleaved Signal, i.e. the Signal data in fig. 5. The complex frequency domain signal data comprises a real part signal data_i and an imaginary part signal data_q corresponding to the interleaved signal, the complex frequency domain signal is divided into two paths of data of the real part signal data_i and the imaginary part signal data_q, the two paths of data are input to a data_delay module, the data_delay module carries out delay processing on the input complex frequency domain signal, so that the phase of each sampling point of the delayed complex frequency domain signal is consistent with the phase of each sampling point of the sine wave signal and the cosine wave signal output by the dds _core module, and complex multiplication is facilitated.

Step 206, the direct digital frequency signal includes a sine value signal and a cosine value signal of the interleaved signal, and complex multiplication is performed on the sine value signal, the cosine value signal and the complex frequency domain signal according to a preset frequency-moving rule, so as to obtain an interleaved signal after frequency-moving.

The frequency shift processing is performed on the interleaved signal, namely, the frequency spectrum of the interleaved signal is shifted. Specifically, the complex frequency domain signal after delay output by the dds _core module, the sine wave signal and the cosine wave signal and output by the data_delay module are input to the mixer module in fig. 4 for complex multiplication, so that the frequency of the interleaved signal can be carried out. The signal data_in shown in fig. 6 is an interleaved signal after frequency shifting.

Specifically, in the sine wave signal output by any one sampling point P, dds _core module of the interleaved signal in the embodiment of the present invention, the sine value corresponding to the sampling point P is sin _p In the cosine wave signal output by the dds _core module, the cosine value corresponding to the sampling point P is cos _p If the real part value corresponding to the sampling point P is I and the imaginary part value is Q, the real part value corresponding to the sampling point I and the imaginary part value Q in the interleaved signal after frequency shifting can be expressed as:

I＝i*(cos _p +sin _p )-sin _p *(i+q) (3)

Q＝i*(cos _p +sin _p )+cos _p *(q-i) (4)

According to the formula (3) and the formula (4), the real part value and the imaginary part value corresponding to each sampling point in the interleaved signal after frequency moving can be calculated. The mixer module receives the sine value, the cosine value, the real part data and the imaginary part data corresponding to one sampling point, and the real part value and the imaginary part value after frequency moving corresponding to the sampling point can be calculated through the formula (3) and the formula (4), so that the interleaved signal data_in after frequency moving is output.

Step 207, performing delay processing on the interleaved signal after frequency moving according to the data format and the sampling frequency to obtain at least two carrier signals.

Wherein the at least two carrier signals correspond to the at least two carrier data, one of the carrier signals comprising the at least two antenna signals.

And step 208, combining the at least two carrier signals to obtain a combined interleaving signal.

As can be seen from the timing chart of the interleaved signal data_in after frequency shifting shown in fig. 6, the data format of the interleaved signal after frequency shifting is the same as the data format of the interleaved signal originally input to the NCO module, and the interleaved data of the antennas are subjected to peak clipping processing by the mag_protect module shown in fig. 4, that is, the antenna signals are subjected to peak clipping processing by the preset sequence of the antenna signals, so that the interleaved signal after frequency shifting needs to be subjected to a combining processing before the peak clipping processing is performed, specifically, the interleaved signal after frequency shifting is split by the diff_car_data_delay module in fig. 4 to obtain single carrier data, and then the obtained single carrier data is synthesized by the add module to obtain the interleaved signal of the antenna signals.

Taking three-carrier two-antenna signals as an example, referring to fig. 11, a timing diagram of a three-carrier interleaved signal according to an embodiment of the present invention is shown. The Clock signal is a Clock signal, the signal frequency is a preset Clock frequency, the sel signal is a digital signal corresponding to a count value generated by a counter in an NCO model, the signal data_in is an input signal of a diff_car_data_delay module in fig. 4, that is, an interleaved signal after frequency moving, because the interleaved signal data_in after frequency moving contains two antenna signals, and the two Clock periods correspond to a signal corresponding to one carrier in a signal period of one interleaved signal, if the interleaved signal is split into a single carrier signal according to the carrier, when the interleaved signal is subjected to delay processing, the number of the Clock periods of the delay is required to be a multiple of the number of antennas contained in the interleaved signal, and thus the single carrier signal containing all antenna signals in the interleaved signal can be obtained after the split processing of the delayed interleaved signal.

Since the interleaved signal data_in after frequency shifting shown in fig. 11 is an interleaved signal of three carriers and two antennas, the interleaved signal data_in after frequency shifting is delayed by 2 clock cycles to obtain a signal data_in_d2, and the interleaved signal data_in after frequency shifting is delayed by 4 clock cycles to obtain a signal data_in_d4. As can be seen from fig. 11, when the count value corresponding to the sel signal is 4 and 5, the signal data_in corresponds to the two antenna signals C2A0 and C2A1 of the carrier C2, the signal data_in_d2 corresponds to the two antenna signals C1A0 and C1A1 of the carrier C1, the signal data_in_d4 corresponds to the two antenna signals C0A0 and C0A1 of the carrier C0, the signal data_m is introduced at this time, and when the count value corresponding to the sel signal is 4 and 5, the signal data_m outputs the effective value c_all_all. When the signal data_m outputs the valid value c_all_all, the signal sel_en outputs a high level, and when the signal data_m outputs other values, the signal sel_en outputs a low level. Multiplying the signal sel_en with the signal data_in to obtain a signal data_out_c2, wherein the signal data_out_c2 only comprises two paths of antenna signals C2A0 and C2A1 of the carrier C2; multiplying the signal sel_en with the signal data_in_d2 to obtain a signal data_out_c1, wherein the signal data_out_c1 only comprises two paths of antenna signals C1A0 and C1A1 of a carrier C1; the signal sel_en is multiplied by the signal data_in_d4 to obtain a signal data_out_c0, the signal data_out_c0 only comprising the two antenna signals C0A0 and C0A1 of the carrier C0. Thus, a separated single carrier signal is obtained.

Then, the separated single carrier signals data_out_c0, data_out_c1 and data_out_c2 are subjected to a combining process to obtain a combined interleaved signal data_out, and as can be seen from fig. 11, the data format corresponding to the combined interleaved signal data_out has no concept of carrier, and is the interleaved signal of the antenna a0 and the antenna a 1.

And 209, performing peak clipping processing on the combined interleaved signals according to a preset hard peak clipping threshold.

The step may specifically refer to step 105, and the embodiment of the present invention will not be further described herein.

In an optional embodiment of the present invention, in step 209, the peak clipping processing of the combined interleaved signal according to a preset hard peak clipping threshold includes:

and S21, calculating the amplitude value and the sine and cosine value of each sampling point of the combined interleaved signal.

Step S22, if the amplitude value of at least one sampling point is smaller than or equal to the preset hard peak clipping threshold, the amplitude value is used as the amplitude value corresponding to the at least one sampling point in the output signal.

Step S23, if the amplitude value of at least one sampling point is larger than a preset hard peak clipping threshold, taking the preset hard peak clipping threshold as the amplitude value corresponding to the at least one sampling point in the output signal.

Step S24, generating an output signal according to the sine and cosine values of the sampling points and the amplitude values of the sampling points in the output signal, wherein the output signal is an interleaved signal subjected to peak clipping processing.

The preset hard peak clipping threshold may be set according to actual requirements, which is not specifically limited in the embodiment of the present invention. In the NCO model shown in FIG. 4 of the present invention, peak clipping processing of the interleaved signal after combining is realized by a mag_protect module. Referring to fig. 12, a schematic structural diagram of a mag_protection module provided by the embodiment of the present invention is shown, where a signal th is a signal corresponding to a preset hard peak clipping threshold, a signal data_i is a real signal of an interleaved signal data_out after combining in step 208, and a signal data_q is an imaginary signal of the interleaved signal data_out after combining in step 208. The cordic module is used for calculating amplitude values, sine values and cosine values corresponding to all sampling points in the input signal data_i and the signal data_q. The Magx theta module is used for calculating phase information corresponding to the sampling point according to the sine value and the cosine value of the input sampling point. The cordic module inputs the amplitude value, the sine value and the cosine value of each sampling point to the compper module, the compper module is used for comparing the received amplitude value of the sampling point with a preset hard peak clipping threshold and inputting a comparison result to the mux module, if the comparison result received by the mux module is that the amplitude value of the sampling point is larger than the preset hard peak clipping threshold, the mux module takes the preset hard peak clipping threshold as the amplitude value of the sampling point in an output signal and determines the phase information of the sampling point in the output signal according to the phase information of the sampling point calculated by the Magx theta module; if the comparison result received by the mux module is that the amplitude value of the sampling point is smaller than or equal to the preset hard peak clipping threshold, the mux module directly outputs the data of the sampling point in the interleaved signal after delay processing of the delay module. The output signal data_out_i of the mux module is the real part signal of the interleaved signal after the peak clipping process, and the output signal data_out_q is the imaginary part signal of the interleaved signal after the peak clipping process.

As can be seen from fig. 12, the input data of the cordic module is the real signal data_i and the imaginary signal data_q of the combined interleaved signal data_out, and the amplitude value of each sampling point in the input signal needs to be calculated according to the real data and the imaginary data of the sampling point. For example, the amplitude value of each sampling point is calculated using the cordic algorithm.

In an alternative embodiment of the present invention, the calculating the amplitude value of each sampling point of the interleaved signal after combining in step S21 includes:

s211, rotating the combined interleaving signals according to a preset rotation rule to obtain amplitude estimation values of all sampling points of the combined interleaving signals.

S212, determining a compensation coefficient according to the rotation times.

S213, calculating the amplitude value of each sampling point of the combined interleaving signal according to the amplitude estimation value and the compensation coefficient.

In an embodiment of the present invention, the cordic module shown in fig. 12 may calculate the amplitude value of each sampling point in the input signal through a cordic algorithm. The cordic algorithm includes a rotation method and a vector method, and the embodiment of the invention is illustrated by taking the rotation method as an example.

The amplitude value of the sampling point is calculated by adopting a rotation method, namely the phase of the sampling point is rotated to 0 degrees, at the moment, the amplitude value of the sampling point is approximately equal to the real part value of the sampling point, and the imaginary part value of the sampling point is close to 0. The cordic module generally adopts a multi-order structure, each order corresponds to a rotation angle, and amplitude estimation values of sampling points are obtained after multi-order cascading and rotation are carried out for a plurality of times. Taking the 5-order cascade as an example, the rotation angles are 45 °, 26.6 °, 14 °, 7.1 °, 3.6 ° and 1.8 ° in order from 0 to 5. In general, the angle of rotation of the kth order is determined by arctan (1/2 k), and the relationship between input data and output data of the kth order can be expressed as:

Wherein I is _k And Q _k For the k-th order of output data, I _k-1 And Q _k-1 Is the k-th order input data.

Through multiple rotations, when Q _k When the value of (2) is close to 0, the corresponding I _k As an amplitude estimate of the sampling point P.

When a sampling point P of an input signal is rotated counterclockwise by an angle θ from a point a to a point B, the phase of the sampling point P is 0 degrees, coordinates of a set point a are (Xi, yi), coordinates of a point B are (xi+1, yi+1), and the following relationship is given:

X _i+1 ＝cosθ(X _i -Y _i tanθ) (7)

Y _i+1 ＝cosθ(Y _i +X _i tanθ) (8)

also, if the angle θ is rotated clockwise, there are:

X _i+1 ＝cosθ(X _i +Y _i tanθ) (9)

Y _i+1 ＝cosθ(Y _i -X _i tanθ) (10)

let the angle per rotation be α=arctan 2 ^-(i-2) The following steps are:

X _i+1 ＝cosα _i (X _i +Y _i ξ _i 2 ^-(i-2) ) (11)

Y _i+1 ＝cosα _i (Y _i -X _i ξ _i 2 ^-(i-2) ) (12)

wherein, when xi _i When ζ, it rotates clockwise when++1 _i And anticlockwise rotation when= -1. After n rotations, the total rotation angle is:

the number of rotations n determines the algorithm accuracy, and the vector is rotated n times

The amplitude factor K of (2) can be expressed as: />

When n is sufficiently large, K≡ 0.607253, the compensation coefficient in the embodiment of the present invention.

Finally, multiplying the amplitude estimation value of the sampling point P obtained by the formula (5) by the compensation coefficient obtained by the formula (14) to obtain the amplitude value of the sampling point P.

After the amplitude value of the sampling point is obtained, the sine value and the cosine value of the sampling point are combined, so that the data of the sampling point in the output signal of the hard peak clipping module can be obtained, and the same processing is performed on each input sampling point by analogy, so that the interleaved signal after peak clipping processing can be obtained.

It should be noted that the technical solution provided by the embodiment of the present invention may be applicable to various systems, especially a 5G system. For example, suitable systems may be global system for mobile communications (global system of mobile communication, GSM), code division multiple access (code division multiple access, CDMA), wideband code division multiple access (Wideband Code Division Multiple Access, WCDMA) universal packet Radio service (general packet Radio service, GPRS), long term evolution (long term evolution, LTE), LTE frequency division duplex (frequency division duplex, FDD), LTE time division duplex (time division duplex, TDD), long term evolution-advanced (long term evolution advanced, LTE-a), universal mobile system (universal mobile telecommunication system, UMTS), worldwide interoperability for microwave access (worldwide interoperability for microwave access, wiMAX), 5G New air interface (New Radio, NR), and the like. Terminal devices and network devices are included in these various systems. Core network parts such as evolved packet system (Evloved Packet System, EPS), 5G system (5 GS) etc. may also be included in the system.

Example III

Referring to fig. 13, a block diagram of an apparatus according to a third embodiment of the present invention is shown, which specifically includes:

a memory 300 for storing a computer program.

A transceiver 310 for receiving and transmitting data under the control of a processor 320.

A processor 320 for reading the computer program in the memory 300 and performing the following operations:

a11, acquiring a data format of an interleaved signal, wherein the interleaved signal comprises at least two antenna signals and at least two carrier data, and sampling frequencies of the at least two carrier data are consistent;

a12, determining a direct digital frequency signal and a complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency;

a13, carrying out frequency-carrying treatment on the interweaved signals according to the direct digital frequency signals and the complex frequency domain signals to obtain interweaved signals after frequency carrying;

a14, combining the interleaved signals after frequency shifting according to a preset rule to obtain combined interleaved signals;

and A15, carrying out peak clipping treatment on the combined interleaving signals according to a preset hard peak clipping threshold.

Optionally, the processor 320 is further configured to read the computer program in the memory 300 and perform the following operations:

Acquiring at least two carrier data, wherein the sampling frequencies of the at least two carrier data are consistent, and the sampling frequency is a factor of a preset clock frequency;

determining a preset sequence of the at least two carrier data;

and interleaving the at least two antenna signals according to the preset sequence of the at least two carrier data to obtain interleaved signals.

Optionally, the determining, by a12, the direct digital frequency signal and the complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency includes:

determining a frequency offset signal of the interleaved signal according to the data format and the sampling frequency;

generating a direct digital frequency signal of the interleaved signal from the frequency offset signal;

mapping the interleaved signal to a complex frequency domain to obtain real part data and imaginary part data of the interleaved signal;

generating a complex frequency domain signal of the interleaved signal according to the data format, the sampling frequency, the real part data, and the imaginary part data of the interleaved signal.

Optionally, the direct digital frequency signal includes a sine value signal and a cosine value signal of the interleaved signal, and the step a13 of carrying out frequency carrying processing on the interleaved signal according to the direct digital frequency signal and the complex frequency domain signal to obtain an interleaved signal after frequency carrying includes:

And carrying out complex multiplication on the sine value signal, the cosine value signal and the complex frequency domain signal according to a preset frequency carrying rule to obtain an interleaved signal after frequency carrying.

Optionally, the step a14 of performing a combining process on the interleaved signal after frequency moving according to a preset rule to obtain a combined interleaved signal includes:

delay processing is carried out on the interleaved signals after frequency carrying according to the data format and the sampling frequency, so that at least two carrier signals are obtained, the at least two carrier signals correspond to the at least two carrier data, and one carrier signal comprises the at least two antenna signals;

and combining the at least two carrier signals to obtain combined interleaving signals.

Optionally, the peak clipping processing of the combined interleaved signal according to the preset hard peak clipping threshold in a15 includes:

calculating the amplitude value and the sine and cosine value of each sampling point of the combined interleaving signal;

if the amplitude value of at least one sampling point is smaller than or equal to a preset hard peak clipping threshold, taking the amplitude value as the amplitude value corresponding to the at least one sampling point in an output signal;

if the amplitude value of at least one sampling point is larger than a preset hard peak clipping threshold, taking the preset hard peak clipping threshold as the amplitude value corresponding to the at least one sampling point in an output signal;

And generating an output signal according to the sine and cosine values of the sampling points and the amplitude values of the sampling points in the output signal, wherein the output signal is an interleaved signal subjected to peak clipping.

Optionally, the calculating the amplitude value of each sampling point of the interleaved signal after combining includes:

performing rotation processing on the combined interleaving signals according to a preset rotation rule to obtain amplitude estimation values of all sampling points of the combined interleaving signals;

determining a compensation coefficient according to the rotation times;

and calculating the amplitude value of each sampling point of the combined interleaving signal according to the amplitude estimation value and the compensation coefficient.

Optionally, the product of the number of antenna signals of at least two antenna signals and the number of carriers of at least two carrier data contained in the interleaved signal is smaller than or equal to a preset number of signals, and the preset number of signals is equal to a ratio of a preset clock frequency to the sampling frequency.

In fig. 13, the bus interface is an interface to a bus architecture that may include any number of interconnected buses and bridges, with one or more processors, represented by processor 320, and various circuits of the memory, represented by memory 300, being linked together. The bus architecture may also link together various other circuits such as peripheral devices, voltage regulators, power management circuits, etc., which are well known in the art and, therefore, will not be described further herein. The bus interface provides an interface. Transceiver 310 may be a number of elements, including a transmitter and a receiver, providing a means for communicating with various other apparatus over a transmission medium, including wireless channels, wired channels, optical cables, etc. The processor 320 is responsible for managing the bus architecture and general processing, and the memory 300 may store data used by the processor 320 in performing operations.

The processor 320 may be a Central Processing Unit (CPU), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a Field-Programmable gate array (FPGA), or a complex Programmable logic device (Complex Programmable Logic Device, CPLD), and may also employ a multi-core architecture.

It should be noted that, the above device provided in the embodiment of the present invention can implement all the method steps implemented in the method embodiment and achieve the same technical effects, and detailed descriptions of the same parts and beneficial effects as those in the method embodiment in this embodiment are omitted.

Example IV

Referring to fig. 14, a block diagram of a multi-carrier data processing apparatus according to a fourth embodiment of the present invention specifically includes:

a data format obtaining module 401, configured to obtain a data format of an interleaved signal, where the interleaved signal includes at least two antenna signals and at least two carrier data, and sampling frequencies of the at least two carrier data are consistent;

a modulation signal determining module 402, configured to determine a direct digital frequency signal and a complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency;

The frequency-carrying processing module 403 is configured to carry out frequency-carrying processing on the interleaved signal according to the direct digital frequency signal and the complex frequency domain signal, so as to obtain an interleaved signal after frequency carrying;

the combining processing module 404 is configured to perform combining processing on the interleaved signal after frequency moving according to a preset rule to obtain a combined interleaved signal;

and the peak clipping processing module 405 is configured to perform peak clipping processing on the combined interleaved signal according to a preset hard peak clipping threshold.

Optionally, the multi-carrier data processing device further includes:

the carrier data acquisition module is used for acquiring at least two carrier data, wherein the sampling frequencies of the at least two carrier data are consistent, and the sampling frequency is a factor of a preset clock frequency;

the sequence determining module is used for determining the preset sequence of the at least two carrier data;

and the interleaving module is used for interleaving at least two antenna signals according to the preset sequence of the at least two carrier data to obtain interleaved signals.

Optionally, the modulation signal determining module 402 includes:

a frequency offset determining sub-module, configured to determine a frequency offset signal of the interleaved signal according to the data format and the sampling frequency;

A digital frequency signal generation sub-module for generating a direct digital frequency signal of the interleaved signal according to the frequency offset signal;

the complex frequency domain mapping submodule is used for mapping the interleaved signal to a complex frequency domain and acquiring real part data and imaginary part data of the interleaved signal;

and the modulation signal generation sub-module is used for generating a complex frequency domain signal of the interleaving signal according to the data format, the sampling frequency, the real part data and the imaginary part data of the interleaving signal.

Optionally, the direct digital frequency signal includes a sine value signal and a cosine value signal of the interleaved signal, and the frequency-moving processing module 403 includes:

and the frequency-carrying processing sub-module is used for carrying out complex multiplication on the sine value signal, the cosine value signal and the complex frequency domain signal according to a preset frequency-carrying rule to obtain an interleaved signal after frequency carrying.

Optionally, the combining processing module 404 includes:

the delay processing submodule is used for carrying out delay processing on the interleaved signals after frequency carrying according to the data format and the sampling frequency to obtain at least two carrier signals, the at least two carrier signals correspond to the at least two carrier data, and one carrier signal comprises the at least two antenna signals;

And the combining processing sub-module is used for combining the at least two carrier signals to obtain combined interweaved signals.

Optionally, the peak clipping processing module 405 includes:

the computing sub-module is used for computing the amplitude value and the sine and cosine value of each sampling point of the combined interleaving signal;

the first amplitude value determining submodule is used for taking the amplitude value of at least one sampling point as the amplitude value corresponding to the at least one sampling point in the output signal if the amplitude value of the at least one sampling point is smaller than or equal to a preset hard peak clipping threshold;

the second amplitude value determining submodule is used for taking the preset hard peak clipping threshold as the amplitude value corresponding to at least one sampling point in an output signal if the amplitude value of the at least one sampling point is larger than the preset hard peak clipping threshold;

and the output signal generation sub-module is used for generating an output signal according to the sine and cosine values of the sampling points and the amplitude values of the sampling points in the output signal, wherein the output signal is an interleaved signal subjected to peak clipping processing.

Optionally, the computing submodule includes:

the rotation processing unit is used for carrying out rotation processing on the combined interleaving signals according to a preset rotation rule to obtain amplitude estimated values of all sampling points of the combined interleaving signals;

A compensation coefficient determining unit for determining a compensation coefficient according to the number of rotations;

and the amplitude value calculation unit is used for calculating the amplitude value of each sampling point of the interleaved signal after the combination according to the amplitude estimation value and the compensation coefficient.

It should be noted that, in the embodiment of the present invention, the division of the modules and the units is schematic, which is merely a logic function division, and other division manners may be implemented in actual practice. In addition, each functional module and each functional unit in each embodiment of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a processor-readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Embodiments of the present invention also provide a processor-readable storage medium storing a computer program for causing a processor to perform the aforementioned method.

The processor-readable storage medium may be any available medium or data storage device that can be accessed by a processor, including, but not limited to, magnetic storage (e.g., floppy disks, hard disks, magnetic tape, magneto-optical disks (MOs), etc.), optical storage (e.g., CD, DVD, BD, HVD, etc.), semiconductor storage (e.g., ROM, EPROM, EEPROM, nonvolatile storage (NAND FLASH), solid State Disk (SSD)), and the like.

It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, magnetic disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-executable instructions. These computer-executable instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These processor-executable instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.

Claims

1. A method of multi-carrier data processing, the method comprising:

2. The method of claim 1, wherein prior to the obtaining the data format of the interleaved signal, the method further comprises:

determining a preset sequence of the at least two carrier data;

3. The method of claim 1, the determining the direct digital frequency signal and the complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency, comprising:

4. The method according to claim 1, wherein the direct digital frequency signal includes a sine value signal and a cosine value signal of the interleaved signal, and the performing the frequency-shifting processing on the interleaved signal according to the direct digital frequency signal and the complex frequency domain signal to obtain the frequency-shifted interleaved signal includes:

5. The method of claim 1, wherein the combining the interleaved signal after frequency moving according to a preset rule to obtain a combined interleaved signal comprises:

6. The method of claim 1, wherein the peak clipping the combined interleaved signal according to a preset hard peak clipping threshold comprises:

7. The method of claim 6, wherein said calculating the magnitude values of the respective sample points of the combined interleaved signal comprises:

determining a compensation coefficient according to the rotation times;

8. The method of claim 1, wherein the interleaved signal comprises at least two antenna signals having a product of a number of antenna signals and a number of carriers of at least two carrier data less than or equal to a preset number of signals, the preset number of signals being equal to a ratio of a preset clock frequency to the sampling frequency.

9. An apparatus comprising a memory, a transceiver, and a processor:

a memory for storing a computer program; a transceiver for transceiving data under control of the processor; a processor for reading the computer program in the memory and performing the following operations:

10. The apparatus of claim 9, wherein the processor is further configured to read a computer program in the memory and perform the following:

determining a preset sequence of the at least two carrier data;

11. The apparatus of claim 9, wherein said determining the direct digital frequency signal and the complex frequency domain signal of the interleaved signal based on the data format and the sampling frequency comprises:

12. The apparatus of claim 9, wherein the direct digital frequency signal comprises a sine value signal and a cosine value signal of the interleaved signal, wherein the frequency-shifting the interleaved signal according to the direct digital frequency signal and the complex frequency domain signal to obtain the frequency-shifted interleaved signal comprises:

13. The apparatus of claim 9, wherein the combining the interleaved signal after frequency moving according to a preset rule to obtain a combined interleaved signal comprises:

14. The apparatus of claim 9, wherein the peak clipping processing of the combined interleaved signal according to a preset hard peak clipping threshold comprises:

15. The apparatus of claim 14, wherein said calculating the magnitude values of the respective sample points of the combined interleaved signal comprises:

determining a compensation coefficient according to the rotation times;

16. The apparatus of claim 9, wherein the interleaved signal comprises at least two antenna signals having a product of a number of antenna signals and a number of carriers of at least two carrier data less than or equal to a preset number of signals, the preset number of signals being equal to a ratio of a preset clock frequency to the sampling frequency.

17. A multi-carrier data processing apparatus, the apparatus comprising:

18. A processor-readable storage medium, characterized in that the processor-readable storage medium stores a computer program for causing a processor to execute the method of any one of claims 1 to 8.