CN114513281A

CN114513281A - Multi-carrier data processing method, device and storage medium

Info

Publication number: CN114513281A
Application number: CN202011291501.1A
Authority: CN
Inventors: 郑向秀; 常静
Original assignee: Datang Mobile Communications Equipment Co Ltd
Current assignee: Datang Mobile Communications Equipment Co Ltd
Priority date: 2020-11-17
Filing date: 2020-11-17
Publication date: 2022-05-17
Anticipated expiration: 2040-11-17
Also published as: CN114513281B

Abstract

The invention provides a multi-carrier data processing method, a multi-carrier data processing device and a storage medium, and relates to the technical field of communication. The method comprises the following steps: acquiring a data format of an interleaved signal, wherein the interleaved signal comprises at least two antenna signals and at least two carrier data, and the sampling frequencies of the at least two carrier data are consistent; determining a direct digital frequency signal and a complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency; carrying out frequency shifting processing on the interleaved signal according to the direct digital frequency signal and the complex frequency domain signal to obtain a frequency-shifted interleaved signal; combining the frequency-shifted interleaved signals according to a preset rule to obtain combined interleaved signals; and performing peak clipping processing on the combined interweaved signal according to a preset hard peak clipping threshold. The invention can directly carry out peak clipping processing on the interleaved signal containing the multi-carrier data, thereby reducing the resource occupancy rate and improving the processing efficiency.

Description

Multi-carrier data processing method, device and storage medium

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a method and an apparatus for processing multicarrier data, and a storage medium.

Background

Currently, most of AAUs (Active Antenna units) adopt an operating mode supporting multi-carrier data, which requires that the internal components of the AAU have the capability of processing multi-carrier data.

In the prior art, a multi-carrier NCO (digitally Controlled Oscillator) model is used to process multi-carrier data, taking interleaved data of two antennas of three carriers in a downlink as an example, referring to fig. 1, an implementation structure diagram of an NCO model in the prior art is shown, which includes dds _ config (carrier frequency offset selection module), dds _ core (direct digital frequency synthesis module), data _ delay (data delay module), mixer (complex modulation module), add (combiner module), and mag _ protect (hard-cut module). The carrier frequency offset selection module is used for realizing the offset selection function of carrier signals, and different carrier offsets are different; the direct digital frequency synthesis module is a DDS module based on LUT and is used for generating a data sample of sine wave and cosine wave with variable frequency and discrete time; the data delay module delays the input data to align with the generated sine wave and cosine wave; the complex modulation module multiplies the real part and the imaginary part of the input data after the time delay with the corresponding sine value and cosine value in the LUT table to realize the frequency shifting of the input data; the combining module is used for carrying out addition operation on the carrier data after frequency shifting; the hard peak clipping module is mainly used for calculating the peak value of each sampling point of the carrier data after combination, finding out the sampling point which is larger than the threshold value and replacing the sampling point with the threshold value, and therefore reducing the peak-to-average ratio to a certain extent.

As can be seen from the implementation structure of the NCO model shown in fig. 1, when processing multi-carrier data in the prior art, one carrier data corresponds to a group of carrier frequency offset selection module, direct digital frequency synthesis module, data delay module and complex modulation module, and processes one input data interleaved with three carriers, which is equivalent to an NCO model that needs three carriers to process single carrier data, so that the resource occupancy rate is increased.

Disclosure of Invention

The invention provides a multi-carrier data processing method, a multi-carrier data processing device and a storage medium, which are used for solving the problems of high resource occupancy rate and low processing efficiency of multi-carrier data in the prior art.

According to a first aspect of the present invention, there is provided a multicarrier data processing method, the method comprising:

acquiring a data format of an interleaved signal, wherein the interleaved signal comprises at least two antenna signals and at least two carrier data, and the sampling frequencies of the at least two carrier data are consistent;

determining a direct digital frequency signal and a complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency;

carrying out frequency shifting processing on the interleaved signal according to the direct digital frequency signal and the complex frequency domain signal to obtain a frequency-shifted interleaved signal;

combining the frequency-shifted interleaved signals according to a preset rule to obtain combined interleaved signals;

and performing peak clipping processing on the combined interweaved signal according to a preset hard peak clipping threshold.

According to a second aspect of the invention, there is provided an apparatus comprising a memory, a transceiver, a processor: a memory for storing a computer program; a transceiver for transceiving data under the control of the processor; a processor for reading the computer program in the memory and performing the following operations:

According to a third aspect of the present invention, there is provided a multicarrier data processing apparatus comprising:

the data format acquiring module is used for acquiring a data format of an interleaved signal, wherein the interleaved signal comprises at least two antenna signals and at least two carrier data, and the sampling frequencies of the at least two carrier data are consistent;

a modulation signal determination module for determining a direct digital frequency signal and a complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency;

the frequency shifting processing module is used for carrying out frequency shifting processing on the interleaved signal according to the direct digital frequency signal and the complex frequency domain signal to obtain an interleaved signal after frequency shifting;

the combining processing module is used for combining the frequency-shifted interleaved signals according to a preset rule to obtain combined interleaved signals;

and the peak clipping processing module is used for carrying out peak clipping processing on the combined interweaved signal according to a preset hard peak clipping threshold.

According to a fourth aspect of the invention, there is provided a processor-readable storage medium having stored thereon a computer program for causing a processor to perform the aforementioned method.

The invention provides a multi-carrier data processing method, a device and a storage medium, wherein the method comprises the following steps: acquiring a data format of an interleaved signal, wherein the interleaved signal comprises at least two antenna signals and at least two carrier data, and the sampling frequencies of the at least two carrier data are consistent; determining a direct digital frequency signal and a complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency; carrying out frequency shifting processing on the interleaved signal according to the direct digital frequency signal and the complex frequency domain signal to obtain a frequency-shifted interleaved signal; combining the frequency-shifted interleaved signals according to a preset rule to obtain combined interleaved signals; and performing peak clipping processing on the combined interweaved signal according to a preset hard peak clipping threshold. The invention can directly carry out peak clipping processing on the interleaved signal containing the multi-carrier data, thereby reducing the resource occupancy rate and improving the processing efficiency.

The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.

FIG. 1 is a schematic diagram of an implementation structure of a prior NCO model;

fig. 2 is a flowchart illustrating specific steps of a method for processing multicarrier data according to an embodiment of the present invention;

FIG. 3 is a diagram of a data input format of a prior art NCO model;

FIG. 4 is a schematic diagram of an NCO model implementation structure provided in the first embodiment of the present invention;

FIG. 5 is a schematic diagram of a data input format of an NCO model according to an embodiment of the present invention;

FIG. 6 is a timing diagram of a complex frequency domain signal of a direct digital frequency signal and a complex modulation signal according to an embodiment of the present invention;

fig. 7 is a flowchart illustrating specific steps of a method for processing multicarrier data according to a second embodiment of the present invention;

fig. 8 is a schematic diagram of shifting a frequency spectrum of a carrier signal according to a second embodiment of the present invention;

fig. 9 is a timing diagram of a carrier frequency offset signal according to a second embodiment of the present invention;

fig. 10 is a schematic structural diagram of a LUT-based DDS module according to a second embodiment of the present invention;

fig. 11 is a timing diagram of a three-carrier interleaved signal according to a second embodiment of the present invention;

fig. 12 is a schematic structural diagram of a mag _ protect module according to a second embodiment of the present invention;

FIG. 13 is a block diagram of an apparatus according to a third embodiment of the present invention;

fig. 14 is a block diagram of a multicarrier data processing apparatus according to a fourth embodiment of the invention.

Detailed Description

The term "and/or" in the embodiments of the present invention describes an association relationship of associated objects, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

The term "plurality" in the embodiments of the present invention means two or more, and other terms are similar thereto.

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example one

Referring to fig. 2, a flowchart illustrating specific steps of a multicarrier data processing method according to an embodiment of the present invention is shown.

Step 101, obtaining a data format of an interleaved signal, where the interleaved signal includes at least two antenna signals and at least two carrier data, and sampling frequencies of the at least two carrier data are the same.

In the embodiment of the present invention, when the preset clock frequency is a multiple of the sampling frequency of the carrier data, at least two carrier data are interleaved to obtain an interleaved signal, for example, there are three single carrier two antenna signals c0a0c0a1, c1a0c1a1, and c2a0c2a1, where c0, c1, and c2 are three carriers respectively, the antenna a0 and the antenna a1 correspond to one carrier respectively, the sampling frequencies of the three carriers c0, c1, and c2 are consistent, and the preset clock frequency is a multiple of the sampling frequency, the three single carrier two antenna signals are interleaved to three carrier two antenna signals to obtain the interleaved signal.

The preset clock frequency is an operating frequency of a device for executing the multi-carrier data processing method provided by the embodiment of the invention.

When the preset clock frequency is a multiple of the carrier data, if the multi-carrier data processing method provided in the prior art is adopted, the interleaving signal of the multi-carrier data needs to be deinterleaved according to the carrier to obtain each single carrier data, the single carrier data is processed respectively, and then the output data corresponding to each carrier data is re-interleaved to obtain the final output signal. Taking the conventional implementation structure of the NCO model shown in fig. 1 as an example, when the conventional NCO model is used to process the interleaved signals corresponding to the three carriers c0, c1, and c2, the interleaved signals need to be split into single carrier signals, and the three split single carrier signals need to be input into and output from the NCO model for data processing.

Referring to fig. 3, a schematic diagram of a data input format of an existing NCO model is shown, in which sampling frequencies of a carrier c0, a carrier c1 and a carrier c2 are identical, and a Clock frequency of a Clock signal Clock is 8 times of the sampling frequency of three carriers. In fig. 3, the signal frequency of the signal x8_ hd is consistent with the sampling frequency of three carriers, and generally, the FPGA is used for signal processing, and assuming that the clock frequency of the FPGA is 491.52MHZ and the sampling frequency of the three carriers is 61.44MHZ, since the FPGA adopts a parallel processing mode, the FPGA can process 8 channels of data of the signal with the sampling frequency of 61.44MHZ in parallel in one signal period of the x8_ hd signal. In fig. 3, the single-carrier two-antenna signals data _ c0, data _ c1 and data _ c2 corresponding to the carrier c0, the carrier c1 and the carrier c2 have only two paths of valid data in one signal period, and taking the single-carrier two-antenna signal data _ c0 as an example, the signal data _ c0 has only two paths of valid data, i.e., c0a0 and c0a1, in one signal period. The signals freq _ c0, freq _ c1, and freq _ c2 in fig. 3 are frequency offset signals corresponding to the carrier c0, the carrier c1, and the carrier c2, respectively. The freq _ c0 signal in fig. 3 is the input signal dds _ fre (c0) of the dds _ config block in fig. 1, and similarly, the freq _ c1 signal is the input signal dds _ fre (c1), and the freq _ c2 signal is the input signal dds _ fre (c 2).

As can be seen from fig. 1 and fig. 3, for the interleaved signals of three carriers and two antennas, the processing method in the prior art is adopted, the interleaved signals need to be split into single carrier signals according to carriers, and then each single carrier signal is processed and then output in a combined manner, one single carrier signal needs a group of carrier frequency offset selecting module, direct digital frequency synthesizing module, data delay module and complex modulating module, the interleaved signals of one three carriers and two antennas are processed, which is equivalent to the need of three NCO models for processing single carrier data, and this increases resource occupancy rate undoubtedly. Therefore, the embodiment of the invention improves the existing NCO model.

Referring to fig. 4, a schematic diagram of an NCO model implementation structure provided by the embodiment of the present invention is shown. Unlike the conventional NCO model shown in fig. 1, in the NCO model provided by the embodiment of the present invention, the input signal of dds _ config (carrier frequency offset selection module) is an interleaved signal of multi-carrier data, not a single-carrier signal. Taking three-carrier two-antenna signals as an example, referring to fig. 5, a schematic diagram of a data input format of an NCO model provided by the embodiment of the present invention is shown, where the Signal data in fig. 5 is a complex frequency domain Signal corresponding to the interleaved three-carrier two-antenna Signal, that is, an input Signal in of the data _ delay module in fig. 4; the freq signal is a frequency offset signal corresponding to an interleaved signal of three-carrier two-antenna, and the freq signal in fig. 5 is an input signal dds _ fre of the dds _ config module in fig. 4.

As can be seen from fig. 4 and fig. 5, in the embodiment of the present invention, the interleaved signal may be directly processed, and taking a three-carrier two-antenna signal as an example, by using the NCO model provided in the embodiment of the present invention, only one set of carrier frequency offset selection module, direct digital frequency synthesis module, data delay module, and complex modulation module is required, thereby reducing the resource occupancy rate.

In this embodiment of the present invention, a product of the number of antenna signals of at least two antenna signals and the number of carriers of at least two carrier data included in the interleaved signal is less than or equal to a preset signal number, where the preset signal number is equal to a ratio of a preset clock frequency to the sampling frequency.

The product of the number of antenna signals of at least two antenna signals and the number of carriers of at least two carrier data included in the interleaved signal is the number of signals included in the interleaved signal, for example, an interleaved signal of three-carrier two-antenna signals includes 6 channels of signals. The preset number of signals is the maximum number of signals that the interleaved signal can contain. In order to ensure that the interleaved signal can contain the sampling point of each interleaved single-carrier two-antenna signal in one signal period, the number of signals in the interleaved signal cannot be greater than the ratio of the preset clock frequency to the sampling frequency.

In the embodiment of the present invention, the dds _ config module, the dds _ core module, and the data _ delay module all input interleaved signals, but when processing signals inside the modules, data processing is performed on each carrier according to the data format of the interleaved signals, so in the embodiment of the present invention, the data format of the interleaved signals needs to be determined in advance to determine the data processing rule of each module and the data format of the output data of each module. Taking the three-carrier two-antenna interleaved signal as an example, referring to fig. 5, in one signal period, data of the interleaved signal data is arranged according to a preset order of a carrier c0, a carrier c1, and a carrier c2, antenna signals corresponding to each carrier are arranged according to a preset order of an antenna a0 and an antenna a1, and a frequency offset signal freq corresponding to the interleaved signal is obtained according to a data format of the interleaved signal data, as can be seen from fig. 5, data of the freq signal is arranged according to a preset order of a carrier c0, a carrier c1, and a carrier c2, so that when the freq signal shown in fig. 5 is input to the dds _ config module shown in fig. 4, the dds _ config module can determine which carrier the frequency offset to be generated corresponds to according to the data format and the clock frequency of the freq signal.

Step 102, determining a direct digital frequency signal and a complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency.

Specifically, after the data format of the interleaved signal is obtained, the direct digital frequency synthesis module and the complex modulation module in the NCO model can determine which carrier the data to be processed belongs to according to the multiple relation between the clock frequency and the sampling frequency of the carrier in the embodiment of the present invention, and generate the output signal according to the data format of the interleaved signal. The direct digital frequency signal comprises a sine wave signal and a cosine wave signal, and the complex frequency domain signal comprises a real part signal and an imaginary part signal of the interleaved signal on a complex frequency domain.

Taking three-carrier two-antenna signals as an example, referring to fig. 6, a timing diagram of a direct digital frequency signal and a complex frequency domain signal according to an embodiment of the present invention is shown. When the frequency offset signal freq shown in fig. 5 is input to the dds _ config module shown in fig. 4, the dds _ config module outputs the frequency offset corresponding to each carrier according to the input freq data format. The dds _ config module converts the input frequency offset signal into a digital pulse signal according to the multiple relationship between the clock frequency and the sampling frequency, so that the dds _ core module generates a sine wave signal and a cosine wave signal corresponding to each carrier wave according to the input digital pulse signal, and the sin signal shown in fig. 6 is the sine wave signal generated according to the digital pulse signal output by the dds _ config module shown in fig. 4. The sine wave signal generated by the dds _ core module is only related to the carrier, and is not related to the antenna, and the phase difference between the sine wave signal and the cosine wave signal corresponding to the same carrier is 90 degrees, so in order to avoid redundancy, the embodiment of the present invention is exemplified by the sine wave signal.

It should be noted that the Signal data in fig. 5 and fig. 6 in the embodiment of the present invention is a complex frequency domain Signal of the three-carrier two-antenna Signal in the complex frequency domain, that is, the input Signal in of the data _ delay module in fig. 4. The data _ delay module is used for delaying the input complex frequency domain signal, so that the phase of each sampling point of the output delayed complex frequency domain signal is consistent with that of the direct digital frequency signal output by the dds _ core module in fig. 4, thereby facilitating complex multiplication. The complex frequency domain signal data comprises a real part signal data _ i and an imaginary part signal data _ q corresponding to the interleaved signal, and the complex frequency domain signal is divided into two paths of data of the real part signal data _ i and the imaginary part signal data _ q to be input to the data _ delay module. The data format of the real and imaginary signals data _ i and data _ q is the same as that of the interleaved signal. As can be seen from fig. 6, the data format of the sine wave signal generated by the dds _ core module corresponds to the data format of the complex frequency domain signal data.

And 103, carrying out frequency shifting processing on the interleaved signal according to the direct digital frequency signal and the complex frequency domain signal to obtain a frequency-shifted interleaved signal.

The frequency shifting processing is performed on the interleaved signal, namely, the frequency spectrum of the interleaved signal is translated. Specifically, complex multiplication is performed on the direct frequency signal obtained in step 102 and the complex frequency domain signal, so that frequency shifting of the interleaved signal can be realized. The signal data _ in shown in fig. 6 is an interleaved signal after the frequency shifting.

And 104, combining the frequency-shifted interleaved signals according to a preset rule to obtain combined interleaved signals.

As can be seen from the timing diagram of the interleaved signal data _ in after the frequency shifting shown in fig. 6, the data format of the interleaved signal after the frequency shifting is the same as the data format of the interleaved signal initially input to the NCO module, and the interleaved signal is interleaved according to the preset order of the carrier c0, the carrier c1 and the carrier c2, while the mag _ protect module shown in fig. 4 performs the peak clipping process on the interleaved data of the antenna signal, that is, the peak clipping process is performed on the antenna signal according to the preset order of the antenna signal, so that before the peak clipping process is performed, the interleaved signal after the frequency shifting needs to be combined, specifically, the interleaved signal after the frequency shifting needs to be split by the diff _ car _ data _ delay module in fig. 4 to obtain a single carrier signal, and the obtained single carrier signal is synthesized by the add module to obtain the interleaved signal of the antenna signal.

And 105, performing peak clipping processing on the combined interleaved signal according to a preset hard peak clipping threshold.

Specifically, calculating an amplitude value of each sampling point of the combined interleaved signal, comparing the amplitude value of each sampling point with a preset hard peak clipping threshold, and if the amplitude value of at least one sampling point is smaller than or equal to the preset hard peak clipping threshold, taking the amplitude value as the amplitude value corresponding to the at least one sampling point in the output signal; and if the amplitude value of at least one sampling point is larger than a preset hard peak clipping threshold, taking the preset hard peak clipping threshold as the amplitude value corresponding to the at least one sampling point in the output signal.

In summary, in the embodiments of the present invention, the interleaved signal including the multicarrier data is directly input into the NCO model, and the corresponding modulation signal is generated according to the data format of the interleaved signal, so that the peak clipping processing on the multicarrier data is performed by using a group of carrier frequency offset selection module, direct digital frequency synthesis module, complex modulation module, and hard peak clipping module, thereby reducing the resource occupancy rate and improving the processing efficiency.

Example two

Referring to fig. 7, a flowchart illustrating specific steps of a multicarrier data processing method according to a second embodiment of the present invention is shown.

Step 201, at least two carrier data are obtained, sampling frequencies of the at least two carrier data are consistent, and the sampling frequency is a factor of a preset clock frequency.

The preset clock frequency is an operating frequency of a device for executing the multi-carrier data processing method provided by the embodiment of the present invention, for example, a clock frequency of an FPGA (Field Programmable Gate Array). Taking the NCO model shown in fig. 4 provided by the present invention as an example, the preset clock frequency is the operating frequency of the NCO model, and in the NCO model shown in fig. 4, the operating frequencies of the modules are consistent and can be represented by the clock frequency.

In the embodiment of the invention, when the sampling frequencies of at least two carriers are consistent, and the sampling frequency is a factor of the preset clock frequency, namely the preset clock frequency is a multiple of the sampling frequency, the at least two carriers can be interleaved to obtain the interleaved signals of multiple carriers, and then the multi-carrier data processing method provided by the invention is directly adopted to process the interleaved signals of the multiple carriers without separately processing each carrier data, thereby reducing the resource occupancy rate and improving the data processing efficiency.

Step 202, determining a preset sequence of the at least two carrier data.

Step 203, interleaving the at least two antenna signals according to the preset sequence of the at least two carrier data to obtain an interleaved signal.

After at least two carrier data meeting the preset condition are obtained, the preset sequence of the carrier data can be set, and at least two antenna signals corresponding to the carriers are interleaved according to the preset sequence of the carriers to obtain interleaved signals, so that the data formats of the interleaved signals are the same in each signal period, and the interleaved signals are further processed conveniently. For example, there are three single-carrier two-antenna signals c0a0c0a1, c1a0c1a1, and c2a0c2a1, where c0, c1, and c2 are three carriers, each of the antenna a0 and the antenna a1 corresponds to one carrier, sampling frequencies of the carrier c0, the carrier c1, and the carrier c2 are consistent, and the preset clock frequency is a multiple of the sampling frequency, then the three single-carrier two-antenna signals may be interleaved into three-carrier two-antenna signals according to a preset order of the carrier c0, the carrier c1, and the carrier c2 to obtain an interleaved signal, and the three single-carrier two-antenna signals may also be interleaved according to another preset order, for example: the carrier c0, the carrier c2, and the carrier c1, or the carrier c1, the carrier c2, and the carrier c0, which is not specifically limited in this embodiment of the present invention. In the embodiment of the present invention, a preset sequence of a carrier c0, a carrier c1, and a carrier c2 is used for illustration, as shown in fig. 5, a signal data is a timing diagram of a three-carrier two-antenna signal obtained by interleaving according to a preset sequence of a carrier c0, a carrier c1, and a carrier c2, where c0a0, c0a1, c1a0, c1a1, c2a0, and c2a1 are listed sampling points, and as can be seen from fig. 5, in each signal period, data of an interleaved signal is arranged according to the preset sequence.

The product of the number of antenna signals of at least two antenna signals included in the interleaved signal and the number of carriers of at least two carrier data is the number of signals included in the interleaved signal, for example, the interleaved signal of three-carrier two-antenna signals includes 6 channels of signals. The preset number of signals is the maximum number of signals that the interleaved signal can contain. In order to ensure that the interleaved signal can contain the sampling point of each interleaved single-carrier two-antenna signal in one signal period, the number of signals in the interleaved signal cannot be greater than the ratio of the preset clock frequency to the sampling frequency.

Taking the three-carrier two-antenna signal as an example, referring to fig. 5, the signal data is a complex frequency domain signal corresponding to the interleaved three-carrier two-antenna signal, the signal frequency of the Clock signal Clock is the preset Clock frequency in the embodiment of the present invention, and the signal frequency of the signal x8_ hd is consistent with the sampling frequency of three carriers, as can be seen from fig. 5, the preset Clock frequency of the Clock signal Clock is 8 times the sampling frequency of the interleaved signal data, that is, the signal period of the interleaved signal data is 8 times the signal period of the Clock signal Clock, and at most 8 paths of data can be contained in one signal period of the interleaved signal.

Step 204, obtaining the data format of the interleaved signal.

As can be seen from step 201 to step 203, in the embodiment of the present invention, the interleaved signal includes at least two antenna signals and at least two carrier data, and sampling frequencies of the at least two carrier data are the same.

This step may specifically refer to step 101, and further details of the embodiment of the present invention are not described herein.

Step 205, determining a direct digital frequency signal and a complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency.

This step may specifically refer to step 102, and further description of the embodiments of the present invention is not repeated herein.

In an optional embodiment of the present invention, the determining 205 a direct digital frequency signal and a complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency comprises:

step S11, determining a frequency offset signal of the interleaved signal according to the data format and the sampling frequency.

Step S12, generating a direct digital frequency signal of the interleaved signal according to the frequency offset signal.

Step S13, mapping the interleaved signal to a complex frequency domain, and obtaining real part data and imaginary part data of the interleaved signal.

Step S14, generating a complex frequency domain signal of the interleaved signal according to the data format of the interleaved signal, the sampling frequency, the real part data, and the imaginary part data.

In combination with the foregoing, in this embodiment of the present invention, in each signal period of the interleaved signal, the data in each channel is arranged according to a preset sequence of at least two carriers included in the interleaved signal, and in each signal period, the arrangement manner of the data is the data format of the interleaved signal in this embodiment of the present invention. The frequency offset is a value to be shifted for the frequency spectrum of each carrier. The NCO model shown in fig. 4 provided in the embodiment of the present invention essentially shifts the frequency spectrum of different carrier signals according to the requirement, and then performs peak clipping on the interleaved signal after frequency shifting and combining. Therefore, in the embodiment of the present invention, it is first necessary to determine the frequency offset of each carrier in the interleaved signal. Referring to fig. 8, a schematic diagram of shifting a spectrum of a carrier signal according to an embodiment of the present invention is shown. As can be seen from fig. 8, since the amount of shifting of the frequency spectrum is different for different carriers, the frequency offset is different for different carriers. The frequency offset is carrier dependent only and antenna independent. In the embodiment of the present invention, in the NCO model shown in fig. 4, the dds _ fre signal input by the dds _ config module is a frequency offset signal freq of an interleaved signal, as can be seen from fig. 5, the frequency offset signal freq is arranged according to a preset sequence of the carrier c0, the carrier c1 and the carrier c2, and the dds _ config module needs to generate a corresponding digital pulse signal according to the input frequency offset signal freq, so that the dds _ core module identifies a frequency offset according to the received digital pulse signal and generates a corresponding sine wave signal and cosine wave signal, therefore, in order to identify data corresponding to each carrier in the interleaved frequency offset signal freq, the embodiment of the present invention improves the dds _ config module, and the inside of the dds _ config module can select and process data corresponding to the carrier by using a sel signal.

Taking three-carrier two-antenna signals as an example, referring to fig. 9, a timing diagram of a carrier frequency offset signal according to an embodiment of the present invention is shown. The frequency offset signal freq interleaved according to the carrier is input to the dds _ config module in fig. 4, and the digital pulse signal of the frequency offset corresponding to each carrier is generated according to the count value corresponding to the sel signal, so as to obtain the pulse signal freq _ in of the frequency offset corresponding to the interleaved signal. The sel signal is a digital signal corresponding to a counter value generated by a counter, and the count value of the counter is 0 to (N-1), wherein N is the ratio of a preset clock frequency to a sampling frequency. Taking the example of N being 8 shown in fig. 9, the preset sequence of three carriers is carrier c0, carrier c1 and carrier c1, and one carrier corresponds to two antenna signals, so that one carrier corresponds to two count values, so that when the count value is 0 or 1, the dds _ config module outputs a digital pulse signal (freq _ c0) corresponding to the frequency offset corresponding to carrier c0, and by analogy, when the count value is 2 or 3, the dds _ config module outputs a digital pulse signal (freq _ c1) corresponding to the frequency offset corresponding to carrier c1, and when the count value is 4 or 5, the dds _ config module outputs a digital pulse signal (freq _ c2) corresponding to the frequency offset corresponding to carrier 2. Since there is currently three-carrier two-antenna data, when the count value is 6 or 7, there is no corresponding data input, and the dds _ config module may output 0. In practical applications, the dds _ config module outputs an interleaved digital pulse signal freq _ in, and in order to explain the operation principle of the dds _ config module, the embodiment of the present invention introduces a digital pulse signal freq _ c0, a digital pulse signal freq _ c1, and a digital pulse signal freq _ c2 for explanation, and actually, the dds _ config module only needs to directly output the interleaved digital pulse signal freq _ in according to the input frequency offset signal freq and sel signal.

The output signal freq _ in of the dds _ config block in fig. 4 is input to the dds _ core block, and the dds _ core block generates a corresponding sine wave signal and cosine wave signal according to the input digital pulse signal with frequency offset. The DDS _ core module in the NCO model provided by the embodiment of the present invention is actually a DDS (Direct Digital Synthesis) module based on a Look-Up Table (LUT), and is composed of a phase accumulator and a waveform memory. Referring to fig. 10, a schematic diagram of a structure of a LUT-based DDS module according to an embodiment of the present invention is shown, in which a phase accumulator is used to convert a received digital pulse signal with a frequency offset into a phase, and each time a digital pulse is received, a phase increment is added to a phase value corresponding to the digital pulse. The waveform memory is an LUT in the FPGA, the LUT stores waveform data of one cycle according to a phase, in practical application, matlab may be used to generate sine wave data or cosine wave data to be stored, taking sine wave data as an example, sine wave data stored in the sin LUT shown in fig. 10 may be represented as:

where N is the depth of the LUT, and assuming that the bit width of the phase accumulator is N bits, the depth N of the LUT is 2ⁿ. In practical application, the sine value corresponding to each phase value of the sine wave generated by the DDS module can be calculated in advance according to the formula (1), the phase value corresponding to each sine value is used as a storage address, and the calculated sine value is stored in the LUT. When the DDS module receives a sampling point of a carrier signal, a phase value is generated, a sine value corresponding to the phase value is searched in the LUT according to the generated phase value, and the searched sine value is used as the sampling pointThe amplitude value of the corresponding sine wave signal.

Assuming the step value of the phase accumulator bit in fig. 10 is μ, the sampling frequency of the interleaved signal is f_sThe center frequency f of sine wave and cosine wave output by DDS_cExpressed as:

the step value μ of the bit of the phase accumulator is also the frequency control word of the carrier, and the frequency control word of the carrier is used to indicate the frequency offset of the carrier when the frequency spectrum of the carrier signal is shifted, as can be seen from formula (2), the center frequencies of the sine wave and the cosine wave output by the DDS module are related to the value of the frequency spectrum of the carrier that needs to be shifted.

And calculating the amplitude value of the sampling point of the carrier signal corresponding to the sine wave signal according to the formula (1), and calculating the center frequency of the sine wave signal corresponding to the carrier signal according to the formula (2), so as to generate the sine wave signal corresponding to the carrier signal according to the amplitude value and the center frequency of each sampling point. The phase difference between the sine wave signal and the cosine wave signal corresponding to the same carrier is 90 degrees, and therefore, in order to avoid redundancy, the sine wave signal is exemplified in the embodiment of the present invention. As shown in fig. 6, the signal sin is a sine wave signal corresponding to a three-carrier two-antenna signal generated by the NCO model according to the embodiment of the present invention.

In the embodiment of the present invention, because the carrier signal needs to be subjected to spectrum shifting, in order to facilitate data processing, the time-domain interleaved signal needs to be mapped to the complex frequency domain through fourier transform, so as to obtain the complex frequency domain signal of the interleaved signal. Specifically, real part data and imaginary part data of each sampling point of the interleaved signal are calculated, and a complex frequency domain signal of the interleaved signal is generated according to the data format and the sampling frequency of the interleaved signal. In the NCO model shown in fig. 4, the input Signal in of the data _ delay module is the complex frequency domain Signal of the interleaved Signal, i.e. the Signal data in fig. 5. The complex frequency domain signal data comprises a real part signal data _ i and an imaginary part signal data _ q corresponding to the interleaved signal, the complex frequency domain signal is divided into two paths of data of the real part signal data _ i and the imaginary part signal data _ q to be input into the data _ delay module, and the data _ delay module carries out delay processing on the input complex frequency domain signal, so that the phases of each sampling point of the delayed complex frequency domain signal and each sampling point of the sine wave signal and the cosine wave signal output by the dds _ core module are consistent, and complex multiplication is convenient to carry out.

And step 206, the direct digital frequency signal includes a sine value signal and a cosine value signal of the interleaved signal, and the sine value signal, the cosine value signal and the complex frequency domain signal are subjected to complex multiplication according to a preset frequency shifting rule to obtain a frequency-shifted interleaved signal.

The frequency shifting processing is performed on the interleaved signal, namely, the frequency spectrum of the interleaved signal is translated. Specifically, the sine wave signal and the cosine wave signal output by the sum dds _ core module and the delayed complex frequency domain signal output by the data _ delay module are input to the mixer module in fig. 4 for complex multiplication, so as to carry out frequency shifting on the interleaved signal. The signal data _ in shown in fig. 6 is an interleaved signal after the frequency shifting.

Specifically, assume that, in a sine wave signal output by any sampling point P, dds _ core module of the interleaved signal in the embodiment of the present invention, a sine value corresponding to the sampling point P is sin_pDds _ core module outputs cosine wave signal, where the cosine value corresponding to the sampling point P is cos_pIf the real part value corresponding to the sampling point P is I and the imaginary part value is Q, then, in the interleaved signal after frequency shifting, the real part value corresponding to the sampling point is I and the imaginary part value is Q may be respectively expressed as:

I＝i*(cos_p+sin_p)-sin_p*(i+q) (3)

Q＝i*(cos_p+sin_p)+cos_p*(q-i) (4)

according to the formula (3) and the formula (4), the real part value and the imaginary part value corresponding to each sampling point in the interlaced signal after frequency shifting can be calculated. The mixer module receives a sine value, a cosine value, real part data and imaginary part data corresponding to a sampling point, and calculates the real part value and the imaginary part value corresponding to the sampling point after frequency shifting through the formula (3) and the formula (4), thereby outputting an interleaved signal data _ in after frequency shifting.

And step 207, performing time delay processing on the frequency-shifted interleaved signal according to the data format and the sampling frequency to obtain at least two carrier signals.

Wherein the at least two carrier signals correspond to the at least two carrier data, one of the carrier signals containing the at least two antenna signals.

And 208, combining the at least two carrier signals to obtain a combined interleaved signal.

As can be seen from the timing diagram of the interleaved signal data _ in after the frequency shifting shown in fig. 6, the data format of the interleaved signal after the frequency shifting is the same as the data format of the interleaved signal initially input to the NCO module, and the interleaved signal is interleaved according to the preset order of the carrier c0, the carrier c1 and the carrier c2, while the mag _ protect module shown in fig. 4 performs the peak clipping process on the interleaved data of the antenna, that is, the peak clipping process is performed on the antenna signal according to the preset order of the antenna signal, so before the peak clipping process is performed, the interleaved signal after the frequency shifting needs to be combined, specifically, the interleaved signal after the frequency shifting is split by the diff _ car _ data _ delay module in fig. 4 to obtain single carrier data, and the obtained single carrier data is synthesized by the add module to obtain the interleaved signal of the antenna signal.

Taking three-carrier two-antenna signals as an example, referring to fig. 11, a timing diagram of a three-carrier interleaved signal according to an embodiment of the present invention is shown. The Clock signal is a Clock signal, the signal frequency is a preset Clock frequency, the sel signal is a digital signal corresponding to a count value generated by a counter in an NCO model, the signal data _ in is an input signal of a diff _ car _ data _ delay module in fig. 4, that is, an interleaved signal after frequency shifting, because the interleaved signal data _ in after frequency shifting includes two antenna signals, two Clock cycles correspond to a signal corresponding to a carrier in a signal cycle of an interleaved signal, if the interleaved signal is to be split into a single carrier signal according to the carrier, and when the interleaved signal is subjected to delay processing, the number of Clock cycles of delay needs to be a multiple of the number of antennas included in the interleaved signal, so that the single carrier signal including all the antenna signals in the interleaved signal can be obtained by splitting the interleaved signal after delay.

Since the shifted interleaved signal data _ in shown in fig. 11 is a three-carrier two-antenna interleaved signal, the shifted interleaved signal data _ in is delayed by 2 clock cycles to obtain the signal data _ in _ d2, and the shifted interleaved signal data _ in is delayed by 4 clock cycles to obtain the signal data _ in _ d 4. As can be seen from fig. 11, when the count values corresponding to the sel signals are 4 and 5, the signal data _ in corresponds to the two antenna signals C2a0 and C2a1 of the carrier C2, the signal data _ in _ d2 corresponds to the two antenna signals C1a0 and C1a1 of the carrier C1, and the signal data _ in _ d4 corresponds to the two antenna signals C0a0 and C0a1 of the carrier C0, at this time, the signal data _ m is introduced, and when the count values corresponding to the sel signals are 4 and 5, the signal data _ m outputs a valid value C _ ALL. The signal sel _ en outputs a high level when the signal data _ m outputs a valid value C _ ALLA _ ALL, and outputs a low level when the signal data _ m outputs other values. Multiplying the signal sel _ en by the signal data _ in to obtain a signal data _ out _ C2, wherein the signal data _ out _ C2 only comprises two antenna signals C2A0 and C2A1 of the carrier C2; multiplying the signal sel _ en by the signal data _ in _ d2 to obtain a signal data _ out _ C1, wherein the signal data _ out _ C1 only comprises two antenna signals C1A0 and C1A1 of the carrier C1; the signal sel _ en is multiplied by the signal data _ in _ d4 to obtain a signal data _ out _ C0, and the signal data _ out _ C0 only includes two antenna signals C0a0 and C0a1 of the carrier C0. Thus, a single carrier signal after separation is obtained.

And then combining the separated single-carrier signals data _ out _ c0, data _ out _ c1 and data _ out _ c2 to obtain a combined interleaved signal data _ out, as can be seen from fig. 11, the concept that no carrier exists in the data format corresponding to the combined interleaved signal data _ out, which is the interleaved signal of the antenna a0 and the antenna a 1.

And 209, performing peak clipping processing on the combined interleaved signal according to a preset hard peak clipping threshold.

This step may specifically refer to step 105, and further description of the embodiments of the present invention is not repeated herein.

In an optional embodiment of the present invention, the performing, in step 209, peak clipping processing on the combined interleaved signal according to a preset hard peak clipping threshold includes:

and step S21, calculating the amplitude value and the sine and cosine value of each sampling point of the combined interleaved signal.

In step S22, if the amplitude value of at least one sampling point is smaller than or equal to the preset hard peak clipping threshold, the amplitude value is used as the amplitude value corresponding to the at least one sampling point in the output signal.

Step S23, if the amplitude value of at least one sampling point is greater than a preset hard peak clipping threshold, taking the preset hard peak clipping threshold as the amplitude value corresponding to the at least one sampling point in the output signal.

And step S24, generating an output signal according to the sine and cosine values of the sampling points and the amplitude values of the sampling points in the output signal, wherein the output signal is an interleaved signal subjected to peak clipping processing.

The preset hard peak clipping threshold may be set according to actual requirements, which is not specifically limited in the embodiment of the present invention. In the NCO model shown in fig. 4 of the present invention, peak clipping processing of the combined interleaved signal is realized by a mag _ protect module. Referring to fig. 12, a schematic structural diagram of a mag _ protect module according to an embodiment of the present invention is shown, where a signal th is a signal corresponding to a preset hard peak clipping threshold, a signal data _ i is a real part signal of the interleaved signal data _ out combined in step 208, and a signal data _ q is an imaginary part signal of the interleaved signal data _ out combined in step 208. The cordic module is used for calculating amplitude values, sine values and cosine values corresponding to all sampling points in the input signals data _ i and data _ q. And the Magx theta module is used for calculating phase information corresponding to the sampling point according to the sine value and the cosine value of the input sampling point. The cordic module inputs the amplitude value, the sine value and the cosine value of each sampling point into the comp module, the comp module is used for comparing the amplitude value of the received sampling point with a preset hard peak clipping threshold and inputting the comparison result into the mux module, if the comparison result received by the mux module is that the amplitude value of the sampling point is larger than the preset hard peak clipping threshold, the mux module takes the preset hard peak clipping threshold as the amplitude value of the sampling point in the output signal and determines the phase information of the sampling point in the output signal according to the phase information of the sampling point calculated by the Magx theta module; and if the comparison result received by the mux module is that the amplitude value of the sampling point is less than or equal to the preset hard peak clipping threshold, the mux module directly outputs the data of the sampling point in the interleaved signal subjected to the delay processing by the delay module. The output signal data _ out _ i of the mux module is the real part signal of the interleaved signal after the peak clipping processing, and the output signal data _ out _ q is the imaginary part signal of the interleaved signal after the peak clipping processing.

As can be seen from fig. 12, the input data of the cordic module is the real part signal data _ i and the imaginary part signal data _ q of the combined interleaved signal data _ out, and if the amplitude value of each sampling point in the input signal is to be calculated, the amplitude value of the sampling point needs to be calculated according to the real part data and the imaginary part data of the sampling point. For example, a cordic algorithm is used to calculate the amplitude value of each sample point.

In an optional embodiment of the present invention, the calculating an amplitude value of each sample point of the combined interleaved signal in step S21 includes:

s211, rotating the combined interlaced signal according to a preset rotation rule to obtain an amplitude estimation value of each sampling point of the combined interlaced signal.

S212, determining a compensation coefficient according to the rotation times.

And S213, calculating the amplitude value of each sampling point of the combined interlaced signal according to the amplitude estimation value and the compensation coefficient.

In the embodiment of the present invention, the cordic module shown in fig. 12 may calculate the amplitude value of each sampling point in the input signal by a cordic algorithm. The cordic algorithm has two types of rotation method and vector method, and the embodiment of the invention is described by taking the rotation method as an example.

The amplitude value of the sampling point is calculated by adopting a rotation method, and the phase of the sampling point is basically rotated to 0 degree, at the moment, the amplitude value of the sampling point is approximately equal to the real part value of the sampling point, and the imaginary part value of the sampling point is close to 0. The cordic module generally adopts a multi-stage structure, each stage corresponds to a rotation angle, and the amplitude estimation value of the sampling point is obtained after the rotation is performed for multiple times through multi-stage cascade connection. Taking 5-step cascade as an example, the rotation angles are 45 °, 26.6 °, 14 °, 7.1 °, 3.6 ° and 1.8 ° in sequence from 0 to 5. In general, the angle of the k-th order rotation is determined by arctan (1/2k), and the relationship between the input data and the output data of the k-th order can be expressed as:

wherein, I_kAnd Q_kIs output data of the k-th order, I_k-1And Q_k-1Is the input data of the k-th order.

After multiple rotations, when Q_kWhen the value of (A) is close to 0, the corresponding I_kAs an amplitude estimate of the sample point P.

Assuming that when a sampling point P of an input signal is rotated counterclockwise by an angle θ from point a to point B, the phase of the sampling point P is 0 degrees, the coordinates of point a are (Xi, Yi), and the coordinates of point B are (Xi +1, Yi +1), the following relationships exist:

X_i+1＝cosθ(X_i-Y_itanθ) (7)

Y_i+1＝cosθ(Y_i+X_itanθ) (8)

likewise, if rotated clockwise by an angle θ, then there are:

X_i+1＝cosθ(X_i+Y_itanθ) (9)

Y_i+1＝cosθ(Y_i-X_itanθ) (10)

let the angle of each rotation be α ═ arctan2^-(i-2)Then, there are:

X_i+1＝cosα_i(X_i+Y_iξ_i2^-(i-2)) (11)

Y_i+1＝cosα_i(Y_i-X_iξ_i2^-(i-2)) (12)

wherein when xi_iClockwise when +1, and xi_iWhen-1, it is rotated counterclockwise. After n rotations, the total rotation angle is:

the number n of rotations determines the precision of the algorithm, and after n rotations, the vector is obtained

The amplitude factor K of (a) may be expressed as:

when n is sufficiently large, K ≈ 0.607253, which is a compensation coefficient in the embodiment of the invention.

And finally, multiplying the amplitude estimation value of the sampling point P obtained by the formula (5) by the compensation coefficient obtained by the formula (14) to obtain the amplitude value of the sampling point P.

After the amplitude value of the sampling point is obtained, the data of the sampling point in the output signal of the hard peak clipping module can be obtained by combining the sine value and the cosine value of the sampling point, and by analogy, the same processing is carried out on each input sampling point, and then the interleaved signal after the peak clipping processing can be obtained.

It should be noted that the technical solution provided by the embodiment of the present invention can be applied to various systems, especially 5G systems. For example, the applicable system may be a global system for mobile communication (GSM) system, a Code Division Multiple Access (CDMA) system, a Wideband Code Division Multiple Access (WCDMA) General Packet Radio Service (GPRS) system, a long term evolution (long term evolution, LTE) system, an LTE Frequency Division Duplex (FDD) system, an LTE Time Division Duplex (TDD) system, an LTE-a (long term evolution) system, a universal mobile system (universal mobile telecommunications system, UMTS), a Worldwide Interoperability for Mobile Access (WiMAX) system, a New Radio network (NR 5) system, etc. These various systems include terminal devices and network devices. The System may further include a core network portion, such as an Evolved Packet System (EPS), a 5G System (5GS), and the like.

EXAMPLE III

Referring to fig. 13, which shows a structure diagram of an apparatus provided in the third embodiment of the present invention, specifically including:

a memory 300 for storing a computer program.

A transceiver 310 for receiving and transmitting data under the control of a processor 320.

A processor 320 for reading the computer program in the memory 300 and performing the following operations:

a11, acquiring a data format of an interleaved signal, wherein the interleaved signal comprises at least two antenna signals and at least two carrier data, and the sampling frequencies of the at least two carrier data are consistent;

a12, determining a direct digital frequency signal and a complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency;

a13, carrying out frequency shifting processing on the interleaved signal according to the direct digital frequency signal and the complex frequency domain signal to obtain a frequency-shifted interleaved signal;

a14, combining the frequency-shifted interleaved signals according to a preset rule to obtain combined interleaved signals;

and A15, performing peak clipping processing on the combined interleaved signal according to a preset hard peak clipping threshold.

Optionally, the processor 320 is further configured to read the computer program in the memory 300 and perform the following operations:

acquiring at least two carrier data, wherein the sampling frequencies of the at least two carrier data are consistent, and the sampling frequency is a factor of a preset clock frequency;

determining a preset sequence of the at least two carrier data;

and according to the preset sequence of the at least two carrier data, performing interleaving processing on the at least two antenna signals to obtain interleaved signals.

Optionally, the determining the direct digital frequency signal and the complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency, a12, includes:

determining a frequency offset signal of the interleaved signal according to the data format and the sampling frequency;

generating a direct digital frequency signal of the interleaved signal from the frequency offset signal;

mapping the interleaved signal to a complex frequency domain to obtain real part data and imaginary part data of the interleaved signal;

generating a complex frequency domain signal of the interleaved signal according to the data format of the interleaved signal, the sampling frequency, the real part data, and the imaginary part data.

Optionally, the direct digital frequency signal includes a sine value signal and a cosine value signal of the interleaved signal, and a13 performs frequency shifting processing on the interleaved signal according to the direct digital frequency signal and the complex frequency domain signal to obtain a frequency-shifted interleaved signal, including:

and carrying out complex multiplication on the sine value signal, the cosine value signal and the complex frequency domain signal according to a preset frequency shifting rule to obtain a frequency-shifted interleaved signal.

Optionally, the combining the frequency-shifted interleaved signal according to the preset rule to obtain a combined interleaved signal in a14 includes:

performing delay processing on the interleaved signal after frequency shifting according to the data format and the sampling frequency to obtain at least two carrier signals, wherein the at least two carrier signals correspond to the at least two carrier data, and one carrier signal comprises the at least two antenna signals;

and combining the at least two carrier signals to obtain a combined interleaved signal.

Optionally, the performing peak clipping processing on the combined interleaved signal according to a preset hard peak clipping threshold by a15 includes:

calculating amplitude values and sine and cosine values of all sampling points of the combined interweaved signal;

if the amplitude value of at least one sampling point is smaller than or equal to a preset hard peak clipping threshold, taking the amplitude value as the amplitude value corresponding to the at least one sampling point in the output signal;

if the amplitude value of at least one sampling point is larger than a preset hard peak clipping threshold, taking the preset hard peak clipping threshold as the amplitude value corresponding to the at least one sampling point in the output signal;

and generating an output signal according to the sine and cosine values of the sampling points and the amplitude values of the sampling points in the output signal, wherein the output signal is an interweaved signal subjected to peak clipping processing.

Optionally, the calculating the amplitude value of each sampling point of the combined interleaved signal includes:

rotating the combined interleaved signal according to a preset rotation rule to obtain an amplitude estimation value of each sampling point of the combined interleaved signal;

determining a compensation coefficient according to the rotation times;

and calculating the amplitude value of each sampling point of the combined interweaved signal according to the amplitude estimation value and the compensation coefficient.

Optionally, a product of the number of antenna signals of at least two antenna signals and the number of carriers of at least two carrier data included in the interleaved signal is less than or equal to a preset signal number, where the preset signal number is equal to a ratio of a preset clock frequency to the sampling frequency.

Where in fig. 13 the bus interface is an interface to a bus architecture, the bus architecture may include any number of interconnected buses and bridges, with one or more processors, represented by processor 320, and various circuits of memory, represented by memory 300, being linked together. The bus architecture may also link together various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. The bus interface provides an interface. The transceiver 310 may be a number of elements including a transmitter and a receiver that provide a means for communicating with various other apparatus over a transmission medium including wireless channels, wired channels, fiber optic cables, and the like. The processor 320 is responsible for managing the bus architecture and general processing, and the memory 300 may store data used by the processor 320 in performing operations.

The processor 320 may be a Central Processing Unit (CPU), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or a Complex Programmable Logic Device (CPLD), and may also have a multi-core architecture.

It should be noted that, the apparatus provided in the embodiment of the present invention can implement all the method steps implemented by the method embodiment and achieve the same technical effect, and detailed descriptions of the same parts and beneficial effects as the method embodiment in this embodiment are omitted here.

Example four

Referring to fig. 14, which shows a structure diagram of a multi-carrier data processing apparatus according to a fourth embodiment of the present invention, specifically, the structure diagram includes:

a data format obtaining module 401, configured to obtain a data format of an interleaved signal, where the interleaved signal includes at least two antenna signals and at least two carrier data, and sampling frequencies of the at least two carrier data are consistent;

a modulation signal determination module 402, configured to determine a direct digital frequency signal and a complex frequency domain signal of the interleaved signal according to the data format and the sampling frequency;

a frequency shifting processing module 403, configured to perform frequency shifting processing on the interleaved signal according to the direct digital frequency signal and the complex frequency domain signal, so as to obtain a frequency-shifted interleaved signal;

a combining processing module 404, configured to perform combining processing on the frequency-shifted interleaved signals according to a preset rule to obtain combined interleaved signals;

and a peak clipping processing module 405, configured to perform peak clipping processing on the combined interleaved signal according to a preset hard peak clipping threshold.

Optionally, the multi-carrier data processing apparatus further includes:

the device comprises a carrier data acquisition module, a clock frequency generation module and a clock frequency generation module, wherein the carrier data acquisition module is used for acquiring at least two pieces of carrier data, the sampling frequencies of the at least two pieces of carrier data are consistent, and the sampling frequency is a factor of a preset clock frequency;

the sequence determining module is used for determining a preset sequence of the at least two carrier data;

and the interleaving module is used for performing interleaving processing on the at least two antenna signals according to the preset sequence of the at least two carrier data to obtain interleaved signals.

Optionally, the modulation signal determining module 402 includes:

a frequency offset determination submodule for determining a frequency offset signal of the interleaved signal according to the data format and the sampling frequency;

a digital frequency signal generation submodule for generating a direct digital frequency signal of the interleaved signal from the frequency offset signal;

a complex frequency domain mapping submodule, configured to map the interleaved signal to a complex frequency domain, and obtain real part data and imaginary part data of the interleaved signal;

and the modulation signal generation sub-module is used for generating a complex frequency domain signal of the interleaved signal according to the data format of the interleaved signal, the sampling frequency, the real part data and the imaginary part data.

Optionally, the direct digital frequency signal includes a sine value signal and a cosine value signal of the interleaved signal, and the frequency shift processing module 403 includes:

and the frequency shifting processing submodule is used for carrying out complex multiplication on the sine value signal, the cosine value signal and the complex frequency domain signal according to a preset frequency shifting rule to obtain an interleaved signal after frequency shifting.

Optionally, the combining processing module 404 includes:

a delay processing sub-module, configured to perform delay processing on the frequency-shifted interleaved signal according to the data format and the sampling frequency to obtain at least two carrier signals, where the at least two carrier signals correspond to the at least two carrier data, and one carrier signal includes the at least two antenna signals;

and the combining processing submodule is used for combining the at least two carrier signals to obtain an interwoven signal after combination.

Optionally, the peak reduction processing module 405 includes:

the calculation submodule is used for calculating the amplitude value and the sine and cosine value of each sampling point of the combined interweaved signal;

the first amplitude value determining sub-module is used for taking the amplitude value as the amplitude value corresponding to the at least one sampling point in the output signal if the amplitude value of the at least one sampling point is smaller than or equal to a preset hard peak clipping threshold;

the second amplitude value determination sub-module is used for taking the preset hard peak clipping threshold as an amplitude value corresponding to the at least one sampling point in the output signal if the amplitude value of the at least one sampling point is larger than the preset hard peak clipping threshold;

and the output signal generation submodule is used for generating an output signal according to the sine and cosine values of the sampling points and the amplitude values of the sampling points in the output signal, and the output signal is an interweaved signal subjected to peak clipping processing.

Optionally, the computation submodule includes:

the rotation processing unit is used for performing rotation processing on the combined interlaced signal according to a preset rotation rule to obtain an amplitude estimation value of each sampling point of the combined interlaced signal;

a compensation coefficient determining unit for determining a compensation coefficient according to the number of rotations;

and the amplitude value calculating unit is used for calculating the amplitude value of each sampling point of the combined interweaved signal according to the amplitude estimation value and the compensation coefficient.

It should be noted that, the division of the modules and units in the embodiment of the present invention is schematic, and is only a logic function division, and there may be another division manner in actual implementation. In addition, each functional module and each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented as a software functional unit and sold or used as a stand-alone product, may be stored in a processor readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

An embodiment of the present invention further provides a processor-readable storage medium, which stores a computer program, where the computer program is used to enable a processor to execute the foregoing method.

The processor-readable storage medium can be any available medium or data storage device that can be accessed by a processor, including, but not limited to, magnetic memory (e.g., floppy disks, hard disks, magnetic tape, magneto-optical disks (MOs), etc.), optical memory (e.g., CDs, DVDs, BDs, HVDs, etc.), and semiconductor memory (e.g., ROMs, EPROMs, EEPROMs, non-volatile memory (NAND FLASH), Solid State Disks (SSDs)), etc.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer-executable instructions. These computer-executable instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These processor-executable instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method for multi-carrier data processing, the method comprising:

2. The method of claim 1, wherein before obtaining the data format of the interleaved signal, the method further comprises:

acquiring at least two carrier data, wherein the sampling frequencies of the at least two carrier data are consistent, and the sampling frequencies are factors of a preset clock frequency;

determining a preset sequence of the at least two carrier data;

and interleaving the at least two antenna signals according to the preset sequence of the at least two carrier data to obtain an interleaved signal.

3. The method of claim 1, the determining a direct digital frequency signal and a complex frequency domain signal of the interleaved signal from the data format and the sampling frequency, comprising:

4. The method according to claim 1, wherein the direct digital frequency signal includes a sine value signal and a cosine value signal of the interleaved signal, and the performing a frequency-shifting process on the interleaved signal according to the direct digital frequency signal and the complex frequency domain signal to obtain a frequency-shifted interleaved signal includes:

5. The method according to claim 1, wherein the combining the frequency-shifted interleaved signals according to a preset rule to obtain combined interleaved signals comprises:

6. The method of claim 1, wherein the performing peak clipping on the combined interleaved signal according to a preset hard peak clipping threshold comprises:

calculating the amplitude value and the sine and cosine value of each sampling point of the combined interweaved signal;

7. The method of claim 6, wherein said calculating amplitude values for respective sample points of the combined interleaved signal comprises:

determining a compensation coefficient according to the rotation times;

8. The method of claim 1, wherein the interleaved signal comprises a product of a number of antenna signals of at least two antenna signals and a number of carriers of at least two carrier data, which is less than or equal to a preset number of signals, and wherein the preset number of signals is equal to a ratio of a preset clock frequency to the sampling frequency.

9. An apparatus, comprising a memory, a transceiver, a processor:

a memory for storing a computer program; a transceiver for transceiving data under control of the processor; a processor for reading the computer program in the memory and performing the following:

10. The apparatus of claim 9, wherein the processor is further configured to read the computer program in the memory and perform the following:

determining a preset sequence of the at least two carrier data;

11. The apparatus of claim 9, wherein determining the direct digital frequency signal and the complex frequency domain signal of the interleaved signal based on the data format and the sampling frequency comprises:

12. The apparatus according to claim 9, wherein the direct digital frequency signal includes a sine value signal and a cosine value signal of the interleaved signal, and the performing a frequency-shifting process on the interleaved signal according to the direct digital frequency signal and the complex frequency domain signal to obtain a frequency-shifted interleaved signal includes:

and carrying out complex multiplication on the sine value signal, the cosine value signal and the complex frequency domain signal according to a preset frequency shifting rule to obtain an interleaved signal after frequency shifting.

13. The apparatus of claim 9, wherein the combining the frequency-shifted interleaved signals according to a preset rule to obtain combined interleaved signals comprises:

14. The apparatus of claim 9, wherein the performing peak clipping on the combined interleaved signal according to a preset hard peak clipping threshold comprises:

15. The apparatus of claim 14, wherein said calculating the amplitude value of each sample point of the combined interleaved signal comprises:

determining a compensation coefficient according to the rotation times;

16. The apparatus of claim 9, wherein the interleaved signal comprises a product of a number of antenna signals of at least two antenna signals and a number of carriers of at least two carrier data, which is less than or equal to a preset number of signals, and wherein the preset number of signals is equal to a ratio of a preset clock frequency to the sampling frequency.

17. A multi-carrier data processing apparatus, characterized in that the apparatus comprises:

18. A processor-readable storage medium, characterized in that the processor-readable storage medium stores a computer program for causing a processor to perform the method of any one of claims 1 to 8.