CN114513274B - Internet-oriented multi-hop high-precision time synchronization protocol implementation method and device - Google Patents
Internet-oriented multi-hop high-precision time synchronization protocol implementation method and device Download PDFInfo
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Abstract
The invention provides a method and a device for realizing a multi-hop high-precision time synchronization protocol facing to the Internet, wherein the method comprises the steps of constructing a detection network, constructing back-to-back data packets, and acquiring the back-to-back data packets which are less influenced by the delay of network equipment in the detection network; calculating positive and negative random propagation delay distribution of back-to-back data packets which are less influenced by network equipment delay based on an SVM (support vector machine); substituting the positive and negative random propagation delay distribution into an L estimator for calculation, and estimating a preliminary time deviation; applying a weight-based loop correction to the preliminary time offset, and calculating to obtain a final time offset; and adjusting a hardware clock according to the final time deviation to realize clock synchronization. The method has the characteristics of high precision, low cost and high expansibility.
Description
Technical Field
The invention relates to the field of computer network systems, in particular to an internet-oriented multi-hop high-precision time synchronization protocol.
Background
Time synchronization is essential in an increasingly digital, networked world. Almost all infrastructures rely on accurate time synchronization. Clocks in network devices can drift and, therefore, calculate time at slightly different frequencies, thereby creating time offsets. The clock synchronization protocol is intended to keep the device time in the synchronous network at a specified accuracy.
Specifically, clock synchronization consists of frequency synchronization and phase synchronization. Frequency synchronization refers to allocating precise frequencies in a network. Phase synchronization, also referred to as time synchronization, means that multiple clocks have the same frequency and phase, i.e. the phase difference equals zero.
In addition, the time synchronization algorithm can be classified into a hierarchical type and a distributed type according to different network topologies of the time synchronization algorithm. The hierarchical structure is composed of a root clock and a plurality of layers of sub-clocks, time synchronization is carried out from high to low along the hierarchy, and the hierarchical structure is mainly used for the hierarchical structure of the internet, a data center and the like. The distributed structure is composed of a plurality of equal nodes, time synchronization is carried out in a decentralized mode, and the distributed structure is mostly used in a sensor network.
Time synchronization has become an important infrastructure in social productive life. For example, in financial and electronic commerce, clock synchronization is critical to determining transaction order. Trading platforms need to be matched in order of bids even though they are coming into the trading platform from different gateways. In a distributed database, accurate clock synchronization allows the database to perform external consistency, improving the throughput of the database. In a 5G digital substation, interference caused by cross time slots exists between base stations, and can be avoided only by high-precision time synchronization. In industrial automation systems, highly demanding metering systems and event sequence analysis control systems also require highly accurate time synchronization. In the military field, high-precision clock synchronization is also needed when a cluster formed by unmanned aerial vehicles flies, tracks and strikes targets and transmits key control signals. In fact, highly accurate synchronized clocks help to correct the "clock-less" assumption behind system design.
In the aspect of development of the time synchronization protocol, from the traditional NTP protocol to the PTP protocol with higher precision, and from 2006 to the time synchronization system, which is a white rabbit scheme, constructed by the research center of european nucleons for a large hadron collider, and in recent years, the time synchronization protocol, which is a data center-oriented protocol, is protocols such as DTP, HUYGENS, DPTP, and the like, the time synchronization protocol is increasingly developed in three directions of high precision, high expansibility, and low cost.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art.
Therefore, the first objective of the present invention is to provide an internet-oriented multi-hop high-precision time synchronization protocol implementation method for high-precision clock synchronization.
The second purpose of the invention is to provide an internet-oriented multi-hop high-precision time synchronization protocol implementation device.
A third object of the invention is to propose a computer device.
A fourth object of the invention is to propose a computer-readable storage medium.
In order to achieve the above object, an embodiment of a first aspect of the present invention provides an internet-oriented multi-hop high-precision time synchronization protocol implementation method, including:
constructing a detection network, constructing back-to-back data packets, and acquiring the back-to-back data packets which are less influenced by network equipment delay in the detection network;
calculating positive and negative random propagation delay distribution of the back-to-back data packets which are less influenced by the delay of the network equipment on the basis of the SVM;
substituting the positive and negative random propagation delay distribution into an L estimator for calculation, and estimating a preliminary time deviation;
applying a weight-based loop correction to the preliminary time offset, and calculating to obtain a final time offset;
and adjusting a hardware clock according to the final time deviation to realize clock synchronization.
In addition, the method for implementing the internet-oriented multi-hop high-precision time synchronization protocol according to the above embodiment of the present invention may further have the following additional technical features:
further, in one embodiment of the present invention, the constructing a probe network includes:
and selecting a random number K, detecting K other servers by each server, wherein each detection represents a directed edge, and the detection end and the detected end represent nodes at two ends of the directed edge to form the detection network.
Further, in an embodiment of the present invention, the acquiring back-to-back data packets in the probe network, which are less affected by network device delay, includes:
sending a preset number of back-to-back data packets to the detection network;
and filtering the back-to-back data packets to obtain the back-to-back data packets which are less influenced by the delay of the network equipment.
Further, in an embodiment of the present invention, the calculating, based on SVM, a positive-negative random propagation delay distribution for the back-to-back data packets that are less affected by the network device delay includes:
performing SVM processing on the upper limit data and the lower limit data of the back-to-back data packet which are less influenced by the delay of the network equipment to obtain two support vectors;
and calculating the positive and negative random propagation delay distribution based on the support vector.
Further, in an embodiment of the present invention, the calculating forward and reverse random propagation delay distributions based on support vectors includes:
taking the support vector as an upper limit and a lower limit, and calculating the longitudinal distance between a data point above the upper support vector and the upper support vector to obtain forward random queuing delay;
and calculating the longitudinal distance between the data point below the lower support vector and the lower support vector to obtain the negative random queuing delay.
Further, in an embodiment of the present invention, the substituting the delay profile into an L estimator for calculation and estimating a preliminary time offset includes:
in each period of the L estimator, obtaining a random delay distribution through random delay estimation based on SVM;
and when the number of the cycles reaches k historical cycles of the extended model of the L estimator, calculating parameters of the L estimator in the current cycle and the previous k cycles, and then calculating according to the parameters to obtain the preliminary time deviation.
Further, in an embodiment of the invention, the applying a weight-based loop correction to the preliminary time offset to calculate a final time offset includes:
calculating the weight of each directed edge in the loop according to the absolute value of the preliminary time deviation;
allocating the time offset sum of the loop according to the weight;
and adding the time deviation sum to the preliminary time deviation of each directed edge, and calculating to obtain a final time deviation.
In order to achieve the above object, a second embodiment of the present invention provides an internet-oriented multi-hop high-precision time synchronization protocol implementation apparatus, including:
the acquisition module is used for constructing a detection network and acquiring data packets which are less influenced by the delay of network equipment by utilizing back-to-back data packets;
the time delay calculation module is used for calculating the positive and negative random propagation time delay distribution of the data packet which is less influenced by the delay of the network equipment based on the SVM;
a preliminary time deviation calculation module for substituting the positive and negative random propagation delay distribution into an L estimator for calculation and estimating a preliminary time deviation;
a final time deviation calculation module, configured to apply a weight-based loop correction to the preliminary time deviation, and calculate a final time deviation;
and the synchronization module is used for adjusting a hardware clock according to the final time deviation to realize clock synchronization.
In order to achieve the above object, a third embodiment of the present invention provides a computer device, which is characterized by comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the internet-oriented multi-hop high-precision time synchronization protocol implementation method.
To achieve the above object, a fourth aspect of the present invention provides a computer-readable storage medium, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the internet-oriented multi-hop high-precision time synchronization protocol implementation method as described above.
The internet-oriented multi-hop high-precision time synchronization protocol implementation method has good deployment flexibility, realizes high-precision and low-cost time synchronization, does not need hop-by-hop deployment, does not need to add special functions to network relay equipment such as routers and switches, and is particularly suitable for internet-scale high-precision time synchronization. The method is mainly divided into three parts: the first part obtains a data packet which is slightly influenced by the delay of network equipment by using back-to-back data packets, and obtains two support vectors by using an SVM (support vector machine) to process the filtered data, thereby obtaining the distribution of positive and negative random propagation delay; a second part estimates a preliminary time offset using an L estimator; and the third part uses weight-based loop correction to obtain final time deviation, calculates the weight of each directed edge in the loop according to the absolute value of the initial time deviation, and then adjusts a hardware clock to realize clock synchronization. The method has the characteristics of high precision, low cost and high expansibility, and achieves the expected invention aim.
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The foregoing and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic flowchart of a method for implementing a multi-hop high-precision time synchronization protocol for internet according to an embodiment of the present invention.
Fig. 2 is a schematic flowchart of an internet-oriented multi-hop high-precision time synchronization protocol implementation apparatus according to an embodiment of the present invention.
Fig. 3 is a time synchronization precision histogram of three protocols with different hop counts according to an embodiment of the present invention, where the ordinate represents synchronization precision of the three protocols in nanoseconds, the abscissa represents different hop counts, and the histograms with different grays represent different time synchronization protocols.
Fig. 4 is a graph showing the time deviation variation of PTP, huggyns and M-PTP at 5 hops in 60 seconds, in which the ordinate represents the time deviation of three protocols in nanoseconds, the abscissa represents time, and different curves represent different time synchronization protocols, according to an embodiment of the present invention.
Fig. 5 is a CDF schematic diagram of time synchronization accuracy of the HUYGENS and the M-PTP in 5-hop according to an embodiment of the present invention, where the ordinate represents probability and the abscissa represents synchronization time deviation.
Fig. 6 is a schematic diagram of the accuracy of time synchronization of three protocols under different network loads according to the embodiment of the present invention, where an ordinate represents time deviation of the three protocols, and a unit is nanosecond, and an abscissa represents different network loads.
Fig. 7 is a schematic diagram illustrating an influence of CPU loads on PTP, HUYGENS, and M-PTP according to an embodiment of the present invention, where four different CPU loads (50, 0), (100, 0), (0, 50), (0, 100) are set, where the CPU load (x, y) indicates that the CPU load percentage of the slave clock is x, and the CPU load percentage of the master clock is y.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative and intended to explain the present invention and should not be construed as limiting the present invention.
The method and the device for implementing the internet-oriented multi-hop high-precision time synchronization protocol according to the embodiments of the present invention are described below with reference to the accompanying drawings.
Fig. 1 is a schematic flowchart of a method for implementing a multi-hop high-precision time synchronization protocol for internet according to an embodiment of the present invention.
As shown in fig. 1, the internet-oriented multi-hop high-precision time synchronization protocol implementation method includes the following steps:
s1: constructing a detection network, constructing back-to-back data packets, and acquiring the back-to-back data packets which are less influenced by the delay of network equipment in the detection network;
s2: calculating positive and negative random propagation delay distribution of back-to-back data packets which are less influenced by network equipment delay based on an SVM (support vector machine);
s3: substituting the positive and negative random propagation delay distribution into an L estimator for calculation, and estimating a preliminary time deviation;
s4: applying a weight-based loop correction to the preliminary time offset, and calculating to obtain a final time offset;
s5: and adjusting a hardware clock according to the final time deviation to realize clock synchronization.
Further, in one embodiment of the invention, a probing network is constructed comprising:
and selecting a random number K, detecting K other servers by each server, wherein each detection represents a directed edge, and the detection end and the detected end represent nodes at two ends of the directed edge to form a detection network.
Further, in an embodiment of the present invention, acquiring back-to-back data packets in the probe network, which are less affected by the network device delay, includes:
sending a preset number of back-to-back data packets to a detection network;
and filtering the back-to-back data packets to obtain the back-to-back data packets which are less influenced by the delay of the network equipment.
Further, in an embodiment of the present invention, the calculating, based on SVM, a positive-negative random propagation delay distribution for the back-to-back data packets that are less affected by the network device delay includes:
performing SVM processing on the upper limit data and the lower limit data of the back-to-back data packet which are less influenced by the delay of the network equipment to obtain two support vectors;
and calculating the positive and negative random propagation delay distribution based on the support vector.
Further, in an embodiment of the present invention, the calculating forward and backward random propagation delay distributions based on support vectors includes:
taking the support vector as an upper limit and a lower limit, and calculating the longitudinal distance between a data point above the upper support vector and the upper support vector to obtain forward random queuing delay;
and calculating the longitudinal distance between the data point below the lower support vector and the lower support vector to obtain the negative random queuing delay.
Further, in an embodiment of the present invention, the substituting the delay profile into an L estimator for calculation and estimating a preliminary time offset includes:
in each period of the L estimator, obtaining a random delay distribution through random delay estimation based on SVM;
and when the number of the cycles reaches k historical cycles of the extended model of the L estimator, calculating parameters of the L estimator in the current cycle and the previous k cycles, and then calculating according to the parameters to obtain the preliminary time deviation.
Further, in an embodiment of the present invention, the applying a weight-based loop correction to the preliminary time offset and calculating a final time offset includes:
calculating the weight of each directed edge in the loop according to the absolute value of the preliminary time deviation;
assigning a time offset sum of the loop according to the weight;
and adding the time deviation sum to the preliminary time deviation of each directed edge, and calculating to obtain a final time deviation.
The internet-oriented multi-hop high-precision time synchronization protocol of the embodiment of the present application is described in detail by way of example as follows:
the application divides the multi-hop high-precision time synchronization protocol facing the Internet into five parts:
the first step is as follows: constructing a detection network, specifically as follows:
step 1, for a time synchronization network, the following steps are sequentially executed:
step 1-1, a random number K is selected.
And step 1-2, each server detects K other servers.
And 1-3, each probe represents a directed edge, and the probe end and the detected end represent nodes at two ends of the directed edge to form a probe network.
The second step: constructing back-to-back data packets, acquiring data packets which are slightly influenced by network equipment delay, and calculating the distribution of forward and reverse random propagation delay based on the SVM, wherein the distribution is as follows:
and 2-1, constructing back-to-back data packets, wherein the data packets are encoded in sequence, and the interval of the sending time stamps between the back-to-back data packets from the sending server to the receiving server is s.
And 2-2, filtering the back-to-back data packets. When the sending server detects the receiving server, the sending timestamp interval between back-to-back data packets is small, which is s. When the receiving server receives the back-to-back data packets, if the distance between the receiving time stamps is also very close to s, the back-to-back data packets are considered to be not influenced by the burst factors such as network congestion, i.e. to be 'pure', and the encoding and time stamp data of the back-to-back data packets are saved. Otherwise, they are "dirty" and their data is discarded.
And 2-3, processing the filtered back-to-back data packet to obtain upper limit data and lower limit data.
And 2-4, carrying out SVM processing, and obtaining two support vectors after the processing is finished.
The third step: calculating the distribution of forward and backward random propagation delay based on the support vector, specifically as follows:
and 3-1, calculating the random time delay distribution by using the support vector as an upper limit and a lower limit. The vertical distance of the green data point above the upper bound from the upper bound is its random queuing delay. Similarly, the vertical distance of the red data point below the lower bound from the lower bound is its random queuing delay.
And 3-2, obtaining the forward and reverse random queuing delay distribution of all data points, and then obtaining the expected value and the covariance of the data points.
The fourth step: the preliminary time offset is estimated using an L estimator as follows:
and 4-1, storing the time stamp data of the current period in each period. If B cycles are not full, the cycle continues.
And 4-2, once B periods are met (B is the historical period number of the extended model), calculating L-estimated parameters (expected values and covariance) of the current period and the previous B periods according to an inference result of the L-estimator, and calculating deviation estimation according to the parameters, namely initial time deviation.
The fifth step: using a weight-based loop correction to obtain a final time offset, and then adjusting a hardware clock to realize clock synchronization, which is specifically as follows:
and 5-1, calculating the weight of each directed edge in the loop according to the absolute value of the initial time deviation.
And 5-2, allocating the time deviation sum of the loops according to the weight.
And 5-3, adding the time difference to the initial time difference of each directed edge, and calculating to obtain the final time difference.
And 5-4, adjusting a hardware clock according to the final time deviation to realize clock synchronization.
Secondly, evaluating a multi-hop high-precision time synchronization protocol facing the internet, specifically as follows:
in our experimental platform, three servers A, B and C represent three clocks C, respectively 1 ,C 2 And C 3 . Servers A, B and C are connected through four switches. The server B has a plurality of network cards. One of the network cards is connected with the switch 3, and the other network card is connected with the switch 4. There are 2 paths between server B and switch 4. One path is Server B —>Exchanger 3->A switch 4. Another path is Server B —>A switch 4. The model of the three servers is PowerEdge R7525, and the switch connected to the server A, B, C is Huawei S5720-36C-EI-AC switch. This switch need not support the lower cost PTP protocol. Furthermore, there is no need to deploy M-PTP hop-by-hop. The network card in the server is an intel ethernet controller X710 with a bandwidth of 10000Mb/s and supports hardware time stamping. Let C be 1 Is the reference clock for all synchronous clocks. A probe network is established between three clocks, each probing another clock. That is, server A probes server B and server B probesAnd detecting the server C, and detecting the server A by the server C, thereby forming a loop detection network.
First, we tested PTP, HUYGENS and M-PTP in an environment of different hop counts. We tested the accuracy of time synchronization for 1 hop to 5 hops in an experimental environment. One hop means that two servers are directly connected. The path represented by 5 hops is server a- > switch 1- > switch 2- > switch 3- > switch 4- > server C. We define the average of the time offsets as the synchronization accuracy.
According to statistics of experimental results, under the test of 1 hop, 2 hop, 3 hop, 4 hop and 5 hop, the PTP can reach the synchronization accuracy of 20.63ns, 66.96ns, 134.86ns, 236.96ns and 312.17.96ns, HUYGENS can reach the synchronization accuracy of 10.1ns, 15.88 ns, 18.61ns, 30.47ns and 31.64ns, and M-PTP can reach 9.26ns, 13.46 ns, 18.62ns, 12.93ns and 11.61 ns.
Fig. 3 shows time synchronization accuracy histograms of three protocols at different hop counts. First, the synchronization accuracy of PTP is lowest at different hop counts. Next, compared to PTP, the accuracy of HUYGENS is less affected by the number of hops, and the synchronization accuracy of HUYGENS at 5 hops is 31.64 ns. Third, the precision of M-PTP is the best of the three protocols. The advantages of M-PTP are more and more prominent with the increase of the hop count. The M-PTP can achieve synchronization precision of 11.61ns at 5 hops, which is about 3 times of HUYGENS precision and about 30 times of PTP precision. While FIG. 4 shows the time offset variation of PTP, HUYGENS and M-PTP at 5-hop within 60 seconds.
FIG. 5 shows a CDF plot of the time synchronization accuracy of HUYGENS and M-PTP at 5 hops. It can be seen that the time offset distribution of the M-PTP is more concentrated around 10ns, which indicates that the synchronization accuracy is better than that of the HUYGENS. Furthermore, M-PTP does not require hop-by-hop deployment.
Fig. 6 shows the time synchronization accuracy of three protocols under different network loads. According to the experimental result, the PTP can achieve the synchronization precision of 3266.4ns, 3413.63ns, 4273.36ns and 4647.96ns in the environment of 20% load, 40% load, 60% load and 80% load. HUYGENS can achieve synchronization accuracies of 88.93ns, 294.73ns, 421.59ns, and 636.62 ns. M-PTP can achieve synchronization accuracy of 53.87ns, 154.66ns, 181.62ns and 222.21 ns.
It can be seen that the accuracy of the PTP will be severely degraded when the network load increases. In all four network load scenarios, the precision of the PTP cannot be maintained at ns, and its precision drops to 4647.96ns at 80% load. Second, at 80% load, the accuracy of HUYGENS is 636.62ns, while the M-PTP accuracy can reach 222.21 ns.
FIG. 7 shows the effect of CPU load on PTP, HUYGENS and M-PTP. We set four different CPU loads (50, 0), (100, 0), (0, 50), (0, 100). The CPU load (x, y) indicates that the CPU load percentage of the slave clock is x and the CPU load percentage of the master clock is y. According to the experimental result, the PTP can respectively reach the synchronization precision of 4572.63ns, 4821.54ns, 4410.93ns and 4932.22ns under the CPU loads of (50, 0), (100, 0), (0, 50) and (0, 100). HUYGENS can realize the synchronization precision of 591.73ns, 782.61ns, 539.15ns and 606.96 ns. M-PTP can realize synchronization precision of 207.42ns, 371.03ns, 189.76ns and 223.32 ns.
It can be found that the synchronization accuracy of PTP under different CPU loads is the worst. Further, the PTP has almost the same synchronization accuracy under CPU loads (0, 50) and (50, 0), (0, 100) and (100, 0). This indicates that the CPU load on the slave and master clocks has a similar effect on PTP. This is because the computational resources required for PTP of the slave and master clocks are similar. Second, the CPU load on the slave clock has a greater effect on HUYGENS than the master clock. This is because the main computational resources required for HUYGENS are located at the slave clock, so the impact of the CPU load is greater here. Third, it can be seen that the M-PTP achieves the best synchronization accuracy of the three protocols under heavy CPU load.
In conclusion, the embodiments of the present invention achieve the intended purposes.
The method for realizing the internet-oriented multi-hop high-precision time synchronization protocol comprises the steps of obtaining a data packet which is less influenced by network equipment delay by utilizing back-to-back data packets, and calculating the distribution of positive and negative random propagation delay based on an SVM (support vector machine); estimating a preliminary time offset by using an L estimator; the clock synchronization is achieved using weight-based loop correction to obtain the final time offset, and then adjusting the hardware clock. Therefore, the method has good deployment flexibility, realizes time synchronization with high precision and low cost, does not need hop-by-hop deployment, does not need to add special functions to network relay equipment such as a router, a switch and the like, and is particularly suitable for high-precision time synchronization of the Internet scale.
In order to implement the above embodiments, the present invention further provides an internet-oriented multi-hop high-precision time synchronization protocol implementation apparatus.
Fig. 2 is a schematic structural diagram of an internet-oriented multi-hop high-precision time synchronization protocol implementation apparatus according to an embodiment of the present invention.
As shown in fig. 2, the internet-oriented multi-hop high-precision time synchronization protocol implementation apparatus includes: the system comprises an acquisition module 10, a time delay calculation module 20, a preliminary time deviation calculation module 30, a final time deviation calculation module 40 and a synchronization module 50; the acquisition module is used for constructing a detection network and acquiring data packets which are slightly influenced by the delay of network equipment by using back-to-back data packets; the time delay calculation module is used for calculating the positive and negative random propagation time delay distribution of the data packet which is less influenced by the delay of the network equipment based on the SVM; a preliminary time deviation calculation module for substituting the positive and negative random propagation delay distribution into an L estimator for calculation and estimating a preliminary time deviation; a final time deviation calculation module for applying a weight-based loop correction to the preliminary time deviation to calculate a final time deviation; and the synchronization module is used for adjusting a hardware clock according to the final time deviation so as to realize clock synchronization.
In order to achieve the above object, a third embodiment of the present invention provides a computer device, which is characterized by comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the internet-oriented multi-hop high-precision time synchronization protocol implementation method.
To achieve the above object, a fourth aspect of the present invention provides a computer-readable storage medium, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the internet-oriented multi-hop high-precision time synchronization protocol implementation method as described above.
In the description of the present specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless explicitly specified otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.
The logic and/or steps represented in the flowcharts or otherwise described herein, such as an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are well known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried out in the method of implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and the program, when executed, includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may also be stored in a computer-readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.
Claims (8)
1. An internet-oriented multi-hop high-precision time synchronization protocol implementation method is characterized by comprising the following steps:
constructing a detection network, constructing back-to-back data packets, and acquiring the back-to-back data packets which are less influenced by network equipment delay in the detection network;
calculating positive and negative random propagation delay distribution of the back-to-back data packets which are less influenced by the delay of the network equipment on the basis of the SVM;
substituting the positive and negative random propagation delay distribution into an L estimator for calculation, and estimating a preliminary time deviation;
applying a weight-based loop correction to the preliminary time offset, and calculating to obtain a final time offset;
adjusting a hardware clock according to the final time deviation to realize clock synchronization;
wherein, the calculating the positive and negative random propagation delay distribution of the back-to-back data packet with less influence of the network equipment delay based on SVM includes:
carrying out SVM processing on the upper limit data and the lower limit data of the back-to-back data packet which is less influenced by the delay of the network equipment to obtain two support vectors;
calculating the distribution of positive and negative random propagation delay based on the support vector;
further, the calculating forward and backward random propagation delay distribution based on the support vector includes:
taking the support vector as an upper limit and a lower limit, and calculating the longitudinal distance between a data point above the upper support vector and the upper support vector to obtain forward random queuing delay;
and calculating the longitudinal distance between the data point below the lower support vector and the lower support vector to obtain the negative random queuing delay.
2. The method of claim 1, wherein constructing a probing network comprises:
and selecting a random number K, wherein each server detects K other servers, each detection represents a directed edge, and the detection end and the detected end represent nodes at two ends of the directed edge to form the detection network.
3. The method of claim 1, wherein the obtaining back-to-back data packets in the probe network that are less affected by network device delay comprises:
sending a preset number of back-to-back data packets to the detection network;
and filtering the back-to-back data packets to obtain the back-to-back data packets which are less influenced by the delay of the network equipment.
4. The method of claim 1, wherein the substituting the delay profile into an L estimator for calculation and estimating a preliminary time offset comprises:
in each period of the L estimator, obtaining a random delay distribution through random delay estimation based on SVM;
and when the number of the cycles reaches k historical cycles of the extended model of the L estimator, calculating parameters of the L estimator in the current cycle and the previous k cycles, and then calculating according to the parameters to obtain the preliminary time deviation.
5. The method of claim 1, wherein applying a weight-based loop correction to the preliminary time offset to calculate a final time offset comprises:
calculating the weight of each directed edge in the loop according to the absolute value of the preliminary time deviation;
assigning a time offset sum of the loop according to the weight;
and adding the time deviation sum to the preliminary time deviation of each directed edge, and calculating to obtain a final time deviation.
6. An Internet-oriented multi-hop high-precision time synchronization protocol implementation device is characterized by comprising:
the acquisition module is used for constructing a detection network and acquiring data packets which are slightly influenced by the delay of network equipment by using back-to-back data packets;
the time delay calculation module is used for calculating the positive and negative random propagation time delay distribution of the data packet which is less influenced by the delay of the network equipment based on the SVM;
a preliminary time deviation calculation module for substituting the positive and negative random propagation delay distribution into an L estimator for calculation and estimating a preliminary time deviation;
a final time deviation calculation module for applying a weight-based loop correction to the preliminary time deviation to calculate a final time deviation;
the synchronization module is used for adjusting a hardware clock according to the final time deviation to realize clock synchronization;
wherein, the calculating the positive and negative random propagation delay distribution of the back-to-back data packet which is less influenced by the network device delay based on the SVM includes:
performing SVM processing on the upper limit data and the lower limit data of the back-to-back data packet which are less influenced by the delay of the network equipment to obtain two support vectors;
calculating positive and negative random propagation delay distribution based on the support vector;
further, the calculating forward and backward random propagation delay distribution based on the support vector includes:
taking the support vector as an upper limit and a lower limit, and calculating the longitudinal distance between a data point above the upper support vector and the upper support vector to obtain forward random queuing delay;
and calculating the longitudinal distance between the data point below the lower support vector and the lower support vector to obtain the negative random queuing delay.
7. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the internet-oriented multi-hop high-precision time synchronization protocol implementation method as claimed in any one of claims 1 to 5.
8. A computer-readable storage medium, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the internet-oriented multi-hop high-precision time synchronization protocol implementation method according to any one of claims 1 to 5.
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