CN114513178A - Differential operational amplifier circuit and electronic equipment - Google Patents

Differential operational amplifier circuit and electronic equipment Download PDF

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Publication number
CN114513178A
CN114513178A CN202210149002.1A CN202210149002A CN114513178A CN 114513178 A CN114513178 A CN 114513178A CN 202210149002 A CN202210149002 A CN 202210149002A CN 114513178 A CN114513178 A CN 114513178A
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China
Prior art keywords
differential
tube
bias
resistor
input
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陈婷
胡眺
胡万成
汤雪川
陈出新
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Hunan Goke Microelectronics Co Ltd
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Hunan Goke Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45484—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit
    • H03F3/45488—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with bipolar transistors as the active amplifying circuit by using feedback means

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Abstract

The embodiment of the invention discloses a differential operational amplifier circuit and electronic equipment, wherein the differential operational amplifier circuit comprises a differential amplifier and a common-mode feedback circuit, and the common-mode feedback circuit comprises a bias sub-circuit, a first resistor and a second resistor; one end of the common mode feedback circuit is connected with the power supply input end, and the other end of the common mode feedback circuit is connected with the power supply output end; the bias sub-circuit comprises a first bias tube and a second bias tube, the input end of the differential amplifier is connected with the differential signal input end, the first output end of the differential amplifier is connected with the first bias tube through a first resistor, the second output end of the differential amplifier is connected with the second bias tube, and the second output end of the differential amplifier is connected with the second bias tube through a second resistor. The common-mode feedback is realized by detecting the resistor, the quick response can be realized on the basis of simplifying the circuit structure, and the circuit is suitable for various high-speed signal amplification scenes.

Description

Differential operational amplifier circuit and electronic equipment
Technical Field
The invention relates to the field of integrated circuits, in particular to a differential operational amplifier circuit and electronic equipment.
Background
The fully differential operational amplifier circuit is an integrated circuit which converts a single-end signal into a differential signal or converts the differential signal into the differential signal, and has the characteristics of low noise, capability of effectively inhibiting common-mode noise and capability of outputting a larger voltage swing amplitude.
In a high-gain fully-differential operational amplifier circuit, the output common-mode level is very susceptible to the characteristics and mismatch of devices. In addition, the fully differential operational amplifier circuit cannot stabilize the dc operating point through negative feedback of the differential signal. A common-mode feedback network is usually added to detect the common-mode level of the output of the fully-differential operational amplifier circuit and adjust the bias current. However, the addition of the common mode feedback network requires an additional control chip, which makes the structure design of the integrated circuit more complicated and cannot ensure a stable output common mode level.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a differential operational amplifier circuit and an electronic device to solve the problem that a common mode feedback network cannot output a stable common mode level.
In a first aspect, an embodiment of the present application provides a differential operational amplifier circuit, which includes a differential amplifier and a common-mode feedback circuit, where the common-mode feedback circuit includes a bias sub-circuit, a first resistor and a second resistor;
one end of the common mode feedback circuit is connected with the power supply input end, and the other end of the common mode feedback circuit is connected with the power supply output end;
the bias sub-circuit comprises a first bias tube and a second bias tube, the input end of the differential amplifier is connected with the differential signal input end, the first output end of the differential amplifier is connected with the first bias tube through the first resistor, the second output end of the differential amplifier is connected with the second bias tube through the second resistor, and the grid electrode of the first bias tube is connected with the grid electrode of the second bias tube;
the differential amplifier is used for outputting differential signals to the bias subcircuit, the bias subcircuit is used for setting output level, the first resistor is used for feeding back positive signals output by the differential amplifier to the bias subcircuit, and the second resistor is used for feeding back negative signals output by the differential amplifier to the bias subcircuit.
With reference to the first aspect, in a first possible implementation manner, the apparatus further includes an enable switching tube, where one end of the enable switching tube is connected to the power input end of the differential amplifier, and the other end of the enable switching tube is connected to one end of the common mode feedback circuit;
the enabling switch tube is used for receiving an external enabling signal to control the on-off of the common mode feedback circuit.
With reference to the first aspect, in a second possible implementation manner, the differential amplifier includes an NMOS differential input tube, a first output end of the NMOS differential input tube is connected to a drain of the first bias tube, and the first output end of the NMOS differential input tube is further connected to a gate of the first bias tube through the first resistor, a second output end of the NMOS differential input tube is connected to a drain of the second bias tube, and the second output end of the NMOS differential input tube is further connected to a gate of the second bias tube through the second resistor.
With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner, the common mode feedback circuit further includes a first switch tube and a second switch tube, a first output end of the NMOS differential input tube is connected to the first resistor through the first switch tube, a second output end of the NMOS differential input tube is connected to the second resistor through the second switch tube, and a gate of the first switch tube is connected to a gate of the second switch tube.
With reference to the first aspect, in a fourth possible implementation manner, the differential amplifier includes a PMOS differential input tube, a first output end of the PMOS differential input tube is connected to a drain of the first bias tube, and the first output end of the PMOS differential input tube is further connected to a gate of the first bias tube through the first resistor, a second output end of the PMOS differential input tube is connected to a drain of the second bias tube, and a second output end of the PMOS differential input tube is further connected to a gate of the second bias tube through the second resistor.
With reference to the fourth possible implementation manner of the first aspect, in a fifth possible manner, the common mode feedback circuit further includes a third switch tube and a fourth switch tube, the first output end of the PMOS differential input tube is connected to the first resistor through the third switch tube, and the second output end of the PMOS differential input tube is connected to the second resistor through the fourth switch tube.
With reference to the fourth possible implementation manner of the first aspect, in a sixth possible implementation manner, the common mode feedback circuit further includes a fifth switching tube and a sixth switching tube, the first output end of the PMOS differential input tube is connected to the power input end through the fifth switching tube, and the second output end of the PMOS differential input tube is connected to the power input end through the sixth switching tube.
With reference to the first aspect, in a seventh possible implementation manner, the common mode feedback circuit further includes a filter capacitor, and a gate of the first bias tube is connected to the power output terminal through the filter capacitor.
With reference to the first aspect, in an eighth possible implementation manner, the input end of the differential amplifier includes a first input end and a second input end, the first input end of the differential amplifier is connected to a non-inverting signal input end of the differential signal input end, the second input end of the differential amplifier is connected to a negative-phase signal input end of the differential signal input end, the first output end of the differential amplifier is connected to a drain of the first bias transistor, a gate of the first bias transistor is connected to the first resistor, the second output end of the differential amplifier is connected to a drain of the second bias transistor, and a gate of the second bias transistor is connected to the second resistor.
In a second aspect, an embodiment of the present application provides an electronic device, including a power input terminal, a power output terminal, a differential signal input terminal, and the differential operational amplifier circuit according to the first aspect, wherein the power input terminal is connected to the power output terminal through the differential operational amplifier circuit, and an input terminal of the differential amplifier is connected to the differential signal input terminal.
The application provides a differential operational amplifier circuit, which comprises a differential amplifier and a common-mode feedback circuit, wherein the common-mode feedback circuit comprises a biasing sub-circuit, a first resistor and a second resistor; one end of the common mode feedback circuit is connected with the power supply input end, and the other end of the common mode feedback circuit is connected with the power supply output end; the bias sub-circuit comprises a first bias tube and a second bias tube, the input end of the differential amplifier is connected with the differential signal input end, the first output end of the differential amplifier is connected with the first bias tube through a first resistor, the second output end of the differential amplifier is connected with the second bias tube, and the second output end of the differential amplifier is connected with the second bias tube through a second resistor. The common-mode feedback is realized by detecting the resistor without configuring an additional control chip, so that the circuit structure is simplified, an additional bias circuit is not needed, and the circuit area is reduced. Meanwhile, the differential operational amplifier circuit can respond quickly, can be used as an independent module, and is suitable for various high-speed signal amplification scenes.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings required in the embodiments will be briefly described below, and it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope of the present invention. Like components are numbered similarly in the various figures.
Fig. 1 shows a first structural schematic diagram of a differential operational amplifier circuit provided in an embodiment of the present application;
fig. 2 is a schematic diagram illustrating a second structure of a differential operational amplifier circuit provided in an embodiment of the present application;
fig. 3 is a schematic diagram illustrating a third structure of a differential operational amplifier circuit according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram illustrating a fourth structure of a differential operational amplifier circuit provided in an embodiment of the present application;
fig. 5 shows a schematic structural diagram of an electronic device provided in an embodiment of the present application.
Description of the main element symbols:
100-differential operational amplifier circuit, 200-differential signal input end; 110-common mode feedback circuit; 111-bias subcircuit; VDD-power input terminal, VSS-power output terminal; the power supply comprises an OP-differential amplifier, a POP-PMOS differential input tube, an NOP-NMOS differential input tube, an R1-first resistor, an R2-second resistor, an R3-first protection resistor, an R4-second protection resistor, an M1-first bias tube, an M2-second bias tube, an MEN-enable switch tube, a VDD-VDS-power input end of a pass-through enable switch tube, an M3-first switch tube, an M4-second switch tube, an M5-third switch tube, an M6-fourth switch tube, an M7-fifth switch tube, an M8-sixth switch tube and a C-filter capacitor; the first input end of the INP-differential amplifier, the second input end of the INN-differential amplifier, the first output end of the OUTN-differential amplifier, the second output end of the OUTP-differential amplifier, the first output end of the OUTN1-PMOS differential input tube, the second output end of the OUTP1-PMOS differential input tube, the first output end of the OUTN2-NMOS differential input tube and the second output end of the OUTP2-NMOS differential input tube.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
Hereinafter, the terms "including", "having", and their derivatives, which may be used in various embodiments of the present invention, are intended to indicate only specific features, numerals, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the presence of or adding to one or more other features, numerals, steps, operations, elements, components, or combinations of the foregoing.
Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating a first structure of a differential operational amplifier circuit according to an embodiment of the present disclosure. Exemplarily, the differential operational amplifier circuit 100 of the present application includes a differential amplifier OP and a common-mode feedback circuit 110, the common-mode feedback circuit 110 includes a bias sub-circuit 111, a first resistor R1 and a second resistor R2;
one end of the common mode feedback circuit 110 is connected with a power input end VDD, and the other end of the common mode feedback circuit 110 is connected with a power output end VSS;
the bias sub-circuit 111 comprises a first bias tube M1 and a second bias tube M2, the input end of the differential amplifier is connected with the differential signal input end, the first output end OUTN of the differential amplifier is connected with the first bias tube M1, and the first output end OUTN of the differential amplifier is connected with the first bias tube M1 through the first resistor R1, the second output end OUTP of the differential amplifier is connected with the second bias tube M2, and the second output end OUTP of the differential amplifier is connected with the second bias tube M2 through the second resistor R2, and the gate of the first bias tube M1 is connected with the gate of the second bias tube M2;
the differential amplifier OP is configured to output a differential signal to the bias sub-circuit 111, the bias sub-circuit 111 is configured to set an output level, the first resistor R1 is configured to feed back a positive signal output by the differential amplifier OP to the bias sub-circuit 111, and the second resistor R2 is configured to feed back a negative signal output by the differential amplifier OP to the bias sub-circuit 111.
The differential amplifier OP is used to amplify the difference between the two input voltages with a fixed gain, resulting in an output signal that is stronger than the input signal. Meanwhile, the differential amplifier OP requires a common-mode input voltage range as wide as possible, a signal at the output end of the differential amplifier OP is fed back to the bias sub-circuit 111 through a resistor, common-mode feedback is realized through a resistor detection mode, an additional control chip is not required to be configured, and the circuit structure is simplified. Meanwhile, the common mode feedback circuit 110 can respond quickly, so that the differential operational amplifier circuit 100 of the present application can be applied to various high-speed signal amplification scenarios.
It should be understood that the first bias transistor M1 and the second bias transistor M2 may be any field effect transistors, and are not limited herein. In order to facilitate understanding of the present application, in the present embodiment, MOS (Metal-Oxide-Semiconductor Field-Effect) transistors are used as the first bias transistor M1 and the second bias transistor M2. The signal at the output terminal of the differential amplifier OP is fed back to the gate terminals of the first bias tube M1 and the second bias tube M2 through resistors, so that when the output voltage changes due to the change of the input voltage, the voltages at the gates of the first bias tube M1 and the second bias tube M2 can be adjusted in time. The currents of the first bias tube M1 and the second bias tube M2 vary with the output, and a stable output common mode level is obtained.
The first output terminal OUTN of the differential amplifier is fed back to the gate of the first bias tube M1 through the first resistor R1, the second output terminal OUTP of the differential amplifier is fed back to the gate of the second bias tube M2 through the second resistor R2, and the currents of the first bias tube M1 and the second bias tube M2 vary with the output. The common mode level that is finally output to the power supply output terminal VSS can be determined as:
Vout＝(Voutp+Voutn)*0.5
it is to be understood that VoutFor a common mode level, V, output to the power supply output terminal VSSoutnIs the voltage value, V, of the first resistor R1outpIs the voltage value of the second resistor R2. When the voltage of the first output terminal OUTN of the differential amplifier is greater than the voltage of the second output terminal OUTP of the differential amplifier, the voltage value of the second resistor R2 is greater than the voltage value of the first resistor R1, and a stable common mode level is output. When the voltage of the first output terminal OUTN of the differential amplifier gradually decreases to be equal to the voltage of the second output terminal OUTP of the differential amplifier, the current of the first bias tube M1 is increased, and the current of the second bias tube M2 is decreased, so that a stable common mode level is ensured to be output. Similarly, when the voltage of the first output terminal OUTN of the differential amplifier gradually decreases to be less than the voltage of the second output terminal OUTP of the differential amplifier, the current of the first bias tube M1 is increased, and the current of the second bias tube M2 is decreased, so that a stable common mode level is ensured to be output.
Referring to fig. 2, fig. 2 is a schematic diagram illustrating a second structure of a differential operational amplifier circuit according to an embodiment of the present disclosure. In an optional example, the differential operational amplifier circuit 100 further includes an enable switch MEN, one end of the enable switch MEN is connected to the power input end of the differential amplifier OP, and the other end of the enable switch MEN is connected to one end of the common mode feedback circuit 110;
the enable switch MEN is configured to receive an external enable signal to control the common mode feedback circuit 110 to be turned on or off.
When the differential operational amplifier circuit 100 is not required to operate, the enable switch MEN receives an enable signal sent from the outside, and turns off the common mode feedback circuit 110 in real time, so as to reduce the power consumption of the differential operational amplifier circuit 100. After the power input end VDD passes through the enable switch tube MEN, the voltage changes, and a power input end VDD-VDS passing through the enable switch tube is formed.
In an optional example, the differential amplifier OP includes an NMOS differential input transistor NOP, a first output terminal OUTN2 of the NMOS differential input transistor is connected to the drain of the first bias transistor M1, and a first output terminal OUTN2 of the NMOS differential input transistor is further connected to the gate of the first bias transistor M1 through the first resistor R1, a second output terminal OUTP2 of the NMOS differential input transistor is connected to the drain of the second bias transistor M2, and a second output terminal OUTP2 of the NMOS differential input transistor is further connected to the gate of the second bias transistor M2 through the second resistor R2.
In practical application scenarios, different input swing ranges are required. When the difference between the input signals at the non-inverting signal input terminal of the differential signal input terminal 200 and the negative signal input terminal of the differential signal input terminal 200 is 0.5 times or more the voltage value at the voltage input terminal, it is determined that the input voltage is a high voltage section, and the differential input pair composed of the NMOS differential input tubes NOP functions as an operational amplifier.
In an optional example, the common mode feedback circuit 110 further includes a first switching tube M3 and a second switching tube M4, the first output terminal OUTN2 of the NMOS differential input tube is connected to the first resistor R1 through the first switching tube M3, the second output terminal OUTP2 of the NMOS differential input tube is connected to the second resistor R2 through the second switching tube M4, and the gate of the first switching tube M3 is connected to the gate of the second switching tube M4.
The static operating point is also called as a bias point, when the alternating current input signal of the transistor is zero, the circuit is in a direct current operating state, and the point at which the numerical values of the current and the voltage are determined by the characteristic curve is the static operating point. The static operating point is added to the first switch tube M3 to obtain a bias current, so as to prevent the first resistor R1 from being directly connected to the first output terminal OUTN2 of the NMOS differential input tube. And a static working point is added to the second switching tube M4 to obtain a bias current, so that the second resistor R2 is prevented from being directly connected to the second output end OUTP2 of the NMOS differential input tube.
It should be understood that, in this embodiment, the first switch transistor M3 and the second switch transistor M4 are both NMOS transistors, and the gate of the first switch transistor M3 is connected to the gate of the second switch transistor M4, so as to set a static operating point.
In an optional example, the differential amplifier OP includes a PMOS differential input pipe POP, a first output terminal OUTN1 of the PMOS differential input pipe is connected to the drain of the first bias pipe M1, and a first output terminal OUTN1 of the PMOS differential input pipe is further connected to the gate of the first bias pipe M1 through the first resistor R1, a second output terminal OUTP1 of the PMOS differential input pipe is connected to the drain of the second bias pipe M2, and a second output terminal OUTP1 of the PMOS differential input pipe is further connected to the gate of the second bias pipe M2 through the second resistor R2.
When the difference between the input signals at the non-inverting signal input terminal of the differential signal input terminal 200 and the inverting signal input terminal of the differential signal input terminal 200 is less than 0.5 times the voltage value at the voltage input terminal, it is determined that the input voltage is a low voltage section, and the differential input pair formed by the PMOS differential input transistor POP functions as an operational amplifier.
In addition, when the input voltage has both high voltage and low voltage, the differential input formed by the PMOS differential input tube POP and the NMOS differential input tube NOP simultaneously functions as an operational amplifier, so that when the full-swing input signal is input, the differential operational amplifier circuit 100 of the present application can work normally, and application scenarios are increased.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating a third structure of a differential operational amplifier circuit according to an embodiment of the present disclosure.
In an optional example, the common mode feedback circuit 110 further includes a third switching tube M5 and a fourth switching tube M6, the first output terminal OUTN1 of the PMOS differential input tube is connected to the first resistor R1 through the third switching tube M5, and the second output terminal OUTP1 of the PMOS differential input tube is connected to the second resistor R2 through the fourth switching tube M6.
In this embodiment, the gates of the third switching tube M5 and the fourth switching tube M6 are both connected to the first resistor R1 to form a bias current, so as to provide a proper static operating point for the common mode feedback circuit 110.
In an optional example, the common mode feedback circuit 110 further includes a fifth switching tube M7 and a sixth switching tube M8, the first output terminal OUTN1 of the PMOS differential input tube is connected to the power supply input terminal VDD through the fifth switching tube M7, and the second output terminal OUTP1 of the PMOS differential input tube is connected to the power supply input terminal VDD through the sixth switching tube M8.
In this embodiment, the gates of the fifth switch transistor M7 and the sixth switch transistor M8 are both connected to the power input terminal VDD to form a bias current, so as to provide a proper static operating point for the common mode feedback circuit 110. The switching tube provides an accurate static working point for the common mode feedback circuit 110, so that the differential output of the differential operational amplifier circuit 100 is accurate, and a circuit responsible for compensation is not required to be arranged through an integrated circuit such as a control chip for quick response, so that the differential operational amplifier circuit 100 is simple in structure.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating a fourth structure of the differential operational amplifier circuit according to the embodiment of the present disclosure. In order to facilitate understanding of the present application, in this embodiment, the gate of the first bias transistor M1 is connected to the gate of the second bias transistor M2, the gate of the first switching transistor M3 is connected to the gate of the second switching transistor M4, the gate of the third switching transistor M5 is connected to the gate of the fourth switching transistor M6, and the gate of the fifth switching transistor M7 is connected to the gate of the sixth switching transistor M8, so as to form a bias current path, and provide a static operating point required by the differential operational amplifier circuit.
The grid electrode of the first switching tube M3 is connected with the grid electrode of the first biasing tube M1 through a first protection resistor R3, so as to prevent the first switching tube M3 from being directly connected with the first biasing tube M1; the gate of the second switching tube M4 is connected to the gate of the second bias tube M2 through the second protection resistor R4, so as to avoid the direct connection between the second switching tube M4 and the second bias tube M2 from affecting the formation of the current bias point.
In an optional example, the common mode feedback circuit 110 further includes a filter capacitor C, and a gate of the first bias tube M1 is used for being connected to the power supply output terminal VSS through the filter capacitor C.
The filter capacitor C is used for reducing the alternating current ripple coefficient so as to obtain smooth direct current output. Meanwhile, the filter capacitor C is used for filtering noise, so that the differential operational amplifier circuit 100 outputs a signal with a specific frequency.
In an optional example, the input terminals of the differential amplifier OP include a first input terminal and a second input terminal, the first input terminal INP of the differential amplifier is configured to be connected to the non-inverting input terminal of the differential signal input terminal 200, the second input terminal INN of the differential amplifier is configured to be connected to the inverting input terminal of the differential signal input terminal 200, the first output terminal OUTN of the differential amplifier is connected to the drain of the first bias transistor M1, the gate of the first bias transistor M1 is connected to the first resistor R1, the second output terminal OUTP of the differential amplifier is connected to the drain of the second bias transistor M2, and the gate of the second bias transistor M2 is connected to the second resistor R2.
The differential transmission is a signal transmission technique, and specifically, in the present embodiment, the signals input to the first input terminal INP of the differential amplifier and the second input terminal INN of the differential amplifier have the same amplitude and opposite phases. The signal difference between the first output end OUTN and the second output end OUTP of the differential amplifier is used as an output signal, so that errors can be effectively reduced.
The application provides a differential operational amplifier circuit, which comprises a differential amplifier and a common-mode feedback circuit, wherein the common-mode feedback circuit comprises a biasing sub-circuit, a first resistor and a second resistor; one end of the common mode feedback circuit is connected with the power supply input end, and the other end of the common mode feedback circuit is connected with the power supply output end; the bias sub-circuit comprises a first bias tube and a second bias tube, the input end of the differential amplifier is connected with the differential signal input end, the first output end of the differential amplifier is connected with the first bias tube through a first resistor, the second output end of the differential amplifier is connected with the second bias tube, and the second output end of the differential amplifier is connected with the second bias tube through a second resistor. The common-mode feedback is realized by detecting the resistor without configuring an additional control chip, so that the circuit structure is simplified, an additional bias circuit is not needed, and the circuit area is reduced. Meanwhile, the differential operational amplifier circuit can respond quickly, can be used as an independent module, and is suitable for various high-speed signal amplification scenes.
Referring to fig. 5, fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure. The electronic device includes a power input terminal VDD, a power output terminal VSS, a differential signal input terminal 200, and the differential operational amplifier circuit 100 in this embodiment, the power input terminal VDD is connected to the power output terminal VSS through the differential operational amplifier circuit 100, and an input terminal of the differential amplifier OP is connected to the differential signal input terminal 200.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative and, for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, each functional module or unit in each embodiment of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention or a part of the technical solution that contributes to the prior art in essence can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention.

Claims (10)

1. The differential operational amplifier circuit is characterized by comprising a differential amplifier and a common-mode feedback circuit, wherein the common-mode feedback circuit comprises a biasing sub-circuit, a first resistor and a second resistor;
one end of the common mode feedback circuit is connected with the power supply input end, and the other end of the common mode feedback circuit is connected with the power supply output end;
the bias sub-circuit comprises a first bias tube and a second bias tube, the input end of the differential amplifier is connected with the differential signal input end, the first output end of the differential amplifier is connected with the first bias tube through the first resistor, the second output end of the differential amplifier is connected with the second bias tube through the second resistor, and the grid electrode of the first bias tube is connected with the grid electrode of the second bias tube;
the differential amplifier is used for outputting differential signals to the bias subcircuit, the bias subcircuit is used for setting output level, the first resistor is used for feeding back positive signals output by the differential amplifier to the bias subcircuit, and the second resistor is used for feeding back negative signals output by the differential amplifier to the bias subcircuit.
2. The differential operational amplifier circuit according to claim 1, further comprising an enable switch, wherein one end of the enable switch is connected to the power input terminal of the differential amplifier, and the other end of the enable switch is connected to one end of the common mode feedback circuit;
the enabling switch tube is used for receiving an external enabling signal to control the on-off of the common mode feedback circuit.
3. The differential operational amplifier circuit as claimed in claim 1, wherein the differential amplifier comprises an NMOS differential input transistor, the first output terminal of the NMOS differential input transistor is connected to the drain of the first bias transistor, and the first output terminal of the NMOS differential input transistor is further connected to the gate of the first bias transistor through the first resistor, the second output terminal of the NMOS differential input transistor is connected to the drain of the second bias transistor, and the second output terminal of the NMOS differential input transistor is further connected to the gate of the second bias transistor through the second resistor.
4. The differential operational amplifier circuit according to claim 3, wherein the common mode feedback circuit further comprises a first switch tube and a second switch tube, the first output terminal of the NMOS differential input tube is connected to the first resistor through the first switch tube, the second output terminal of the NMOS differential input tube is connected to the second resistor through the second switch tube, and the gate of the first switch tube is connected to the gate of the second switch tube.
5. The differential operational amplifier circuit according to claim 1, wherein the differential amplifier comprises a PMOS differential input transistor, a first output terminal of the PMOS differential input transistor is connected to a drain of the first bias transistor, and the first output terminal of the PMOS differential input transistor is further connected to a gate of the first bias transistor through the first resistor, a second output terminal of the PMOS differential input transistor is connected to a drain of the second bias transistor, and the second output terminal of the PMOS differential input transistor is further connected to a gate of the second bias transistor through the second resistor.
6. The differential operational amplifier circuit according to claim 5, wherein the common mode feedback circuit further comprises a third switching tube and a fourth switching tube, the first output terminal of the PMOS differential input tube is connected to the first resistor through the third switching tube, and the second output terminal of the PMOS differential input tube is connected to the second resistor through the fourth switching tube.
7. The differential operational amplifier circuit according to claim 5, wherein the common mode feedback circuit further comprises a fifth switching tube and a sixth switching tube, the first output terminal of the PMOS differential input tube is connected to the power input terminal through the fifth switching tube, and the second output terminal of the PMOS differential input tube is connected to the power input terminal through the sixth switching tube.
8. The differential operational amplifier circuit according to claim 1, wherein the common mode feedback circuit further comprises a filter capacitor, and the gate of the first bias transistor is connected to the power output terminal through the filter capacitor.
9. The differential operational amplifier circuit according to claim 1, wherein the input terminals of the differential amplifier comprise a first input terminal and a second input terminal, the first input terminal of the differential amplifier is connected to a non-inverting signal input terminal of the differential signal input terminals, the second input terminal of the differential amplifier is connected to a negative signal input terminal of the differential signal input terminals, the first output terminal of the differential amplifier is connected to the drain of the first bias transistor, the gate of the first bias transistor is connected to the first resistor, the second output terminal of the differential amplifier is connected to the drain of the second bias transistor, and the gate of the second bias transistor is connected to the second resistor.
10. An electronic device comprising a power input terminal, a power output terminal, a differential signal input terminal, and the differential operational amplifier circuit as claimed in any one of claims 1 to 9, wherein the power input terminal is connected to the power output terminal through the differential operational amplifier circuit, and wherein the input terminal of the differential amplifier is connected to the differential signal input terminal.
CN202210149002.1A 2022-02-18 2022-02-18 Differential operational amplifier circuit and electronic equipment Pending CN114513178A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210149002.1A CN114513178A (en) 2022-02-18 2022-02-18 Differential operational amplifier circuit and electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210149002.1A CN114513178A (en) 2022-02-18 2022-02-18 Differential operational amplifier circuit and electronic equipment

Publications (1)

Publication Number Publication Date
CN114513178A true CN114513178A (en) 2022-05-17

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210149002.1A Pending CN114513178A (en) 2022-02-18 2022-02-18 Differential operational amplifier circuit and electronic equipment

Country Status (1)

Country Link
CN (1) CN114513178A (en)

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