CN114510104A

CN114510104A - Band gap reference starting circuit

Info

Publication number: CN114510104A
Application number: CN202210111393.8A
Authority: CN
Inventors: 李雪民
Original assignee: Suzhou Linghui Lixin Technology Co ltd
Current assignee: Suzhou Linghui Lixin Technology Co ltd
Priority date: 2022-01-29
Filing date: 2022-01-29
Publication date: 2022-05-17
Anticipated expiration: 2042-01-29
Also published as: CN114510104B

Abstract

The invention discloses a band gap reference starting circuit, comprising: the band-gap reference circuit module and the starting circuit module; the band gap reference circuit module is connected with a power supply; the starting circuit module is respectively connected with the band-gap reference circuit module and the power supply, and when the band-gap reference circuit module is at a zero working point, the starting circuit module enables the band-gap reference circuit module to recover normal work; the starting circuit module comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube, and the first NMOS tube, the fourth NMOS tube and the fifth NMOS tube are respectively connected with the band gap reference circuit module. The invention ensures that the output voltage can recover the work of the band-gap reference circuit under any condition, so that the band-gap reference starting circuit has better robustness.

Description

Band gap reference starting circuit

Technical Field

The invention belongs to the technical field of electronic circuits, and particularly relates to a band-gap reference starting circuit.

Background

The Bandgap reference (Bandgap) circuit provides a voltage to the chip that is not variable with temperature and process variations. However, bandgap circuits typically have two reasonable operating points, one being a normal operating point and the other being a zero voltage operating point. In actual operation, the zero operating point is avoided as much as possible, so that the common bandgap circuit needs a starting circuit.

The bandgap start-up circuit typically mirrors one path of current generated by the bandgap circuit to compare with another path of current that is not zero. If the bandgap circuit is at the zero working point, the starting circuit pulls the grid electrode of the NMOS tube high or pulls the grid electrode of the PMOS tube low through the output of the current operational amplifier, so that the circuit is separated from the zero working point. If the bandgap circuit is in the normal operating mode, the startup circuit is disabled.

Fig. 1 is a schematic diagram of a bandgap circuit and its start-up circuit. In normal operation, VN is VP due to the virtual short characteristic of operational amplifier, and thus dvbe vtln (m) is added across R1 to generate PTAT current, where m is the area ratio of Q2 to Q1, and assuming that R2 is R3, VREF is VBE2+ dvbe/R1 (R3+ 2R 4), the first term is a negative temperature Coefficient (CTAT) term, and the second term is a positive temperature coefficient (PTAT) term. At this time, the current mirrored from PM4 to NM3 is greater than the current flowing through the linear region transistor formed by connecting PMa1 to PMaN in series, so VCOMP is 0, the transistor NM _ clamp is not turned on, and the start-up circuit does not operate. At the zero operating point, the currents flowing through R1/R2/R3/R4 are all 0, VREF is a voltage smaller than that of the transistor VEB, and no current flows from PM1 to PM4, at this time, the current mirrored from PM4 to NM3 is smaller than the current flowing through the linear region transistor formed by connecting PMa1 to PMaN in series, VCOMP is high level, so that the transistor NM _ clamp is turned on, and the gate voltage VAMP of NM1 is pulled high to be away from the zero operating point.

The starting scheme only detects the current generated by the circuit to judge whether the circuit is started successfully. However, in some cases a single sensed current may not guarantee that the output Voltage (VREF) will output a normal value. For example, during a slow power-up of the power supply, there is a possibility that the current of NM3 is just equal to or slightly larger than the current of PMa1 PMaN, VCOMP goes low, transistor NM _ clamp is turned off, and the start-up circuit is no longer functional. But at this time, because the current in the circuit is very small (for example, tens of nA), the VREF voltage still does not reach about 1.2V. The offset exists due to the finite gain of the operational amplifier, and the difference between VP and VN is not negligible (because the voltage difference between R1 is small), and dvbe and VT ln (m) are no longer true. On the other hand, the operational amplifier may not work normally at this time because the bias current of the operational amplifier also comes from the circuit. In this case, the negative feedback loop is broken, and the output VREF cannot be set to about 1.2V. VREF is much less than 0.7V, typically due to the small current.

Therefore, a robust start-up circuit is particularly needed, and the output voltage of the bandgap reference circuit can make the bandgap reference circuit recover to work under various voltage values.

Disclosure of Invention

The invention aims to provide a starting circuit with good robustness, and the output voltage of a band-gap reference circuit can enable the band-gap reference circuit to recover to work under various voltage values.

In order to achieve the above object, the present invention provides a bandgap reference start circuit, including: the band-gap reference circuit module and the starting circuit module; the band-gap reference circuit module is connected with a power supply; the starting circuit module is respectively connected with the band-gap reference circuit module and the power supply, and the starting circuit module enables the band-gap reference circuit module to recover normal work; the starting circuit module comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube; the first PMOS tube is respectively connected with the power supply, a second PMOS tube and a third PMOS tube, the second PMOS tube is respectively connected with the first PMOS tube and the third PMOS tube, and the third PMOS tube is respectively connected with the second PMOS tube, the first NMOS tube, the second NMOS tube and the third NMOS tube; the band-gap reference circuit comprises a band-gap reference circuit module, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a band-gap reference circuit module, wherein the first NMOS tube is connected with the band-gap reference circuit module, the third PMOS tube is connected with the fourth NMOS tube, the third NMOS tube and the fourth NMOS tube, the third NMOS tube is connected with the third PMOS tube, the first NMOS tube, the second NMOS tube and the fifth NMOS tube, the fourth NMOS tube is connected with the second NMOS tube, the fifth NMOS tube and the band-gap reference circuit module, and the fifth NMOS tube is connected with the third NMOS tube, the fourth NMOS tube and the band-gap reference circuit module.

Preferably, a source electrode of the first PMOS transistor is connected with the positive electrode of the power supply, a drain electrode of the first PMOS transistor is connected with a source electrode of the second PMOS transistor, and a gate electrode of the first PMOS transistor is respectively connected with a gate electrode of the second PMOS transistor and a gate electrode of the third PMOS transistor; the source electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the second PMOS tube is respectively connected with the grid electrode of the first PMOS tube and the grid electrode of the third PMOS tube, and the drain electrode of the second PMOS tube is connected with the source electrode of the third PMOS tube; the source electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the third PMOS tube is respectively connected with the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is respectively connected with the drain electrode of the first NMOS tube, the grid electrode of the first NMOS tube and the drain electrode of the third NMOS tube; the source electrode of the fourth PMOS tube is connected with the positive electrode of the power supply, the drain electrode of the fourth PMOS tube is respectively connected with the grid electrode and the drain electrode of the second NMOS tube and the grid electrode of the third NMOS tube, and the grid electrode of the fourth PMOS tube is connected with the band-gap reference circuit module; the drain electrode of the first NMOS tube is respectively connected with the grid electrode of the first NMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube, the grid electrode of the first NMOS tube is respectively connected with the drain electrode of the first NMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube, and the source electrode of the first NMOS tube is connected with the band-gap reference circuit module; the drain electrode of the second NMOS tube is respectively connected with the grid electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the fourth PMOS tube, the grid electrode of the second NMOS tube is respectively connected with the drain electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the fourth PMOS tube, and the source electrode of the second NMOS tube is connected with the drain electrode of the fourth NMOS tube; the drain electrode of the third NMOS tube is respectively connected with the drain electrode and the grid electrode of the first NMOS tube and the drain electrode of the third PMOS tube, the grid electrode of the third NMOS tube is respectively connected with the grid electrode and the drain electrode of the second NMOS tube and the drain electrode of the fourth PMOS tube, and the source electrode of the third NMOS tube is connected with the drain electrode of the fifth NMOS tube.

Preferably, a gate of the fourth NMOS transistor is connected to the gate of the fifth NMOS transistor and the bandgap reference circuit module, a drain of the fourth NMOS transistor is connected to a source of the second NMOS transistor, and a source of the fourth NMOS transistor is connected to a negative electrode of the power supply; the grid electrode of the fifth NMOS tube is respectively connected with the grid electrode of the fourth NMOS tube and the band-gap reference circuit module, the drain electrode of the fifth NMOS tube is connected with the source electrode of the third NMOS tube, and the source electrode of the fifth NMOS tube is connected with the negative electrode of the power supply.

Preferably, the bandgap reference circuit module includes: the transistor comprises a fifth PMOS (P-channel metal oxide semiconductor) tube, a sixth PMOS tube, a seventh PMOS tube, a first resistor, a second-section resistor, a third resistor, a first triode, a second triode, an operational amplifier and a sixth NMOS (N-channel metal oxide semiconductor) tube; a source electrode of the fifth PMOS tube is connected with the positive electrode of the power supply, a grid electrode of the fifth PMOS tube is respectively connected with a grid electrode of the fourth PMOS tube, a grid electrode of the sixth PMOS tube and a grid electrode of the seventh PMOS tube, and a drain electrode of the fifth PMOS tube is connected with one end of the fourth resistor, the grid electrode of the fifth NMOS tube and the grid electrode of the fourth NMOS tube; a source electrode of the sixth PMOS tube is connected with the positive electrode of the power supply, a grid electrode of the sixth PMOS tube is respectively connected with a grid electrode of the fourth PMOS tube, a grid electrode of the fifth PMOS tube and a grid electrode of the seventh PMOS tube, and a drain electrode of the sixth PMOS tube is connected with the first end of the operational amplifier; the source electrode of the seventh PMOS tube is connected with the positive electrode of the power supply, the grid electrode of the seventh PMOS tube is respectively connected with the grid electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the sixth NMOS tube.

Preferably, the other end of the fourth resistor is connected to one end of the second resistor and one end of the third resistor, the other end of the second resistor is connected to one end of the first resistor and the negative phase input end of the operational amplifier, the other end of the first resistor is connected to the emitter of the first triode, and the other end of the third resistor is connected to the positive phase input end of the operational amplifier and the emitter of the second triode; an emitting electrode of the first triode is connected with the other end of the first resistor, and a base electrode and a collector electrode of the first triode are both connected with the negative electrode of the power supply; and the emitter of the second triode is connected with the other end of the third resistor, and the base and the collector of the second triode are both connected with the negative electrode of the power supply.

Preferably, a negative phase input end of the operational amplifier is connected to the other end of the second resistor and one end of the first resistor, a positive phase input end of the operational amplifier is connected to the other end of the third resistor and an emitter of the second amplifier, a first end of the operational amplifier is connected to a drain of the sixth PMOS transistor, and an output end of the operational amplifier is connected to a gate of the sixth NMOS transistor and a source of the first NMOS transistor; the grid electrode of the sixth NMOS tube is respectively connected with the output end of the operational amplifier and the source electrode of the first NMOS tube, the drain electrode of the sixth NMOS tube is connected with the drain electrode of the seventh PMOS tube, and the source electrode of the sixth NMOS tube is connected with the negative electrode of the power supply.

Preferably, the voltage at the junction of the drain of the fifth PMOS transistor, one end of the fourth resistor, the gate of the fifth NMOS transistor, and the gate of the fourth NMOS transistor is the output voltage of the operational amplifier.

The invention has the beneficial effects that: the starting circuit module in the bandgap reference starting circuit enables the bandgap reference circuit module to recover normal work, and the bandgap reference circuit can recover work under the condition that the output voltage of the bandgap reference circuit module is various voltage values, so that the bandgap reference starting circuit has better robustness.

The apparatus of the present invention has other features and advantages which will be apparent from or are set forth in detail in the accompanying drawings and the following detailed description, which are incorporated herein, and which together serve to explain certain principles of the invention.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail exemplary embodiments thereof with reference to the attached drawings, in which like reference numerals generally represent like parts throughout.

Figure 1 shows a schematic diagram of a prior art bandgap reference start-up.

Fig. 2 shows a schematic diagram of a bandgap reference start-up circuit according to the present invention.

Description of reference numerals:

102. starting a circuit module; 104. a band gap reference circuit module; PMa1, a first PMOS tube; PMa2, a second PMOS tube; PMaN and a third PMOS tube; PM4 and a fourth PMOS tube; PM3 and a fifth PMOS tube; PM2 and a sixth PMOS tube; PM1, seventh PMOS tube; NM-clamp, first NMOS tube; NM1, sixth NMOS tube; NM2, a second NMOS tube; NM3, third NMOS tube; NM4, fourth NMOS tube; NM5, fifth NMOS tube; r1, a first resistor; r2, a second resistor; r3, third resistor; r4, fourth resistor; q1, the first triode; q2, the second triode; u1, operational amplifier; AVDD, positive pole of the power supply; AGND, negative electrode of power supply; VREF, output voltage.

Detailed Description

Preferred embodiments of the present invention will be described in more detail below. While the following describes preferred embodiments of the present invention, it should be understood that the present invention may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

A bandgap reference start-up circuit according to the present invention comprises: the band-gap reference circuit module and the starting circuit module; the band gap reference circuit module is connected with a power supply; the starting circuit module is respectively connected with the band-gap reference circuit module and the power supply, and the starting circuit module enables the band-gap reference circuit module to recover normal work; the starting circuit module comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube; the first PMOS tube is respectively connected with the power supply, the second PMOS tube and the third PMOS tube, the second PMOS tube is respectively connected with the first PMOS tube and the third PMOS tube, and the third PMOS tube is respectively connected with the second PMOS tube, the first NMOS tube, the second NMOS tube and the third NMOS tube; the first NMOS tube is respectively connected with the band gap reference circuit module, the third PMOS tube and the third NMOS tube, the second NMOS tube is respectively connected with the fourth PMOS tube, the third NMOS tube and the fourth NMOS tube, the third NMOS tube is respectively connected with the third PMOS tube, the first NMOS tube, the second NMOS tube and the fifth NMOS tube, the fourth NMOS tube is respectively connected with the second NMOS tube, the fifth NMOS tube and the band gap reference circuit module, and the fifth NMOS tube is respectively connected with the third NMOS tube, the fourth NMOS tube and the band gap reference circuit module.

Specifically, when the bandgap reference circuit is at a zero point, the bandgap reference circuit recovers normal operation due to the combined action of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the first NMOS transistor, the second NMOS transistor and the third NMOS transistor, and when the bandgap reference circuit is not at the zero point and the output voltage of the bandgap reference circuit is less than the threshold voltage, the bandgap reference circuit recovers normal operation due to the combined action of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor and the fifth NMOS transistor, and the threshold voltage is preferably 0.7V.

According to an exemplary embodiment, the starting circuit module in the bandgap reference starting circuit enables the bandgap reference circuit module to recover normal operation, and the bandgap reference circuit can recover operation under the condition that the output voltage of the bandgap reference circuit module is various voltage values, so that the bandgap reference starting circuit has better robustness.

As a preferred scheme, a source electrode of a first PMOS tube is connected with a positive electrode of a power supply, a drain electrode of the first PMOS tube is connected with a source electrode of a second PMOS tube, and a grid electrode of the first PMOS tube is respectively connected with a grid electrode of the second PMOS tube and a grid electrode of a third PMOS tube; the source electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the second PMOS tube is respectively connected with the grid electrode of the first PMOS tube and the grid electrode of the third PMOS tube, and the drain electrode of the second PMOS tube is connected with the source electrode of the third PMOS tube; the source electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the third PMOS tube is respectively connected with the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is respectively connected with the drain electrode of the first NMOS tube, the grid electrode of the first NMOS tube and the drain electrode of the third NMOS tube; a source electrode of the fourth PMOS tube is connected with the positive electrode of the power supply, a drain electrode of the fourth PMOS tube is respectively connected with a grid electrode and a drain electrode of the second NMOS tube and a grid electrode of the third NMOS tube, and the grid electrode of the fourth PMOS tube is connected with the band-gap reference circuit module; the drain electrode of the first NMOS tube is respectively connected with the grid electrode of the first NMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube, the grid electrode of the first NMOS tube is respectively connected with the drain electrode of the first NMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube, and the source electrode of the first NMOS tube is connected with the band gap reference circuit module; the drain electrode of the second NMOS tube is respectively connected with the grid electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the fourth PMOS tube, the grid electrode of the second NMOS tube is respectively connected with the drain electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the fourth PMOS tube, and the source electrode of the second NMOS tube is connected with the drain electrode of the fourth NMOS tube; the drain electrode of the third NMOS tube is respectively connected with the drain electrode of the first NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the third PMOS tube, the grid electrode of the third NMOS tube is respectively connected with the grid electrode of the second NMOS tube, the drain electrode of the second NMOS tube and the drain electrode of the fourth PMOS tube, and the source electrode of the third NMOS tube is connected with the drain electrode of the fifth NMOS tube.

Specifically, when the output voltage is higher than 0.7V, the current mirrored from the fourth PMOS transistor to the third NMOS transistor is smaller than the current flowing through the linear region transistor formed by connecting the first PMOS transistor to the third PMOS transistor in series, and VCOMP is at a high level, so that the first NMOS transistor is turned on, and the gate voltage VAMP of the sixth NMOS transistor is pulled high to be away from a zero operating point.

As a preferred scheme, a grid electrode of a fourth NMOS tube is respectively connected with a grid electrode of a fifth NMOS tube and a band-gap reference circuit module, a drain electrode of the fourth NMOS tube is connected with a source electrode of a second NMOS tube, and a source electrode of the fourth NMOS tube is connected with a negative electrode of a power supply; the grid electrode of the fifth NMOS tube is respectively connected with the grid electrode of the fourth NMOS tube and the band-gap reference circuit module, the drain electrode of the fifth NMOS tube is connected with the source electrode of the third NMOS tube, and the source electrode of the fifth NMOS tube is connected with the negative electrode of the power supply.

Specifically, when the output voltage is less than 0.7V, the fourth NMOS transistor and the fifth NMOS transistor are added in the starting circuit, and the gates of the fourth NMOS transistor and the fifth NMOS transistor are connected to VREF, so that it can be ensured that no current flows in the second NMOS transistor and the third NMOS transistor, VCOMP is pulled high, the gate of the first NMOS transistor is pulled high, and the circuit finally enters a normal operating mode through negative feedback.

Preferably, the bandgap reference circuit module includes: the transistor comprises a fifth PMOS (P-channel metal oxide semiconductor) tube, a sixth PMOS tube, a seventh PMOS tube, a first resistor, a second-section resistor, a third resistor, a first triode, a second triode, an operational amplifier and a sixth NMOS (N-channel metal oxide semiconductor) tube; a source electrode of the fifth PMOS tube is connected with a positive electrode of the power supply, a grid electrode of the fifth PMOS tube is respectively connected with a grid electrode of the fourth PMOS tube, a grid electrode of the sixth PMOS tube and a grid electrode of the seventh PMOS tube, and a drain electrode of the fifth PMOS tube is connected with one end of the fourth resistor, the grid electrode of the fifth NMOS tube and the grid electrode of the fourth NMOS tube; a source electrode of the sixth PMOS tube is connected with the positive electrode of the power supply, a grid electrode of the sixth PMOS tube is respectively connected with a grid electrode of the fourth PMOS tube, a grid electrode of the fifth PMOS tube and a grid electrode of the seventh PMOS tube, and a drain electrode of the sixth PMOS tube is connected with the first end of the operational amplifier; the source electrode of the seventh PMOS tube is connected with the positive electrode of the power supply, the grid electrode of the seventh PMOS tube is respectively connected with the grid electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the sixth NMOS tube.

Specifically, the current flowing through the fifth PMOS transistor is shunted and flows into the operational amplifier.

As a preferred scheme, the other end of the fourth resistor is respectively connected with one end of the second resistor and one end of the third resistor, the other end of the second resistor is respectively connected with one end of the first resistor and the negative phase input end of the operational amplifier, the other end of the first resistor is connected with the emitter of the first triode, and the other end of the third resistor is respectively connected with the positive phase input end of the operational amplifier and the emitter of the second triode; the emitter of the first triode is connected with the other end of the first resistor, and the base and the collector of the first triode are both connected with the negative electrode of the power supply; and an emitting electrode of the second triode is connected with the other end of the third resistor, and a base electrode and a collector electrode of the second triode are both connected with the negative electrode of the power supply.

Specifically, the current is shunted by the first resistor, the second resistor and the third resistor, and the shunted current flows into the positive phase input end and the negative phase input end of the operational amplifier respectively.

As a preferred scheme, a negative phase input end of the operational amplifier is respectively connected with the other end of the second resistor and one end of the first resistor, a positive phase input end of the operational amplifier is respectively connected with the other end of the third resistor and an emitter of the second amplifier, a first end of the operational amplifier is connected with a drain electrode of the sixth PMOS transistor, and an output end of the operational amplifier is respectively connected with a gate electrode of the sixth NMOS transistor and a source electrode of the first NMOS transistor; the grid electrode of the sixth NMOS tube is respectively connected with the output end of the operational amplifier and the source electrode of the first NMOS tube, the drain electrode of the sixth NMOS tube is connected with the drain electrode of the seventh PMOS tube, and the source electrode of the sixth NMOS tube is connected with the negative electrode of the power supply.

Specifically, when the output voltage is greater than 0.7V, the output voltage of the operational amplifier is high, the operational amplifier operates normally, and the output of the operational amplifier pulls the gate of the sixth NMOS transistor high, so that the circuit is separated from the zero operating point.

Preferably, the voltage at the connection position of the drain of the fifth PMOS transistor, one end of the fourth resistor, the gate of the fifth NMOS transistor and the gate of the fourth NMOS transistor is the output voltage of the operational amplifier.

Examples

As shown in fig. 2, the bandgap reference start-up circuit includes: a band-gap reference circuit module 104 and a starting circuit module 102; the band-gap reference circuit module 104 is connected with a power supply; the starting circuit module 102 is respectively connected with the bandgap reference circuit module 104 and the power supply, and when the output voltage of the bandgap reference circuit module 104 is zero, the starting circuit module 102 enables the bandgap reference circuit module 104 to recover to normal operation; the startup circuit module 102 includes a first PMOS transistor PMa1, a second PMOS transistor PMa2, a third PMOS transistor PMaN, a fourth PMOS transistor PM4, a first NMOS transistor NM-clamp, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, and a fifth NMOS transistor NM 5; the first PMOS tube PMa1 is respectively connected with a power supply, a second PMOS tube PMa2 and a third PMOS tube PMaN, the second PMOS tube PMa2 is respectively connected with the first PMOS tube PMa1 and the third PMOS tube PMaN, and the third PMOS tube PMaN is respectively connected with the second PMOS tube PMa2, a first NMOS tube NM-clamp, a second NMOS tube NM2 and a third NMOS tube NM 3; the first NMOS transistor NM-clamp is connected to the bandgap reference circuit module 104, the third PMOS transistor PMaN and the third NMOS transistor NM3, the second NMOS transistor NM2 is connected to the fourth PMOS transistor PM4, the third NMOS transistor NM3 and the fourth NMOS transistor NM4, the third NMOS transistor NM3 is connected to the third PMOS transistor PMaN, the first NMOS transistor NM-clamp, the second NMOS transistor NM2 and the fifth NMOS transistor NM5, the fourth NMOS transistor NM4 is connected to the second NMOS transistor NM2, the fifth NMOS transistor NM5 and the bandgap reference circuit module 104, and the fifth NMOS transistor NM5 is connected to the third NMOS transistor NM3, the fourth NMOS transistor NM4 and the bandgap reference circuit module 104.

The source electrode of the first PMOS transistor PMa1 is connected with the positive electrode of a power supply, the drain electrode of the first PMOS transistor PMa1 is connected with the source electrode of the second PMOS transistor PMa2, and the grid electrode of the first PMOS transistor PMa1 is respectively connected with the grid electrode of the second PMOS transistor PMa2 and the grid electrode of the third PMOS transistor PMaN; the source electrode of the second PMOS pipe PMa2 is connected with the drain electrode of the first PMOS pipe PMa1, the grid electrode of the second PMOS pipe PMa2 is respectively connected with the grid electrode of the first PMOS pipe PMa1 and the grid electrode of the third PMOS pipe PMaN, and the drain electrode of the second PMOS pipe PMa2 is connected with the source electrode of the third PMOS pipe PMaN; the source electrode of the third PMOS pipe PMaN is connected with the drain electrode of the second PMOS pipe PMa2, the grid electrode of the third PMOS pipe PMaN is respectively connected with the grid electrode of the first PMOS pipe PMa1 and the grid electrode of the second PMOS pipe PMa2, and the drain electrode of the third PMOS pipe PMaN is respectively connected with the drain electrode and the grid electrode of the first NMOS pipe NM-clamp and the drain electrode of the third NMOS pipe NM 3; the source electrode of the fourth PMOS transistor PM4 is connected with the positive electrode of the power supply, the drain electrode of the fourth PMOS transistor PM4 is connected with the gate electrode and the drain electrode of the second NMOS transistor NM2 and the gate electrode of the third NMOS transistor NM3 respectively, and the gate electrode of the fourth PMOS transistor PM4 is connected with the bandgap reference circuit module 104; the drain electrode of the first NMOS tube NM-clamp is respectively connected with the grid electrode thereof, the drain electrode of the third PMOS tube PMaN and the drain electrode of the third NMOS tube NM3, the grid electrode of the first NMOS tube NM-clamp is respectively connected with the drain electrode thereof, the drain electrode of the third PMOS tube PMaN and the drain electrode of the third NMOS tube NM3, and the source electrode of the first NMOS tube NM-clamp is connected with the band gap reference circuit module 104; the drain electrode of the second NMOS transistor NM2 is connected to the gate electrode thereof, the gate electrode of the third NMOS transistor NM3 and the drain electrode of the fourth PMOS transistor PM4, the gate electrode of the second NMOS transistor NM2 is connected to the drain electrode thereof, the gate electrode of the third NMOS transistor NM3 and the drain electrode of the fourth PMOS transistor PM4, and the source electrode of the second NMOS transistor NM2 is connected to the drain electrode of the fourth NMOS transistor NM 4; the drain of the third NMOS transistor NM3 is connected to the drain and the gate of the first NMOS transistor NM-clamp and the drain of the third PMOS transistor PMaN, respectively, the gate of the third NMOS transistor NM3 is connected to the gate and the drain of the second NMOS transistor NM2 and the drain of the fourth PMOS transistor PM4, respectively, and the source of the third NMOS transistor NM3 is connected to the drain of the fifth NMOS transistor NM 5.

The gate of the fourth NMOS transistor NM4 is connected to the gate of the fifth NMOS transistor NM5 and the bandgap reference circuit module 104, the drain of the fourth NMOS transistor NM4 is connected to the source of the second NMOS transistor NM2, and the source of the fourth NMOS transistor NM4 is connected to the negative electrode AGND of the power supply; the gate of the fifth NMOS transistor NM5 is connected to the gate of the fourth NMOS transistor NM4 and the bandgap reference circuit module 104, the drain of the fifth NMOS transistor NM5 is connected to the source of the third NMOS transistor NM3, and the source of the fifth NMOS transistor NM5 is connected to the negative electrode AGND of the power supply.

The bandgap reference circuit module 104 includes: a fifth PMOS tube PM3, a sixth PMOS tube PM2, a seventh PMOS tube PM1, a first resistor R1, a second-section resistor, a third resistor R3, a first triode Q1, a second triode Q2, an operational amplifier U1 and a sixth NMOS tube NM 1; the source electrode of a fifth PMOS tube PM3 is connected with the positive electrode AVDD of the power supply, the grid electrode of the fifth PMOS tube PM3 is respectively connected with the grid electrode of a fourth PMOS tube PM4, the grid electrode of a sixth PMOS tube PM2 and the grid electrode of a seventh PMOS tube PM1, and the drain electrode of the fifth PMOS tube PM3 is connected with one end of a fourth resistor R4, the grid electrode of a fifth NMOS tube NM5 and the grid electrode of a fourth NMOS tube NM 4; the source electrode of the sixth PMOS tube PM2 is connected with the positive electrode AVDD of the power supply, the grid electrode of the sixth PMOS tube PM2 is respectively connected with the grid electrode of the fourth PMOS tube PM4, the grid electrode of the fifth PMOS tube PM3 and the grid electrode of the seventh PMOS tube PM1, and the drain electrode of the sixth PMOS tube PM2 is connected with the first end of the operational amplifier U1; the source electrode of the seventh PMOS transistor PM1 is connected to the positive electrode AVDD of the power supply, the gate electrode of the seventh PMOS transistor PM1 is connected to the gate electrode of the fourth PMOS transistor PM4, the gate electrode of the fifth PMOS transistor PM3 and the gate electrode of the sixth PMOS transistor PM2, respectively, and the drain electrode of the seventh PMOS transistor PM1 is connected to the drain electrode of the sixth NMOS transistor NM 1.

The other end of the fourth resistor R4 is connected to one end of the second resistor R2 and one end of the third resistor R3, the other end of the second resistor R2 is connected to one end of the first resistor R1 and the negative phase input end of the operational amplifier U1, the other end of the first resistor R1 is connected to the emitter of the first triode Q1, and the other end of the third resistor R3 is connected to the positive phase input end of the operational amplifier U1 and the emitter of the second triode Q2; an emitting electrode of the first triode Q1 is connected with the other end of the first resistor R1, and a base electrode and a collector electrode of the first triode Q1 are both connected with the negative electrode AGND of the power supply; an emitting electrode of the second triode Q2 is connected with the other end of the third resistor R3, and a base electrode and a collecting electrode of the second triode Q2 are both connected with the negative electrode AGND of the power supply.

The positive-negative phase input end of the operational amplifier U1 is connected with the other end of the second resistor R2 and one end of the first resistor R1 respectively, the positive-direction input end of the operational amplifier U1 is connected with the other end of the third resistor R3 and the emitter of the second amplifier respectively, the first end of the operational amplifier U1 is connected with the drain of the sixth PMOS tube PM2, and the output end of the operational amplifier U1 is connected with the gate of the sixth NMOS tube NM1 and the source of the first NMOS tube NM-clamp respectively; the gate of the sixth NMOS transistor NM1 is connected to the output terminal of the operational amplifier U1 and the source of the first NMOS transistor NM-clamp, the drain of the sixth NMOS transistor NM1 is connected to the drain of the seventh PMOS transistor PM1, and the source of the sixth NMOS transistor NM1 is connected to the negative electrode AGND of the power supply.

The voltage at the connection of the drain of the fifth PMOS transistor PM3, one end of the fourth resistor R4, the gate of the fifth NMOS transistor NM5 and the gate of the fourth NMOS transistor NM4 is the output voltage VREF of the operational amplifier U1.

Having described embodiments of the present invention, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A bandgap reference start-up circuit, comprising: the band-gap reference circuit module and the starting circuit module;

the band-gap reference circuit module is connected with a power supply;

the starting circuit module is respectively connected with the band-gap reference circuit module and the power supply, and the starting circuit module enables the band-gap reference circuit module to recover normal work;

the starting circuit module comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube;

the first PMOS tube is respectively connected with the power supply, a second PMOS tube and a third PMOS tube, the second PMOS tube is respectively connected with the first PMOS tube and the third PMOS tube, and the third PMOS tube is respectively connected with the second PMOS tube, the first NMOS tube, the second NMOS tube and the third NMOS tube;

the band-gap reference circuit comprises a band-gap reference circuit module, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a band-gap reference circuit module, wherein the first NMOS tube is connected with the band-gap reference circuit module, the third PMOS tube is connected with the fourth NMOS tube, the third NMOS tube and the fourth NMOS tube, the third NMOS tube is connected with the third PMOS tube, the first NMOS tube, the second NMOS tube and the fifth NMOS tube, the fourth NMOS tube is connected with the second NMOS tube, the fifth NMOS tube and the band-gap reference circuit module, and the fifth NMOS tube is connected with the third NMOS tube, the fourth NMOS tube and the band-gap reference circuit module.

2. The bandgap reference starting circuit according to claim 1, wherein a source of the first PMOS transistor is connected to the positive power supply, a drain of the first PMOS transistor is connected to a source of the second PMOS transistor, and a gate of the first PMOS transistor is connected to a gate of the second PMOS transistor and a gate of the third PMOS transistor, respectively;

the source electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the second PMOS tube is respectively connected with the grid electrode of the first PMOS tube and the grid electrode of the third PMOS tube, and the drain electrode of the second PMOS tube is connected with the source electrode of the third PMOS tube;

the source electrode of the third PMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the third PMOS tube is respectively connected with the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube, and the drain electrode of the third PMOS tube is respectively connected with the drain electrode of the first NMOS tube, the grid electrode of the first NMOS tube and the drain electrode of the third NMOS tube;

the source electrode of the fourth PMOS tube is connected with the positive electrode of the power supply, the drain electrode of the fourth PMOS tube is respectively connected with the grid electrode and the drain electrode of the second NMOS tube and the grid electrode of the third NMOS tube, and the grid electrode of the fourth PMOS tube is connected with the band-gap reference circuit module;

the drain electrode of the first NMOS tube is respectively connected with the grid electrode of the first NMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube, the grid electrode of the first NMOS tube is respectively connected with the drain electrode of the first NMOS tube, the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube, and the source electrode of the first NMOS tube is connected with the band-gap reference circuit module;

the drain electrode of the second NMOS tube is respectively connected with the grid electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the fourth PMOS tube, the grid electrode of the second NMOS tube is respectively connected with the drain electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the fourth PMOS tube, and the source electrode of the second NMOS tube is connected with the drain electrode of the fourth NMOS tube;

the drain electrode of the third NMOS tube is respectively connected with the drain electrode and the grid electrode of the first NMOS tube and the drain electrode of the third PMOS tube, the grid electrode of the third NMOS tube is respectively connected with the grid electrode and the drain electrode of the second NMOS tube and the drain electrode of the fourth PMOS tube, and the source electrode of the third NMOS tube is connected with the drain electrode of the fifth NMOS tube.

3. The bandgap reference starting circuit according to claim 2, wherein a gate of the fourth NMOS transistor is connected to the gate of the fifth NMOS transistor and the bandgap reference circuit module, respectively, a drain of the fourth NMOS transistor is connected to a source of the second NMOS transistor, and a source of the fourth NMOS transistor is connected to a negative electrode of the power supply;

the grid electrode of the fifth NMOS tube is respectively connected with the grid electrode of the fourth NMOS tube and the band-gap reference circuit module, the drain electrode of the fifth NMOS tube is connected with the source electrode of the third NMOS tube, and the source electrode of the fifth NMOS tube is connected with the negative electrode of the power supply.

4. The bandgap reference start-up circuit of claim 3, wherein the bandgap reference circuit module comprises: the transistor comprises a fifth PMOS (P-channel metal oxide semiconductor) tube, a sixth PMOS tube, a seventh PMOS tube, a first resistor, a second-section resistor, a third resistor, a first triode, a second triode, an operational amplifier and a sixth NMOS (N-channel metal oxide semiconductor) tube;

a source electrode of the fifth PMOS tube is connected with the positive electrode of the power supply, a grid electrode of the fifth PMOS tube is respectively connected with a grid electrode of the fourth PMOS tube, a grid electrode of the sixth PMOS tube and a grid electrode of the seventh PMOS tube, and a drain electrode of the fifth PMOS tube is connected with one end of the fourth resistor, the grid electrode of the fifth NMOS tube and the grid electrode of the fourth NMOS tube;

a source electrode of the sixth PMOS tube is connected with the positive electrode of the power supply, a grid electrode of the sixth PMOS tube is respectively connected with a grid electrode of the fourth PMOS tube, a grid electrode of the fifth PMOS tube and a grid electrode of the seventh PMOS tube, and a drain electrode of the sixth PMOS tube is connected with the first end of the operational amplifier;

the source electrode of the seventh PMOS tube is connected with the positive electrode of the power supply, the grid electrode of the seventh PMOS tube is respectively connected with the grid electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the sixth NMOS tube.

5. The bandgap reference start-up circuit according to claim 4, wherein the other end of the fourth resistor is connected to one end of the second resistor and one end of a third resistor, respectively, the other end of the second resistor is connected to one end of the first resistor and the negative phase input terminal of the operational amplifier, the other end of the first resistor is connected to the emitter of the first triode, and the other end of the third resistor is connected to the positive phase input terminal of the operational amplifier and the emitter of the second triode, respectively;

an emitting electrode of the first triode is connected with the other end of the first resistor, and a base electrode and a collector electrode of the first triode are both connected with the negative electrode of the power supply;

and the emitter of the second triode is connected with the other end of the third resistor, and the base and the collector of the second triode are both connected with the negative electrode of the power supply.

6. The bandgap reference start-up circuit according to claim 5, wherein a negative phase input terminal of the operational amplifier is connected to another terminal of the second resistor and one terminal of the first resistor, a positive phase input terminal of the operational amplifier is connected to another terminal of the third resistor and an emitter of the second amplifier, a first terminal of the operational amplifier is connected to a drain of the sixth PMOS transistor, and an output terminal of the operational amplifier is connected to a gate of the sixth NMOS transistor and a source of the first NMOS transistor;

the grid electrode of the sixth NMOS tube is respectively connected with the output end of the operational amplifier and the source electrode of the first NMOS tube, the drain electrode of the sixth NMOS tube is connected with the drain electrode of the seventh PMOS tube, and the source electrode of the sixth NMOS tube is connected with the negative electrode of the power supply.

7. The bandgap reference starting circuit of claim 6, wherein a voltage at a connection point of a drain of the fifth PMOS transistor, one end of the fourth resistor, a gate of the fifth NMOS transistor and a gate of the fourth NMOS transistor is an output voltage of the operational amplifier.