CN114501775A - Device and method for adjusting characteristic impedance of IO line on circuit board - Google Patents
Device and method for adjusting characteristic impedance of IO line on circuit board Download PDFInfo
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0002—Apparatus or processes for manufacturing printed circuits for manufacturing artworks for printed circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to an IO line characteristic impedance adjusting device and method on a circuit board. The device comprises: the test circuit board is provided with a plurality of routing groups with different lengths, each routing group comprises a plurality of routing lines with the same length, and the plurality of routing lines in the same routing group are respectively cut off at different positions; the compensation resistor corresponding to each wire is connected in series at the cut-off position; the transmitter is provided with an output pin corresponding to each wire, the receiver is provided with an input pin corresponding to each wire, the output pin and the input pin are respectively connected with two ends of the corresponding wire, and the transmitter is configured to transmit signals to the receiver; an oscilloscope configured to display a signal waveform generated at an input pin; and when the signal waveform of a certain output pin displayed by the oscilloscope has overshoot, adjusting the resistance value of the compensation resistor on the wiring until the overshoot is eliminated. The scheme of the invention is beneficial to improving the design efficiency of the circuit board.
Description
Technical Field
The invention relates to the field of circuit board design, in particular to a device and a method for adjusting characteristic impedance of an IO line on a circuit board.
Background
Characteristic impedance is also called characteristic impedance, and belongs to the concept of long line transmission. In a high frequency range, an instant current is generated between a signal line and a reference plane (a power supply or a ground plane) due to the establishment of an electric field at the position where a signal arrives along a signal transmission line, if the transmission line is isotropic, a current I always exists as long as the signal is transmitted, and if the output level of the signal is V, the transmission line is equivalent to a resistor in the signal transmission process, and the equivalent resistor is called as the characteristic impedance Z (with the magnitude of V/I) of the transmission line. During the transmission of a signal, if the characteristic impedance of a transmission path changes, the signal is reflected at a node where the impedance is discontinuous. The line characteristic impedance is determined by several factors: line width, copper thickness, dielectric layer thickness. Once the PCB is designed, the impedance of each line is theoretically determined because several of the above elements have been determined. However, due to the influence of the manufacturing process, such as the variation of the line width, the variation of the copper thickness, and the control of the dielectric layer thickness, the characteristic impedance is changed.
In the process of signal transmission, signals are often not standard rectangular wave signals, especially in high-speed signals, it is very important to ensure the integrity of the signals, one of the most important factors influencing the integrity of the signals is impedance mismatching, which is usually shown on a transmission line, and the impedance mismatching directly causes the reflection of the signals, and the superposition of the reflected signals and the original signals can cause the signal integrity problems of overshoot, return channel, step and the like. After the signal level jumps, the first peak voltage or the first valley voltage exceeds the set standard voltage and is mainly represented as a top pulse. When the overshoot amplitude is large or the duration is long, the failure of circuit components may be caused, the overshoot causes ringing, the generated voltage fluctuation may cross the voltage threshold of the logic level many times, and the erroneous judgment of the receiving end may be caused. To solve this problem, the following two adjustments are often required to be made to the designed motherboard: on one hand, the magnitude of the driving current of the signal sending driving end is adjusted; on the other hand, when the matching resistor is placed at a signal sending end, theoretically, when the resistance value of the resistor is equal to the characteristic impedance of the transmission line, the reflection is minimum, but the actual design condition of the mainboard is very complex, the matching resistor is often placed at the signal sending end at an insufficient spatial position, the matching resistor can only be connected at other positions of the signal line in series, and the lengths of all signal lines are different, so that the resistance value of the matching resistor needs to be adjusted according to the actual condition, and complicated design and verification work is increased.
Disclosure of Invention
In view of the above, it is desirable to provide an apparatus and a method for adjusting IO line characteristic impedance on a circuit board, and a method for designing a circuit board.
According to a first aspect of the present invention, there is provided an IO line characteristic impedance adjusting apparatus on a circuit board, the apparatus including:
the test circuit board is provided with a plurality of wiring groups with different lengths, each wiring group comprises a plurality of wirings with the same length, and the plurality of wirings belonging to the same wiring group are respectively cut off at different positions in the wiring length direction and leave a first cut-off end and a second cut-off end;
the compensation resistor corresponds to each wire, and two ends of the compensation resistor are respectively connected with the first cut-off end and the second cut-off end;
the transmitter is provided with an output pin corresponding to each wire, the receiver is provided with an input pin corresponding to each wire, the output pin and the input pin are respectively connected with two ends of the corresponding wire, and the transmitter is configured to transmit signals to the receiver;
the oscilloscope is connected with the input pin of the receiver and is configured to display a signal waveform generated at the input pin; and
and responding to overshoot of the signal waveform of a certain output pin shown by the oscilloscope, and adjusting the resistance value of the compensation resistor on the wire corresponding to the certain output pin until the overshoot is eliminated.
In some embodiments, the transmitter and the receiver are both complex programmable logic devices.
In some embodiments, among the plurality of traces belonging to the same trace group, the number of traces on the side of the truncation position close to the transmitter is greater than the number of traces on the side of the truncation position closer to the receiver.
In some embodiments, each of the routing line groups includes nine routes, and the cutting positions of the nine routes are respectively located at one tenth of the total length of the routes, two tenths of the total length of the routes, three tenths of the total length of the routes, four tenths of the total length of the routes, five tenths of the total length of the routes, six tenths of the total length of the routes, seven tenths of the total length of the routes, eight tenths of the total length of the routes, and nine tenths of the total length of the routes.
In some embodiments, the magnitude of the drive current for the output pin comprises at least one of 4 millimeters, 8 milliamps, and 16 milliamps.
In some embodiments, the number of sets of traces is thirteen, and the corresponding trace lengths of the thirteen sets of traces are 2 inches, 2.5 inches, 3 inches, 4 inches, 6 inches, 8 inches, 10 inches, 15 inches, 20 inches, 25 inches, 30 inches, 35 inches, 40 inches, respectively.
In some embodiments, the compensation resistance is a patch resistance.
According to a second aspect of the present invention, there is provided an IO line characteristic impedance adjusting method on a circuit board, where the method employs the above IO line characteristic impedance adjusting apparatus on a circuit board, and the IO line characteristic impedance adjusting method includes:
configuring a drive current of the output pin of the transmitter;
configuring all output pins of the transmitter to continuously output level signals with high-low interval conversion;
judging whether the level signal connected with the input pin has overshoot or not according to the waveform signal displayed by the oscilloscope;
responding to the overshoot of the level signal of the input pin, adjusting the resistance value of the compensation resistor and returning to execute the step of judging whether the overshoot of the level signal of the input pin exists through the waveform signal displayed by the oscilloscope;
and responding to the fact that the level signal of the input pin does not have overshoot, and associating the current resistance value of the compensation resistor with the current driving current, the wiring group to which the wiring connected with the compensation resistor belongs and the truncation position of the wiring connected with the compensation resistor to generate a compensation resistor configuration table.
According to a third aspect of the present invention, there is also provided a circuit board design method including:
acquiring target driving current, target wiring length and target truncation position of a wiring to be designed;
reading the compensation resistance configuration table generated by adopting the IO line characteristic impedance adjusting method on the circuit board;
and inquiring a target resistance value for the wiring to be designed from the compensation resistor configuration table based on the target driving current, the target wiring length and the target truncation position.
In some embodiments, the target driving current, the target trace length, and the query priority of the target truncation position are sequentially decreased.
Above-mentioned IO line characteristic impedance adjusting device on circuit board, set up a plurality of lines group on the test circuit board, and every line group is walked including many lines, many lines of every line group are walked to every and are cut in the position of difference, the department of cutting is established ties through compensating resistor, will send the ware and the both ends that the receiver is connected to every line, send the ware to the receiver and send the signal, and observe the signal waveform of receiver one side through oscilloscope, then adjust compensating resistor's resistance when the signal waveform exists and overshoot, through survey test panel simulation multiple line situation, realize that the simulation eliminates the overshoot phenomenon on the different grade type IO line, the data support has been provided for circuit board design, a large amount of manpowers have been saved, material resources and time, help improving circuit board design efficiency.
In addition, the technical effects can be achieved by the method for adjusting the characteristic impedance of the IO line on the circuit board and the method for designing the circuit board, which are provided by the invention, and are not described herein again.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an IO line characteristic impedance adjusting apparatus 100 on a circuit board according to an embodiment of the present invention;
fig. 2 is a schematic flowchart of a method 200 for adjusting IO line characteristic impedance on a circuit board according to another embodiment of the present invention;
fig. 3 is a circuit board design method 300 according to another embodiment of the invention.
[ description of reference ]
101: a wiring group; 102: routing; 103: a compensation resistor; 104: a transmitter; 105: a receiver; 106: an oscilloscope;
a: a first wiring group; b: a second wiring group; c: a third wiring group; d: and a fourth wire group.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In one embodiment, referring to fig. 1, the present invention provides an IO line characteristic impedance adjusting apparatus 100 on a circuit board, specifically including:
a test circuit board (not shown in fig. 1), on which a plurality of routing groups 101 (areas indicated by dashed line boxes in fig. 1) with different lengths are opened, each routing group 101 includes a plurality of routing lines 102 with the same length, and the plurality of routing lines 101 belonging to the same routing group 101 are respectively cut at different positions in the routing length direction and leave a first cut-off end and a second cut-off end;
the compensation resistor 103 corresponds to each trace 102, and two ends of the compensation resistor 103 are respectively connected with the first cut-off end and the second cut-off end; preferably, the compensation resistor 103 is a patch resistor.
A transmitter 104 and a receiver 105, wherein the transmitter 104 has an output pin corresponding to each trace, the receiver 104 has an input pin corresponding to each trace, the output pin and the input pin are respectively connected with two ends of the corresponding trace, and the transmitter 104 is configured to transmit a signal to the receiver 105;
an oscilloscope 106 connected to the input pin of the receiver and configured to display a signal waveform generated at the input pin; and
and responding to overshoot of the signal waveform of a certain output pin shown by the oscilloscope, and adjusting the resistance value of the compensation resistor on the wire corresponding to the certain output pin until the overshoot is eliminated.
Above-mentioned IO line characteristic impedance adjusting device on circuit board, set up a plurality of wiring groups on the test circuit board, and every wiring group includes many lines, many lines of every wiring group are cut in the position of difference, the department of cutting is established ties through the compensating resistor, will send the ware and the both ends that the receiver is connected to every line, send the ware to the receiver send signal, and observe the signal waveform of receiver one side through oscilloscope, then adjust compensating resistor's resistance when signal waveform exists the overshoot, through testing the multiple line situation of walking of test panel simulation, realize that the simulation eliminates the overshoot phenomenon on the different grade type IO line, the design of circuit board has been provided data support, a large amount of manpowers has been saved, material resources and time, help improving circuit board design efficiency.
In some embodiments, the transmitter 104 and the receiver 105 are both complex programmable logic devices.
In some embodiments, the number of traces 102 belonging to the same trace group 101 on the side of the truncation position close to the transmitter is greater than the number of traces on the side of the truncation position closer to the receiver.
In the embodiment, more cutting positions are designed by one-time measurement of the routing close to the transmitter, so that more choices are provided for selecting proper compensation resistors on one side close to the transmitter for subsequent circuit board design, and the optimal resistance value can be matched more accurately.
In some embodiments, each of the routing line groups 101 includes nine tracks 102, and the cutting positions of the nine tracks are respectively located at one tenth of the total track length, two tenths of the total track length, three tenths of the total track length, four tenths of the total track length, five tenths of the total track length, six tenths of the total track length, seven tenths of the total track length, eight tenths of the total track length, and nine tenths of the total track length.
In some embodiments, the magnitude of the drive current for the output pin comprises at least one of 4 millimeters, 8 milliamps, and 16 milliamps.
In some embodiments, the number of sets of traces 101 is thirteen, and the corresponding trace lengths of the thirteen sets of traces 101 are 2 inches, 2.5 inches, 3 inches, 4 inches, 6 inches, 8 inches, 10 inches, 15 inches, 20 inches, 25 inches, 30 inches, 35 inches, 40 inches, respectively.
In another embodiment, referring to fig. 2, the present invention further provides a method 200 for adjusting IO line characteristic impedance on a circuit board, the method comprising the following steps:
In another embodiment, referring to fig. 3, the invention further provides a circuit board design method 300, which includes:
In some embodiments, the target driving current, the target trace length, and the query priority of the target truncation position are sequentially decreased.
In some embodiments, to facilitate understanding of the technical solution of the present invention, the following is to simulate the functions of a transmitter and a receiver by using two CPLD chips, where multiple IOs of two CPLD signals are interconnected with each other by 50OHM characteristic impedance traces with different lengths and are compensated in series at different positions of the traces, and the specific implementation is as follows:
(1) the GPIO signals of the CPLD are divided into four groups, each group of signals are wired with different wire lengths, a plurality of wires are started on the test circuit board to be used for simulating the wire lengths of different single-wire IO signals on the server mainboard, the wire lengths are equal in each group, but the positions for placing compensation are different, and the GPIO signals are used for simulating the server mainboard to place series compensation resistors at different positions of the IO signals according to device layout and wiring space. For example, the test circuit board includes a first wire group a, a second wire group B, a third wire group C, and a fourth wire group D, each wire group has ten wires with the same length, taking the wires in the first wire group a as an example, the CPLD serving as a transmitter has a plurality of output pins denoted IOA1-IOAn, the CPLD serving as a receiver has a plurality of input pins denoted INA1-INAn, and two ends of the wires are connected to the input pins and the output pins, respectively.
(2) Writing a CPLD program, setting an output pin of a CPLD as a transmitter to be transmitting, setting an IO of a CPLD2 as a receiver to be receiving, continuously transmitting high and low levels of high and low conversion to the GPIO of the CPLD by the GPIO of the generator, setting GPIO driving capacities of the CPLD of the transmitter to be 4mA,8mA and 16mA respectively, measuring overshoot conditions of signals on the receiving pin of the CPLD of the receiver by using an oscilloscope, replacing a resistor when the overshoot exists, overshoot and debugging the signals to be in a proper specification, recording positions and resistance values of the resistor on a signal wire with a corresponding length, and forming the following three tables corresponding to IO driving strengths of 4mA,8mA and 16 mA.
When the IO driving capability of the transmitter CPLD is 16mA and the compensation resistors are placed at different positions by the wires with different lengths, the resistance values of the compensation resistors needed for eliminating overshoot are shown in table 1:
table 1 resistance meter corresponding to IO drive current of 16ma
When the IO driving capability of the transmitter CPLD is 8mA, and the wires with different lengths place compensation resistors at different positions, the resistance value of the compensation resistor required for eliminating overshoot is shown in table 2:
table 2 resistance meter corresponding to IO driving current of 8ma
When the IO driving capability of the transmitter CPLD is 4mA and the compensation resistors are placed at different positions by the wires with different lengths, the resistance values of the compensation resistors needed for eliminating overshoot are shown in table 3.
Table 3 resistance meter corresponding to IO driving current 4ma
(3) After the test obtains the result of form, when redesigning the mainboard, alright in order to walk the length of line and the position that compensation resistor placed according to the IO, the resistance of direct adjustment compensation resistor.
For example, assume that there are two kinds of traces on a circuit board to be designed, and the specification of the first kind of trace is: 25000mils, a compensation resistor is placed at 7500mils, and the drive current of the wire is 16 milliamps, so that the target resistance value is 160 ohms as queried from table 1; it is not assumed that the second middle trace specification is 24000mils, the compensation resistor is disposed at 7000mils, and the driving current of the trace is 4 mm, since the highest priority of the driving current satisfies the data in table 3, although the third trace does not have 24000mils long, it is 25000mils closest to the trace, and 7000mils is approximately equal to cut off at 0.29, and it is appropriate to determine that the compensation resistor is selected to be 75 ohms by querying.
It should be noted that the length of the routing line and the truncation position in this embodiment are only used for illustration, and in the specific implementation process, a user may set a variety of lines on the circuit board again according to actual design requirements to obtain a richer line compensation resistance table, so as to query a more accurate resistance value when designing the circuit board.
The scheme of the invention at least has the following beneficial effects:
1. through the test result of the test board, the actual situation of the circuit board to be designed is combined, for single line IO, matching resistors with different resistance values are placed according to different line lengths and positions of the matching resistors, the problem of overshoot of most single line signals is solved at one time, and the situation that simulation is inaccurate due to the fact that the actual situations of plates, lamination and the like are complex is avoided;
2. the overshoot of the BOM is modified due to repeated tests caused by signal overshoot, and a large amount of manpower, material resources and time are saved;
3. the reason for the overshoot is basically determined, and the processing mode can be borrowed to other board cards, has better universality and is suitable for various types of circuit boards.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. An IO line characteristic impedance adjusting apparatus on a circuit board, the apparatus comprising:
the test circuit board is provided with a plurality of wiring groups with different lengths, each wiring group comprises a plurality of wirings with the same length, and the plurality of wirings belonging to the same wiring group are respectively cut off at different positions in the wiring length direction and leave a first cut-off end and a second cut-off end;
the compensation resistor corresponds to each wire, and two ends of the compensation resistor are respectively connected with the first cut-off end and the second cut-off end;
the transmitter is provided with an output pin corresponding to each wire, the receiver is provided with an input pin corresponding to each wire, the output pin and the input pin are respectively connected with two ends of the corresponding wire, and the transmitter is configured to transmit signals to the receiver;
the oscilloscope is connected with the input pin of the receiver and is configured to display a signal waveform generated at the input pin; and
and responding to overshoot of the signal waveform of a certain output pin shown by the oscilloscope, and adjusting the resistance value of the compensation resistor on the wire corresponding to the certain output pin until the overshoot is eliminated.
2. The IO line characteristic impedance adjusting apparatus according to claim 1, wherein the transmitter and the receiver are both complex programmable logic devices.
3. The IO line characteristic impedance adjusting apparatus according to claim 1, wherein, among the plurality of traces belonging to the same trace group, a number of traces at a side of the truncation position close to the transmitter is greater than a number of traces at a side of the truncation position closer to the receiver.
4. The apparatus of claim 1, wherein each of the sets of traces includes nine traces, and the cutting positions of the nine traces are respectively located at one tenth of the total trace length, two tenths of the total trace length, three tenths of the total trace length, four tenths of the total trace length, five tenths of the total trace length, six tenths of the total trace length, seven tenths of the total trace length, eight tenths of the total trace length, and nine tenths of the total trace length.
5. The IO line characteristic impedance adjustment apparatus according to claim 1, wherein the driving current of the output pin includes at least one of 4 mm, 8ma and 16 ma.
6. The IO line characteristic impedance adjusting apparatus according to claim 1, wherein the number of the running line groups is thirteen, and the running lengths of the running line groups are 2 inches, 2.5 inches, 3 inches, 4 inches, 6 inches, 8 inches, 10 inches, 15 inches, 20 inches, 25 inches, 30 inches, 35 inches, and 40 inches, respectively.
7. The apparatus of claim 1, wherein the compensation resistor is a chip resistor.
8. An IO line characteristic impedance adjusting method on a circuit board, the method using the IO line characteristic impedance adjusting apparatus on the circuit board according to any one of claims 1 to 7, the IO line characteristic impedance adjusting method comprising:
configuring a drive current of the output pin of the transmitter;
configuring all output pins of the transmitter to continuously output level signals with high-low interval conversion;
judging whether the level signal connected with the input pin has overshoot or not according to the waveform signal displayed by the oscilloscope;
responding to the overshoot of the level signal of the input pin, adjusting the resistance value of the compensation resistor and returning to execute the step of judging whether the overshoot of the level signal of the input pin exists through the waveform signal displayed by the oscilloscope;
and responding to the fact that the level signal of the input pin does not have overshoot, and associating the current resistance value of the compensation resistor with the current driving current, the wiring group to which the wiring connected with the compensation resistor belongs and the truncation position of the wiring connected with the compensation resistor to generate a compensation resistor configuration table.
9. A circuit board design method is characterized by comprising the following steps:
acquiring target driving current, target wiring length and target truncation position of a wiring to be designed;
reading the compensation resistance configuration table generated by adopting the IO line characteristic impedance adjustment method on the circuit board according to claim 8;
and inquiring a target resistance value for the wire to be designed from the compensation resistance configuration table based on the target driving current, the target wire length and the target truncation position.
10. The method of claim 9, wherein the target driving current, the target trace length, and the query priority of the target truncation position are sequentially decreased.
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| CN202111591516.4A CN114501775B (en) | 2021-12-23 | 2021-12-23 | Device and method for regulating characteristic impedance of IO line on circuit board |
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| CN202111591516.4A CN114501775B (en) | 2021-12-23 | 2021-12-23 | Device and method for regulating characteristic impedance of IO line on circuit board |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020118042A1 (en) * | 2001-02-27 | 2002-08-29 | Helt Christopher G. | Circuit and method for compensation if high-frequency signal loss on a transmission line |
| CN102279830A (en) * | 2011-08-01 | 2011-12-14 | 北京航空航天大学 | Multifunctional data acquisition module based on compact peripheral component interconnect (CPCI) bus |
| CN110798172A (en) * | 2019-10-09 | 2020-02-14 | 深圳市紫光同创电子有限公司 | Impedance control circuit and device |
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2021
- 2021-12-23 CN CN202111591516.4A patent/CN114501775B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020118042A1 (en) * | 2001-02-27 | 2002-08-29 | Helt Christopher G. | Circuit and method for compensation if high-frequency signal loss on a transmission line |
| CN102279830A (en) * | 2011-08-01 | 2011-12-14 | 北京航空航天大学 | Multifunctional data acquisition module based on compact peripheral component interconnect (CPCI) bus |
| CN110798172A (en) * | 2019-10-09 | 2020-02-14 | 深圳市紫光同创电子有限公司 | Impedance control circuit and device |
Non-Patent Citations (1)
| Title |
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| 罗尧宇;孙长江;许迪;: "一种适用于多电源电压IO的阻抗匹配结构", 电脑与电信, no. 11 * |
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