CN114499764A - A rate matching and dematching method, device, mobile terminal and storage medium - Google Patents

Abstract

Embodiments of the present disclosure provide a rate matching and de-rate matching method, device, mobile terminal, and storage medium. Wherein, the rate matching method includes: taking sub-blocks as a unit for the codewords that have completed data channel encoding, and adjusting the bit order according to the interleaving order of the first subblock; Interleaving is performed to complete data channel rate matching; wherein, the first sub-block interleaving sequence is determined according to the principle of priority of sub-block importance. Correspondingly, the de-rate matching method includes: after completing the bit de-selection, performing an inverse operation of sub-block interleaving to restore its bit order for subsequent data decoding. In the rate matching scheme provided by the embodiments of the present disclosure, before bit selection and bit interleaving, the bit order is adjusted in units of sub-blocks, and sub-blocks with higher importance are prepended, which can save physical resources and reduce data transmission time. The power consumption of the system is improved, and the transmission performance of the communication system is comprehensively improved.

Description

A rate matching and dematching method, device, mobile terminal and storage medium

technical field

The present invention relates to, but is not limited to, the field of mobile communications, and in particular relates to a rate matching and rate de-matching method, device, mobile terminal and storage medium.

Background technique

In a modern digital communication system, the transmitting end of the digital signal needs to perform rate matching on the channel-coded codewords, so that the length of the code stream matches the actual transmission capability. According to the rate matching scheme of the NR data channel stipulated by the 3GPP protocol, it includes two steps: bit selection and bit interleaving. Combined with the HARQ mechanism and/or the bit interleaving scheme, how to more effectively improve the transmission performance is the direction of continuous exploration in the art.

SUMMARY OF THE INVENTION

The embodiments of the present disclosure provide a rate matching and derate matching method, device, mobile terminal and storage medium. Before performing the bit selection and bit interleaving in the related scheme, the order of bits is adjusted in units of sub-blocks, so that the importance is more important. The high sub-block preposition saves physical resources, reduces the data transmission delay and the power consumption of the system, and comprehensively improves the transmission performance of the communication system.

An embodiment of the present disclosure provides a rate matching method, including:

The codeword that has completed the data channel encoding is taken as a unit, and the bit order is adjusted according to the interleaving order of the first subblock;

According to the codeword adjusted by the bit order, bit selection and bit interleaving are performed to complete data channel rate matching;

Wherein, the first sub-block interleaving sequence is determined according to the sub-block importance priority principle.

An embodiment of the present disclosure also provides a method for rate matching, including:

Perform bit deinterleaving and bit deselecting on the demodulated codeword to obtain the codeword to be deinterleaved;

The to-be-decoded codeword is taken as a unit of sub-block, and the bit order is adjusted according to the first sub-block interleaving order to obtain the to-be-decoded codeword; the to-be-decoded codeword is used for data channel decoding to obtain the decoded codeword;

Wherein, the first sub-block interleaving sequence is determined according to the sub-block importance priority principle.

Embodiments of the present disclosure also provide a rate matching apparatus, including:

The first interleaving module is configured to adjust the bit order according to the first sub-block interleaving sequence by taking the sub-block as the unit of the codeword that has completed the data channel encoding;

The interleaving module is selected, and is set to the codeword adjusted according to the bit order, and performs bit selection and bit interleaving to complete data channel rate matching;

Wherein, the first sub-block interleaving sequence is determined according to the sub-block importance priority principle.

Embodiments of the present disclosure also provide a rate de-matching apparatus, including:

A de-interleaving selection module, configured to perform bit de-interleaving and bit de-selection on the demodulated code word to obtain the code word to be de-interleaved;

The first deinterleaving module is configured to adjust the bit order of the codeword to be deinterleaved in a unit of subblocks according to the interleaving sequence of the first subblock to obtain the codeword to be decoded; the codeword to be decoded is used for data channel decoding to obtain a decoded codeword;

Wherein, the first sub-block interleaving sequence is determined according to the sub-block importance priority principle.

Embodiments of the present disclosure also provide a mobile terminal, including a communication chip configured to perform:

The codeword that has completed the data channel encoding is taken as a unit, and the bit order is adjusted according to the interleaving order of the first subblock;

According to the codeword adjusted by the bit order, bit selection and bit interleaving are performed to complete data channel rate matching;

Wherein, the first sub-block interleaving sequence is determined according to the sub-block importance priority principle.

Embodiments of the present disclosure also provide a mobile terminal, including a communication chip configured to perform:

Perform bit deinterleaving and bit deselecting on the demodulated codeword to obtain the codeword to be deinterleaved;

The to-be-decoded codeword is taken as a unit of sub-block, and the bit order is adjusted according to the first sub-block interleaving order to obtain the to-be-decoded codeword; the to-be-decoded codeword is used for data channel decoding to obtain the decoded codeword;

Wherein, the first sub-block interleaving sequence is determined according to the sub-block importance priority principle.

An embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, implements the rate matching method according to any embodiment of the present disclosure.

An embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, implements the de-rate matching method according to any embodiment of the present disclosure.

Other aspects will become apparent upon reading and understanding of the drawings and detailed description.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can also be obtained according to the structures shown in these drawings without creative efforts.

Fig. 1 is a kind of schematic diagram that can realize data channel rate matching and related modules;

2 is a schematic structural diagram of an NR LDPC encoded codeword;

Fig. 3 is 3GPP to the mapping regulation of bit (b) to modulation symbol (d);

4 is a schematic flow chart of rate matching and de-rate matching proposed in an embodiment of the present disclosure;

5 is a flow chart of a rate matching method in an embodiment of the present disclosure;

6 is a schematic diagram of a sub-block interleaving result in an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a block error rate vs. signal-to-noise ratio simulation result in an embodiment of the present disclosure (MCS=16);

FIG. 8 is a schematic diagram of another block error rate vs. signal-to-noise ratio simulation result in an embodiment of the present disclosure (MCS=20);

FIG. 9 is a schematic diagram of another block error rate vs. signal-to-noise ratio simulation result in an embodiment of the present disclosure (MCS=27);

10 is a flow chart of a method for de-rate matching in an embodiment of the present disclosure;

11 is a schematic structural diagram of a rate matching apparatus according to an embodiment of the present disclosure;

FIG. 12 is a schematic structural diagram of a rate de-matching apparatus according to an embodiment of the present disclosure.

The realization, functional characteristics and advantages of the present invention will be further described with reference to the accompanying drawings in conjunction with the embodiments.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relationship between various components under a certain posture (as shown in the accompanying drawings). The relative positional relationship, the movement situation, etc., if the specific posture changes, the directional indication also changes accordingly.

In addition, descriptions such as "first", "second", etc. in the present invention are only for descriptive purposes, and should not be construed as indicating or implying their relative importance or implicitly indicating the number of indicated technical features. Thus, a feature delimited with "first", "second" may expressly or implicitly include at least one of that feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise expressly and specifically defined.

In the present invention, unless otherwise expressly specified and limited, the terms "connected", "fixed" and the like should be understood in a broad sense, for example, "fixed" may be a fixed connection, a detachable connection, or an integrated; It can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be an internal communication between two elements or an interaction relationship between the two elements, unless otherwise explicitly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

In addition, the technical solutions between the various embodiments of the present invention can be combined with each other, but must be based on the realization by those of ordinary skill in the art. When the combination of technical solutions is contradictory or cannot be achieved, it should be considered that the combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

Before specifically recording the embodiments, the abbreviations of the related terms involved in the present disclosure are explained as follows:

According to the 3GPP protocol (38.212–5.4.2), the rate matching of the NR data channel consists of two steps:

1) Bit selection

Write the bit stream encoded by LDPC into a ring buffer of size N _cb , read the data according to the starting position determined by the redundancy version (rv), until the number of effective bits read reaches a given value E.

2) Bit interleaving

的矩阵，然后按列读出。其中，Q_m表示每个调制符号包含的比特数(例如，对16-QAM Q_m＝4，对256-QAM Q_m＝8)，E/Q_m表示调制符号数(E的计算规则能够保证它是Q_m的整数倍)。Write the bit-selected bitstream row by row with a dimension of

matrix, and then read out column by column. where Q _m represents the number of bits contained in each modulation symbol (for example, Q _m =4 for 16-QAM, Q _m =8 for 256-QAM), and E/Q _m represents the number of modulation symbols (the calculation rule of E can guarantee that It is an integer multiple of _Qm ).

The bit stream obtained after rate matching is processed by code block connection and scrambling, and then mapped to modulation symbols through modulation. Note that code block concatenation and scrambling do not affect the bit order within a single code block. In some achievable solutions, the rate matching process in the NR data channel and its related modules are shown in FIG. 1 .

In the bit-level processing of some achievable data channels, the design of rate matching is closely related to the design of LDPC codes and the HARQ mechanism. After the physical resources allocated to PDSCH and the MCS to be used are determined, the system can calculate the transport block size (TBS), the relevant parameters of the code block (size, base map index and boost value of LDPC coding, etc.), and each The number of transmission bits available for each code block (E). According to the selected base map, the LDPC encoder completely encodes the input information bits to obtain a bit stream corresponding to the lowest coding rate (1/3 for BG 1 and 1/5 for BG 2). The complete codeword of NR LDPC has a specific structure as shown in Figure 2: the first part is the information bit, the second part is the core check bit with a length of 4· _Zc , and the third part corresponds to the extended check with a column degree of 1. bits. Typically, the size of the ring buffer is equal to the length of the complete codeword; that is, all parity bits can be written into the ring buffer.

When the HARQ mechanism is used, the initial transmission starts from the starting position of the codeword for bit selection. If the number of bits available for transmission is less than the size of the ring buffer (E<N _cb ), the actual transmitted codeword is not a complete codeword. Check bits are not transmitted, resulting in a higher effective code rate than the encoded code rate. If the initial transmission and decoding fails, and the sender learns through feedback (NACK) that retransmission is required, the starting position of the new bit selection will be determined according to the reselected redundancy version. Through retransmission, the system can send the parity bits that were not sent in the initial transmission, thereby reducing the effective code rate. When the channel condition is poor and the code block is retransmitted many times, all the sent bits can generally cover the entire ring buffer, and because some bits are repeatedly sent, the effective code rate can be lower than the minimum code rate.

Taking into account factors such as delay, power consumption, and occupied physical resources, the fewer transmissions required for successful decoding, the better. Starting from the design of bit selection, this means that we should try to place the more "important" bits in the codeword before the codeword, so that it is more likely to be sent in the first transmission. It can be seen that the existing LDPC coding and bit selection design of 3GPP conforms to this principle: the information bits are at the front of the codeword, followed by the core check bits participating in multiple check equations, and finally only participating in one check. The extended parity bits of the test equation. On this basis, the design of the bit interleaver also follows this principle: according to the mapping rule shown in Figure 3, the order in which the bits are read from the interleaving matrix (that is, the row order of the interleaving matrix) corresponds to the number of bits in the modulation symbol consisting of High-to-low reliability (note that two bits per symbol in QPSK have the same reliability). That is, the bits written into the interleaving matrix first are given better noise immunity during transmission. For the initial transmission of the code block, the information bits and the core parity bits are written into the interleaving matrix before the extended parity bits, so there is a higher possibility of higher reliability.

The research found that in order to improve the decoding performance as a whole, for a given LDPC coding method and a bit-to-modulation symbol mapping method, the design of bit selection should follow the principle of "importance from high to low". The relevant protocol regulations follow this principle as a whole, but there is still room for optimization in the details. For example, these achievable solutions do not consider the ordering between information bits and between extended parity bits, and cannot make more important bits more likely to appear in the initial transmission and be received with higher reliability . In this scheme, the sub-block interleaving function is added before the bit selection process, and the encoded bit stream is rearranged to a certain extent, so that the more important bits are more likely to appear in the initial transmission and have higher reliability. can be received, thereby improving the decoding performance of the system.

In order to optimize the bit order of the encoded codeword, the solution of the embodiment of the present disclosure proposes to add a sub-block interleaver before the bit selection module of the transmitting end, as shown in FIG. 4 . Correspondingly, when de-rate matching is performed at the receiving end, it is necessary to add a sub-block de-interleaver for inverse operation after de-bit selection.

An embodiment of the present disclosure provides a rate matching method, as shown in FIG. 5 , including:

Step 510, adjusting the bit order according to the interleaving order of the first sub-block in the unit of the codeword of the data channel encoding that has been completed;

Step 520, performing bit selection and bit interleaving to complete data channel rate matching according to the codeword after bit order adjustment;

Wherein, the first sub-block interleaving sequence is determined according to the sub-block importance priority principle.

In some exemplary embodiments, the rate matching method is applied to rate matching of data channels.

The codeword for which the data channel encoding has been completed at least includes: information bits, first check bits and second check bits;

The importance of the sub-block corresponding to the information bit and the importance of the sub-block corresponding to the first check bit are higher than the importance of the sub-block corresponding to the second check bit.

Those skilled in the art can know that the sub-block interleaving refers to rearranging the original sub-block arrangement order in sub-block units, and the sub-block interleaving order is the order used to indicate the sub-block rearrangement in the sub-block interleaving. For example, before interleaving, the encoded codeword includes N sub-blocks, which are arranged from front to back in the order of sub-block numbers 1 to N; after rearrangement (after interleaving), the corresponding sub-block numbers from front to back are: i, x , .., N, n, 1, ... (N sub-blocks in total, i, x, n represent the sub-block number, which is a number greater than 1 and less than N), where the rearranged sub-block number (i, x, .., N, n, 1, ...) is the sub-block interleaving sequence, which can be understood as the sub-block interleaving: the sub-blocks numbered 1-N are rearranged according to the sub-block interleaving sequence to obtain a new codeword.

It should be noted that the importance of the sub-blocks corresponding to different types of bit data indicates the importance of the bit data contained in the sub-blocks for successful decoding. In some exemplary embodiments, in the data channel, the importance of sub-blocks corresponding to information bits (systematic bits) containing service data is greater than or equal to parity bits (parity bits) containing parity data. In some exemplary embodiments, the data channel coding codeword may further include multiple types of check bits, for example: first check bits, second check bits, schemes generated according to these different types of check bits and corresponding The roles in the decoding process can also correspond to the same or different importance levels. In some exemplary embodiments, among the check bits of the same type, the importance levels of different sub-block bit data may also be the same or different. In some exemplary embodiments, the first sub-block interleaving order is determined according to a sub-block importance priority principle. For different coding schemes, the statistical information of the importance of each sub-block (bit) can be obtained through theoretical analysis and/or simulation, and the interleaving order of the first sub-block used in the scheme application process can be determined correspondingly.

In some exemplary embodiments, the codeword whose data channel encoding has been completed is a low density parity check code LDPC codeword, the first check bit is a core check bit, and the second check bit is Extended parity bits.

It should be noted that the solution provided by the embodiments of the present disclosure improves the rate matching solution in the related solution, and adds a sub-block interleaving module (sub-block interleaver) before the bit selection process, so as to optimize the bit order of the data channel coding code words, especially The performance of initial transmission and first retransmission can be improved when using higher order modulation and higher code rate.

In some exemplary embodiments, the LDPC encoded codeword as shown in FIG. 2 includes information bits (systematicbits), core parity bits (kernel parity bits), and degree-1 parity bits (degree-1 paritybits) .

In some exemplary embodiments, among the sub-blocks corresponding to the extended parity check bits, the higher the row weight of the row where each sub-block is located in the LDPC parity check matrix, the higher the importance of the sub-block.

In some exemplary embodiments, in the sub-blocks corresponding to the information bits and the core parity bits, the importance of each sub-block is determined according to the order of the relevant rows of each sub-block and the LDPC parity check matrix.

In some exemplary embodiments, in the sub-blocks corresponding to the information bits and the core parity bits, the importance of each sub-block is determined according to the order of the relevant rows of each sub-block and the LDPC parity check matrix, including:

Determine the row order that each sub-block is related to the LDPC check matrix;

Determine the importance of subblocks earlier in row order than subblocks later in row order.

In some exemplary embodiments, the first sub-block interleaving order is determined according to the sub-block importance priority principle, including:

Sort all the subblocks included in the codewords whose data channel coding has been completed according to the descending order of the importance of the subblocks, and determine that the sorted subblock sequence is the first subblock interleaving sequence.

That is to say, according to the order of importance of the sub-blocks included in the codeword that has completed the data channel encoding, rearrange the sub-blocks to obtain the interleaved codeword. The sub-blocks corresponding to the interleaved codeword are The block sequence is the interleaving sequence of the first sub-blocks. It can be seen that in the interleaved codeword, the importance of the sub-blocks arranged in front is higher than or equal to the importance of the sub-blocks arranged in the back, that is, in the codeword after sub-block interleaving, in the order from front to back, The importance of corresponding sub-blocks is from high to low.

In some exemplary embodiments, the size of the sub-block is the boost value Z _c used in LDPC encoding.

It should be noted that the first sub-block interleaving order is determined according to the principle of priority of sub-block importance, and in step 510 after determination, the bit order of the data channel coding codeword is adjusted according to the determined first sub-block interleaving order.

In some exemplary embodiments, the first sub-block interleaving order determined according to the sub-block importance priority principle satisfies at least one of the following aspects:

Keep information bits and core parity bits ahead of extended parity bits;

For the extended check bits, according to the row weight of the row in the LDPC check matrix, they are arranged in order from high to low;

For information bits and core parity bits, the bits related to the zeroth row of the LDPC parity check matrix are ranked first, and then the bits related to the first, second, and third rows that have not yet participated in the sorting are sorted.

It should be noted that, according to the determined first sub-block interleaving sequence, the bit sequence adjustment of the LDPC coded codeword is performed, which is also called sub-block interleaving. In some exemplary embodiments, the sub-block interleaving can be regarded as a certain adjustment to the order of rows and columns in the LDPC base map, so its addition will not actually increase the complexity of system implementation.

Taking BG1 of LDPC as an example, the codeword after sub-block interleaving is shown in Figure 6. In the codeword after bit order adjustment, the information bits and the core check bits are before the extended check bits; in the sub-blocks corresponding to the information bits and the core check bits, the row order of each sub-block related to the LDPC check matrix is closer. The front, the corresponding adjusted position is higher, that is, the row order of these sub-blocks related to the LDPC check matrix is 0, 1, 2 or 3, respectively, then in the order of row order 0-3, the corresponding sub-blocks are arranged from front to back. Sub-block; in the sub-block corresponding to the extended parity bit, the higher the row weight of each sub-block in the LDPC parity check matrix, the higher the corresponding position after adjustment, that is, in the rearranged extended parity bit, the row The taller ones are in the front, and the lower ones are in the back.

As shown in Figure 7, Figure 8, and Figure 9, the performance simulation results of the initial transmission and the first retransmission when MCS=16, 20, and 27 (according to 38.214-Table 5.1.3.1-2) are given respectively. Note that the performance of the sub-optimal decoding algorithm is greatly affected by the choice of parameters (for example, the performance of the normalized minimum sum algorithm is closely related to the choice of the normalization factor), and the addition of the sub-block interleaver may change the optimal Therefore, in order to ensure the fairness of the comparison simulation, the sum-product algorithm with better performance without parameter adjustment is selected as the LDPC decoding algorithm. Other main simulation conditions include: AWGN channel, the number of simulations for each SNR point is 20000, the redundancy versions of the initial transmission and the first retransmission are 0 and 2 respectively; the decoder adopts hierarchical decoding, and the line weight is from low to low. Layer scheduling is performed in the highest order, and the maximum number of iterations is set to 12. The determined order of sub-block interleaving (Base Figure 1) is as follows: 0, 1, 3, 4, 7, 8, 9, 10, 11, 13, 14, 16, 17, 18, 19, 20, 21, 2 ,5,6,12,15,22,23,28,29,26,31,25,35,34,32,30,27,44,41,40,39,38,37,36,33,64 ,63,61,59,58,56,55,54,53,52,51,50,49,48,46,45,43,42,65,62,60,57,47,24 from the simulation results It can be seen from the comparison that the addition of the sub-block interleaver improves the decoding performance for several different MCSs. In the range of BLER ∈ [10 ^-3 , 10 ^-2 ], the magnitude of improvement is about 0.1-0.2 dB. Some other MCSs, the maximum number of retransmissions, and the maximum number of iterations are also simulated, and different degrees of performance improvement brought by the sub-block interleaver are also observed.

In some exemplary embodiments, the codeword whose data channel encoding has been completed is an LDPC BG1 encoded codeword, and the first sub-block interleaving sequence is:

0, 1, 3, 4, 7, 8, 9, 10, 11, 13, 14, 16, 17, 18, 19, 20, 21, 2, 5, 6, 12, 15, 22, 23,

28,29,26,31,25,35,34,32,30,27,44,41,40,39,38,37,36,33,64,63,61,

59, 58, 56, 55, 54, 53, 52, 51, 50, 49, 48, 46, 45, 43, 42, 65, 62, 57, 47, 24.

It can be seen that, in some exemplary implementations, in step 510, LDPC BG1 is used for the codeword after data channel encoding, and the bit order of the encoded codeword is adjusted according to the above-mentioned first subblock interleaving order in the unit of subblock, and the The adjusted codeword is then subjected to bit selection and bit interleaving to complete data channel rate matching. For codewords using LDPC BG2 for data channel coding, the importance of each sub-block can also be determined through correlation analysis and/or simulation, and the corresponding first sub-block interleaving sequence can be determined for corresponding rate matching and de-rate matching. . More detailed examples are not listed here.

It should be noted that, for a digital signal communication system that uses the HARQ mechanism or realizes the adjustment symbol mapping from high to low reliability through bit interleaving, the rate matching scheme provided by the implementation of the present disclosure can be adopted, so that before the bit selection is performed , sort the bits of the encoded codeword in descending order of importance. For different coding schemes, the statistical information of the importance of each sub-block (bit) is obtained through theoretical analysis and/or simulation, and the corresponding first sub-block interleaving sequence is determined based on this, so as to realize sub-block interleaving before bit selection. The specific first sub-block interleaving order is not limited to the aspects exemplified by the foregoing embodiments of the present disclosure.

An embodiment of the present disclosure also provides a method for de-rate matching, as shown in FIG. 10 , including:

Step 1010, performing bit deinterleaving and bit deselecting on the demodulated codeword to obtain the codeword to be deinterleaved;

Step 1020: The to-be-decoded codeword is taken as a unit of sub-block, and the bit order is adjusted according to the first sub-block interleaving order to obtain the to-be-decoded codeword; the to-be-decoded codeword is used for data channel decoding to obtain a decoded code Character;

Wherein, the first sub-block interleaving sequence is determined according to the sub-block importance priority principle.

In some exemplary embodiments, the derate matching method is applied to a data channel.

It should be noted that the de-rate matching method provided by the embodiment of the present disclosure is a codeword processing method at the receiving end corresponding to the rate matching method provided by the embodiment of the present disclosure, and is an inverse operation of the rate matching method. According to the records of each step of rate matching, those skilled in the art can clearly know the implementation of each step corresponding to de-rate matching, which will not be repeated here.

Wherein, the first sub-block interleaving sequence used in step 1010 is consistent with the first sub-block interleaving sequence determined in the rate matching scheme, and deinterleaving is performed according to the first sub-block interleaving sequence to obtain a codeword whose bit sequence is restored , the recovered codeword can be decoded to obtain corresponding service data according to the relevant channel data decoding scheme. According to the determined first sub-block interleaving sequence, those skilled in the art can clearly know the corresponding implementation steps of sub-block interleaving and sub-block de-interleaving, and specific aspects are not discussed in detail in the embodiments of the present application.

An embodiment of the present disclosure further provides a rate matching apparatus 1100, as shown in FIG. 11, including:

The first interleaving module 1110 is configured to adjust the bit order according to the interleaving order of the first sub-blocks in units of sub-blocks of the codewords that have completed data channel coding;

The selection interleaving module 1120 is configured to perform bit selection and bit interleaving to complete data channel rate matching according to the codeword adjusted according to the bit order;

Wherein, the first sub-block interleaving sequence is determined according to the sub-block importance priority principle.

In some exemplary embodiments, the selection interleaving module 1120 includes: a bit selection unit 1121, configured to perform bit selection according to the codeword adjusted by the bit order; a bit interleaving unit 1122, configured to perform bit selection on the selected codeword. Interleaving to accomplish data channel rate matching.

Embodiments of the present disclosure also provide a mobile terminal, including the rate matching apparatus 1100 as described above.

An embodiment of the present disclosure also provides a rate de-matching apparatus 1200, as shown in FIG. 12, including:

The deinterleaving selection module 1210 is configured to perform bit deinterleaving and bit deselecting on the demodulated codeword to obtain the codeword to be deinterleaved;

The first deinterleaving module 1220 is configured to adjust the bit order of the codeword to be deinterleaved in sub-blocks according to the interleaving order of the first subblock to obtain the codeword to be decoded; the codeword to be decoded is used for data processing. channel decoding to obtain decoded codewords;

Wherein, the first sub-block interleaving sequence is determined according to the sub-block importance priority principle.

In some exemplary embodiments, the deinterleaving selection module 1210 includes: a debit interleaving unit 1211 configured to perform bit deinterleaving on the demodulated codeword; a debit selection unit 1212 configured to perform bit deinterleaving on the deinterleaved codeword The word is bit-deselected to obtain the codeword to be deinterleaved.

It can be understood that the codeword to be deinterleaved here corresponds to the output codeword of the first interleaving module 1110 in the rate matching apparatus 1100 .

An embodiment of the present disclosure further provides a mobile terminal, including the above-mentioned de-rate matching apparatus 1200 .

Embodiments of the present disclosure also provide a mobile terminal, including a communication chip configured to perform:

The codeword that has completed the data channel encoding is taken as a unit, and the bit order is adjusted according to the interleaving order of the first subblock;

According to the codeword adjusted by the bit order, bit selection and bit interleaving are performed to complete data channel rate matching;

Wherein, the first sub-block interleaving sequence is determined according to the sub-block importance priority principle.

Embodiments of the present disclosure also provide a mobile terminal, including a communication chip configured to perform:

Perform bit deinterleaving and bit deselecting on the demodulated codeword to obtain the codeword to be deinterleaved;

The to-be-decoded codeword is taken as a unit of sub-block, and the bit order is adjusted according to the first sub-block interleaving order to obtain the to-be-decoded codeword; the to-be-decoded codeword is used for data channel decoding to obtain the decoded codeword;

Wherein, the first sub-block interleaving sequence is determined according to the sub-block importance priority principle.

An embodiment of the present disclosure further provides a storage medium, where a computer program is stored in the storage medium, wherein the computer program is configured to execute the rate matching method described in any of the foregoing embodiments when running.

An embodiment of the present disclosure further provides a storage medium, where a computer program is stored in the storage medium, wherein the computer program is configured to execute the de-rate matching method described in any one of the foregoing embodiments when the computer program is run.

In the rate matching method provided by the embodiments of the present disclosure, a sub-block interleaving step is added before the bit selection, so that the sub-blocks (bits) with higher importance are prepended, and then bit selection and bit interleaving are performed, so that the importance is higher The sub-blocks (bits) can be initially transmitted or retransmitted for the first time, which saves physical resources, reduces information transmission delay and power consumption of the communication system. Especially in the case of high-order modulation and high code rate, the improvement effect on the initial transmission and the first retransmission is more obvious.

Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, functional modules/units in the systems, and devices can be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be composed of several physical components Components execute cooperatively. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those of ordinary skill in the art, the term computer storage media includes both volatile and nonvolatile implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules or other data flexible, removable and non-removable media. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, magnetic tape, magnetic disk storage or other magnetic storage devices, or may Any other medium used to store desired information and which can be accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and can include any information delivery media, as is well known to those of ordinary skill in the art .

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Under the conception of the present invention, the equivalent structural transformations made by the contents of the description and accompanying drawings of the present invention, or directly/indirectly applied in Other related technical fields are included within the scope of patent protection of the present invention.

Claims (12)

1. A method of rate matching, comprising:

adjusting the bit sequence of the code word which finishes the data channel coding according to the interleaving sequence of the first sub-block by taking the sub-block as a unit;

according to the code word after the bit sequence adjustment, carrying out bit selection and bit interleaving to complete the rate matching of the data channel;

and the interleaving order of the first sub-blocks is determined according to a sub-block importance priority principle.

2. The method of claim 1,

the code word for completing data channel coding at least comprises: information bits, first parity bits, and second parity bits;

wherein the importance of the sub-block corresponding to the information bits and the importance of the sub-block corresponding to the first parity bits are higher than the importance of the sub-block corresponding to the second parity bits.

3. The method of claim 2,

the code word of which the data channel coding is finished is a low-density parity check code (LDPC) coding code word, and the second check bit is an extension check bit;

in the sub-blocks corresponding to the extended check bits, the higher the row weight of the row of each sub-block in the LDPC check matrix is, the higher the importance of the sub-block is.

4. The method of claim 2,

the code word which completes channel coding is a low density parity check code (LDPC) coding code word, and the first check bit is a core check bit;

and in the subblocks corresponding to the information bit and the core check bit, the importance of each subblock is determined according to the row sequence of each subblock relative to the LDPC check matrix.

5. The method of claim 4,

the importance of each sub-block is determined according to the row sequence of each sub-block and the LDPC check matrix, and the method comprises the following steps:

respectively determining the row sequence of each sub-block relative to the LDPC check matrix;

it is determined that the importance of the row-sequentially first sub-block is higher than the importance of the row-sequentially next sub-block.

6. The method of any one of claims 1 to 5,

the interleaving order of the first sub-block is determined according to a sub-block importance priority principle, and comprises the following steps:

and sequencing all the sub-blocks included by the code word which completes the data channel coding according to the sequence of the importance of the sub-blocks from high to low, and determining the sequence of the sequenced sub-blocks as the interleaving sequence of the first sub-blocks.

7. A method for rate de-matching, comprising:

performing bit de-interleaving and bit de-selection on the demodulated code word to obtain a code word to be de-interleaved;

adjusting the bit sequence of the code word to be de-interleaved according to the interleaving sequence of the first sub-block by taking the sub-block as a unit to obtain a code word to be decoded; the code word to be decoded is used for carrying out data channel decoding to obtain a decoded code word;

and the interleaving order of the first sub-blocks is determined according to a sub-block importance priority principle.

8. A rate matching apparatus, comprising:

the first interleaving module is used for adjusting the bit sequence of the code words subjected to the data channel coding according to the interleaving sequence of the first sub-blocks by taking the sub-blocks as units;

the selective interleaving module is set to perform bit selection and bit interleaving according to the code words after the bit sequence adjustment so as to complete the rate matching of the data channel;

and the interleaving order of the first sub-blocks is determined according to a sub-block importance priority principle.

9. A de-rate matching apparatus, comprising:

the de-interleaving selection module is used for performing bit de-interleaving and bit de-selection on the demodulated code word to obtain a code word to be de-interleaved;

the first de-interleaving module is used for adjusting the bit sequence of the code word to be de-interleaved by taking a sub-block as a unit according to the interleaving sequence of the first sub-block to obtain the code word to be decoded; the code word to be decoded is used for carrying out data channel decoding to obtain a decoded code word;

and the interleaving order of the first sub-blocks is determined according to a sub-block importance priority principle.

10. A mobile terminal comprising a communication chip configured to perform:

adjusting the bit sequence of the code word which finishes the data channel coding according to the interleaving sequence of the first sub-block by taking the sub-block as a unit;

according to the code word after the bit sequence adjustment, carrying out bit selection and bit interleaving to complete the rate matching of the data channel;

and the interleaving order of the first sub-blocks is determined according to a sub-block importance priority principle.

11. A mobile terminal comprising a communication chip configured to perform:

performing bit de-interleaving and bit de-selection on the demodulated code word to obtain a code word to be de-interleaved;

adjusting the bit sequence of the code word to be de-interleaved according to the interleaving sequence of the first sub-block by taking the sub-block as a unit to obtain a code word to be decoded; the code word to be decoded is used for carrying out data channel decoding to obtain a decoded code word;

and the interleaving order of the first sub-blocks is determined according to a sub-block importance priority principle.

12. A computer-readable storage medium, on which a computer program is stored, which program, when being executed by a processor, carries out the rate matching method according to any one of claims 1-6; alternatively, the program when executed by a processor implements the de-rate matching method of claim 7.

Images