CN114499764A

CN114499764A - Rate matching and de-matching method and device, mobile terminal and storage medium

Info

Publication number: CN114499764A
Application number: CN202210239270.2A
Authority: CN
Inventors: 柏青
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2022-03-11
Filing date: 2022-03-11
Publication date: 2022-05-13
Anticipated expiration: 2042-03-11
Also published as: CN114499764B

Abstract

The embodiment of the disclosure provides a rate matching method, a rate de-matching device, a mobile terminal and a storage medium. The rate matching method comprises the following steps: adjusting the bit sequence of the code word which finishes the data channel coding according to the interleaving sequence of the first sub-block by taking the sub-block as a unit; according to the code word after the bit sequence adjustment, carrying out bit selection and bit interleaving to complete the rate matching of the data channel; and the interleaving sequence of the first sub-block is determined according to the priority principle of the importance of the sub-blocks. Accordingly, the de-rate matching method comprises the following steps: after bit deselection is complete, the inverse of sub-block interleaving is performed to restore its bit order for subsequent data decoding. According to the rate matching scheme provided by the embodiment of the disclosure, before bit selection and bit interleaving, bit sequence adjustment is performed by taking the sub-blocks as a unit, and the sub-blocks with higher importance are preposed, so that physical resources can be saved, transmission delay of data and power consumption of a system can be reduced, and transmission performance of a communication system can be comprehensively improved.

Description

Rate matching and de-matching method and device, mobile terminal and storage medium

Technical Field

The present invention relates to, but not limited to, the field of mobile communications, and in particular, to a method and an apparatus for rate matching and rate de-matching, a mobile terminal, and a storage medium.

Background

In a modern digital communication system, a sending end of a digital signal needs to perform rate matching on code words subjected to channel coding so as to match the code stream length with the actual transmission capacity. A rate matching scheme for NR data channels according to the 3GPP protocol, comprising: how to more effectively improve the transmission performance by combining the HARQ mechanism and/or the bit interleaving scheme is a direction continuously explored in the field.

Disclosure of Invention

The embodiment of the disclosure provides a rate matching method, a rate de-matching device, a mobile terminal and a storage medium, wherein before bit selection and bit interleaving in a related scheme are executed, bit sequence adjustment is performed by taking sub-blocks as units, the sub-blocks with higher importance are preposed, physical resources are saved, transmission delay of data and power consumption of a system are reduced, and transmission performance of a communication system is comprehensively improved.

The embodiment of the disclosure provides a rate matching method, which includes:

adjusting the bit sequence of the code word which finishes the data channel coding according to the interleaving sequence of the first sub-block by taking the sub-block as a unit;

according to the code word after the bit sequence adjustment, carrying out bit selection and bit interleaving to complete the rate matching of the data channel;

and the interleaving order of the first sub-blocks is determined according to a sub-block importance priority principle.

The embodiment of the present disclosure further provides a method for rate de-matching, including:

performing bit de-interleaving and bit de-selection on the demodulated code word to obtain a code word to be de-interleaved;

adjusting the bit sequence of the code word to be de-interleaved according to the interleaving sequence of the first sub-block by taking the sub-block as a unit to obtain a code word to be decoded; the code word to be decoded is used for carrying out data channel decoding to obtain a decoded code word;

An embodiment of the present disclosure further provides a rate matching apparatus, including:

the first interleaving module is used for adjusting the bit sequence of the code words subjected to the data channel coding according to the interleaving sequence of the first sub-blocks by taking the sub-blocks as units;

the selective interleaving module is set to perform bit selection and bit interleaving according to the code words after the bit sequence adjustment so as to complete the rate matching of the data channel;

The embodiment of the present disclosure further provides a rate de-matching apparatus, including:

the de-interleaving selection module is used for performing bit de-interleaving and bit de-selection on the demodulated code word to obtain a code word to be de-interleaved;

the first de-interleaving module is used for adjusting the bit sequence of the code word to be de-interleaved according to the interleaving sequence of the first sub-blocks by taking the sub-blocks as a unit to obtain the code word to be decoded; the code word to be decoded is used for carrying out data channel decoding to obtain a decoded code word;

An embodiment of the present disclosure further provides a mobile terminal, including a communication chip, where the communication chip is configured to perform:

Embodiments of the present disclosure also provide a computer-readable storage medium, on which a computer program is stored, which when executed by a processor implements a rate matching method according to any of the embodiments of the present disclosure.

The embodiments of the present disclosure also provide a computer-readable storage medium, on which a computer program is stored, which when executed by a processor implements the method for de-rate matching according to any of the embodiments of the present disclosure.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.

FIG. 1 is a block diagram of a module for performing rate matching and correlation of a data channel;

FIG. 2 is a schematic diagram of a structure of an NR LDPC coded codeword;

fig. 3 is a mapping specification for bits (b) to modulation symbols (d) by 3 GPP;

fig. 4 is a schematic diagram illustrating a flow of rate matching and de-rate matching proposed in the embodiment of the present disclosure;

FIG. 5 is a flow chart of a method for rate matching according to an embodiment of the present disclosure;

FIG. 6 is a diagram illustrating a result of sub-block interleaving in an embodiment of the present disclosure;

fig. 7 is a schematic diagram of a simulation result of a block error rate vs signal-to-noise ratio (MCS ═ 16) in the embodiment of the present disclosure;

fig. 8 is a schematic diagram of a simulation result of another block error rate vs snr (MCS ═ 20) in the embodiment of the present disclosure;

fig. 9 is a schematic diagram of a simulation result of another block error rate vs signal-to-noise ratio in the embodiment of the present disclosure (MCS ═ 27);

FIG. 10 is a flow chart of a method for de-rate matching in an embodiment of the present disclosure;

fig. 11 is a schematic diagram of a rate matching apparatus according to an embodiment of the disclosure;

fig. 12 is a schematic structural diagram of a de-rate matching apparatus according to an embodiment of the disclosure.

The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.

In addition, the descriptions related to "first", "second", etc. in the present invention are only for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "connected," "secured," and the like are to be construed broadly, and for example, "secured" may be a fixed connection, a removable connection, or an integral part; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In addition, the technical solutions in the embodiments of the present invention may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination of technical solutions should not be considered to exist, and is not within the protection scope of the present invention.

Before describing the embodiments in detail, the abbreviations of the related terms referred to in the present disclosure are as follows:

according to the protocol specification of 3GPP (38.212-5.4.2), rate matching of NR data channels involves two steps:

1) bit selection (bit selection)

Writing the LDPC coded bit stream into a bit stream of size N_cbUntil the number of effective bits read reaches a given value E, data is read from the start position determined by the redundancy version (rv).

2) Bit interleaving (bit interleaving)

Writing a bit-selected bitstream in rows of a dimension of

And then read out column by column. Wherein Q is_mIndicating the number of bits contained in each modulation symbol (e.g., for 16-QAM Q)_m4, for 256-QAM Q_m＝8)，E/Q_mIndicating the number of modulation symbols (the calculation rule of E can ensure that it is Q_mInteger multiples of).

The bit stream obtained after rate matching is mapped to modulation symbols by modulation through code block concatenation and scrambling. Note that code block concatenation and scrambling do not affect the bit order in a single code block. In some implementations, the rate matching process and its associated modules in the NR data channel are as shown in fig. 1.

In some achievable bit-level processing of data channels, the design of rate matching is closely related to the design of LDPC codes and HARQ mechanisms. When the physical resources allocated to the PDSCH and the MCS to be used are determined, the system can calculate the Transport Block Size (TBS), the code block correlation parameters (size, base map index and lifting value of LDPC coding, etc.), and the number of transmission bits (E) available for each code block. According to the selected base graph, the LDPC encoder performs complete encoding on the input information bits to obtain a bit stream corresponding to the lowest encoding code rate (BG 1 is 1/3, BG2 is 1/5). The complete codeword of NR LDPC has a specific structure as shown in fig. 2: the first part being information bits and the second part being of length 4. Z_cThe third part corresponds to the extension check bit with the column degree of 1. Generally, the size of the circular buffer is equal to the length of a complete codeword; that is, all parity bits can be written to the ring buffer.

When using the HARQ mechanism, the initial transmission starts with the start of the codeword and selects bits if the number of bits available for transmission is smaller than the size of the circular buffer (E)<N_cb) If the codeword is not a complete codeword, part of the check bits will not be transmitted, resulting in an effective code rate higher than the coding code rate. If the initial transmission decoding fails, the transmitting end learns that retransmission needs to be carried out through feedback (NACK), and the initial position of new bit selection is determined according to the reselected redundancy version. Through retransmission, the system can send check bits which are not sent during initial transmission, thereby reducing the effective code rate. When the channel condition is poor and the code block is retransmitted for many times, all the transmitted bits can generally cover the whole annular buffer, and the effective code rate can be lower than the lowest coding code rate because part of the bits are repeatedly transmitted.

Considering the factors of time delay, power consumption, occupied physical resources and the like, the fewer the transmission times required for successful decoding, the better. In terms of bit selection, this means that we should try to place the bits "important" for decoding in front of the codeword, so that it has a greater probability of being transmitted at the beginning of transmission. It can be seen that the 3GPP existing LDPC coding and bit selection design is in line with this principle: the information bits are at the very front of the codeword, followed by core parity bits participating in multiple parity check equations, and finally extended parity bits participating in only one parity check equation. On the basis of this, the design of the bit interleaver also follows this principle: according to the mapping rule shown in fig. 3, the order in which bits are read out from the interleaving matrix (i.e. the row sequence of the interleaving matrix) corresponds to the reliability of bits in modulation symbols from high to low (note that two bits contained in each symbol in QPSK have the same reliability). That is, the bits written first into the interleaving matrix are given better noise immunity during transmission. For the initial transmission of the code block, the information bits and the core check bits are written into the interleaving matrix before the extension check bits, and therefore, the interleaving matrix has a larger possibility of having higher reliability.

Research shows that for improving the decoding performance as a whole, for a given LDPC coding mode and bit-to-modulation symbol mapping mode, the design of bit selection should follow the principle of "importance from high to low". The relevant protocol provisions follow this principle overall, but still leave room for optimization in detail. For example, these realizable schemes do not take into account ordering issues between information bits and between extended parity bits, and do not allow more important bits to be received with greater probability of appearing in the initial transmission and with greater reliability. According to the scheme, the subblock interleaving function is added before bit selection processing, and the coded bit stream is rearranged to a certain extent, so that more important bits are more likely to appear in initial transmission and are received with higher reliability, and the decoding performance of the system is improved.

In order to optimize the bit sequence of the encoded codeword, the solution of the embodiment of the present disclosure proposes to add a sub-block interleaver before the bit selection module at the transmitting end, as shown in fig. 4. Accordingly, when performing rate de-matching at the receiving end, a sub-block deinterleaver for performing an inverse operation needs to be added after the de-bit selection.

An embodiment of the present disclosure provides a rate matching method, as shown in fig. 5, including:

step 510, adjusting the bit sequence of the code word which completes the data channel coding according to the interleaving sequence of the first sub-block by taking the sub-block as a unit;

step 520, according to the code word after the bit sequence adjustment, performing bit selection and bit interleaving to complete the rate matching of the data channel;

In some exemplary embodiments, the rate matching method is applied to rate matching of a data channel.

The code word for completing data channel coding at least comprises: information bits, first parity bits, and second parity bits;

wherein the importance of the sub-block corresponding to the information bits and the importance of the sub-block corresponding to the first parity bits are higher than the importance of the sub-block corresponding to the second parity bits.

As known to those skilled in the art, sub-block interleaving refers to rearranging an original sub-block arrangement order in units of sub-blocks, and a sub-block interleaving order is an order used in sub-block interleaving to indicate the rearrangement of sub-blocks. For example, before interleaving, the encoded codeword includes N sub-blocks, arranged from front to back in the order of sub-block numbers 1 to N; after rearrangement (after interleaving), the corresponding subblock numbers from front to back are: i, x,., N, 1, … (N subblocks, i, x, N representing subblock numbers, which are numbers greater than 1 and less than N), where the rearranged subblock numbers (i, x., N, 1, …) are the subblock interleaving order, it can be understood that subblock interleaving is: the sub-blocks numbered 1-N are rearranged according to the interleaving order of the sub-blocks to obtain new code words.

It should be noted that the importance of the sub-blocks corresponding to different types of bit data indicates the importance of the bit data contained in the sub-blocks for successful decoding. In some exemplary embodiments, in the data channel, the importance of the sub-block corresponding to the information bits (systematic bits) containing the service data is greater than or equal to the parity bits (parity bits) containing the parity data. In some exemplary embodiments, the data channel encoded codeword may further include multiple types of check bits, for example: the first parity bits, the second parity bits, the schemes generated based on these different types of parity bits and corresponding roles in the decoding process may also correspond to the same or different importance levels. In some exemplary embodiments, the importance levels of the bit data of different sub-blocks in the same type of parity bits may be the same or different. In some exemplary embodiments, the first sub-block interleaving order is determined according to a sub-block importance priority principle. For different coding schemes, statistical information of importance of each sub-block (bit) is obtained through theoretical analysis and/or simulation, and the interleaving sequence of the first sub-block used in the scheme application process is correspondingly determined.

In some exemplary embodiments, the codeword for which data channel coding is completed is a low density parity check code LDPC coded codeword, the first check bits are core check bits, and the second check bits are extension check bits.

It should be noted that, in the rate matching scheme in the scheme improvement correlation scheme provided by the embodiments of the present disclosure, a sub-block interleaving module (sub-block interleaver) is added before the bit selection process, so as to optimize the bit sequence of the data channel coding codeword, and especially when high-order modulation and a higher code rate are used, the performance of initial transmission and first retransmission can be improved.

In some exemplary embodiments, the LDPC coded codeword as shown in fig. 2 includes information bits (systematic bits), core parity bits (kernel parity bits), and extension parity bits (depth-1 parity bits) having a rank of 1.

In some exemplary embodiments, in the sub-blocks corresponding to the extended parity bits, the higher the row weight of the row in the LDPC check matrix of each sub-block is, the higher the importance of the sub-block is.

In some exemplary embodiments, the importance of each sub-block in the sub-blocks corresponding to the information bits and the core check bits is determined according to a row sequence of each sub-block relative to the LDPC check matrix.

In some exemplary embodiments, the determining, in the sub-blocks corresponding to the information bits and the core check bits, importance of each sub-block according to a row order of each sub-block related to the LDPC check matrix includes:

respectively determining the row sequence of each sub-block relative to the LDPC check matrix;

it is determined that the importance of the row-sequentially first sub-block is higher than the importance of the row-sequentially next sub-block.

In some exemplary embodiments, the determining the first sub-block interleaving order according to a sub-block importance priority rule includes:

and sequencing all sub-blocks included by the code word which finishes the data channel coding according to the sequence of the importance of the sub-blocks from high to low, and determining the sequence of the sequenced sub-blocks as the interleaving sequence of the first sub-block.

That is to say, according to the order of the importance of each sub-block included in the code word which has completed the data channel coding from high to low, the sub-blocks are rearranged to obtain the interleaved code word, and the order of the sub-blocks corresponding to the interleaved code word is the interleaving order of the first sub-blocks. It can be seen that in the code word after interleaving, the importance of the sub-block arranged in front is higher than or equal to the importance of the sub-block arranged in back, that is, in the code word after sub-block interleaving, the importance of the corresponding sub-block is from high to low in the order from front to back.

In some exemplary embodiments, the sub-block has a size of a lifting value Z employed in the LDPC encoding_c。

It should be noted that the interleaving order of the first sub-block is determined according to the sub-block importance priority principle, and after the determination, in step 510, the bit order of the data channel coding codeword is adjusted according to the determined interleaving order of the first sub-block.

In some exemplary embodiments, the interleaving order of the first sub-blocks determined according to the sub-block importance priority rule satisfies at least one of the following aspects:

keeping the information bit and the core check bit prior to the extension check bit;

arranging the extended check bits according to the row weight of the row in the LDPC check matrix from high to low;

for the information bits and the core check bits, the bits related to the zeroth row of the LDPC check matrix are arranged at the top, and then the bits related to the first, second, and third rows but not yet participating in the ordering are sequentially arranged.

It should be noted that the bit order of the LDPC encoded codeword is adjusted according to the determined first sub-block interleaving order, which is also referred to as sub-block interleaving. In some exemplary embodiments, sub-block interleaving may be regarded as some adjustment of the row-column order in the LDPC base graph, so that its addition does not substantially increase the complexity of system implementation.

Taking BG1 of LDPC as an example, the codeword after sub-block interleaving is shown in fig. 6. In the code word after the bit sequence adjustment, the information bit and the core check bit are in front of the extension check bit; in the subblocks corresponding to the information bit and the core check bit, the row sequence of each subblock relative to the LDPC check matrix is more advanced, and the correspondingly adjusted position is more advanced, namely the row sequence of the subblocks relative to the LDPC check matrix is 0,1, 2 or 3, and the corresponding subblocks are sequentially arranged from front to back according to the sequence of the row sequence 0-3; in the sub-blocks corresponding to the extended check bits, the higher the row weight of the row in which each sub-block is located in the LDPC check matrix, the earlier the corresponding adjusted position is, that is, in the rearranged extended check bits, the row with the higher row weight is arranged in the front, and the row with the lower row weight is arranged in the rear.

As shown in fig. 7, fig. 8, and fig. 9, performance simulation results of the initial transmission and the first retransmission are given when MCS is 16,20, and 27 (according to 38.214-Table 5.1.3.1-2), respectively. It is noted that the performance of the suboptimal decoding algorithm is greatly influenced by parameter selection (for example, the performance of the normalization min-sum algorithm is closely related to the selection of the normalization factor), and the addition of the sub-block interleaver may change the optimal parameter value, so that in order to ensure the fairness of the comparison simulation, a sum-product (sum-product) algorithm which does not need to adjust parameters and has better performance is selected as the LDPC decoding algorithm. Other major simulation conditions include: the simulation times of each SNR point of the AWGN channel are 20000, and the redundancy versions of the initial transmission and the first retransmission are 0 and 2 respectively; the decoder adopts layered decoding, carries out layer scheduling according to the sequence of line weight from low to high, and sets the maximum iteration number as 12. Determined order of sub-block interleaving (base map)One) as follows: 0,1,3,4,7,8,9,10,11,13,14,16,17,18,19,20,21,2,5,6,12,15,22,23,28,29,26,31,25,35,34,32,30,27,44,41,40,39,38,37,36,33,64,63,61,59,58,56,55,54,53,52,51,50,49,48,46,45,43,42,65,62,60,57,47,24 as can be seen from a comparison of simulation results, the addition of a sub-block interleaver to several different MCSs improves decoding performance. In BLER ∈ [10 ]^-3,10^-2]In the range of (1), the improvement is in the range of about 0.1-0.2 dB. Other MCS, maximum retransmission times and maximum iteration times are also simulated, and performance improvement of different degrees brought by a sub-block interleaver is also observed.

In some exemplary embodiments, the code word for which data channel coding is completed is an LDPC BG1 encoded code word, and the first sub-block interleaving order is:

0，1，3,4,7，8,9,10,11,13,14,16，17，18,19,20,21,2,5，6,12，15,22,23，

28,29,26,31,25,35,34,32,30,27,44,41,40,39,38,37,36,33,64,63,61，

59,58,56,55,54,53,52,51,50，49,48,46,45，43，42，65,62,57，47,24。

it can be seen that in some exemplary implementations, in step 510, the code word after data channel coding is performed by using the LDPC BG1, the bit sequence of the coded code word is adjusted according to the above first sub-block interleaving sequence by taking a sub-block as a unit, and the adjusted code word is further subjected to bit selection and bit interleaving to complete data channel rate matching. For the code word which adopts the LDPC BG2 to perform data channel coding, the importance of each sub-block can also be determined through correlation analysis and/or simulation, and the corresponding interleaving order of the first sub-blocks is determined for the corresponding rate matching and de-rate matching. More detailed examples, not just those given.

It should be noted that, for a digital signal communication system using an HARQ mechanism or implementing symbol mapping with high-to-low reliability adjustment through bit interleaving, the rate matching scheme provided by the implementation of the present disclosure may be adopted, so that bits of encoded codewords are sorted from high to low in importance before bit selection is performed. For different coding schemes, statistical information of importance of each sub-block (bit) is obtained through theoretical analysis and/or simulation, and a corresponding first sub-block interleaving sequence is determined based on the statistical information, so that sub-block interleaving before bit selection is realized. The specific interleaving order of the first sub-blocks is not limited to the aspect shown in the above-described embodiments of the present disclosure.

An embodiment of the present disclosure further provides a method for rate de-matching, as shown in fig. 10, including:

step 1010, performing bit de-interleaving and bit de-selection on the demodulated code word to obtain a code word to be de-interleaved;

step 1020, adjusting the bit sequence of the code word to be deinterleaved by taking the sub-block as a unit according to the interleaving sequence of the first sub-block to obtain a code word to be decoded; the code word to be decoded is used for carrying out data channel decoding to obtain a decoded code word;

In some exemplary embodiments, the de-rate matching method is applied to a data channel.

It should be noted that the rate de-matching method provided in the embodiment of the present disclosure is a code word processing method of a receiving end corresponding to the rate matching method provided in the embodiment of the present disclosure, and is an inverse operation of the rate matching method. According to the description of the steps of rate matching, those skilled in the art can clearly know that the steps corresponding to rate de-matching are implemented, and are not described in detail herein.

The interleaving order of the first sub-block used in step 1010 is consistent with the interleaving order of the first sub-block determined in the rate matching scheme, de-interleaving is performed according to the interleaving order of the first sub-block, so that a codeword with a recovered bit sequence can be obtained, and the recovered codeword can be decoded according to a related channel data decoding scheme to obtain corresponding service data. The implementation steps of the sub-block interleaving and sub-block deinterleaving are clearly known to those skilled in the art according to the determined first sub-block interleaving order, and the specific aspects are not discussed in detail in the embodiments of the present application.

An embodiment of the present disclosure further provides a rate matching apparatus 1100, as shown in fig. 11, including:

a first interleaving module 1110, configured to adjust a bit sequence of a codeword that has completed data channel coding according to a first sub-block interleaving sequence in units of sub-blocks;

a selective interleaving module 1120, configured to perform bit selection and bit interleaving according to the codeword adjusted by the bit sequence to complete rate matching of the data channel;

In some exemplary embodiments, the selective interleaving module 1120 includes: a bit selection unit 1121 configured to perform bit selection according to the codeword adjusted by the bit sequence; a bit interleaving unit 1122 is configured to perform bit interleaving on the selected codeword to complete data channel rate matching.

An embodiment of the present disclosure further provides a mobile terminal, which includes the rate matching apparatus 1100.

An embodiment of the present disclosure further provides a rate de-matching apparatus 1200, as shown in fig. 12, including:

a de-interleaving selection module 1210 configured to perform bit de-interleaving and bit de-selection on the demodulated codeword to obtain a codeword to be de-interleaved;

a first de-interleaving module 1220, configured to adjust the bit sequence of the codeword to be de-interleaved in units of sub-blocks according to the interleaving sequence of the first sub-blocks to obtain a codeword to be decoded; the code word to be decoded is used for carrying out data channel decoding to obtain a decoded code word;

In some exemplary embodiments, the deinterleaving selection module 1210 includes: a bit deinterleaving unit 1211 configured to perform bit deinterleaving on the demodulated codeword; the bit de-selection unit 1212 is configured to perform bit de-selection on the codeword after bit de-interleaving to obtain a codeword to be de-interleaved.

It is understood that the codeword to be deinterleaved herein corresponds to the output codeword of the first interleaving module 1110 in the rate matching apparatus 1100.

An embodiment of the present disclosure further provides a mobile terminal, which includes the apparatus 1200 for rate de-matching.

An embodiment of the present disclosure further provides a storage medium, where a computer program is stored in the storage medium, where the computer program is configured to execute the rate matching method described in any of the above embodiments when running.

The embodiments of the present disclosure further provide a storage medium, where a computer program is stored in the storage medium, where the computer program is configured to execute the method for de-rate matching in any of the above embodiments when running.

The rate matching method provided by the embodiment of the disclosure adds a sub-block interleaving step before bit selection, so that after the sub-block (bit) with higher importance is preposed, bit selection and bit interleaving are performed, so that the sub-block (bit) with higher importance can be initially transmitted or retransmitted for the first time, thereby saving physical resources, and reducing the transmission delay of information and the power consumption of a communication system. Especially under the conditions of high-order modulation and high code rate, the effect of improving the initial transmission and the first retransmission is more obvious.

It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as is well known to those skilled in the art.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. A method of rate matching, comprising:

2. The method of claim 1,

3. The method of claim 2,

the code word of which the data channel coding is finished is a low-density parity check code (LDPC) coding code word, and the second check bit is an extension check bit;

in the sub-blocks corresponding to the extended check bits, the higher the row weight of the row of each sub-block in the LDPC check matrix is, the higher the importance of the sub-block is.

4. The method of claim 2,

the code word which completes channel coding is a low density parity check code (LDPC) coding code word, and the first check bit is a core check bit;

and in the subblocks corresponding to the information bit and the core check bit, the importance of each subblock is determined according to the row sequence of each subblock relative to the LDPC check matrix.

5. The method of claim 4,

the importance of each sub-block is determined according to the row sequence of each sub-block and the LDPC check matrix, and the method comprises the following steps:

6. The method of any one of claims 1 to 5,

the interleaving order of the first sub-block is determined according to a sub-block importance priority principle, and comprises the following steps:

and sequencing all the sub-blocks included by the code word which completes the data channel coding according to the sequence of the importance of the sub-blocks from high to low, and determining the sequence of the sequenced sub-blocks as the interleaving sequence of the first sub-blocks.

7. A method for rate de-matching, comprising:

8. A rate matching apparatus, comprising:

9. A de-rate matching apparatus, comprising:

the first de-interleaving module is used for adjusting the bit sequence of the code word to be de-interleaved by taking a sub-block as a unit according to the interleaving sequence of the first sub-block to obtain the code word to be decoded; the code word to be decoded is used for carrying out data channel decoding to obtain a decoded code word;

10. A mobile terminal comprising a communication chip configured to perform:

11. A mobile terminal comprising a communication chip configured to perform:

12. A computer-readable storage medium, on which a computer program is stored, which program, when being executed by a processor, carries out the rate matching method according to any one of claims 1-6; alternatively, the program when executed by a processor implements the de-rate matching method of claim 7.