CN114496998A - EMI filter structure based on electromagnetic shielding film and manufacturing method thereof - Google Patents

EMI filter structure based on electromagnetic shielding film and manufacturing method thereof Download PDF

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CN114496998A
CN114496998A CN202210362633.1A CN202210362633A CN114496998A CN 114496998 A CN114496998 A CN 114496998A CN 202210362633 A CN202210362633 A CN 202210362633A CN 114496998 A CN114496998 A CN 114496998A
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substrate pad
substrate
dry film
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不公告发明人
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Shenzhen Newsonic Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters

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Abstract

The invention provides an EMI filter structure based on an electromagnetic shielding film and a manufacturing method thereof. The EMI filter structure comprises a plurality of chip sets, a substrate and a cover plate; a plurality of chip groups are arranged on the substrate; each chip set comprises a plurality of substrates PAD, two chips, an organic dry film, a dry film window and an EMI shielding layer; the substrate PAD and the chip are arranged on the substrate; arranging an organic dry film on the chip; opening a dry film window on an organic dry film on the substrate PAD; arranging an EMI shielding layer on the chip, the organic dry film and the dry film window; the cover plate and the substrate are bonded to form a packaging structure; wherein the size of the dry film window on the substrate PAD is determined by the window size constraint condition.

Description

EMI filter structure based on electromagnetic shielding film and manufacturing method thereof
Technical Field
The invention provides an EMI filter structure based on an electromagnetic shielding film and a manufacturing method thereof, belonging to the technical field of thin film filters.
Background
The EMI filter acts as two low pass filters: one to attenuate common mode interference and the other to attenuate differential mode interference. The EMI filter attenuates radio frequency energy within the stop band range, while allowing no or little attenuation at power frequency to pass through the EMI filter. EMI filters are the first tools for electronic device design engineers to control conducted and radiated electromagnetic interference. The existing film type EMI filter still has the problem of poor anti-interference capability.
Disclosure of Invention
The invention provides an EMI filter structure based on an electromagnetic shielding film and a manufacturing method thereof, which are used for solving the problem of poor electromagnetic interference resistance of the existing filter, and adopt the following technical scheme:
an EMI filter structure based on an electromagnetic shielding film, the EMI filter structure comprising a plurality of chip sets, a substrate 1 and a cover plate 7; a plurality of chip groups are arranged on the substrate 1; each of the chip sets includes a plurality of substrates PAD2, two chips 3, an organic dry film 4, a dry film window 5, and an EMI shielding layer 6; the substrate PAD2 and the chip 3 are arranged on the substrate 1; an organic dry film 4 is arranged on the chip 3; opening a dry film window 5 on the organic dry film 4 on the substrate PAD 2; arranging an EMI shielding layer 6 on the chip 3, the organic dry film 4 and the dry film windowing 5; the cover plate 7 and the substrate 1 are bonded to form a packaging structure; wherein the size of the dry film window 5 on the substrate PAD2 is determined by the window size constraint. Wherein, the EMI shielding layer 6 is made of conductive epoxy resin material.
Further, the substrates PAD2 are respectively disposed on two sides of the two chips 3, and one substrate PAD2 is disposed between the two chips 3.
Further, the windowing size constraint includes:
when the substrate PAD2 is located on one side of the two chips 3, the dimensional constraints of the corresponding dry film windows 5 on the substrate PAD2 are as follows:
Figure 846156DEST_PATH_IMAGE001
wherein,L 01when the substrate PAD2 is positioned at one side of the two chips 3, the length dimension of the corresponding dry film opening window 5 on the substrate PAD2 is shown;L s indicates PAD2 position of the substrateThe length dimension of the upper surface of the substrate PAD2 at one side of the two chips 3;H 1andH 2respectively representing the thicknesses of the substrate PAD2 and the organic dry film 4;αwhich is indicative of the adjustment coefficient(s),αthe values of (A) are as follows: when in useH 1<H 2When the temperature of the water is higher than the set temperature,α∈[0.08，0.14](ii) a When in useH 2<H 1When the temperature of the water is higher than the set temperature,α∈[0.24，0.32]。
further, the windowing size constraint further comprises:
when the substrate PAD2 is located on the other side of the two chips 3, the dimensional constraint condition of the corresponding dry film window 5 on the substrate PAD2 is as follows:
0.64L 01≤L 02≤0.72L 01
wherein,L 02when the substrate PAD2 is located on the other side of the two chips 3, the length dimension of the corresponding dry film opening 5 on the substrate PAD2 is shown.
Further, the windowing size constraint further comprises:
when the substrate PAD2 is located between the two chips 3, the dimensional constraints of the corresponding dry film window 5 on the substrate PAD2 are as follows:
0.53L 01≤L 03≤0.68L 01
wherein,L 03the length dimension of the corresponding dry film opening 5 on the substrate PAD2 is shown when the substrate PAD2 is located between the two chips 3.
Further, the sizing of the substrate PAD2 includes:
firstly, acquiring the length size and the width size of the chip 3;
secondly, the dimension of the substrate PAD2 is determined by using the dimension in combination with the length dimension and the width dimension of the chip 3 according to a proportional constraint condition, wherein the proportional constraint condition comprises:
when the substrate PAD2 is located at one side of the chip 3 and the substrate PAD2 is not disposed at a position between two adjacent chips 3, the dimensional constraints of the substrate PAD2 are as follows:
Figure 576214DEST_PATH_IMAGE002
Figure 776251DEST_PATH_IMAGE003
wherein,L 1indicates the length dimension corresponding to the long side of the substrate PAD2 when the substrate PAD2 is positioned at one side of the chip 3 and the substrate PAD2 is not arranged at the position between two adjacent chips 3;D 1indicates the length dimension corresponding to the short side of the substrate PAD2 when the substrate PAD2 is positioned at one side of the chip 3 and the substrate PAD2 is not arranged at the position between two adjacent chips 3;Lindicates the length dimension corresponding to the long side of the chip 3;Dindicates the length dimension corresponding to the short side of the chip 3;H 0the size-adjustment parameter is represented by,H 0has a value range of 0.22D≤H 0≤0.94D(ii) a When the size of the chip 3 is satisfiedL=DWhen the temperature of the water is higher than the set temperature,L 1with the constraint ofL 1≤0.23D；
When the substrate PAD2 is located at one side of the chip 3 and the substrate PAD2 is disposed at a position between two adjacent chips 3, the dimensional constraints of the substrate PAD2 are as follows:
Figure 300774DEST_PATH_IMAGE004
Figure 586262DEST_PATH_IMAGE005
wherein,L 2indicates the length dimension corresponding to the long side of the substrate PAD2 when the substrate PAD2 is positioned at one side of the chip 3 and the substrate PAD2 is arranged at the position between two adjacent chips 3;D 2to representWhen the substrate PAD2 is located at one side of the chip 3 and the substrate PAD2 is located at a position between two adjacent chips 3, the length dimension of the short side of the substrate PAD2 corresponds to;Lindicates the length dimension corresponding to the long side of the chip 3;Da length dimension corresponding to a short side of the chip 3;H 0the size-adjustment parameter is represented by,H 0has a value range of 0.22D≤H 0≤0.94D(ii) a When the size of the chip 3 is satisfiedL=DWhen the temperature of the water is higher than the set temperature,L 1with the constraint ofL 1≤0.23D。
A method of manufacturing an EMI filter structure based on an electromagnetic shielding film, the method of manufacturing comprising:
step 1, preparing the chip 3 and the substrate PAD2 on the substrate 1 by using an SMT process; the substrate PAD2 is arranged on two sides of the chip 3, and only one substrate PAD (2) is arranged in front of each two adjacent chips 3;
step 2, attaching an organic dry film 4 on the chip 3 and the substrate PAD 2;
step 3, punching and windowing on the corresponding organic dry film 4 on the substrate PAD2 to form a dry film windowing 5;
step 4, forming an EMI shielding layer 6 on the substrate PAD2 with the dry film window 5 and on the upper surface of the chip 3 corresponding to the substrate PAD2 with the dry film window 5 by means of CVD, PVD or sputtering;
and 5, bonding and packaging the cover plate 7 and the substrate 1 after the EMI shielding layer 6 is formed.
Further, each of the chip sets includes a plurality of substrates PAD2, two chips 3, an organic dry film 4, a dry film window 5, and an EMI shielding layer 6; the substrate PAD2 and the chip 3 are arranged on the substrate 1; an organic dry film 4 is arranged on the chip 3; opening a dry film window 5 on the organic dry film 4 on the substrate PAD 2; arranging an EMI shielding layer 6 on the chip 3, the organic dry film 4 and the dry film windowing 5; the cover plate 7 and the substrate 1 are bonded to form a packaging structure; wherein the size of the dry film window 5 on the substrate PAD2 is determined by the window size constraint.
Further, the windowing size constraint is as follows:
when the substrate PAD2 is located on one side of the two chips 3, the dimensional constraint condition of the corresponding dry film window 5 on the substrate PAD2 is as follows:
Figure 588853DEST_PATH_IMAGE006
wherein,L 01when the substrate PAD2 is positioned at one side of the two chips 3, the length dimension of the corresponding dry film opening window 5 on the substrate PAD2 is shown;L s represents the upper surface length dimension of the substrate PAD2 when the substrate PAD2 is located on one side of the two chips 3;H 1andH 2respectively indicating the thickness of the substrate PAD2 and the organic dry film 4;αwhich is indicative of the adjustment coefficient(s),αthe values of (A) are as follows: when in useH 1<H 2When the temperature of the water is higher than the set temperature,α∈[0.08，0.14](ii) a When in useH 2<H 1When the temperature of the water is higher than the set temperature,α∈[0.24，0.32]；
when the substrate PAD2 is located on the other side of the two chips 3, the dimensional constraint condition of the corresponding dry film window 5 on the substrate PAD2 is as follows:
0.64L 01≤L 02≤0.72L 01
wherein,L 02when the substrate PAD2 is positioned at the other side of the two chips 3, the length dimension of the corresponding dry film opening window 5 on the substrate PAD2 is shown;
when the substrate PAD2 is located between the two chips 3, the dimensional constraints of the corresponding dry film window 5 on the substrate PAD2 are as follows:
0.53L 01≤L 03≤0.68L 01
wherein,L 03the length dimension of the corresponding dry film opening 5 on the substrate PAD2 is shown when the substrate PAD2 is located between the two chips 3.
The invention has the beneficial effects that:
according to the EMI filter structure based on the electromagnetic shielding film and the manufacturing method thereof, the thin metal protective layer can be formed in a mode of arranging the dry film window and the EMI shielding layer and in a mode of spraying the conductive epoxy resin, and the thin metal protective layer is connected with the substrate PAD and plays a role in isolating electromagnetic interference between chips. Meanwhile, in order to reduce the size of the filter to the maximum extent and effectively improve the stable signal connectivity among the functional circuits of each chip, the size of the filter is effectively reduced and the stability of the signal connection among the functional circuits of each chip is improved in a mode of limiting the size of the substrate PAD, so that the stability of the functional operation of the filter is effectively improved.
On the other hand, the thin film type EMI filter structure and the manufacturing method thereof provided by the invention can ensure that the EMI shielding layer can be effectively attached to the functional surface of the substrate PAD at the fastest speed and the most complete attaching degree when the thickness of the organic dry film and the thickness of the substrate PAD are in any proportional relation by setting the size constraint condition of the dry film windowing, thereby effectively preventing the problems that when the thickness of the organic dry film is larger than the thickness of the substrate PAD and the size of the substrate PAD is smaller, the windowing size of the dry film windowing is insufficient, so that the EMI shielding layer is larger in obstacle of the dry film windowing, the manufacturing speed of the EMI shielding layer is lower, the attaching degree of the EMI shielding layer and the functional surface of the substrate PAD is insufficient, and the anti-electromagnetic interference capability of the filter is insufficient.
Drawings
FIG. 1 is a first schematic diagram of a filter according to the present invention;
FIG. 2 is a second schematic diagram of the filter structure according to the present invention;
FIG. 3 is a third schematic diagram of the filter structure according to the present invention;
fig. 4 is a schematic diagram of a filter structure according to the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
As shown in fig. 1, the EMI filter structure based on the electromagnetic shielding film according to the present invention includes a plurality of chip sets, a substrate 1 and a cover plate 7; a plurality of chip groups are arranged on the substrate 1; each of the chip sets includes a plurality of substrates PAD2, two chips 3, an organic dry film 4, a dry film window 5, and an EMI shielding layer 6; the substrate PAD2 and the chip 3 are arranged on the substrate 1; an organic dry film 4 is arranged on the chip 3; opening a dry film window 5 on the organic dry film 4 on the substrate PAD 2; arranging an EMI shielding layer 6 on the chip 3, the organic dry film 4 and the dry film windowing 5; the cover plate 7 and the substrate 1 are bonded to form a packaging structure; wherein the size of the dry film window 5 on the substrate PAD2 is determined by the window size constraint.
The substrates PAD2 are respectively disposed on two sides of the two chips 3, and one substrate PAD2 is disposed between the two chips 3.
The working principle and the effect of the technical scheme are as follows: the EMI filter structure based on the electromagnetic shielding film provided by this embodiment can form a thin metal protection layer and a substrate PAD while playing a role in isolating electromagnetic interference between chips by means of opening a dry film window and providing an EMI shielding layer and spraying a conductive epoxy resin. Meanwhile, in order to reduce the size of the filter to the maximum extent and effectively improve the stable signal connectivity among the functional circuits of each chip, the size of the filter is effectively reduced and the stability of the signal connection among the functional circuits of each chip is improved in a mode of limiting the size of the substrate PAD, so that the stability of the functional operation of the filter is effectively improved.
In one embodiment of the present invention, the windowing size constraint comprises:
when the substrate PAD2 is located on one side of the two chips 3, the dimensional constraint condition of the corresponding dry film window 5 on the substrate PAD2 is as follows:
Figure 643396DEST_PATH_IMAGE001
wherein,L 01when the substrate PAD2 is positioned at one side of the two chips 3, the length dimension of the corresponding dry film opening window 5 on the substrate PAD2 is shown;L s represents the upper surface length dimension of the substrate PAD2 when the substrate PAD2 is located on one side of the two chips 3;H 1andH 2respectively representing the thicknesses of the substrate PAD2 and the organic dry film 4;αwhich is indicative of the adjustment coefficient(s),αthe values of (A) are as follows: when in useH 1<H 2When the temperature of the water is higher than the set temperature,α∈[0.08，0.14](ii) a When in useH 2<H 1When the temperature of the water is higher than the set temperature,α∈[0.24，0.32]。
when the substrate PAD2 is located on the other side of the two chips 3, the dimensional constraint condition of the corresponding dry film window 5 on the substrate PAD2 is as follows:
0.64L 01≤L 02≤0.72L 01
wherein,L 02the length of the dry film window 5 on the substrate PAD2 is shown when the substrate PAD2 is located on the other side of the two chips 3.
When the substrate PAD2 is located between the two chips 3, the dimensional constraints of the corresponding dry film window 5 on the substrate PAD2 are as follows:
0.53L 01≤L 03≤0.68L 01
wherein,L 03the length dimension of the corresponding dry film opening 5 on the substrate PAD2 is shown when the substrate PAD2 is located between the two chips 3.
The working principle and the effect of the technical scheme are as follows: through the setting to the size constraint condition that the dry film windowed, can be at the film filter to various modes, when the thickness of organic dry film and base plate PAD thickness become any proportional relation, all can guarantee that EMI shielding layer can be with fastest speed and the most complete laminating degree with base plate PAD's functional surface carries out effective laminating, effectively prevents when organic dry film thickness is greater than base plate PAD thickness, and, when base plate PAD size is less, the window size of dry film windowing is not enough and leads to EMI shielding layer to lead to EMI shielding layer preparation speed to meet the end and with base plate PAD's functional surface laminating degree inadequately through the obstacle great that leads to of dry film windowing, and then leads to the not enough problem emergence of wave filter anti-electromagnetic interference ability.
In one embodiment of the present invention, the process of sizing the substrate PAD2 includes:
firstly, acquiring the length size and the width size of the chip 3;
secondly, determining the size of the substrate PAD2 by combining the length size and the width size of the chip 3 according to a proportion constraint condition by utilizing the size, wherein the proportion constraint condition comprises the following steps:
when the substrate PAD2 is located at one side of the chip 3 and the substrate PAD2 is not disposed at a position between two adjacent chips 3, the dimensional constraints of the substrate PAD2 are as follows:
Figure 604399DEST_PATH_IMAGE002
Figure 111604DEST_PATH_IMAGE003
wherein,L 1indicates the length dimension corresponding to the long side of the substrate PAD2 when the substrate PAD2 is positioned at one side of the chip 3 and the substrate PAD2 is not arranged at the position between two adjacent chips 3;D 1indicates the length dimension corresponding to the short side of the substrate PAD2 when the substrate PAD2 is positioned at one side of the chip 3 and the substrate PAD2 is not arranged at the position between two adjacent chips 3;Lindicates the length dimension corresponding to the long side of the chip 3;Dindicates the length dimension corresponding to the short side of the chip 3;H 0the size-adjustment parameter is represented by,H 0has a value range of 0.22D≤H 0≤0.94D(ii) a When the size of the chip 3 is satisfiedL=DWhen the temperature of the water is higher than the set temperature,L 1with the constraint ofL 1≤0.23D；
When the substrate PAD2 is located at one side of the chip 3 and the substrate PAD2 is disposed at a position between two adjacent chips 3, the dimensional constraints of the substrate PAD2 are as follows:
Figure 917886DEST_PATH_IMAGE004
Figure 92515DEST_PATH_IMAGE005
wherein,L 2indicates the length dimension corresponding to the long side of the substrate PAD2 when the substrate PAD2 is positioned at one side of the chip 3 and the substrate PAD2 is arranged at the position between two adjacent chips 3;D 2indicates the length dimension corresponding to the short side of the substrate PAD2 when the substrate PAD2 is positioned at one side of the chip 3 and the substrate PAD2 is arranged at the position between two adjacent chips 3;La length dimension corresponding to a long side of the chip 3;Dindicates the length dimension corresponding to the short side of the chip 3;H 0the size-adjustment parameter is represented by,H 0has a value range of 0.22D≤H 0≤0.94D(ii) a When the size of the chip 3 is satisfiedL=DWhen the utility model is used, the water is discharged,L 1with the constraint ofL 1≤0.23D。
The working principle and the effect of the technical scheme are as follows: the size of the substrate PAD obtained through the constraint conditions can be effectively combined with the size proportion of the filter chip to set the size of the substrate PAD, the matching property between the size of the substrate PAD and the size of the filter chip can be effectively improved in the mode, the filter level is more, the chip application amount is larger, the adaptability between the size setting and the layout of the substrate PAD and the layout and the size of the chip is effectively improved, the filter level is more, the size of the filter is further maximally reduced under the larger chip application amount, meanwhile, the stability of the substrate PAD functionality is improved, and the problem that the functionality of the substrate PAD is weakened due to excessive reduction is effectively prevented.
An embodiment of the present invention provides a method for manufacturing an EMI filter structure based on an electromagnetic shielding film, as shown in fig. 1 to 4, the method includes:
step 1, preparing the chip 3 and the substrate PAD2 on the substrate 1 by using an SMT process; the substrates PAD2 are arranged on two sides of the chip 3, and only one substrate PAD2 is arranged in front of each two adjacent chips 3;
step 2, attaching an organic dry film 4 on the chip 3 and the substrate PAD 2;
step 3, punching and windowing on the corresponding organic dry film 4 on the substrate PAD2 to form a dry film windowing 5;
step 4, forming an EMI shielding layer 6 on the substrate PAD2 with the dry film window 5 and on the upper surface of the chip 3 corresponding to the substrate PAD2 with the dry film window 5 by means of CVD, PVD or sputtering;
and 5, bonding and packaging the cover plate 7 and the substrate 1 after the EMI shielding layer 6 is formed.
Wherein each of the chip sets includes a plurality of substrates PAD2, two chips 3, an organic dry film 4, a dry film window 5, and an EMI shielding layer 6; the substrate PAD2 and the chip 3 are arranged on the substrate 1; an organic dry film 4 is arranged on the chip 3; opening a dry film window 5 on the organic dry film 4 on the substrate PAD 2; arranging an EMI shielding layer 6 on the chip 3, the organic dry film 4 and the dry film windowing 5; the cover plate 7 and the substrate 1 are bonded to form a packaging structure; wherein the size of the dry film window 5 on the substrate PAD2 is determined by the window size constraint.
The windowing size constraint is as follows:
when the substrate PAD2 is located on one side of the two chips 3, the dimensional constraint condition of the corresponding dry film window 5 on the substrate PAD2 is as follows:
Figure 958840DEST_PATH_IMAGE006
。
wherein,L 01when the substrate PAD2 is positioned at one side of the two chips 3, the length dimension of the corresponding dry film opening window 5 on the substrate PAD2 is shown;L s represents the upper surface length dimension of the substrate PAD2 when the substrate PAD2 is located on one side of the two chips 3;H 1andH 2respectively indicating the thickness of the substrate PAD2 and the organic dry film 4;αwhich is indicative of the adjustment coefficient(s),αthe values of (A) are as follows: when in useH 1<H 2When the temperature of the water is higher than the set temperature,α∈[0.08，0.14](ii) a When in useH 2<H 1When the temperature of the water is higher than the set temperature,α∈[0.24，0.32]；
when the substrate PAD2 is located on the other side of the two chips 3, the dimensional constraint condition of the corresponding dry film window 5 on the substrate PAD2 is as follows:
0.64L 01≤L 02≤0.72L 01
wherein,L 02when the substrate PAD2 is positioned at the other side of the two chips 3, the length dimension of the corresponding dry film opening window 5 on the substrate PAD2 is shown;
when the substrate PAD2 is located between the two chips 3, the dimensional constraints of the corresponding dry film window 5 on the substrate PAD2 are as follows:
0.53L 01≤L 03≤0.68L 01
wherein,L 03the length dimension of the corresponding dry film opening 5 on the substrate PAD2 is shown when the substrate PAD2 is located between the two chips 3.
The working principle and the effect of the technical scheme are as follows: the EMI filter structure based on the electromagnetic shielding film provided by this embodiment can form a thin metal protection layer and a substrate PAD while playing a role in isolating electromagnetic interference between chips by means of opening a dry film window and providing an EMI shielding layer and spraying a conductive epoxy resin. Meanwhile, in order to reduce the size of the filter to the maximum extent and effectively improve the stable signal connectivity among the functional circuits of each chip, the size of the filter is effectively reduced and the stability of the signal connection among the functional circuits of each chip is improved in a mode of limiting the size of the substrate PAD, so that the stability of the functional operation of the filter is effectively improved. Through the setting to the size constraint condition that the dry film windowed, can be at the film filter to various modes, when the thickness of organic dry film and base plate PAD thickness become any proportional relation, all can guarantee that EMI shielding layer can be with fastest speed and the most complete laminating degree with base plate PAD's functional surface carries out effective laminating, effectively prevents when organic dry film thickness is greater than base plate PAD thickness, and, when base plate PAD size is less, the window size of dry film windowing is not enough and leads to EMI shielding layer to lead to EMI shielding layer preparation speed to meet the end and with base plate PAD's functional surface laminating degree inadequately through the obstacle great that leads to of dry film windowing, and then leads to the not enough problem emergence of wave filter anti-electromagnetic interference ability.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (9)

1. An EMI filter structure based on an electromagnetic shielding film, characterized in that the EMI filter structure comprises a plurality of chip sets, a substrate (1) and a cover plate (7); a plurality of chip groups are arranged on the substrate (1); each chipset comprises a plurality of substrates PAD (2), two chips (3), an organic dry film (4), a dry film window (5) and an EMI shielding layer (6); the substrate PAD (2) and the chip (3) are arranged on the substrate (1); arranging an organic dry film (4) on the chip (3); a dry film window (5) is arranged on the organic dry film (4) on the substrate PAD (2); arranging an EMI shielding layer (6) on the chip (3), the organic dry film (4) and the dry film windowing (5); the cover plate (7) and the substrate (1) are bonded to form a packaging structure; wherein the size of the dry film fenestration (5) on the substrate PAD (2) is determined by a fenestration size constraint.
2. The EMI filter structure of claim 1, characterized in that the substrates PAD (2) are arranged on both sides of the two chips (3), respectively, and one substrate PAD (2) is arranged between the two chips (3).
3. The EMI filter structure of claim 1 or 2, wherein the windowing dimension constraint comprises:
when the substrate PAD (2) is positioned at one side of the whole two chips (3), the size constraint conditions of the corresponding dry film windowing (5) on the substrate PAD (2) are as follows:
Figure 600460DEST_PATH_IMAGE001
wherein,L 01represents the length dimension of the corresponding dry film window (5) on the substrate PAD (2) when the substrate PAD (2) is positioned at one side of the two chips (3);L s represents the length dimension of the upper surface of the substrate PAD (2) when the substrate PAD (2) is positioned at one side of the two chips (3);H 1andH 2respectively representing the thicknesses of the substrate PAD (2) and the organic dry film (4);αwhich is indicative of the adjustment coefficient(s),αthe values of (A) are as follows: when in useH 1<H 2When the temperature of the water is higher than the set temperature,α∈[0.08，0.14](ii) a When in useH 2<H 1When the temperature of the water is higher than the set temperature,α∈[0.24，0.32]。
4. the EMI filter structure of claim 1 or 2, wherein the windowing dimension constraint further comprises:
when the substrate PAD (2) is positioned on the other side of the whole two chips (3), the size constraint conditions of the corresponding dry film windowing (5) on the substrate PAD (2) are as follows:
0.64L 01≤L 02≤0.72L 01
wherein,L 02when the substrate PAD (2) is located on the two coresAnd when the other side of the sheet (3) is positioned, the length of a corresponding dry film window (5) on the substrate PAD (2) is measured.
5. The EMI filter structure of claim 1, wherein the windowing dimension constraint further comprises:
when the substrate PAD (2) is positioned between the two chips (3), the size constraint conditions of the corresponding dry film windowing (5) on the substrate PAD (2) are as follows:
0.53L 01≤L 03≤0.68L 01
wherein,L 03represents the length dimension of a corresponding dry film window (5) on the substrate PAD (2) when the substrate PAD (2) is positioned between the two chips (3).
6. The EMI filter structure of claim 1, wherein the dimensioning of the substrate PAD (2) comprises:
firstly, acquiring the length size and the width size of the chip (3);
secondly, determining the size of the substrate PAD (2) according to the proportional constraint condition and the length size and the width size of the chip (3), wherein the proportional constraint condition comprises the following steps:
when the substrate PAD (2) is positioned at one side of the chips (3), and the substrate PAD (2) is not arranged at a position between two adjacent chips (3), the size constraint conditions of the substrate PAD (2) are as follows:
Figure 48759DEST_PATH_IMAGE002
Figure 94076DEST_PATH_IMAGE003
wherein,L 1when said substrate PAD (2) is locatedThe length dimension corresponding to the long edge of the substrate PAD (2) is arranged on one side of the chip (3), and when the substrate PAD (2) is not arranged at the position between two adjacent chips (3);D 1represents the length dimension corresponding to the short side of the substrate PAD (2) when the substrate PAD (2) is positioned at one side of the chip (3) and the substrate PAD (2) is not arranged at the position between two adjacent chips (3);Lindicates the length dimension corresponding to the long side of the chip (3);Drepresents the length dimension corresponding to the short side of the chip (3);H 0a size-adjustment parameter is indicated that,H 0has a value range of 0.22D≤H 0≤0.94D(ii) a When the size of the chip (3) is satisfiedL=DWhen the utility model is used, the water is discharged,L 1with the constraint ofL 1≤0.23D；
When the substrate PAD (2) is positioned at one side of the chip (3), and the substrate PAD (2) is arranged at a position between two adjacent chips (3), the size constraint conditions of the substrate PAD (2) are as follows:
Figure 20443DEST_PATH_IMAGE004
Figure 365974DEST_PATH_IMAGE005
wherein,L 2when the substrate PAD (2) is positioned at one side of the chip (3), and the substrate PAD (2) is arranged at a position between two adjacent chips (3), the length dimension corresponding to the long edge of the substrate PAD (2) is represented;D 2represents the length dimension corresponding to the short side of the substrate PAD (2) when the substrate PAD (2) is positioned at one side of the chip (3) and the substrate PAD (2) is arranged at the position between two adjacent chips (3);Lindicates the length dimension corresponding to the long side of the chip (3);Da length dimension corresponding to a short side of the chip (3);H 0indicating size adjustmentThe parameters are set to be in a predetermined range,H 0has a value range of 0.22D≤H 0≤0.94D(ii) a When the size of the chip (3) is satisfiedL=DWhen the temperature of the water is higher than the set temperature,L 1with the constraint ofL 1≤0.23D。
7. A method of fabricating an EMI filter structure based on an electromagnetic shielding film, the method comprising:
step 1, preparing a chip (3) and a substrate PAD (2) on a substrate (1) by utilizing an SMT process; the substrate PAD (2) is arranged on two sides of the chip (3), and only one substrate PAD (2) is arranged in front of each two adjacent chips (3);
step 2, attaching an organic dry film (4) on the chip (3) and the substrate PAD (2);
step 3, punching and windowing on the corresponding organic dry film (4) on the substrate PAD (2) to form a dry film windowing (5);
step 4, forming an EMI shielding layer (6) on the substrate PAD (2) with the dry film window (5) and on the upper surface of the chip (3) corresponding to the substrate PAD (2) with the dry film window (5) in a CVD (chemical vapor deposition), PVD (physical vapor deposition) or sputtering mode;
and 5, bonding and packaging the cover plate (7) and the substrate (1) after the EMI shielding layer (6) is formed.
8. The manufacturing method according to claim 7, wherein each of the chip sets comprises a plurality of substrates PAD (2), two chips (3), an organic dry film (4), a dry film window (5), and an EMI shielding layer (6); the substrate PAD (2) and the chip (3) are arranged on the substrate (1); arranging an organic dry film (4) on the chip (3); a dry film window (5) is arranged on the organic dry film (4) on the substrate PAD (2); arranging an EMI shielding layer (6) on the chip (3), the organic dry film (4) and the dry film windowing (5); the cover plate (7) and the substrate (1) are bonded to form a packaging structure; wherein the size of the dry film fenestration (5) on the substrate PAD (2) is determined by a fenestration size constraint.
9. The method of manufacturing according to claim 8, wherein the windowing dimension constraint is as follows:
when the substrate PAD (2) is positioned at one side of the two chips (3), the size constraint conditions of the corresponding dry film windowing (5) on the substrate PAD (2) are as follows:
Figure 719595DEST_PATH_IMAGE006
wherein,L 01represents the length dimension of the corresponding dry film window (5) on the substrate PAD (2) when the substrate PAD (2) is positioned at one side of the two chips (3);L s represents the length dimension of the upper surface of the substrate PAD (2) when the substrate PAD (2) is positioned at one side of the two chips (3);H 1andH 2respectively representing the thicknesses of the substrate PAD (2) and the organic dry film (4);αwhich is indicative of the adjustment coefficient(s),αthe values of (A) are as follows: when in useH 1<H 2When the temperature of the water is higher than the set temperature,α∈[0.08，0.14](ii) a When in useH 2<H 1When the temperature of the water is higher than the set temperature,α∈[0.24，0.32]；
when the substrate PAD (2) is positioned at the other side of the two chips (3), the size constraint conditions of the corresponding dry film windowing (5) on the substrate PAD (2) are as follows:
0.64L 01≤L 02≤0.72L 01
wherein,L 02represents the length dimension of a corresponding dry film window (5) on the substrate PAD (2) when the substrate PAD (2) is positioned at the other side of the two chips (3);
when the substrate PAD (2) is positioned between the two chips (3), the size constraint conditions of the corresponding dry film windowing (5) on the substrate PAD (2) are as follows:
0.53L 01≤L 03≤0.68L 01
wherein,L 03represents the length dimension of a corresponding dry film window (5) on the substrate PAD (2) when the substrate PAD (2) is positioned between the two chips (3).
CN202210362633.1A 2022-04-08 2022-04-08 EMI filter structure based on electromagnetic shielding film and manufacturing method thereof Pending CN114496998A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102306645A (en) * 2011-09-29 2012-01-04 日月光半导体制造股份有限公司 Semiconductor packaging part possessing electromagnetic interference shielding membrane and manufacture method thereof
US20170186697A1 (en) * 2015-12-24 2017-06-29 Intel Corporation Electromagnetically shielded electronic devices and related systems and methods
CN206851157U (en) * 2017-06-29 2018-01-05 歌尔科技有限公司 A kind of welding resistance fenestration, printed circuit board (PCB) and electronic equipment
CN110535450A (en) * 2019-08-29 2019-12-03 无锡嘉硕科技有限公司 Surface acoustic wave filter ceramic package and method with special screen effect

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102306645A (en) * 2011-09-29 2012-01-04 日月光半导体制造股份有限公司 Semiconductor packaging part possessing electromagnetic interference shielding membrane and manufacture method thereof
US20170186697A1 (en) * 2015-12-24 2017-06-29 Intel Corporation Electromagnetically shielded electronic devices and related systems and methods
CN206851157U (en) * 2017-06-29 2018-01-05 歌尔科技有限公司 A kind of welding resistance fenestration, printed circuit board (PCB) and electronic equipment
CN110535450A (en) * 2019-08-29 2019-12-03 无锡嘉硕科技有限公司 Surface acoustic wave filter ceramic package and method with special screen effect

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Application publication date: 20220513