CN114496752A - Nano-gate structure and preparation method and application thereof - Google Patents
Nano-gate structure and preparation method and application thereof Download PDFInfo
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- CN114496752A CN114496752A CN202011269807.7A CN202011269807A CN114496752A CN 114496752 A CN114496752 A CN 114496752A CN 202011269807 A CN202011269807 A CN 202011269807A CN 114496752 A CN114496752 A CN 114496752A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a nano-gate structure which comprises a wafer (1), first dielectric isolation layers (3C), second dielectric isolation layers (4C), third dielectric isolation layers (5C) and fourth dielectric isolation layers (6), wherein the first dielectric isolation layers, the second dielectric isolation layers, the nano-gates (10), the second composite dielectric isolation layers, the nano-gates (10), the fifth dielectric isolation layers (7B), the nano-gates (10), the fifth dielectric isolation layers (7A), the sixth dielectric isolation layers (8C) and the seventh dielectric isolation layers (9) are horizontally arranged on the wafer at intervals, and the third composite isolation layers are formed by the first dielectric isolation layers (3C), the second dielectric isolation layers (4C), the third dielectric isolation layers and the fourth dielectric isolation layers (6). The method can simplify the preparation of the nano-scale gate, accurately control the long dimension of the gate, realize the preparation of a nano-gate device and further improve the performance of an electronic device.
Description
Technical Field
The invention relates to the field of semiconductor device preparation, not only relates to discrete devices, but also covers the field of integrated circuit preparation, and particularly relates to a method for preparing a nano gate by using a thin film deposition technology.
Background
In the field of integrated circuits, there is a constant trend toward higher integration levels, and new processes and techniques are continually developed to achieve smaller line width chips, and are approaching their physical limits.
The gate is the control terminal of the transistor and the gate size has a significant impact on the performance of the electronic device. At present, the processing of nanoscale gate length dimensions for devices becomes increasingly difficult. When an electronic device is prepared by using the existing photoetching technology, the gate length of the electronic device not only depends on the resolution of photoetching equipment, but also depends on various influence factors such as photoresist types, baking temperature, exposure dose, developing temperature and time in the photoetching process. This results in devices with gate length dimensions that are not easily controlled precisely, especially with gates of nanometer scale that are difficult to fabricate. At present, the mode of preparing the nano pattern is mainly to use an extreme ultraviolet lithography machine to combine with a FIN-FET process for preparation, the cost is high, the requirement on equipment is high, and the production is not easy to carry out.
In addition to the preparation of fine patterns having a size of 100nm or less using an extreme ultraviolet lithography machine, the preparation can be carried out by Electron Beam Lithography (EBL), and a fine structure having a wavelength of 10nm or less can be prepared by making the electron beam have a very short de Broglie wavelength. However, EBL is inefficient, has a strong proximity effect, has a high requirement for the stability of the device, and has a great problem in the developing and etching processes for electron beam exposure.
In order to maintain the continuous development of the integrated circuit industry, a new preparation method needs to be developed, so that the preparation of a gate with a nanoscale can be simplified, the long dimension of the gate can be accurately controlled, the preparation of a nano-pattern device can be realized, and the performance of an electronic device can be further improved.
Disclosure of Invention
The invention aims to provide a method for preparing a nano gate by combining a thin film deposition technology aiming at the defects of the existing means and the preparation and acquisition of the nano gate, so that the preparation process of a device is improved, and the preparation cost of the device is reduced.
Before setting forth the context of the present invention, the terms used herein are defined as follows:
the term "ALD" refers to: atom layer Deposition.
The term "CMP" refers to: chemical Mechanical Polishing.
The term "RIE" refers to: reaction ion etching.
The term "PECVD" refers to: plasma Enhanced Chemical Vapor Deposition, Plasma Enhanced Chemical Vapor Deposition.
The term "ICP-CVD" means: inductively Coupled Plasma Chemical Vapor Deposition.
The term "DUV lithography" refers to: deep ultraviolet lithography.
The term "EUV lithography" refers to: and (4) performing extreme ultraviolet lithography.
The term "HEMT" means: a high electron mobility transistor.
The term "NAND" refers to: not AND, computer flash memory device.
The term "PSG" refers to: phosphosilicate glass.
The term "ICP" refers to: inductively coupled plasma.
The term "MESFET" refers to: Metal-Semiconductor Field Effect Transistor (MOSFET).
The term "MOSFET" refers to: Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).
In order to achieve the above object, a first aspect of the present invention provides a nano-gate structure, which includes a wafer (1), and a first composite dielectric isolation layer formed by first dielectric isolation layers (3C) and second dielectric isolation layers (4C) horizontally arranged on the wafer at intervals, a third dielectric isolation layer (5C) and a fourth dielectric isolation layer (6), a nano-gate (10), a second composite dielectric isolation layer formed by the first dielectric isolation layer (3C) and the second dielectric isolation layer (4B), a nano-gate (10), a fifth dielectric isolation layer (7A), a sixth dielectric isolation layer (8C) and a third composite isolation layer formed by a seventh dielectric isolation layer (9);
and the line width of the nano gate is consistent with the thicknesses of the first dielectric isolation layer, the third dielectric isolation layer and the sixth dielectric isolation layer.
The nanogate structure according to the first aspect of the invention wherein the wafer material is selected from one or more of the following: silicon, gallium arsenic, silicon carbide, gallium nitride, gallium oxide, indium phosphorus, germanium, a wafer with a functional layer;
the material of the nano gate is selected from one or more of the following materials: gold, cobalt, aluminum, nickel, titanium, platinum, palladium, titanium nitride, tantalum nitride, tungsten, polysilicon, silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride; and/or
The material of the isolation layer is selected from one or more of the following: silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, photoresist, polyimide;
preferably, the line width of the nano-gate structure is 100nm or less, preferably 28nm or less, preferably 14nm or less, preferably 7nm or less, more preferably 5nm or less, and most preferably 3nm or less.
According to the nano-gate structure of the first aspect of the invention, the first, third and sixth dielectric isolation layers are made of the same material; and/or
The second, fourth, fifth and seventh medium isolating layers are made of the same material;
preferably, the etching selection ratio of the materials of the first dielectric isolation layer and the second dielectric isolation layer is larger than 1: 2.
A second aspect of the present invention provides a method for preparing a nanogate as described in the first aspect, the method comprising the steps of:
(a) providing a wafer required by process preparation;
(b) preparing an isolation layer material on a wafer; preferably, the thickness of the isolation layer is 5nm or more;
(c) preparing the isolation layer into a first graph structure;
(d) depositing a first medium isolation layer material to coat the first graph structure;
(e) depositing a second medium isolation layer material to coat the graph structure;
(f) depositing a third medium isolation layer material to coat the graph structure; preferably, the third dielectric spacer material is the same as the first dielectric spacer material;
(g) depositing a fourth medium isolation layer material, filling the groove and covering the surface; preferably, the material of the fourth dielectric isolation layer is the same as that of the second dielectric isolation layer;
(h) flattening the surface of the material obtained in the step (g) to obtain a structure in which an isolation layer material, a first medium isolation layer, a second composite medium isolation layer formed by overlapping the second medium isolation layer with the first medium isolation layer, a third composite medium isolation layer, a second composite medium isolation layer formed by overlapping the first medium isolation layer, and a first composite isolation layer formed by overlapping the fourth composite medium isolation layer, the third composite medium isolation layer and the second composite medium isolation layer are arranged alternately, so that the height of the residual medium isolation layer is the height of the isolation layer material initially deposited in the step (b);
(i) removing the isolation layer material obtained in step (b) to obtain a second pattern structure complementary to the first pattern structure;
(j) depositing a fifth medium isolating layer material to cover the second graph structure; preferably, the material of the fifth dielectric isolation layer is the same as that of the second dielectric isolation layer;
(k) depositing a sixth medium isolation layer material to cover the graph structure; preferably, the material of the sixth dielectric isolation layer is the same as the material of the first dielectric isolation layer;
(l) Depositing a seventh medium isolation layer material, filling the groove and covering the surface; preferably, the seventh dielectric spacer material is the same as the second dielectric spacer material;
(m) flattening the surface of the material obtained in the step (l) to obtain a structure with a first medium isolation layer, a second composite medium isolation layer formed by superposing the second medium isolation layer on the first medium isolation layer, a fourth composite medium isolation layer formed by superposing the first medium isolation layer, a first composite medium isolation layer formed by superposing the fourth medium isolation layer, the third medium isolation layer and the second medium isolation layer, a fifth composite medium isolation layer formed by superposing the sixth medium isolation layer and a structure with a seventh composite medium isolation layer and a sixth composite medium isolation layer arranged alternately;
(n) etching to remove the materials at the positions of the exposed first dielectric isolation layer, the exposed fourth composite dielectric isolation layer and the exposed fifth dielectric isolation layer to the surface of the wafer;
(o) depositing a nano-gate material, filling the trench and covering the surface;
and (p) removing the nano-gate material on the surface of the material obtained in the step (o) to obtain the nano-gate structure.
The preparation method according to the second aspect of the present invention, wherein, in steps (d) - (g), (j) - (l), (o), the deposition method is a thin film deposition technique, preferably, the thin film deposition technique is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering, spin coating and electron beam evaporation;
the manufacturing method according to the second aspect of the present invention, wherein the pattern manufacturing technique in step (c) is selected from one or more of: lithography, electron beam exposure, laser direct writing, and the like;
preferably, the lithographic technique is selected from one or more of: ultraviolet lithography, DUV lithography, EUV lithography, immersion lithography.
The production method according to the second aspect of the present invention, wherein the planarization method in the steps (h) and (m) is selected from one or more of: CMP techniques, PSG techniques (depositing PSG material in combination with heating to planarize the surface), ion selective bombardment (bombarding the surface with ion selectivity to planarize it), large area etching (including argon ion etching, RIE techniques, ICP techniques); preferably a CMP technique; .
The production method according to the second aspect of the present invention, wherein the method further comprises the steps of:
(q) processing the non-nano gate reserved area by adopting a conventional process to obtain a required mesa structure;
preferably, the conventional process is selected from one or more of the following: photolithography, wet etching, dry etching, and the like.
A third aspect of the present invention provides a semiconductor device comprising a nanogate as in the first aspect and/or a nanogate produced by the production method according to the second or third aspect;
preferably, the semiconductor device is selected from one or more of: integrated circuit, HEMT, MESFET, MOSFET, NAND Flash, NOR Flash, DRAM.
The invention relates to the field of semiconductor device preparation, not only relates to discrete devices, but also covers the field of integrated circuit preparation.
The invention provides a method for preparing a nano gate by combining a thin film deposition technology, which sequentially comprises the following structures from bottom to top:
wafers required by the process;
the first, second and third dielectric isolation layers form a first composite dielectric isolation layer, a nano-gate, a second composite dielectric isolation layer formed by the first and second dielectric isolation layers, a third composite isolation layer formed by the nano-gate, a fifth dielectric isolation layer, a sixth dielectric isolation layer and a seventh dielectric isolation layer; and flattening the surface of the material.
Preferably, the wafer includes, but is not limited to, a silicon substrate, a sapphire substrate, etc.;
preferably, the wafer refers to a wafer with a functional layer;
preferably, the material of the dielectric isolation layer includes, but is not limited to, silicon nitride, silicon oxide, and the like;
preferably, the first dielectric isolation layer is made of the same material as the third and sixth dielectric isolation layers;
preferably, the second dielectric isolation layer is made of the same material as the fourth, fifth and seventh dielectric isolation layers;
preferably, the etching selection ratio between the first dielectric isolation layer and the second dielectric isolation layer is greater than 1: 2;
preferably, the dielectric isolation layer is prepared by methods including but not limited to ALD, PECVD, ICP-CVD, etc.;
preferably, the material of the nano-gate includes, but is not limited to, gold, nickel, aluminum, polysilicon, titanium nitride, etc.;
preferably, the nano-grid is prepared by means of electron beam evaporation, sputtering, or the like.
The invention provides a method for preparing a nano gate by using a thin film deposition technology, which comprises the following steps:
providing a wafer with a flattened surface required by the process;
preparing an isolation layer material on the surface of the wafer;
preparing the isolation layer to obtain a first graph structure by utilizing a photoetching technology or other graph preparation technologies;
growing a first medium isolation layer material by using a thin film deposition technology to coat the graph structure;
growing a second medium isolation layer material by using a thin film deposition technology to coat the graph structure;
growing a third medium isolation layer material by using a thin film deposition technology to coat the graph structure;
growing a fourth medium isolation layer material by using a thin film deposition technology, filling the groove and covering the surface;
obtaining a flattened surface by utilizing a CMP technology, and simultaneously obtaining a structure in which an isolation layer material, a first medium isolation layer, a second composite medium isolation layer formed by overlapping the second medium isolation layer with the first medium isolation layer, a third composite isolation layer, a second composite isolation layer formed by overlapping the first medium isolation layer, a fourth composite isolation layer formed by overlapping the first medium isolation layer, and a first composite isolation layer formed by overlapping the fourth composite isolation layer, the third composite isolation layer and the second composite isolation layer with the first medium isolation layer are arranged at intervals;
removing the material of the isolation layer to obtain a second graph structure which is complementary with the first graph structure;
growing a fifth medium isolation layer material by using a thin film deposition technology to coat the graph structure;
growing a sixth medium isolation layer material by using a thin film deposition technology to coat the graph structure;
growing a seventh medium isolation layer material by using a thin film deposition technology, filling the groove and covering the surface;
obtaining a flattened surface by utilizing a CMP technology, and simultaneously obtaining a structure with alternately arranged structures of a first medium isolation layer, a second composite medium isolation layer formed by superposing the first medium isolation layer on the second medium isolation layer, a third composite medium isolation layer, a second composite medium isolation layer formed by superposing the first medium isolation layer, a first composite medium isolation layer formed by superposing the first medium isolation layer on the fourth composite medium isolation layer, the third composite medium isolation layer, the second composite medium isolation layer formed by superposing the first medium isolation layer, a fifth composite medium isolation layer formed by superposing the fifth medium isolation layer on the sixth composite medium isolation layer, and a third composite medium isolation layer formed by superposing the fifth medium isolation layer on the seventh composite medium isolation layer and the sixth composite medium isolation layer;
removing materials at the positions of the exposed first dielectric isolation layer, the exposed fourth composite dielectric isolation layer and the exposed fifth dielectric isolation layer to the surface of the wafer by using an etching technology;
depositing a nano gate material by using a material deposition technology, filling the groove and covering the surface;
removing the surface nano-gate material by using a CMP technology, and exposing the first, second and third dielectric isolation layers to form a structure in which a first composite dielectric isolation layer, a nano-gate, a second composite dielectric isolation layer formed by the first and second dielectric isolation layers, a nano-gate, a fifth dielectric isolation layer, a nano-gate, a fifth, sixth and seventh dielectric isolation layers are arranged alternately;
and carrying out subsequent processes of the required preparation structure.
The wafer not only comprises common substrate materials such as substrates of silicon, gallium arsenic, silicon carbide and the like, but also comprises a wafer with a functional layer;
depositing a medium isolation layer material on a wafer by using a thin film deposition technology, wherein the thin film deposition technology comprises but is not limited to ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering and other technologies;
the preparation technology of the isolation layer comprises but is not limited to ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering, spin coating and other technologies;
the dielectric isolation layer material includes but is not limited to silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride and the like;
the isolation layer material includes but is not limited to silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, photoresist, polyimide, etc.;
preparing a related graph structure on the isolation layer by utilizing a photoetching technology or other graph preparation technologies, wherein the photoetching technology comprises common controllable photoetching technologies such as ultraviolet photoetching, DUV photoetching, EUV photoetching and immersion photoetching;
preparing the isolation layer into a related graph structure by utilizing a photoetching technology or other graph preparation technologies, wherein the other graph preparation technologies comprise but are not limited to an electron beam exposure technology, a laser direct writing technology and other controllable graph preparation technologies;
growing a third dielectric isolation layer material and a sixth dielectric isolation layer material by using a thin film deposition technology, wherein the third dielectric isolation layer material and the sixth dielectric isolation layer material are the same as the first dielectric isolation layer material;
growing fourth, fifth and seventh dielectric isolation layer materials by using a thin film deposition technology, wherein the materials of the fourth, fifth and seventh dielectric isolation layers are consistent with the material of the second dielectric isolation layer;
the first dielectric isolation layer material and the second dielectric isolation layer material are grown by using a thin film deposition technology, the two materials should have a larger etching selection ratio, and the etching selection ratio of the materials of the first dielectric isolation layer and the second dielectric isolation layer is larger than 1: 2;
the method comprises the steps of depositing materials by using a material deposition technology, filling the grid grooves and covering the surface, wherein the deposition technology comprises but is not limited to electron beam evaporation, sputtering, chemical deposition and the like;
depositing a material by using a material deposition technology, filling the grid grooves and covering the surface, wherein the material comprises but is not limited to gold, aluminum, nickel, titanium, polysilicon, tungsten, titanium nitride and other materials;
in the process, the non-nano gate reserved area can be processed by a conventional process to obtain a required mesa structure;
the final line width is determined by the thicknesses of the first dielectric isolation layer, the third dielectric isolation layer and the sixth dielectric isolation layer, the thicknesses are not specifically specified, and the current processes of 100nm, 28nm, 14nm and 7nm can be covered, and even the processes of 5nm, 3nm and the like can be widened;
the process result is a nano-gate structure, and the subsequent process application of the nano-gate comprises but is not limited to microelectronic devices such as HEMT and the like and storage devices such as NAND and the like.
The method of the present invention may have, but is not limited to, the following beneficial effects:
the method can simplify the preparation of the nano-scale gate, accurately control the long dimension of the gate, realize the preparation of a nano-gate device and further improve the performance of an electronic device.
Drawings
Embodiments of the invention are described in detail below with reference to the attached drawing figures, wherein:
FIG. 1 shows a flow chart of embodiments 1-2 of the present invention.
FIG. 2 shows a schematic of the preparation of a barrier layer according to examples 1-2 of the present invention.
Fig. 3 shows a schematic diagram of the preparation of a patterned structure on an isolation layer according to embodiments 1-2 of the present invention.
Fig. 4 shows a schematic diagram of the patterned structure coated with the first dielectric isolation layer according to embodiments 1-2 of the present invention.
Fig. 5 shows a schematic diagram of the patterned structure coated with a second dielectric isolation layer according to embodiments 1-2 of the present invention.
Fig. 6 shows a schematic diagram of coating a patterned structure with a third dielectric isolation layer according to embodiments 1-2 of the present invention.
Fig. 7 shows a schematic view of filling a trench with a fourth dielectric isolation layer according to embodiments 1-2 of the present invention.
Fig. 8 shows a schematic view after surface planarization by CMP in examples 1-2 of the present invention.
Fig. 9 shows a schematic diagram after removing the isolation layer according to embodiment 1-2 of the present invention.
Fig. 10 shows a schematic diagram of the patterned structure coated with a fifth dielectric isolation layer according to embodiments 1-2 of the present invention.
Fig. 11 shows a schematic diagram of a patterned structure coated with a sixth dielectric isolation layer according to embodiments 1-2 of the present invention.
Fig. 12 shows a schematic view of filling a trench with a seventh dielectric isolation layer according to embodiments 1-2 of the present invention.
Fig. 13 shows a schematic view after surface planarization by CMP in examples 1-2 of the present invention.
Fig. 14 is a schematic diagram illustrating that materials at the positions of the first dielectric isolation layer, the fourth composite dielectric isolation layer, and the fifth dielectric isolation layer are removed to the surface of the wafer by using an etching technique in embodiment 1-2 of the present invention.
Fig. 15 shows a schematic diagram of the gate electrode prepared by the material deposition technology in the embodiments 1-2 of the present invention.
Fig. 16 shows a schematic diagram of removing surface gate material by CMP technique according to embodiments 1-2 of the present invention.
Description of reference numerals:
1. a wafer; 2. isolation layer material; 3A, 3B, 3C, a first dielectric isolation layer material; 4A, 4B, 4C second dielectric isolation layer material; 5A, 5B, 5C and a third medium isolation layer material; 6. a fourth dielectric isolation layer material; 7A, 7B and 7C of a fifth dielectric isolation layer material; 8A, 8B, 8C and a sixth dielectric isolation layer material; 9. a seventh dielectric isolation layer material; 10. a gate material.
Detailed Description
The invention is further illustrated by the following specific examples, which, however, are to be construed as merely illustrative, and not limitative of the remainder of the disclosure in any way whatsoever.
This section generally describes the materials used in the testing of the present invention, as well as the testing methods. Although many materials and methods of operation are known in the art for the purpose of carrying out the invention, the invention is nevertheless described herein in as detail as possible. It will be apparent to those skilled in the art that the materials and methods of operation used in the present invention are well within the skill of the art, provided that they are not specifically illustrated.
Example 1
This example illustrates the method of fabricating a nanogate using thin film deposition techniques according to the invention.
The specific process is shown in fig. 1, and comprises the following steps:
s100: providing a wafer 1 required by process preparation;
s200: preparing an isolating layer material 2;
s300: preparing the isolation layer 2 into a strip-shaped graph structure;
s400: depositing a first medium isolating layer material 3 which is divided into 3A, 3B and 3C according to different deposition positions;
s500: depositing a second medium isolating layer material 4 which is divided into 4A, 4B and 4C according to different deposition positions;
s600: depositing a third medium isolating layer material 5 which is divided into 5A, 5B and 5C according to different deposition positions;
s700: depositing a fourth medium isolating layer material 6, and filling the groove;
s800: flattening the surface of the material to obtain an isolation layer material, a first medium isolation layer, a second composite medium isolation layer formed by overlapping the second medium isolation layer with the first medium isolation layer, a third composite isolation layer, a second composite isolation layer formed by overlapping the first medium isolation layer, a fourth composite isolation layer formed by overlapping the first medium isolation layer, and a structure in which the first composite isolation layers formed by overlapping the fourth, third and second first medium isolation layers are arranged at intervals;
s900: removing the material of the isolation layer;
s1000: depositing a fifth medium isolating layer material 7 which is divided into 7A, 7B and 7C according to different deposition positions;
s1100: depositing a sixth medium isolating layer material 8 which is divided into 8A, 8B and 8C according to different deposition positions;
s1200: depositing a seventh medium isolating layer material 9 and filling the groove;
s1300: flattening the surface of the material to obtain a structure with a first medium isolation layer, a second composite medium isolation layer formed by superposing the second medium isolation layer on the first medium isolation layer, a fourth composite medium isolation layer formed by superposing the first medium isolation layer, a first composite medium isolation layer formed by superposing the first medium isolation layer, a fourth composite medium isolation layer, a third composite medium isolation layer and the second composite medium isolation layer, a fifth composite medium isolation layer formed by superposing the fifth medium isolation layer, and a structure with alternate arrangements of structures of the third composite medium isolation layer formed by superposing the fifth medium isolation layer;
s1400: etching to remove the materials at the positions of the exposed first dielectric isolation layer, the exposed third dielectric isolation layer and the exposed sixth dielectric isolation layer to the surface of the wafer;
s1500: depositing a gate material 10;
s1600: and (5) flattening the surface of the material, and removing the gate material 10 on the surface.
In this embodiment, the material of the wafer 1 in S100 may be selected from one or more of the following: silicon, gallium arsenide, silicon carbide, gallium nitride, gallium oxide, indium phosphide, germanium, and wafers having functional layers.
In a preferred embodiment, the material of the wafer 1 is a silicon substrate with a (001) crystal orientation.
S200, the preparation technology of the isolation layer is selected from one or more of the following technologies: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering, spin-coating, and the like.
The material of the dielectric isolation layer in this embodiment is selected from one or more of the following: silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, photoresist, polyimide, and the like.
In a preferred embodiment, the photoresist material 2 of the spacer layer material 1um is spin coated using a spin coating technique, as shown in fig. 2.
The pattern preparation technique in S300 is selected from one or more of: lithography, electron beam exposure, laser direct writing; the lithographic technique is selected from one or more of: ultraviolet lithography, DUV lithography, EUV lithography, immersion lithography.
In a preferred embodiment, the line width and the pitch are determined by the design requirements and the subsequent process design using photolithography in combination with a photolithography mask having a line width of 190nm, a pitch of 230nm, and a period of 420 nm. And carrying out exposure and development treatment by combining a photoetching technology to obtain a corresponding photoresist pattern structure. As shown in fig. 3.
The deposition method in S400 is a thin film deposition technique, and the thin film deposition technique is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering.
In a preferred scheme, the ALD technology is utilized to grow 20nm first dielectric isolation layer materials 3A, 3B and 3C, the deposition temperature of silicon dioxide is 200 ℃, the adopted precursor materials are aminosilane and water vapor, the deposition time is 1h, and the surface pattern structure is coated, as shown in figure 4.
The deposition method in S500 is a thin film deposition technique, and the thin film deposition technique is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering.
In a preferred embodiment, the 50nm thick second dielectric isolation layer material 4A, 4B, 4C is deposited by using ALD technique, the deposition temperature of alumina is 300 ℃, the precursor materials used are trimethylaluminum and water vapor, and the deposition time is 2h, as shown in fig. 5.
The deposition method in S600 is a thin film deposition technique, and the thin film deposition technique is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering.
In a preferred scheme, the ALD technology is utilized to grow the third dielectric isolation layer materials 5A, 5B and 5C with the thickness of 20nm, the deposition temperature of silicon dioxide is 200 ℃, the adopted precursor materials are aminosilane and water vapor, the deposition time is 1h, and the surface pattern structure is coated, as shown in FIG. 6.
The deposition method in S700 is a thin film deposition technique, and the thin film deposition technique is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering.
In a preferred scheme, the fourth dielectric isolation layer material 6A, 6B, 6C with the thickness of 1um is deposited by using the CVD technique, the deposition temperature of alumina is 380 ℃, the adopted precursor materials are trimethylaluminum and water vapor, and the deposition time is 30min, as shown in fig. 7.
The planarization method in S800 is selected from one or more of the following: CMP technique, PSG technique, ion selective bombardment, and large-area etching.
In a preferred embodiment, the surface is planarized using a CMP technique: polishing treatment is carried out by combining a polishing machine with alumina polishing solution, the polishing rate is 10nm/min, the height of the residual medium isolation layer is 1um which is the height of the initially deposited isolation layer material 2 photoresist, and the surface is exposed with the alternately arranged patterns of alumina, silicon oxide and alumina, as shown in fig. 8.
The method for removing the isolation layer material in S900 includes wet etching and dry etching.
In a preferred scheme, the isolating layer 2 is removed by soaking in acetone for 3 minutes and wiping; as shown in fig. 9.
The deposition method in S1000 is a thin film deposition technique, and the thin film deposition technique is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering.
In a preferred embodiment, the deposition temperature of the alumina is 300 ℃, the precursor materials of trimethyl aluminum and water vapor are adopted, and the deposition time is 2h, which is shown in fig. 10, by using the ALD technique to deposit the fifth dielectric isolation layer material 7A, 7B, 7C with the thickness of 50 nm.
The deposition method in S1100 is a thin film deposition technique selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering.
In a preferred scheme, the ALD technology is used to grow the sixth dielectric isolation layer material 8A, 8B, 8C with a thickness of 20nm at a deposition temperature of 200 ℃, the precursor materials used are aminosilane and water vapor, the deposition time is 1h, and the surface pattern structure is coated, as shown in fig. 11.
The deposition method in S1200 is a thin film deposition technique, and the thin film deposition technique is selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering.
In a preferred approach, a 1um thick seventh dielectric spacer material 9 alumina material is deposited using CVD techniques to fill the patterned trenches, as shown in fig. 12.
The planarization method in S1300 is selected from one or more of the following: CMP technique, PSG technique, ion selective bombardment, and large-area etching.
In a preferred embodiment, the surface is planarized using a CMP technique: polishing treatment is performed by using a polishing machine in combination with an alumina polishing solution, the polishing rate is 10nm/min, so that the height of the residual dielectric isolation layer is equal to the height of the initially deposited isolation layer material 2, namely 1um, as shown in fig. 13.
The etching method in S1400 is selected from one or more of the following: RIE, ICP.
In a preferred scheme, etching to remove the exposed materials at the positions of the first dielectric isolation layer 3B, the third dielectric isolation layer 5B and the sixth dielectric isolation layer 8B to the surface of the wafer by RIE etching technology; with CHF3And O2As etching gas, the power was set to 150w and the flow rates were CHF, respectively3:25sccm/O225sccm, and the etching time is 25min, to obtain a trench structure with a width of 20nm, as shown in FIG. 14.
The deposition method in S1500 is selected from one or more of: electron beam evaporation techniques, sputtering, ALD, etc.
The material of the grid electrode in the S1500 is selected from one or more of the following materials: gold, aluminum, nickel, titanium, germanium, platinum, chromium, polysilicon, titanium nitride, and the like.
In a preferred embodiment, the aluminum metal is deposited by electron beam evaporation: and evaporating the metal aluminum at the rate of 1A/s by using an electron beam evaporation device, filling the grooves generated by etching, and realizing full coverage of the surface layer, as shown in FIG. 15.
The planarization method in S1600 is selected from one or more of the following: CMP techniques, PSG techniques, ion selective bombardment.
In a preferred embodiment, the surface is planarized using CMP techniques: and (4) polishing by using a polishing machine and combining with the metal aluminum polishing solution, wherein the polishing rate is 10nm/min, and removing the metal aluminum 10 of the grid metal on the surface. Finally, a device structure with aluminum metal as a gate is obtained, as shown in fig. 16.
FIG. 2 is a schematic diagram of spin coating a photoresist on a silicon surface in this embodiment; FIG. 3 corresponds to a schematic diagram of the patterned structure on the photoresist in this example; FIG. 4 corresponds to a schematic view of a structure of a blanket pattern of grown silicon dioxide in the present invention; FIG. 5 corresponds to a schematic view of a deposited alumina material covered silica structure of the present invention; FIG. 6 corresponds to a schematic view of a structure of the present invention in which a silicon dioxide material is deposited over aluminum oxide; FIG. 7 corresponds to a schematic view after depositing alumina to fully cover the trench according to the present invention; FIG. 8 corresponds to a schematic representation of the present invention after surface planarization by CMP; FIG. 9 corresponds to the schematic after removal of the photoresist; FIG. 10 corresponds to a schematic view of a deposited alumina material covered silica structure of the present invention; FIG. 11 corresponds to a schematic view of a structure of the present invention deposited silica material overlying alumina; FIG. 12 corresponds to a schematic view after depositing alumina to fully cover the trench according to the present invention; FIG. 13 corresponds to a schematic representation of the present invention after surface planarization by CMP; FIG. 14 corresponds to the schematic illustration after the exposed silicon dioxide is etched away; FIG. 15 corresponds to a schematic diagram after depositing aluminum metal using electron beam; FIG. 16 is a schematic diagram of the present invention using CMP to planarize the surface and remove the aluminum metal on the surface.
Example 2
The embodiment of the invention relates to a method for preparing a nano gate by using a thin film deposition technology, and the specific flow is shown in figure 1, and the method comprises the following steps:
s100: providing a wafer 1 required by process preparation;
s200: preparing an isolating layer material 2;
s300: preparing the isolation layer 2 into a strip-shaped graph structure;
s400: depositing a first medium isolating layer material 3 which is divided into 3A, 3B and 3C according to different deposition positions;
s500: depositing a second medium isolating layer material 4 which is divided into 4A, 4B and 4C according to different deposition positions;
s600: depositing a third medium isolating layer material 5 which is divided into 5A, 5B and 5C according to different deposition positions;
s700: depositing a fourth medium isolating layer material 6, and filling the groove;
s800: flattening the surface of the material to obtain an isolation layer material, a first medium isolation layer, a second composite medium isolation layer formed by overlapping the second medium isolation layer with the first medium isolation layer, a third composite isolation layer, a second composite isolation layer formed by overlapping the first medium isolation layer, a fourth composite isolation layer formed by overlapping the first medium isolation layer, and a structure in which the first composite isolation layers formed by overlapping the fourth, third and second first medium isolation layers are arranged at intervals;
s900: removing the material of the isolation layer;
s1000: depositing a fifth medium isolating layer material 7 which is divided into 7A, 7B and 7C according to different deposition positions;
s1100: depositing a sixth medium isolating layer material 8 which is divided into 8A, 8B and 8C according to different deposition positions;
s1200: depositing a seventh medium isolating layer material 9, and filling the groove;
s1300: flattening the surface of the material to obtain a structure with a first medium isolation layer, a second composite medium isolation layer formed by superposing the second medium isolation layer on the first medium isolation layer, a fourth composite medium isolation layer formed by superposing the first medium isolation layer, a first composite medium isolation layer formed by superposing the first medium isolation layer, a fourth composite medium isolation layer, a third composite medium isolation layer and the second composite medium isolation layer, a fifth composite medium isolation layer formed by superposing the fifth medium isolation layer, and a structure with alternate arrangements of structures of the third composite medium isolation layer formed by superposing the fifth medium isolation layer;
s1400: etching to remove the materials at the positions of the exposed first dielectric isolation layer, the exposed third dielectric isolation layer and the exposed sixth dielectric isolation layer to the surface of the wafer;
s1500: depositing a gate material 10;
s1600: and (5) flattening the surface of the material, and removing the gate material 10 on the surface.
In this embodiment, a 100nm thick photoresist of the isolation layer material 2 is first spin-coated on a silicon substrate in a (001) crystal orientation of the provided wafer 1 by using a spin-coating technique. As shown in fig. 2.
Then, by utilizing the photoetching technology, carrying out exposure and development treatment by combining a photoetching plate with the line width of 40nm, the interval of 50nm and the period of 90nm, wherein the exposure time is 4s, and the development time is 30s, so as to obtain a corresponding photoresist pattern structure; as shown in fig. 3. The line width and spacing are selected based on design requirements and subsequent process design. Then, depositing 5nm of first dielectric isolation layer materials 3A, 3B and 3C silicon oxide materials by using an ALD technology; the deposition temperature is 200 ℃, the adopted precursor materials are aminosilane and water vapor, and the deposition time is 0.5h, as shown in figure 4;
then, growing 10nm of second dielectric isolation layer materials 4A, 4B and 4C of silicon nitride by using an ALD (atomic layer deposition) technology, wherein the deposition temperature is 200 ℃, the adopted precursor materials are aminosilane and nitrogen, the deposition time is 1h, and the surface pattern structure is coated, as shown in figure 5;
then depositing 5nm of third dielectric isolation layer materials 5A, 5B and 5C silicon oxide materials by using an ALD technology; the deposition temperature is 200 ℃, the adopted precursor materials are aminosilane and water vapor, and the deposition time is 0.5h, as shown in figure 6;
then, by using a CVD technology, depositing a fourth dielectric isolation layer material 6 with the thickness of 100nm, namely a silicon nitride material, at the deposition temperature of 380 ℃, adopting aminosilane and water vapor as precursor materials, wherein the deposition time is 3min, and filling the grooves of the graph, as shown in FIG. 7;
then, surface planarization is carried out by utilizing a CMP technology: polishing treatment is carried out by combining a polishing machine with polishing liquid, the polishing rate is 2nm/min, the height of the residual medium isolation layer is the height of the photoresist of the isolation layer material 2 which is initially spun, namely 100nm, and the surface is exposed with silicon oxide, silicon nitride and a graph which is arranged among the silicon oxide, as shown in fig. 8;
then removing the photoresist by using acetone to obtain a new pattern structure, as shown in fig. 9;
then growing 10nm of fifth medium isolation layer materials 7A, 7B and 7C of silicon nitride by using an ALD technology, wherein the deposition temperature is 200 ℃, the adopted precursor materials are aminosilane and nitrogen, the deposition time is 1h, and the surface pattern structure is coated, as shown in FIG. 10;
then depositing 5nm of sixth dielectric isolation layer materials 8A, 8B and 8C silicon oxide materials by using an ALD technology; the deposition temperature is 200 ℃, the adopted precursor materials are aminosilane and water vapor, and the deposition time is 0.5h, as shown in figure 11;
then, depositing a seventh dielectric isolation layer material 9 with the thickness of 100nm by using a CVD technology, wherein the deposition temperature of the silicon nitride material is 380 ℃, the adopted precursor materials are aminosilane and water vapor, the deposition time is 3min, and the groove of the graph is filled, as shown in FIG. 12;
then, surface planarization is carried out by utilizing a CMP technology: polishing treatment is carried out by combining a polishing machine with polishing liquid, the polishing rate is 2nm/min, the height of the residual medium isolation layer is the height of the initial spin-on photoresist, namely 100nm, and the surface is exposed with silicon oxide, silicon nitride and a graph in which the silicon oxide is arranged alternately, as shown in fig. 13;
followed by RIE etching using CHF2Etching the silicon nitride and silicon oxide at the positions of the exposed first dielectric isolation layer material 3B, the exposed third dielectric isolation layer 5B and the exposed sixth dielectric isolation layer 8B as etching gas by adopting CHF2As etching gas, the power was set to 150w and the flow rates were CHF, respectively225sccm, and etching time is 3min, to obtain a groove structure with a width of 5nm, as shown in FIG. 14;
then, depositing metal aluminum by using an electron beam evaporation technology at a rate of 1A/s, filling the groove generated by etching, and realizing full coverage of the surface layer, as shown in FIG. 15;
finally, the surface is planarized by using a CMP technology: and (4) polishing by using a polishing machine and combining with the metal aluminum polishing solution, wherein the polishing rate is 2nm/min, and removing the metal aluminum on the surface. Finally, a device structure with the gate metal 5, metal aluminum, as the gate is obtained, as shown in fig. 16.
FIG. 2 is a schematic diagram of spin coating a photoresist on a silicon surface in this embodiment; FIG. 3 corresponds to a schematic diagram of the patterned structure on the photoresist in this example; FIG. 4 corresponds to a schematic view of a structure of a blanket pattern of grown silicon dioxide in the present invention; FIG. 5 is a schematic view of a deposited silicon nitride material overlying a silicon oxide structure in accordance with the present invention; FIG. 6 corresponds to a schematic view of a structure of the present invention deposited silicon dioxide material overlying silicon nitride; FIG. 7 corresponds to a schematic view after depositing a silicon nitride full coverage trench according to the present invention; FIG. 8 corresponds to a schematic representation of the present invention after surface planarization by CMP; FIG. 9 corresponds to the schematic after removal of the photoresist; FIG. 10 corresponds to a schematic view of a deposited silicon nitride material overlying a silicon oxide structure in accordance with the present invention; FIG. 11 corresponds to a schematic view of a structure of the present invention deposited silicon dioxide material overlying silicon nitride; FIG. 12 corresponds to the present invention after depositing a silicon nitride full coverage trench; FIG. 13 corresponds to a schematic representation of the present invention after surface planarization by CMP; FIG. 14 corresponds to the schematic illustration after the exposed silicon dioxide is etched away; FIG. 15 corresponds to a schematic diagram after deposition of aluminum metal using electron beams; FIG. 16 is a schematic diagram of the present invention using CMP to planarize the surface and remove the aluminum metal on the surface.
The etching selection ratio of the materials of the first dielectric isolation layer and the second dielectric isolation layer is more than 1: 2.
although the present invention has been described to a certain extent, it is apparent that appropriate changes in the respective conditions may be made without departing from the spirit and scope of the present invention. It is to be understood that the invention is not limited to the described embodiments, but is to be accorded the scope consistent with the claims, including equivalents of each element described.
Claims (10)
1. A nano-gate structure is characterized by comprising a wafer (1), and a first composite dielectric isolation layer formed by first dielectric isolation layers (3C), second dielectric isolation layers (4C), third dielectric isolation layers (5C) and a fourth dielectric isolation layer (6) which are horizontally arranged on the wafer at intervals, a nano-gate (10), a second composite dielectric isolation layer formed by the first dielectric isolation layers (3C) and the second dielectric isolation layers (4B), a nano-gate (10), a fifth dielectric isolation layer (7A), a sixth dielectric isolation layer (8C) and a seventh dielectric isolation layer (9);
and the line width of the nano gate is consistent with the thicknesses of the first dielectric isolation layer, the third dielectric isolation layer and the sixth dielectric isolation layer.
2. The nanogate structure of claim 1 wherein the wafer material is selected from one or more of the group consisting of: silicon, gallium arsenic, silicon carbide, gallium nitride, gallium oxide, indium phosphorus, germanium, a wafer with a functional layer;
the material of the nano gate is selected from one or more of the following materials: gold, cobalt, aluminum, nickel, titanium, platinum, palladium, titanium nitride, tantalum nitride, tungsten, polysilicon, silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride; and/or
The material of the isolation layer is selected from one or more of the following: silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum nitride, zirconium nitride, hafnium nitride, nickel oxide, gallium oxide, niobium oxide, zirconium nitride, photoresist, polyimide;
preferably, the line width of the nano-gate structure is 100nm or less, preferably 28nm or less, preferably 14nm or less, preferably 7nm or less, more preferably 5nm or less, and most preferably 3nm or less.
3. The nanogate structure of claim 1 or 2 wherein the first, third and sixth dielectric spacers are of the same material; and/or
The second, fourth, fifth and seventh medium isolating layers are made of the same material;
preferably, the etching selection ratio of the materials of the first dielectric isolation layer and the second dielectric isolation layer is larger than 1: 2.
4. A method of fabricating a nanogate structure according to any one of claims 1 to 3, comprising the steps of:
(a) providing a wafer required by process preparation;
(b) preparing an isolation layer material on a wafer; preferably, the thickness of the isolation layer is 5nm or more;
(c) preparing the isolation layer into a first graph structure;
(d) depositing a first medium isolation layer material to coat the first graph structure;
(e) depositing a second medium isolation layer material to coat the graph structure;
(f) depositing a third medium isolation layer material to coat the graph structure; preferably, the third dielectric spacer material is the same as the first dielectric spacer material;
(g) depositing a fourth medium isolation layer material, filling the groove and covering the surface; preferably, the material of the fourth dielectric isolation layer is the same as that of the second dielectric isolation layer;
(h) flattening the surface of the material obtained in the step (g) to obtain a structure in which an isolation layer material, a first dielectric isolation layer, a second composite dielectric isolation layer formed by superposing a second dielectric isolation layer on a first dielectric isolation layer, a third composite isolation layer, a second composite isolation layer formed by superposing a first dielectric isolation layer, and a first composite isolation layer formed by superposing a fourth composite isolation layer, a third composite isolation layer and a second composite isolation layer are arranged alternately, so that the height of the residual dielectric isolation layer is the height of the isolation layer material initially deposited in the step (b);
(i) removing the isolation layer material obtained in step (b) to obtain a second pattern structure complementary to the first pattern structure;
(j) depositing a fifth medium isolating layer material to cover the second graph structure; preferably, the material of the fifth dielectric isolation layer is the same as that of the second dielectric isolation layer;
(k) depositing a sixth medium isolation layer material to cover the graph structure; preferably, the material of the sixth dielectric isolation layer is the same as the material of the first dielectric isolation layer;
(l) Depositing a seventh medium isolation layer material, filling the groove and covering the surface; preferably, the seventh dielectric spacer material is the same as the second dielectric spacer material;
(m) flattening the surface of the material obtained in the step (l) to obtain a structure with a first medium isolation layer, a second composite medium isolation layer formed by superposing the second medium isolation layer on the first medium isolation layer, a fourth composite medium isolation layer formed by superposing the first medium isolation layer, a first composite medium isolation layer formed by superposing the fourth medium isolation layer, the third medium isolation layer and the second medium isolation layer, a fifth composite medium isolation layer formed by superposing the sixth medium isolation layer and a structure with a seventh composite medium isolation layer and a sixth composite medium isolation layer arranged alternately;
(n) etching to remove the materials at the positions of the exposed first dielectric isolation layer, the exposed fourth composite dielectric isolation layer and the exposed fifth dielectric isolation layer to the surface of the wafer;
(o) depositing a nano-gate material, filling the trench and covering the surface;
and (p) removing the nano-gate material on the surface of the material obtained in the step (o) to obtain the nano-gate structure.
5. The method according to claim 4, wherein the material deposition method is a thin film deposition technique, preferably selected from one or more of the following: ALD, PECVD, ICP-CVD, reactive ion magnetron sputtering, spin coating, electron beam evaporation.
6. The method according to claim 4 or 5, wherein the pattern structure in step (c) has a spacing between patterns of not less than 2 times the thickness of the first dielectric spacer layer.
7. The method according to any of claims 4 to 6, wherein the pattern preparation technique in step (c) of argon ion etching, RIE technique, ICP technique is selected from one or more of the following: lithography, electron beam exposure, laser direct writing;
preferably, the lithographic technique is selected from one or more of: ultraviolet lithography, DUV lithography, EUV lithography, immersion lithography.
8. The method according to any one of claims 4 to 7, wherein the planarization method in steps (h), (m) is selected from one or more of the following: CMP technology, PSG technology, ion selective bombardment, argon ion etching, RIE technology and ICP technology; preferably a CMP technique; and/or
The process for removing the surface nano gate material in the step (p) is selected from one or more of the following processes: CMP technology, PSG technology, ion selective bombardment, argon ion etching, RIE technology and ICP technology; CMP techniques are preferred.
9. The method according to any one of claims 4 to 8, characterized in that it further comprises the steps of:
(q) processing the non-nano gate reserved area by adopting a conventional process to obtain a required mesa structure;
preferably, the conventional process is selected from one or more of the following: photolithography, wet etching, dry etching, and the like.
10. A semiconductor device comprising a nanogate according to any one of claims 1 to 3 and/or a nanogate produced by the production method according to any one of claims 4 to 8;
preferably, the semiconductor device is selected from one or more of: integrated circuit, HEMT, MESFET, MOSFET, NAND Flash, NOR Flash, DRAM.
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