CN114496734A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN114496734A
CN114496734A CN202011153434.7A CN202011153434A CN114496734A CN 114496734 A CN114496734 A CN 114496734A CN 202011153434 A CN202011153434 A CN 202011153434A CN 114496734 A CN114496734 A CN 114496734A
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China
Prior art keywords
layer
trench
forming
barrier layer
substrate
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Chinese (zh)
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徐锦心
王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202011153434.7A priority Critical patent/CN114496734A/en
Publication of CN114496734A publication Critical patent/CN114496734A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The embodiment of the invention provides a method for forming a semiconductor structure, which comprises the following steps: providing a substrate; forming a patterned barrier layer on the substrate, wherein the barrier layer covers the second trench region and the isolation region and exposes the first trench region; forming a patterned first mask layer, wherein the first mask layer exposes the substrate of the first trench region, the second trench region and the barrier layer of the isolation region; etching the substrate by taking the barrier layer and the first mask layer as masks to form a first groove; forming a second mask layer which covers the first groove and the isolation region and exposes the second groove region; and etching the substrate by taking the first mask layer and the second mask layer as masks to form a second groove. The method reduces the process complexity and the process precision of the semiconductor structure forming process.

Description

Method for forming semiconductor structure
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
In semiconductor manufacturing, integrated circuit feature sizes continue to decrease with the trend toward very large scale integrated circuits. Especially, the characteristic dimension is rapidly developed towards the direction of micron and nanometer, and the line width of the pattern is also getting thinner and thinner, which puts higher requirements on the semiconductor process.
In the subsequent processing of integrated circuits, the transfer of the integrated circuit pattern is usually realized in a photolithography (Lithograph) technique. However, the finer the line width of the integrated circuit pattern, the higher the process requirements for the photolithography technique. When the existing photoetching technology cannot meet the corresponding process requirements, a series of problems are easy to generate, so that the existing semiconductor device is complex in forming process and high in process precision requirement.
Disclosure of Invention
The embodiment of the invention provides a method for forming a semiconductor structure, which reduces the process complexity and process precision of a semiconductor structure forming process.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including:
providing a substrate, wherein the substrate comprises a first groove region and a second groove region which are arranged in a staggered mode along a first direction, and an isolation region located between the first groove region and the second groove region;
forming a patterned barrier layer on the substrate, wherein the barrier layer covers the second trench region and the isolation region and exposes the first trench region;
forming a patterned first mask layer, wherein the first mask layer exposes the substrate of the first trench region, the second trench region and the barrier layer of the isolation region;
etching the substrate by taking the barrier layer and the first mask layer as masks to form a first groove;
forming a second mask layer covering the first groove and the isolation region and exposing the second groove region;
and etching the substrate by taking the first mask layer and the second mask layer as masks to form a second groove.
Optionally, the forming a patterned barrier layer on the substrate includes:
forming a patterned barrier layer body covering the second trench region, exposing the isolation region and the first trench region;
forming a barrier layer side wall on the side wall of the barrier layer main body, wherein the barrier layer side wall covers the isolation region;
and taking the barrier layer main body and the barrier layer side wall as the barrier layer.
Optionally, the forming a second mask layer covering the first trench and the isolation region and exposing the second trench region includes:
forming a sacrificial layer covering the first trench;
and removing the barrier layer main body exposed by the first mask layer, and taking the sacrificial layer and the residual barrier layer as second mask layers.
Optionally, the forming a patterned barrier layer main body includes:
forming a barrier body material layer covering the substrate surface;
forming a patterned photoresist layer on the barrier main material layer;
and patterning the barrier main body material layer by taking the photoresist layer as a mask to form the barrier main body.
Optionally, forming a barrier layer sidewall on the sidewall of the barrier layer main body includes:
forming a side wall material layer which conformally covers the barrier layer main body;
and removing the side wall material layers on the top of the barrier layer main body and the top of the substrate, and taking the residual side wall material layers as the barrier layer side walls.
Optionally, in the step of forming a sacrificial layer covering the first trench, a top surface of the sacrificial layer is not higher than a top surface of the barrier layer.
Optionally, after the forming the second trench, the method further includes:
removing the first mask layer and the second mask layer, and exposing the substrate and a first groove and a second groove which are positioned on the substrate;
and forming a conductive interconnection layer in the first groove and the second groove, wherein the top surface of the conductive interconnection layer is not higher than the surface of the substrate.
Optionally, the substrate includes a plurality of first trench regions and a plurality of second trench regions that are parallel and staggered along a first direction, where in a second direction, the first trench regions and the second trench regions are staggered, and the second direction is perpendicular to the first direction.
Optionally, in the first direction, the first trench region, the second trench region, and the isolation region in the same row are used as one trench region, wherein a trench isolation region is further included between adjacent trench regions, and in the step of forming the patterned barrier layer, the barrier layer further covers at least part of the trench isolation region of the substrate.
Optionally, the forming a second mask layer covering the first trench and the isolation region and exposing the second trench region includes:
forming a second mask material layer covering one side of the substrate, wherein the barrier layer is formed;
and patterning the second mask material layer to form a second mask layer.
Optionally, the etching the substrate with the second mask layer and the first mask layer as masks to form a second trench includes:
etching the barrier layer by taking the second mask layer and the first mask layer as masks to form a second initial groove exposing the substrate;
and etching the substrate exposed by the second initial groove to form a second groove.
Optionally, the first mask layer is made of TiN, AlN or Al2O3Or the material of the first mask layer is one or more of SiC, SiN, SiON or Si.
Optionally, the material of the barrier layer main body is one or more of TiN, AlN or Al2O 3; the barrier layer side wall is made of TiN, AlN and Al2O3One or more of SiC, SiN, SiON or Si; and the material of the barrier layer main body is different from that of the barrier layer side wall.
Optionally, the material of the sacrificial layer is one or more of amorphous silicon, amorphous carbon, an organic dielectric layer, or a spin-on carbon layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the embodiment of the invention, the barrier layer does not simply realize the isolation of the adjacent conductive groove regions in the first direction, but divides the conductive groove pattern into the first groove region and the second groove region, so that the barrier layer simultaneously covers the second groove region and the isolation region which are staggered with the first groove region. And, in the process of forming the second trench after the first trench is formed, the density of the pattern is reduced by half, thereby reducing the process complexity and the process precision.
Drawings
FIG. 1 is a layout diagram of a conductive trench pattern of a semiconductor structure;
fig. 2 to 7 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the invention;
fig. 8 to 16 are schematic structural views corresponding to steps in another embodiment of the method for forming a semiconductor structure according to the embodiment of the invention.
Detailed Description
As can be seen from the background art, the devices formed by the prior art process still have poor performance. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
In the prior art, a conductive interconnection structure for connecting to-be-interconnected structures (such as a gate electrode and a source/drain electrode) needs to be formed in a semiconductor structure, and specifically, the conductive interconnection structure can be formed in a conductive trench by forming a conductive trench exposing the to-be-interconnected structure above the to-be-interconnected structure and depositing a conductive material in the conductive trench. However, referring to fig. 1, due to the small feature size and complex layout of the pattern of the conductive trenches 110, a patterned mask layer 120 is usually required to achieve lateral isolation of adjacent conductive trenches 110 and longitudinal isolation of adjacent conductive trenches 110 in the same row by the patterned barrier layer 130 when forming the conductive trenches 110.
However, as the feature size of the device is reduced, the feature size of the pattern of the conductive trench is further reduced, and the pattern density is gradually increased, the feature size of the pattern of the barrier layer for isolating adjacent conductive trenches is correspondingly reduced, and the pattern density is also correspondingly increased, so that the process of forming the barrier layer needs to repeat the photolithography and etching processes for multiple times to meet the requirements of the corresponding feature size and pattern density.
Obviously, the prior art has complex process and high requirement on process precision.
In an embodiment of the present invention, a method for forming a semiconductor structure is provided, the method including: providing a substrate, wherein the substrate comprises a first groove region and a second groove region which are arranged in a staggered mode along a first direction, and an isolation region located between the first groove region and the second groove region; forming a patterned barrier layer on the substrate, wherein the barrier layer covers the second groove region and the isolation region and exposes the first groove region; forming a patterned first mask layer, wherein the substrate of the first trench region, the barrier layer of the second trench region and the barrier layer of the isolation region are exposed by the first mask layer; etching the substrate by taking the barrier layer and the first mask layer as masks to form a first groove; forming a second mask layer which covers the first groove and the isolation region and exposes the second groove region; and etching the substrate by taking the first mask layer and the second mask layer as masks to form a second groove.
It can be seen that, in the embodiment of the present invention, the barrier layer does not simply realize the isolation of the adjacent conductive trench regions in the first direction, but divides the conductive trench pattern into the first trench region and the second trench region, so that the barrier layer covers the second trench region and the isolation region which are staggered with the first trench region at the same time. And, in the process of forming the second trench after the first trench is formed, the density of the pattern is reduced by half, thereby reducing the process complexity and the process precision.
It should be noted that, in an alternative example, the barrier layer is formed by combining two structures, that is, the barrier layer main body covering the second trench region and the barrier layer sidewall covering the longitudinal isolation region are formed separately, so that when the second mask layer exposing the second trench region is formed subsequently, the barrier layer main body can be directly removed, thereby simplifying the process steps and reducing the process complexity.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 2 to 7 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 2, a substrate 200 is provided, where the substrate 200 includes first trench regions 201 and second trench regions 202 arranged in a staggered manner along a first direction X, and an isolation region 203 located between the first trench regions and the second trench regions;
the first trench region 201 and the second trench region 202 are used for forming a conductive trench, wherein the first trench region 201 and the second trench region 202 are divided to distinguish adjacent trench regions, so that conductive trenches at different positions of the adjacent trench regions can be formed in sequence in the embodiment of the present invention, thereby reducing the density of a mask pattern in the process of forming the conductive trench.
It will be appreciated that the first trench region and the second trench region may differ only in relative position and not in structural distinction. In other examples, the first trench region and the second trench region may further have a structural difference, and the present invention is not specifically limited herein.
It is understood that, in the process of reducing the pattern density, the adjacent trench regions may be divided into a first trench region and a second trench region to reduce the pattern density to half of the original density, and in some other examples, three trench regions adjacent to each other in the first direction may be divided into a first trench region, a second trench region and a third trench region, respectively, so that the conductive trench may be formed three times, so that the pattern density is reduced to one third of the original density in each process of forming the conductive trench, thereby further reducing the process precision and the process difficulty.
In the embodiment of the present invention, the trench region is divided into the first trench region 201 and the second trench region 202.
The first direction is the extending direction of the groove regions, a plurality of groove regions arranged at intervals are arranged in the extending direction, and an isolation region is arranged between every two adjacent groove regions, so that the intervals between the groove regions are realized.
Optionally, in the embodiment of the present invention, the substrate may include a plurality of parallel first trench regions 201 and second trench regions 202 arranged in a staggered manner along a first direction X, referring to fig. 2, taking the first direction X as a transverse direction as an example, in the first direction, the first trench regions 201, the second trench regions 202 and the isolation region 203 located in the same row are taken as one trench region 20, in the embodiment of the present invention, the substrate may include a plurality of rows of trench regions 20 extending transversely, a trench isolation region 204 is further included between adjacent trench regions, and in a second direction Y (i.e., a longitudinal direction in this example) perpendicular to the first direction, the first trench regions 201 and the second trench regions 202 are arranged in a staggered manner, so that adjacent trench regions are successively formed in the second direction Y, and a density of a mask pattern in a conductive trench forming process may be reduced in the second direction Y.
In the embodiment of the present invention, the base may include a substrate, gate structures located on the substrate, doped structures located between the gate structures, and the like, the substrate is used to provide support for other structures, the material of the substrate may be silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, or the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The grid structure is used as a grid of a device structure in the substrate to realize the control of the device. The doped structure is used as a source/drain structure of a device structure in the substrate and realizes control of the device together with a grid structure of the device. An interlayer dielectric layer is formed on the gate structure and the doped structure, and the first trench region and the second trench region are used for defining the position of the gate structure and/or the doped structure to be exposed so as to form a first trench and a second trench penetrating through the interlayer dielectric layer at the corresponding positions, thereby exposing the gate structure and/or the doped structure.
It should be noted that the above-mentioned substrate structure is only an optional example, and in other embodiments of the present invention, the substrate may also be another type of structure, in which a corresponding electrical connection structure is embedded in the substrate, and the electrical connection structure therein is exposed by forming the conductive trench.
Referring to fig. 3, a patterned barrier layer 210 is formed on the substrate, wherein the barrier layer 210 covers the second trench region 202 and the isolation region 203, exposing the first trench region 201;
the barrier layer 210 covers the second trench region 202 and the isolation region 203 of the substrate, and exposes the first trench region 201 of the substrate, so that in the embodiment of the present invention, the conductive trench of the first trench region is formed first, and after the conductive trench of the first trench region is formed, the conductive trench of the second trench region is formed.
The material of the barrier layer 210 may be TiN, AlN or Al2O3And may be one or more of SiC, SiN, SiON, or Si.
Specifically, the forming process of the barrier layer 210 may include: forming a barrier material layer covering the surface of the substrate, and forming a graphical photoresist layer on the barrier material layer; and patterning the barrier material layer by taking the photoresist layer as a mask so as to form the barrier layer.
The photoresist layer can be a positive photoresist or a negative photoresist formed by a photoetching process.
In the embodiment of the present invention, based on that the pattern density of the barrier layer 210 is low, and the feature size of the pattern is the sum of the feature sizes of the isolation region and the second trench region, the feature size is large, so that the photoresist layer in the embodiment of the present invention can preferably form a corresponding pattern by only one lithography process, and does not need to be subjected to multiple lithography to form a pattern with a large density and a small feature size.
In the embodiment of the present invention, the substrate includes a plurality of parallel first trench regions and second trench regions staggered in the first direction, that is, when the substrate includes a plurality of parallel trench regions 20, a trench partition region 204 is further included between adjacent trench regions, and the barrier layer may also cover at least a part of the trench partition region 204 of the substrate, so that the feature size is further enlarged, and the process difficulty is reduced.
Referring to fig. 4, a patterned first mask layer 220 is formed, wherein the first mask layer 220 exposes the substrate of the first trench region, the barrier layer 210 of the second trench region and the isolation region;
optionally, taking the first direction and the second direction defined as being perpendicular to each other on the substrate surface as an example, the first trench regions and the second trench regions are arranged in a staggered manner along the first direction X, and the first mask layer is used to define positions of the first trench regions and the second trench regions in the second direction Y.
Taking the first direction X as the lateral direction and the second direction Y as the longitudinal direction in fig. 4 as an example, the first trench regions 201 and the second trench regions 202 are arranged in a staggered manner along the lateral direction, and the first mask layer 220 is used to define the positions of the first trench regions 201 and the second trench regions 202 in the longitudinal direction. It is understood that when there are multiple parallel rows of trench regions, the first mask layer 220 covers the trench isolation regions 204 to achieve lateral isolation of adjacent rows.
It is understood that when the barrier layer 210 covers a portion of the trench isolation region 204, the first mask layer 220 simultaneously covers the barrier layer 210 of the trench isolation region 204.
Optionally, when the first mask layer 220 is only used to expose the substrate 200 of the first trench region, and the barrier layer 210 of the second trench region and the isolation region, the first mask layer only exposes the substrate 200 of the first trench region, and the barrier layer 210 of the second trench region and the isolation region, and covers other regions of the substrate.
Optionally, the first mask layer 220 may be a hard mask layer, and correspondingly, the material of the first mask layer may be TiN, AlN or Al2O3One or more of TiN, AlN, and Al2O3One or more of silicon carbide SiC, silicon nitride SiN, silicon oxynitride SiON or silicon Si, wherein, when the first mask layer is made of a plurality of materials, the corresponding structure may be a stacked structure of the plurality of materials.
Referring to fig. 5, the substrate is etched by using the barrier layer 210 and the first mask layer 220 as masks to form a first trench 230;
after the barrier layer 210 and the first mask layer 220 are formed, only the first trench region 201 is exposed on the substrate, so that the substrate 200 is etched by using the barrier layer 210 and the first mask layer 220 as masks to form a first trench 230.
Alternatively, the substrate may be etched by wet etching, dry etching, or a combination of wet and dry etching to form the first trench 230.
Referring to fig. 6, a second mask layer 240 covering the first trench and the isolation region 203 and exposing the second trench region 202 is formed;
the second mask layer 240 is used as a mask for exposing the second trench region 202, thereby implementing etching of the second trench region 202.
The second mask layer 240 may be a photoresist layer, such as a positive photoresist or a negative photoresist, and is patterned by a photolithography development process to expose the second trench region 202. Or, the second mask layer may have a layer structure different from that of the barrier layer, so that the exposed barrier layer and the substrate are etched by using the second mask layer and the first mask layer as masks.
Specifically, the forming a second mask layer covering the first trench and the isolation region and exposing the second trench region includes: forming a second mask material layer covering one side of the substrate, wherein the barrier layer is formed; and patterning the second mask material layer to form a second mask layer.
Referring to fig. 7, the substrate is etched by using the first mask layer and the second mask layer as masks, so as to form a second trench;
in this embodiment, after the second mask layer is formed, a blocking layer is further formed on the exposed second trench region, and accordingly, in this embodiment, the blocking layer exposed by the second mask layer is removed first.
Specifically, with the second mask layer and the first mask layer as masks, etching the substrate to form a second trench, including: etching the barrier layer by taking the second mask layer and the first mask layer as masks to form a second initial groove exposing the substrate; and etching the substrate exposed by the second initial groove to form a second groove.
Optionally, the barrier layer and the substrate may be etched by wet etching, dry etching, or a process combining wet etching and dry etching.
In the embodiment of the invention, the barrier layer does not simply realize the isolation of the adjacent conductive trenches in the same extension direction, but simultaneously covers the second trench regions and the isolation regions which are staggered with the first trench regions, which means that the density of the pattern is reduced by half, and the characteristic size is correspondingly changed into the sum of the second trench regions and the isolation regions, thereby reducing the process complexity and the process precision for forming the barrier layer. In addition, after the first groove is formed, the second groove is formed, which is equivalent to reducing the density of the pattern by one time, thereby reducing the process complexity and the process precision.
In another embodiment of the present invention, a method for forming a semiconductor structure is further provided, in which different structures are formed in different regions during forming a barrier layer, so that the second trench region can be exposed by removing the structure located in the second trench region and retaining the structure of the isolation region.
Specifically, fig. 8 to 16 are schematic structural diagrams corresponding to steps in another embodiment of the method for forming a semiconductor structure according to the embodiment of the invention.
Referring to fig. 8, a substrate 300 is provided, where the substrate 300 includes first trench regions 301 and second trench regions 302 arranged in a staggered manner along a first direction X, and an isolation region 303 located between the first trench regions 301 and the second trench regions 302;
optionally, in the embodiment of the present invention, the substrate may include a plurality of parallel first trench regions 301 and second trench regions 302 arranged in a staggered manner along a first direction X, and referring to fig. 8, taking the first direction X as a transverse direction as an example, in the first direction, the first trench regions 301, the second trench regions 302 and the isolation region 303 located in the same row are taken as one trench region 30, in the embodiment of the present invention, the substrate may include a plurality of rows of trench regions 30 extending transversely, a trench partition region 304 is further included between adjacent trench regions, and in a second direction Y (i.e., a longitudinal direction in this example) perpendicular to the first direction, the first trench regions 301 and the second trench regions 302 are arranged in a staggered manner, so that adjacent trench regions are successively formed in the second direction Y, and density of mask patterns in a conductive trench forming process may be reduced in the second direction Y.
Referring to fig. 9, a patterned barrier layer 310 is formed on the substrate, the barrier layer 310 covering the second trench region 302 and the isolation region 303, exposing the first trench region 301;
in this embodiment, the barrier layer main body 311 may be formed in the second trench region 302, and the barrier layer sidewall 312 may be formed in the isolation region 303, so that barrier layers with different structures are formed in different regions, and are etched according to different structures in subsequent steps, so as to serve as a second mask layer to expose the second trench region, without adding a layer of structure as a second mask layer.
It should be noted that, based on the fact that the feature size of the isolation region is smaller and smaller, the isolation region is covered by the sidewall structure, so that the requirement of the small feature size of the isolation region can be met, and the layout requirements of the trench region and the isolation region can be met.
Specifically, the step of forming the patterned barrier layer may include:
a patterned barrier layer body 311 is formed covering the second trench region, exposing the isolation region 303 and the first trench region 301.
Optionally, when the substrate has a plurality of rows of trench regions, the barrier layer main body may further cover at least a portion of the trench isolation region 304, so as to enlarge the characteristic dimension of the barrier layer main body, and reduce the process difficulty and process precision for forming the barrier layer main body.
The material of the barrier layer main body 311 is titanium nitride TiN, aluminum nitride AlN or aluminum oxide Al2O3One or more of (a).
Specifically, the forming process of the barrier layer body 311 may include: forming a barrier body material layer covering the substrate surface; forming a patterned photoresist layer on the barrier main material layer; and patterning the barrier main body material layer by taking the photoresist layer as a mask to form the barrier main body.
Wherein the barrier body material layer may be formed by a deposition process; the material of the photoresist layer can be a positive photoresist or a negative photoresist, and the patterned photoresist layer can be formed through a photoetching development process; the barrier main body material layer is patterned, and the barrier main body material layer can be patterned through an etching process, so that the barrier main body is formed.
Then, forming a barrier layer side wall 312 on the side wall of the barrier layer main body 311, wherein the barrier layer side wall 312 covers the isolation region;
the barrier layer body 311 and the barrier layer sidewall spacers 312 are used as the barrier layer 310.
The material of the barrier layer sidewall 312 may be titanium nitride TiN, aluminum nitride AlN, aluminum oxide Al2O3Silicon carbide SiC, silicon nitride SiN, silicon oxynitride SiON or silicon Si, and the material of the barrier spacers 312 is different from the material of the barrier body.
Specifically, forming a barrier layer sidewall on the sidewall of the barrier layer main body includes: forming a side wall material layer which conformally covers the barrier layer main body; and removing the side wall material layers on the top of the barrier layer main body and the top of the substrate, and taking the residual side wall material layers as the barrier layer side walls.
The sidewall material layer may be formed by a deposition process, and the sidewall material layer on the top of the barrier layer main body and the top of the substrate may be removed by a dry etching process.
Referring to fig. 10, a patterned first mask layer 320 is formed, wherein the first mask layer 320 exposes the substrate of the first trench region, and the barrier layers of the second trench region and the isolation region;
while the barrier layer 310 covers a portion of the trench isolation region 304, the first mask 320 layer simultaneously covers the barrier layer 310 of the trench isolation region 304.
Referring to fig. 11, the substrate is etched by using the barrier layer and the first mask layer 320 as masks to form a first trench 330;
optionally, the substrate may be etched by wet etching, dry etching, or a process combining wet etching and dry etching to form the first trench 330.
Referring to fig. 12 to 13, a second mask layer covering the first trench and the isolation region and exposing the second trench region is formed.
Optionally, the forming process of the second mask layer may include:
referring to fig. 12, a sacrificial layer 340 covering the first trench is formed;
the sacrificial layer 340 is formed to cover the first trench, so as to protect the first trench and prevent the first trench from being damaged in a subsequent process.
The material of the sacrificial layer 340 may be amorphous silicon, amorphous carbon, an Organic Dielectric Layer (ODL) or a spin-on carbon layer, which is easily removed, so that the sacrificial layer 340 is removed in a subsequent process to expose the first trench.
Wherein the top surface of the sacrificial layer 340 is not higher than the top surface of the barrier layer 310, thereby exposing the barrier layer 310, so as to expose the second trench region 302 by removing part of the barrier layer. Further, the top surface of the sacrificial layer 340 is not lower than the top surface of the substrate at the same time, so as to completely cover the first trench and protect the first trench from being damaged.
Specifically, the forming process of the sacrificial layer 340 may include: forming a sacrificial material layer covering one side of the substrate with the first groove; and removing part of the thickness of the sacrificial material layer until the remaining sacrificial material layer exposes the barrier layer and the first mask layer, and taking the remaining sacrificial material layer as the sacrificial layer.
Referring to fig. 13, the barrier layer body exposed by the first mask layer is removed, and the sacrificial layer 340 and the remaining barrier layer are used as a second mask layer.
Based on the barrier layer main body covering the second trench area 302 and the barrier layer sidewall 312 covering the isolation area, the substrate of the second trench area is exposed by removing the barrier layer main body exposed by the first mask layer 320, and meanwhile, the barrier layer sidewall 312 is reserved, so that the isolation area is protected. Wherein, in this example, the remaining barrier layer is the barrier sidewall spacers 312.
Correspondingly, the sacrificial layer 340 covers the first trench, so that the sacrificial layer 340 and the remaining barrier layer are used as a second mask layer, and etching of the second trench can be achieved.
Optionally, the removal of the barrier layer main body may be achieved by using a dry etching process, a wet etching process, or an etching process combining a dry etching process and a wet etching process.
Referring to fig. 14, the substrate is etched using the first mask layer 320 and the second mask layer (i.e., the sacrificial layer 340 and the remaining barrier spacers 312) as masks to form a second trench 350.
Optionally, the substrate may be etched by wet etching, dry etching, or a process combining wet etching and dry etching to form the second trench 350.
Referring to fig. 15, the first mask layer and the second mask layer are removed, exposing the substrate 300 and the first trench 330 and the second trench 350 on the substrate;
by exposing the substrate 300 and the first and second trenches 330 and 350 located thereon, respective conductive interconnect layers are formed within the first and second trenches 330 and 350.
Optionally, the first mask layer and the second mask layer may be removed by an etching or stripping process.
Referring to fig. 16, a conductive interconnection layer 360 is formed in the first and second trenches, and a top surface of the conductive interconnection layer 360 is not higher than the substrate surface.
The material of the conductive interconnection layer 360 may be one or more of Al, Cu, Ru, Ag, Au, Pt, Ni, Ti, Co, or W.
Specifically, the forming process of the conductive interconnection layer 360 may include: forming a layer of conductive interconnect material completely covering the first and second trenches; and etching and removing part of the thickness of the conductive interconnection material layer until the top surface of the substrate is exposed, and taking the conductive interconnection material layer remained in the first groove and the second groove as a conductive interconnection layer.
It should be noted that the top surface of the conductive interconnect layer 360 is not higher than the top surface of the substrate 300, and preferably lower than the top surface of the substrate 300, so as to avoid short circuit between adjacent conductive interconnect layers 360.
In the embodiments of the present invention, when the barrier layer is formed, different structures are formed in different regions, so that the structure in the second trench region is removed, the structure of the isolation region is retained, and the second trench region is exposed, thereby simplifying the formation process of the second mask layer and reducing the process cost.
While various embodiments of the present invention have been described above, various alternatives described in the various embodiments can be combined and cross-referenced without conflict to extend the variety of possible embodiments that can be considered disclosed and disclosed in connection with the embodiments of the present invention.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.

Claims (14)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first groove region and a second groove region which are arranged in a staggered mode along a first direction, and an isolation region located between the first groove region and the second groove region;
forming a patterned barrier layer on the substrate, wherein the barrier layer covers the second groove region and the isolation region and exposes the first groove region;
forming a patterned first mask layer, wherein the substrate of the first trench region, the barrier layer of the second trench region and the barrier layer of the isolation region are exposed by the first mask layer;
etching the substrate by taking the barrier layer and the first mask layer as masks to form a first groove;
forming a second mask layer which covers the first groove and the isolation region and exposes the second groove region;
and etching the substrate by taking the first mask layer and the second mask layer as masks to form a second groove.
2. The method of forming a semiconductor structure of claim 1, wherein forming a patterned barrier layer on the substrate comprises:
forming a patterned barrier layer body covering the second trench region, exposing the isolation region and the first trench region;
forming a barrier layer side wall on the side wall of the barrier layer main body, wherein the barrier layer side wall covers the isolation region;
and taking the barrier layer main body and the barrier layer side wall as the barrier layer.
3. The method of forming a semiconductor structure of claim 2, wherein said forming a second mask layer covering said first trench and said isolation region and exposing said second trench region comprises:
forming a sacrificial layer covering the first trench;
and removing the barrier layer main body exposed by the first mask layer, and taking the sacrificial layer and the residual barrier layer as second mask layers.
4. The method of forming a semiconductor structure of claim 2, wherein said forming a patterned barrier body comprises:
forming a barrier body material layer covering the substrate surface;
forming a patterned photoresist layer on the barrier main material layer;
and patterning the barrier main body material layer by taking the photoresist layer as a mask to form the barrier main body.
5. The method of forming a semiconductor structure of claim 2, wherein forming a barrier spacer on a sidewall of the barrier body comprises:
forming a side wall material layer which conformally covers the barrier layer main body;
and removing the side wall material layers on the top of the barrier layer main body and the top of the substrate, and taking the residual side wall material layers as the barrier layer side walls.
6. The method of forming a semiconductor structure according to claim 3, wherein in the step of forming a sacrificial layer covering the first trench, a top surface of the sacrificial layer is not higher than a top surface of the barrier layer.
7. The method of forming a semiconductor structure of claim 1, wherein after forming the second trench, further comprising:
removing the first mask layer and the second mask layer, and exposing the substrate and a first groove and a second groove which are positioned on the substrate;
and forming a conductive interconnection layer in the first groove and the second groove, wherein the top surface of the conductive interconnection layer is not higher than the surface of the substrate.
8. The method of claim 1, wherein the substrate comprises a plurality of parallel first trench regions and second trench regions staggered along a first direction, wherein the first trench regions and the second trench regions are staggered along a second direction, the second direction being perpendicular to the first direction.
9. The method of claim 8, wherein the first trench region, the second trench region and the isolation region in the same row are one trench region in the first direction, wherein a trench isolation region is further included between adjacent trench regions, and wherein the step of forming the patterned barrier layer further covers at least a portion of the trench isolation region of the substrate.
10. The method of forming a semiconductor structure according to claim 1, wherein said forming a second mask layer covering said first trench and said isolation region and exposing said second trench region comprises:
forming a second mask material layer covering one side of the substrate, wherein the barrier layer is formed;
and patterning the second mask material layer to form a second mask layer.
11. The method for forming a semiconductor structure according to claim 10, wherein the etching the substrate with the second mask layer and the first mask layer as masks to form a second trench includes:
etching the barrier layer by taking the second mask layer and the first mask layer as masks to form a second initial groove exposing the substrate;
and etching the substrate exposed by the second initial groove to form a second groove.
12. The method according to claim 1, wherein the first mask layer is made of one or more of titanium nitride, aluminum nitride, and aluminum oxide, or is made of one or more of silicon carbide, silicon nitride, silicon oxynitride, and silicon.
13. The method of claim 2, wherein the barrier layer body is made of one or more of titanium nitride, aluminum nitride, or aluminum oxide; the barrier layer side wall is made of one or more of titanium nitride, aluminum oxide, silicon carbide, silicon nitride, silicon oxynitride or silicon; and the material of the barrier layer main body is different from that of the barrier layer side wall.
14. The method of claim 3, wherein the sacrificial layer is one or more of amorphous silicon, amorphous carbon, an organic dielectric layer, or a spun-on carbon layer.
CN202011153434.7A 2020-10-26 2020-10-26 Method for forming semiconductor structure Pending CN114496734A (en)

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