CN114495784B - Scanning circuit, grid driving circuit and driving method thereof - Google Patents
Scanning circuit, grid driving circuit and driving method thereof Download PDFInfo
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- CN114495784B CN114495784B CN202011260722.2A CN202011260722A CN114495784B CN 114495784 B CN114495784 B CN 114495784B CN 202011260722 A CN202011260722 A CN 202011260722A CN 114495784 B CN114495784 B CN 114495784B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
Abstract
A scanning circuit, a gate driving circuit and a driving method thereof, the scanning circuit includes: a shift register and a gating circuit, wherein the shift register outputs a grid driving signal through a first node; when the grid driving signal of the first node is a first level signal and the grid gating signal of the grid gating signal end is a second level signal, the gating circuit outputs an effective level signal to the output end, and when the grid driving signal of the first node is not the first level signal or the grid gating signal of the grid gating signal end is not the second level signal, the gating circuit outputs an ineffective level signal to the output end. The scanning circuit provided by the embodiment of the disclosure controls whether to output the effective level signal or not by controlling the gate gating signal end, so that local refreshing is conveniently realized, and further power consumption is saved.
Description
Technical Field
Embodiments of the present disclosure relate to, but are not limited to, display technologies, and in particular, to a scanning circuit, a gate driving circuit, and a driving method thereof.
Background
When the eyes watch the screen, the eyes watch a certain area on the screen, which is called a gazing area. In the gazing area, the human eyes can clearly recognize the picture content, while in the non-gazing area, the picture content cannot be clearly seen.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The embodiment of the application provides a scanning circuit, a grid driving circuit and a driving method thereof.
In one aspect, embodiments of the present disclosure provide a scan circuit, comprising: shift register, gating circuit, wherein:
the shift register is connected with a first node and is used for outputting a grid driving signal through the first node;
the gating circuit is connected with the first node, the gate gating signal end and the output end, and is configured to output an effective level signal to the output end when the gate driving signal of the first node is a first level signal and the gate gating signal of the gate gating signal end is a second level signal, and output an ineffective level signal to the output end when the gate driving signal of the first node is not the first level signal or the gate gating signal of the gate gating signal end is not the second level signal.
In an exemplary embodiment, the gating circuit includes: a gating sub-circuit and an output sub-circuit, wherein:
the gating sub-circuit is connected with the first node, the gate gating signal end and the second node and is used for providing a gate gating signal of the gate gating signal end for the second node under the control of the first node;
the output sub-circuit is connected with the first node, the second node and the output end, and is configured to output an effective level signal to the output end when the gate driving signal of the first node is a first level signal and the signal of the second node is a second level signal; and outputting a non-effective level signal to the output end when the grid driving signal of the first node is not a first level signal or the signal of the second node is not a second level signal.
In an exemplary embodiment, the gating circuit further includes a storage sub-circuit connected to the second node and the first power terminal and configured to store a voltage between the second node and the first power terminal.
In an exemplary embodiment, the gate sub-circuit includes a first transistor having a control electrode connected to the first node, a first electrode connected to the gate signal terminal, and a second electrode connected to the second node.
In an exemplary embodiment, the storage sub-circuit includes a capacitor, a first terminal of which is connected to the second node, and a second terminal of which is connected to the first power supply terminal.
In an exemplary embodiment, the output sub-circuit includes an and gate, a first input terminal of the and gate is connected to the first node, a second input terminal of the and gate is connected to the second node, and an output terminal of the and gate is an output terminal of the output sub-circuit.
In an exemplary embodiment, the and gate includes: a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, wherein:
the control electrode of the second transistor is connected with the second node, the first electrode is connected with the second power supply end, and the second electrode is connected with the third node;
the control electrode of the third transistor is connected with the first node, the first electrode is connected with the second power supply end, and the second electrode is connected with the third node;
the control electrode of the fourth transistor is connected with the first node, the first electrode is connected with the third node, and the second electrode is connected with the fourth node;
the control electrode of the fifth transistor is connected with the second node, the first electrode is connected with the fourth node, and the second electrode is connected with a third power supply end;
the control electrode of the sixth transistor is connected with the third node, the first electrode is connected with the second power supply end, and the second electrode is connected with the output end;
and a control electrode of the seventh transistor is connected with the third node, a first electrode of the seventh transistor is connected with the output end, and a second electrode of the seventh transistor is connected with the third power supply end.
In an exemplary embodiment, the gating circuit includes a first transistor, a capacitor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, wherein:
the control electrode of the first transistor is connected with the first node, the first electrode is connected with the gate gating signal end, and the second electrode is connected with the second node;
the first end of the capacitor is connected with the second node, and the second end of the capacitor is connected with the first power supply end;
the control electrode of the second transistor is connected with the second node, the first electrode is connected with the second power supply end, and the second electrode is connected with the third node;
the control electrode of the third transistor is connected with the first node, the first electrode is connected with the second power supply end, and the second electrode is connected with the third node;
the control electrode of the fourth transistor is connected with the first node, the first electrode is connected with the third node, and the second electrode is connected with the fourth node;
the control electrode of the fifth transistor is connected with the second node, the first electrode is connected with the fourth node, and the second electrode is connected with a third power supply end;
the control electrode of the sixth transistor is connected with the third node, the first electrode is connected with the second power supply end, and the second electrode is connected with the output end;
and a control electrode of the seventh transistor is connected with the third node, a first electrode of the seventh transistor is connected with the output end, and a second electrode of the seventh transistor is connected with the third power supply end.
In an exemplary embodiment, the second, third and sixth transistors are P-type transistors, and the fourth, fifth and seventh transistors are N-type transistors.
In yet another aspect, an embodiment of the present disclosure provides a gate driving circuit, including a plurality of the above-mentioned scan circuits, the plurality of scan circuits are connected to a same gate strobe signal terminal, and shift registers in the plurality of scan circuits are cascaded.
In still another aspect, an embodiment of the present disclosure provides a driving method of a gate driving circuit, which is applied to the gate driving circuit, including:
determining one or more rows of pixels to be refreshed;
when the pixel row to be refreshed corresponds to a scanning period, outputting a first level signal to a first node of a gating circuit corresponding to the current pixel row through a shift register corresponding to the current pixel row, and loading a second level signal to the gate driving circuit through the gate gating signal end;
when the scanning period corresponding to the pixel row which is not refreshed is the current scanning period, a first level signal is output to a first node of a gating circuit corresponding to the current pixel row through a shift register corresponding to the current pixel row, and a non-second level signal is loaded to the gate driving circuit through the gate gating signal end.
The disclosed embodiments provide a scan circuit including: shift register, gating circuit, wherein: the shift register is connected with a first node and is used for outputting a grid driving signal through the first node; the gating circuit is connected with the first node, the gate gating signal end and the output end, and is configured to output an effective level signal to the output end when the gate driving signal of the first node is a first level signal and the gate gating signal of the gate gating signal end is a second level signal, and output an ineffective level signal to the output end when the gate driving signal of the first node is not the first level signal or the gate gating signal of the gate gating signal end is not the second level signal. The scanning circuit provided by the embodiment of the disclosure controls whether to output the effective level signal or not by controlling the gate gating signal end, so that local refreshing is conveniently realized, and further power consumption is saved.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate and do not limit the application.
FIG. 1 is a schematic diagram of a scan circuit provided in an embodiment of the disclosure;
FIG. 2 is a schematic diagram of a gating circuit according to an embodiment;
FIG. 3 is a schematic diagram of a gating circuit according to another embodiment;
FIG. 4 is a schematic diagram of a gating sub-circuit according to an embodiment;
FIG. 5 is a schematic diagram of a memory sub-circuit according to an embodiment;
FIG. 6 is a schematic diagram of an output sub-circuit according to an embodiment;
FIG. 7 is a schematic diagram of an AND gate according to one embodiment;
FIG. 8 is a schematic diagram of a scan circuit according to an embodiment;
FIG. 9 is a schematic diagram of a gate driving circuit according to an embodiment;
FIG. 10 is a timing diagram of a gate driving circuit according to an embodiment;
fig. 11 is a flowchart of a driving method of a gate driving circuit according to an embodiment.
Detailed Description
Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings. Embodiments of the application and features of the embodiments may be combined with one another arbitrarily without conflict.
The steps illustrated in the flowchart of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, while a logical order is depicted in the flowchart, in some cases, the steps depicted or described may be performed in a different order than presented herein.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs.
The ordinal numbers of "first", "second", "third", etc. in the present disclosure are provided to avoid intermixing of constituent elements, and do not denote any order, quantity, or importance.
In this disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly, unless otherwise specifically indicated and defined. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art in the specific context.
In this disclosure, a transistor refers to an element including at least three terminals of a gate electrode (or referred to as a control electrode), a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region through which current mainly flows.
In the present disclosure, the first electrode may be a drain electrode, and the second electrode may be a source electrode, or the first electrode may be a source electrode, and the second electrode may be a drain electrode. In the case of using a transistor having opposite polarity, or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Thus, in this disclosure, the "source electrode" and the "drain electrode" may be interchanged.
In this disclosure, "electrically connected" includes a case where constituent elements are connected together by an element having some electric action. The "element having a certain electric action" is not particularly limited as long as it can transmit and receive an electric signal between the constituent elements connected. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.
According to the characteristics of the gazing area and the non-gazing area, the resolution, refresh frequency and the like of the non-gazing area can be properly reduced without affecting the image quality, which is called as a smartview technology. In the smart view concept, it is often desirable to locally refresh certain sections of a panel (panel), and conventional row-by-row refresh array substrate gate drive (Gate Driver on ArrayGOA) circuitry is not available. The embodiment of the disclosure provides a gate driving circuit, which can realize local refreshing of any N rows (N is more than or equal to 1 and less than or equal to the total number of rows).
Fig. 1 is a schematic diagram of a scan circuit according to an embodiment of the present application. As shown in fig. 1, the scanning circuit may include: a shift register and a gating circuit, wherein:
the shift register is connected with the first node G and is used for outputting a grid driving signal through the first node G;
the gating circuit is connected with the first node G, the gate gating signal end S and the output end G_out, and is configured to output an effective level signal to the output end G_out when the gate driving signal of the first node G is a first level signal and the gate gating signal of the gate gating signal end S is a second level signal; when the gate driving signal of the first node G is not the first level signal or the gate gating signal of the gate gating signal terminal S is not the second level signal, an inactive level signal is output to the output terminal g_out.
The scanning circuit provided by the embodiment can control whether to output an effective level signal or not by controlling the gate gating signal end, namely whether to refresh the current row or not, so as to realize local refresh.
In an exemplary embodiment, the active level signal output by the output terminal g_out refers to a signal capable of turning on the pixel unit, the inactive level signal refers to a signal for turning off the pixel unit, the active level signal may be a high level signal, and the inactive level signal may be a low level signal; alternatively, the active level signal may be a low level signal and the inactive level signal may be a high level signal.
In an exemplary embodiment, the first level signal may be a low level signal or a high level signal, and the second level signal may be a low level signal or a high level signal.
In an exemplary implementation, the first level signal may be a high level signal, the second level signal may be a high level signal, and the active level signal may be a high level signal, that is, the shift register outputs the high level signal, and when the gate strobe signal terminal S loads the high level signal, the output terminal g_out outputs the high level signal, and turns on the pixel unit of the corresponding pixel row; when the shift register outputs a low-level signal, the output end G_out outputs the low-level signal, and the pixel units of the corresponding pixel rows are turned off; when the gate strobe signal terminal S loads a low level signal, the output terminal g_out outputs a low level signal, turning off the pixel units of the corresponding pixel row. When the scanning circuit is applied to the gate driving circuit, only one shift register outputs a high-level signal in one scanning period, and other shift registers output low-level signals, at this time, signals at the output end can be controlled through signals at the gate gating signal end, namely, the pixel row needing to be refreshed can be started by setting the gate gating signal of the scanning period corresponding to the pixel row needing to be refreshed to be high level, and the pixel row needing not to be refreshed can be turned off by setting the gate gating signal of the scanning period corresponding to the pixel row needing not to be refreshed to be low level.
In an exemplary embodiment, the shift register may be connected to an input terminal (not shown in fig. 1) and configured to shift a signal input from the input terminal and output the shifted signal through the first node G. The shift register may also be connected to a first clock signal terminal, a second clock signal terminal, a reset terminal, etc., depending on the structure of the shift register. The embodiment of the application does not limit the realization of the shift register.
Fig. 2 is a schematic diagram of a gating circuit according to an embodiment. As shown in fig. 2, the gating circuit may include: a gating sub-circuit and an output sub-circuit, wherein:
the gating sub-circuit is connected with a first node G, a gate gating signal end S and a second node H and is used for providing a gate gating signal of the gate gating signal end S for the second node H under the control of the first node G;
the output sub-circuit is connected with the first node G, the second node H and the output terminal g_out, and is configured to output an active level signal to the output terminal g_out when the gate driving signal of the first node G is a first level signal and the signal of the second node H is a second level signal, and output an inactive level signal to the output terminal g_out when the gate driving signal of the first node G is not the first level signal or the signal of the second node H is not the second level signal.
An exemplary structure of the gate circuit is shown in the present embodiment. Those skilled in the art will readily understand that the implementation of the gating circuit is not limited thereto, as long as its function can be implemented.
Fig. 3 is a schematic diagram of a gating circuit according to an embodiment. As shown in fig. 3, the gating circuit may further include: a memory sub-circuit, wherein: the storage sub-circuit is connected with the second node H and the first power supply terminal V1 and is used for storing the voltage between the second node H and the first power supply terminal V1. The first power terminal V1 provides a fixed voltage signal, such as a ground terminal (GND). The storage sub-circuit provided by the embodiment can store the voltage between the second node H and the first power supply terminal V1, keep the voltage of the second node H and enhance the reliability of the circuit. In addition, the reference voltage may be provided to the AND gate when the subsequent output subcircuit is implemented using the AND gate.
Fig. 4 is a schematic diagram of a gating sub-circuit according to an embodiment. As shown in fig. 4, the gate sub-circuit may include a first transistor T1, where a control electrode of the first transistor T1 is connected to the first node G, a first electrode is connected to the gate signal terminal S, and a second electrode is connected to the second node H.
An exemplary structure of the gating sub-circuit is shown in the present embodiment. Those skilled in the art will readily appreciate that the implementation of the gating sub-circuit is not limited thereto, as long as its function can be implemented.
FIG. 5 is a schematic diagram of a memory sub-circuit according to an embodiment. As shown in fig. 5, the storage sub-circuit may include a capacitor Cst, where a first terminal of the capacitor Cst is connected to the second node H, and a second terminal of the capacitor Cst is connected to the first power supply terminal V1.
An exemplary structure of the memory sub-circuit is shown in the present embodiment. Those skilled in the art will readily appreciate that the implementation of the memory sub-circuit is not limited thereto, as long as its functionality can be implemented.
Fig. 6 is a schematic diagram of an output sub-circuit according to an embodiment. As shown in fig. 6, the output sub-circuit may include an and gate, where a first input terminal a of the and gate is connected to the first node G, a second input terminal B of the and gate is connected to the second node H, and an output terminal of the and gate is an output terminal g_out of the output sub-circuit.
An exemplary structure of the output sub-circuit is shown in the present embodiment. Those skilled in the art will readily appreciate that the implementation of the output subcircuit is not limited thereto, so long as it is capable of performing its functions.
Fig. 7 is a schematic diagram of an and gate according to an embodiment. As shown in fig. 7, the and gate may include: a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, wherein:
the control electrode of the second transistor T2 is connected with the second input end B, the second input end B is connected with the second node H, the first electrode is connected with the second power supply end VDD, and the second electrode is connected with the third node C;
the control electrode of the third transistor T3 is connected to the first input terminal a, the first input terminal a is connected to the first node G, the first electrode is connected to the second power supply terminal VDD, and the second electrode is connected to the third node C;
the control electrode of the fourth transistor T4 is connected to the first input terminal a (i.e., to the first node G), the first electrode is connected to the third node C, and the second electrode is connected to the fourth node D;
a control electrode of the fifth transistor T5 is connected to the second input terminal B (i.e., to the second node H), a first electrode is connected to the fourth node D, and a second electrode is connected to the power supply terminal VSS;
a control electrode of the sixth transistor T6 is connected to the third node C, a first electrode is connected to the second power supply terminal VDD, and a second electrode is connected to the output terminal g_out;
the control electrode of the seventh transistor T7 is connected to the third node C, the first electrode is connected to the output terminal g_out, and the second electrode is connected to the third power supply terminal VSS.
In an exemplary embodiment, the voltage signal provided by the second power supply terminal VDD is, for example, a high level, and the voltage signal provided by the third power supply terminal VSS is, for example, a low level.
An exemplary structure of an and gate is shown in this embodiment. It will be readily appreciated by those skilled in the art that the implementation of an and gate is not limited thereto, as long as its function is enabled.
Fig. 8 is a schematic diagram of a scan circuit according to an embodiment. As shown in fig. 8, the scan circuit may include a shift register and a gate circuit, and the gate circuit may include a first transistor T1, a capacitor Cst, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, wherein:
the control electrode of the first transistor T1 is connected with the first node G, the first electrode is connected with the grid gating signal end S, and the second electrode is connected with the second node H;
the first end of the capacitor Cst is connected with the second node H, and the second end of the capacitor Cst is connected with a first power supply end V1;
the control electrode of the second transistor T2 is connected with the second node H, the first electrode is connected with the second power supply end VDD, and the second electrode is connected with the third node C;
the control electrode of the third transistor T3 is connected to the first node G, the first electrode is connected to the second power supply terminal VDD, and the second electrode is connected to the third node C;
the control electrode of the fourth transistor T4 is connected to the first node G, the first electrode is connected to the third node C, and the second electrode is connected to the fourth node D;
the control electrode of the fifth transistor T5 is connected to the second node H, the first electrode is connected to the fourth node D, and the second electrode is connected to the third power supply terminal VSS;
a control electrode of the sixth transistor T6 is connected to the third node C, a first electrode is connected to the second power supply terminal VDD, and a second electrode is connected to the output terminal g_out;
the control electrode of the seventh transistor T7 is connected to the third node C, the first electrode is connected to the output terminal g_out, and the second electrode is connected to the third power supply terminal VSS.
In an exemplary embodiment, the second, third and sixth transistors T2, T3 and T6 may be P-type transistors, and the fourth, fifth and seventh transistors T4, T5 and T7 may be N-type transistors. Embodiments of the application are not so limited.
In the scan circuit provided in this embodiment, the first level signal is a high level, the second level signal is a high level, the effective level signal is a high level, and the first transistor T1 is an N-type transistor as an example.
When the shift register outputs a high-level signal through the first node G, the first transistor T1 is turned on, the gate gating signal is written into the second node H through the first transistor T1, when the gate gating signal of the gate gating signal end S is a high-level signal, the high-level signal of the first node G and the high-level signal phase of the second node H output a high-level signal, namely the output end G_out outputs a high-level signal; when the gate strobe signal of the gate strobe signal terminal S is a low level signal, the high level signal of the first node G and the low level signal phase of the second node H output a low level signal, i.e., the output terminal g_out outputs a low level signal.
In the next period, the shift register outputs a low level signal through the first node G, the first transistor T1 is turned off, and the potential of the second node H is maintained by the storage capacitor Cst. The storage capacitor can stabilize the potential of H, and the reliability of the circuit is improved.
The scanning circuit provided by the embodiment can control whether to refresh the corresponding pixel row or not by setting the signal of the gate gating signal end to control the signal of the output end, thereby realizing local refresh.
Fig. 9 is a schematic diagram of a gate driving circuit according to an embodiment. As shown in fig. 9, the present embodiment provides a gate driving circuit, which includes a plurality of the above-mentioned scan circuits, the plurality of scan circuits are connected to the same gate strobe signal terminal S, and shift registers in the plurality of scan circuits are cascaded.
As shown in fig. 9, the shift register cascade includes: the output G1 of the first shift register is connected to the input of the second shift register and so on, the output G (N-1) of the N-1 th shift register is connected to the input of the N-th shift register. In this embodiment, the cascade connection of the shift registers may refer to a cascade connection manner of the shift registers in the gate driving circuit without the gate circuit, which is not limited in the embodiment of the present application.
In an exemplary embodiment, the shift register may be connected to the first clock signal terminal CLK and the second clock signal terminal CLB.
In an exemplary embodiment, when the ith shift register outputs the first level signal and the gate strobe signal terminal S loads the second level signal, the corresponding output terminal gi_out outputs the active level signal; when the ith shift register outputs a first level signal and the gate strobe signal terminal S loads a non-second level signal, the corresponding output terminal Gi_out outputs a non-effective level signal; that is, whether or not the ith row of pixels (in this embodiment, the ith scanning circuit corresponds to the ith row of pixels) is refreshed may be controlled by the gate strobe signal of the control gate strobe signal terminal S. Accordingly, the level of the gate strobe signal at the gate strobe signal terminal S at each scanning period can be set according to the pixel row that needs to be refreshed. The method comprises the steps of controlling a grid gating signal to be a second level signal in a scanning period corresponding to a pixel row needing to be refreshed, and controlling the grid gating signal to be a non-second level signal in a scanning period corresponding to a pixel row not needing to be refreshed, so that local refreshing is realized, for example, the grid gating signal is the second level signal in the scanning period corresponding to m pixel rows, and the grid gating signal is the non-second level signal in the scanning period corresponding to the rest N-m pixel rows, wherein m is not less than 1 and not more than N, and N is the pixel row.
The gate driving circuit provided in this embodiment outputs a first level signal sequentially from a 1 st scanning period to an nth scanning period through the 1 st shift register to the nth shift register when driving; in the ith scanning period, i is 1 to N, the ith shift register outputs a first level signal, the rest shift registers output non-first level signals, when a pixel row corresponding to the ith scanning period needs to be refreshed, a gate gating signal is set to be a second level signal in the ith scanning period, at the moment, an output end Gi_out outputs an effective level signal, and the ith pixel row is started; when the pixel row corresponding to the ith scanning period does not need to be refreshed, the gate gating signal is set to be a non-second level signal in the ith scanning period, and at the moment, the output end Gi_out outputs a non-effective level signal to turn off the ith pixel row.
According to the scheme provided by the embodiment, the local refreshing can be realized through the control gate gating signal terminal.
The technical scheme provided by the embodiment of the disclosure is described below by the working process of the gate driving circuit. In the following embodiments, the first level signal is a high level signal, the second level signal is a high level signal, the active level signal is a high level signal, the first transistor T1 is an N-type transistor, the second transistor T2, the third transistor T3, the sixth transistor T6 are P-type transistors, and the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are N-type transistors. Fig. 10 is a timing chart of the operation of the gate driving circuit according to the present embodiment. The present embodiment is based on the gate driving circuit shown in fig. 9. In this embodiment, the source of the first transistor T1 is connected to the gate strobe signal terminal S. Table 1 is a truth table of the and gate in this embodiment.
Table 1 AND gate truth table
In fig. 10, 5 shift registers are taken as an example, and correspond to the 1 st pixel row to the 5 th pixel row, respectively. The signals output from the first nodes G1 to G5, the signals output from the gate strobe signal terminal S, and the signals output from the output terminals g1_out to g5_out are shown in fig. 10. As shown in fig. 10, t1 to t5 are scanning periods of 1 st pixel row to 5 th pixel row, respectively, wherein:
in the period T1, the first shift register outputs a high-level signal through the first node G1, at this time, the gate strobe signal terminal S outputs a low-level signal, T11 is turned on, the signals of the gate strobe signal terminal S are loaded to the low-level signal phase of the second node H1 and the high-level signal phase of the H1, and a low-level signal is output through g1_out, at this time, the first pixel row is not refreshed; the rest shift registers output low-level signals, the corresponding output ends G2 out to G5 out output low-level signals, and the 2 nd to 5 th pixel rows are not refreshed;
in the period T2, the second shift register outputs a high-level signal through G2, at this time, the gate strobe signal terminal S outputs a high-level signal, the high-level signal of G2 and the high-level signal phase of H2 are loaded to the second node H2 through T12, and the high-level signal is output through g2_out, at this time, the second pixel row is refreshed; the rest shift registers output low-level signals, the corresponding output ends output low-level signals, the 1 st pixel row and the 3 rd to 5 th pixel rows are not refreshed;
in the period T3, the third shift register outputs a high level signal through G3, at this time, the gate strobe signal terminal S outputs a low level signal, the high level signal of G3 and the low level signal phase of H3 are loaded to the second node H3 through T13, and the low level signal is output through g3_out, at this time, the third pixel row is not refreshed; the rest shift registers output low-level signals, the corresponding output ends output low-level signals, the 1 st pixel row, the 2 nd pixel row and the 4 th pixel row and the 5 th pixel row are not refreshed;
in the period T4, the fourth shift register outputs a high-level signal through G4, at this time, the gate strobe signal terminal S outputs a high-level signal, the high-level signal of G4 and the high-level signal phase of H4 are loaded to the second node H4 through T14, and the high-level signal is output through g4_out, at this time, the fourth pixel row is refreshed; the rest shift registers output low-level signals, the corresponding output ends output low-level signals, the 1 st, 2 nd and 3 rd pixel rows and the 5 th pixel row are not refreshed;
in the period T5, the fifth shift register outputs a high level signal through G5, and at this time, the gate strobe signal terminal S outputs a high level signal, and the high level signal of G5 and the high level signal of H5 are loaded to the second node H5 through T15, and the high level signal is output through g5_out, and at this time, the 5 th pixel row is refreshed. The rest shift registers output low-level signals, the corresponding output ends output low-level signals, and the 1 st to 4 th pixel rows are not refreshed.
In this embodiment, the refresh of the 2,4,5 th pixel row is achieved by setting the gate strobe signal to the high level signal in the scanning period corresponding to the 2,4,5 th pixel row, that is, the refresh of a part of the pixel rows in one scanning period (including the scanning period of all the pixel rows) is achieved. For any pixel row j1 needing refreshing, setting a gate gating signal in a scanning period corresponding to the pixel row j1 as a high-level signal, so that the pixel row j1 can be refreshed, and for any pixel row j2 not needing refreshing, setting a gate gating signal in a scanning period corresponding to the pixel row j2 as a low-level signal, so that the pixel row j2 can not be refreshed, wherein j1 is more than or equal to 1 and less than or equal to N, and j2 is more than or equal to 1 and less than or equal to N, and N is the number of pixel rows. j1 and j2 may be set as desired, for example, may be set as a pixel row of the noted area. The scheme provided by the embodiment can realize local refreshing and save power consumption.
Fig. 11 is a flowchart of a driving method of a gate driving circuit according to an exemplary embodiment. As shown in fig. 11, the present embodiment provides a driving method of a gate driving circuit, which is applied to the gate driving circuit, where the gate driving circuit includes a plurality of scan circuits, each scan circuit corresponds to a pixel row, and the driving method includes:
step 1101, determining one or more pixel rows to be refreshed;
step 1102, when the pixel row to be refreshed corresponds to a scanning period, outputting a first level signal to a first node of a gate circuit corresponding to the current pixel row through a shift register corresponding to the current pixel row, and loading a second level signal to the gate driving circuit through the gate signal end;
the shift register corresponding to the current pixel row is the shift register in the scanning circuit corresponding to the current pixel row, and the gating circuit corresponding to the current pixel row is the gating circuit in the scanning circuit corresponding to the current pixel row. The current pixel row is the pixel row to be refreshed currently.
In step 1103, when the scanning period is the scanning period corresponding to the pixel row that is not refreshed currently, a first level signal is output to a first node of a gate circuit corresponding to the current pixel row through a shift register corresponding to the current pixel row (i.e., the pixel row that is not refreshed currently), and a non-second level signal is loaded to the gate driving circuit through the gate signal terminal.
In the conventional gate driving circuit, one pixel row is refreshed in each scanning period, in this embodiment, only when the gate strobe signal of the gate strobe signal end in the scanning period is the second level signal, the pixel row corresponding to the scanning period is refreshed, and when the gate strobe signal of the gate strobe signal end in the scanning period is the non-second level signal, the pixel row corresponding to the scanning period is not refreshed. According to the scheme provided by the embodiment, the refreshing of the pixel rows needing refreshing is realized by setting the signals of the grid gating signal end in different scanning periods, and the local refreshing is realized without refreshing the pixel rows needing refreshing, so that the power consumption can be saved.
In the scheme provided by the embodiment, due to the self characteristics of the shift registers, only one shift register outputs the first level signal in each scanning period, and the other shift registers output the non-first level signal, so that for any scanning period, the output ends of other pixel rows except the pixel row corresponding to the scanning period are all non-effective level signals, and therefore, the refreshing cannot be performed.
In an exemplary embodiment, the first level signal is, for example, a high level signal, and the second level signal is, for example, a high level signal, but the embodiment of the present disclosure is not limited thereto.
In an exemplary embodiment, the one or more pixel rows to be refreshed may include a pixel row of a noted region. The embodiments of the present disclosure are not limited thereto and may be any pixel row.
The embodiment of the disclosure also provides a display device comprising the gate driving circuit. The display device may be: OLED panel, cell phone, tablet computer, TV, display, notebook computer, digital photo frame, navigator, etc.
Although the embodiments of the present application are described above, the embodiments are only used for facilitating understanding of the present application, and are not intended to limit the present application. Any person skilled in the art can make any modification and variation in form and detail without departing from the spirit and scope of the present disclosure, but the scope of the present disclosure is to be determined by the appended claims.
Claims (11)
1. A scanning circuit, comprising: a shift register and a gating circuit, wherein:
the shift register is connected with a first node and is used for outputting a grid driving signal through the first node;
the gating circuit is connected with the first node, the gate gating signal end and the output end, and is configured to output an effective level signal to the output end when the gate driving signal of the first node is a first level signal and the gate gating signal of the gate gating signal end is a second level signal, and output an ineffective level signal to the output end when the gate driving signal of the first node is not the first level signal or the gate gating signal of the gate gating signal end is not the second level signal.
2. The scan circuit of claim 1, wherein the gating circuit comprises: a gating sub-circuit and an output sub-circuit, wherein:
the gating sub-circuit is connected with the first node, the gate gating signal end and the second node and is used for providing a gate gating signal of the gate gating signal end for the second node under the control of the first node;
the output sub-circuit is connected with the first node, the second node and the output end, and is configured to output an effective level signal to the output end when the gate driving signal of the first node is a first level signal and the signal of the second node is a second level signal; and outputting a non-effective level signal to the output end when the grid driving signal of the first node is not a first level signal or the signal of the second node is not a second level signal.
3. The scan circuit of claim 2, wherein the gating circuit further comprises a storage sub-circuit coupled to the second node and the first power terminal and configured to store a voltage between the second node and the first power terminal.
4. The scan circuit of claim 2, wherein the gating sub-circuit comprises a first transistor having a control electrode coupled to the first node, a first electrode coupled to the gate gating signal terminal, and a second electrode coupled to the second node.
5. A scan circuit according to claim 3, wherein the storage sub-circuit comprises a capacitor, a first terminal of the capacitor being connected to the second node, and a second terminal of the capacitor being connected to the first power supply terminal.
6. The scan circuit of claim 2, wherein the output sub-circuit comprises an and gate, a first input of the and gate being connected to the first node, a second input of the and gate being connected to the second node, and an output of the and gate being an output of the output sub-circuit.
7. The scan circuit of claim 6, wherein the and gate comprises: a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, wherein:
the control electrode of the second transistor is connected with the second node, the first electrode is connected with the second power supply end, and the second electrode is connected with the third node;
the control electrode of the third transistor is connected with the first node, the first electrode is connected with the second power supply end, and the second electrode is connected with the third node;
the control electrode of the fourth transistor is connected with the first node, the first electrode is connected with the third node, and the second electrode is connected with the fourth node;
the control electrode of the fifth transistor is connected with the second node, the first electrode is connected with the fourth node, and the second electrode is connected with a third power supply end;
the control electrode of the sixth transistor is connected with the third node, the first electrode is connected with the second power supply end, and the second electrode is connected with the output end;
and a control electrode of the seventh transistor is connected with the third node, a first electrode of the seventh transistor is connected with the output end, and a second electrode of the seventh transistor is connected with the third power supply end.
8. The scan circuit of claim 1, wherein the gating circuit comprises a first transistor, a capacitor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, wherein:
the control electrode of the first transistor is connected with the first node, the first electrode is connected with the gate gating signal end, and the second electrode is connected with the second node;
the first end of the capacitor is connected with the second node, and the second end of the capacitor is connected with the first power supply end;
the control electrode of the second transistor is connected with the second node, the first electrode is connected with the second power supply end, and the second electrode is connected with the third node;
the control electrode of the third transistor is connected with the first node, the first electrode is connected with the second power supply end, and the second electrode is connected with the third node;
the control electrode of the fourth transistor is connected with the first node, the first electrode is connected with the third node, and the second electrode is connected with the fourth node;
the control electrode of the fifth transistor is connected with the second node, the first electrode is connected with the fourth node, and the second electrode is connected with a third power supply end;
the control electrode of the sixth transistor is connected with the third node, the first electrode is connected with the second power supply end, and the second electrode is connected with the output end;
and a control electrode of the seventh transistor is connected with the third node, a first electrode of the seventh transistor is connected with the output end, and a second electrode of the seventh transistor is connected with the third power supply end.
9. The scan circuit of claim 7 or 8, wherein the second transistor, the third transistor, and the sixth transistor are P-type transistors, and the fourth transistor, the fifth transistor, and the seventh transistor are N-type transistors.
10. A gate drive circuit comprising a plurality of scan circuits according to any one of claims 1 to 9, the plurality of scan circuits being connected to the same gate strobe signal terminal, and shift registers in the plurality of scan circuits being cascaded.
11. A driving method of a gate driving circuit, applied to the gate driving circuit as claimed in claim 10, comprising:
determining one or more rows of pixels to be refreshed;
when the pixel row to be refreshed corresponds to a scanning period, outputting a first level signal to a first node of a gating circuit corresponding to the current pixel row through a shift register corresponding to the current pixel row, and loading a second level signal to the gate driving circuit through the gate gating signal end;
when the scanning period corresponding to the pixel row which is not refreshed is the current scanning period, a first level signal is output to a first node of a gating circuit corresponding to the current pixel row through a shift register corresponding to the current pixel row, and a non-second level signal is loaded to the gate driving circuit through the gate gating signal end.
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