CN114493985A - Data processing method and device, integrated circuit and electronic equipment - Google Patents

Abstract

The application relates to a data processing method, a data processing device, an integrated circuit and an electronic device, and belongs to the technical field of image processing. The data processing method comprises the following steps: alternately storing the received data stream to be processed into a first memory and a second memory; and continuously reading data from the first memory and the second memory for preprocessing, wherein the rate of writing data is greater than the rate of reading data and is not greater than twice the rate of reading data. The data processing method can process high-speed data flow by using a low-speed processing module, thereby saving hardware cost and enhancing the applicability of a scheme.

Description

Data processing method and device, integrated circuit and electronic equipment

Technical Field

The application belongs to the technical field of image processing, and particularly relates to a data processing method and device, an integrated circuit and electronic equipment.

Background

In digital image processing, a planar digital image to be processed can be viewed as a large matrix, with each pixel of the image corresponding to each element in the large matrix. Assuming that the resolution of the planar digital image is 1024 × 768, the corresponding large matrix has 1024 rows and 768 columns. The small matrix of filters (also called convolution kernel) used for filtering is generally a square matrix, i.e. the number of rows and columns is the same. The filtering (also called convolution calculation) is to calculate the product of the surrounding pixels and the corresponding position elements of the small filter matrix for each pixel in the large matrix, then add the results together, and finally obtain the value as the new value of the pixel, thus completing the filtering.

Convolution calculation is the basis of the deep learning neural network, and only the faster the operation is executed can the deep learning-oriented application run efficiently and quickly. Compared with a processor of a conventional computer architecture, such as a Central Processing Unit (CPU), a Graphic Processing Unit (GPU), and the like, a Field Programmable Gate Array (FPGA) has higher computational efficiency when Processing these operations, and is widely used. In the FPGA, the low-speed data processing module cannot process the data stream of the high-speed port, and if the high-speed processing modules are all adopted, the hardware cost is greatly increased. How to use a low-speed processing module to process a high-speed data stream is a technical problem to be solved by the present application.

Disclosure of Invention

In view of the above, the present application aims to provide a data processing method, an apparatus, an electronic device and a computer readable storage medium, so as to achieve the purpose of processing a high-speed data stream by using a low-speed processing module.

The embodiment of the application is realized as follows:

in a first aspect, an embodiment of the present application provides a data processing method, including: alternately storing the received data stream to be processed into a first memory and a second memory; and continuously reading data from the first memory and the second memory for preprocessing, wherein the rate of writing data is greater than the rate of reading data and is not greater than twice the rate of reading data. In the embodiment of the application, the two memories are used for alternately storing data to realize ping-pong operation, so that each memory can have a certain time gap to process unprocessed data, and a low-speed processing module is used for processing a high-speed data stream.

With reference to a possible implementation manner of the embodiment of the first aspect, the alternately storing the received to-be-processed data stream into the first memory and the second memory includes: sequentially fragmenting the data stream to be processed according to a preset size; and alternately storing each fragment data stream into the first memory and the second memory according to the fragment sequence until all fragment data streams are stored. In the embodiment of the application, the data stream to be processed is fragmented, and the fragmented data streams are alternately stored in the first memory and the second memory according to the fragmentation sequence, so that the input data can be a complete data stream, and the applicability of the scheme is further enhanced.

With reference to a possible implementation manner of the embodiment of the first aspect, before sequentially fragmenting the to-be-processed data stream according to a preset size, the method further includes: acquiring the size of a storage space of the first storage and the size of a storage space of the second storage; selecting the minimum storage space in the first storage and the second storage, and determining the preset size based on the minimum storage space. In the embodiment of the application, the preset size is determined by selecting the minimum storage space in the first storage and the second storage, so that the segmented data stream can be just stored in the storage with the minimum storage space.

With reference to a possible implementation manner of the embodiment of the first aspect, the data stream is a to-be-processed image pixel stream, and the preprocessing is convolution processing. In the embodiment of the application, because the calculation amount of convolution calculation is large, the hardware cost for convolution processing can be effectively reduced by adopting the method provided by the embodiment of the application.

In a second aspect, an embodiment of the present application further provides a data processing apparatus, including: the device comprises a first memory, a second memory, an input unit and a data processing unit; an input unit for writing the received data stream alternately into the first memory and the second memory; and the data processing unit is used for reading data from the first memory and the second memory without interruption for preprocessing, wherein the rate of writing data is greater than the rate of reading data and is not greater than twice the rate of reading data.

In combination with one possible implementation manner of the second surface embodiment, the input unit includes: and the first selector is used for alternately writing the received data stream into the first memory and the second memory according to an input selection signal.

In combination with one possible implementation manner of the second aspect, the data processing unit includes: a first data processing unit and a second data processing unit; the first data processing unit is connected with the first memory and used for reading data from the first memory for preprocessing, and the processing rate of the first data processing unit is smaller than the rate of writing data into the first memory; and the second data processing unit is connected with the second memory and used for reading data from the second memory for preprocessing, and the processing rate of the second data processing unit is less than the rate of writing data into the second memory.

With reference to one possible implementation manner of the second aspect, the data processing unit further includes: and the input end of the second selector is respectively connected with the first data processing unit and the second data processing unit, and the second selector is used for alternately outputting the data output by the first data processing unit and the data output by the second data processing unit according to an input selection signal.

In a third aspect, embodiments of the present application further provide an integrated circuit, which integrates the data processing apparatus as provided in the second aspect and/or in combination with any one of the possible implementation manners of the second aspect.

In a fourth aspect, an embodiment of the present application further provides an electronic device, including: a device body and a data processing apparatus as provided in the above second aspect embodiment and/or in connection with any possible implementation of the second aspect embodiment, or an integrated circuit as provided in the above third aspect embodiment.

In a fifth aspect, this embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to perform the method in the foregoing first aspect and/or any possible implementation manner of the first aspect.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. The foregoing and other objects, features and advantages of the application will be apparent from the accompanying drawings. Like reference numerals refer to like parts throughout the drawings. The drawings are not intended to be to scale as practical, emphasis instead being placed upon illustrating the subject matter of the present application.

Fig. 1 shows a schematic structural diagram of a data processing apparatus according to an embodiment of the present application.

Fig. 2 is a schematic structural diagram of another data processing apparatus provided in an embodiment of the present application.

Fig. 3 is a timing signal diagram of a data processing apparatus according to an embodiment of the present application.

Fig. 4 shows a flowchart of a data processing method provided in an embodiment of the present application.

Fig. 5 shows a schematic structural diagram of an electronic device provided in an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, relational terms such as "first," "second," and the like may be used solely in the description herein to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Further, the term "and/or" in the present application is only one kind of association relationship describing the associated object, and means that three kinds of relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone.

In view of the fact that the low-speed data processing module in the prior art cannot process the data stream of the high-speed port, if the high-speed processing module is adopted, the hardware cost is greatly increased, and therefore the embodiment of the application provides a data processing device to realize the purpose that the low-speed processing module can be used for processing the high-speed data stream, so that the hardware cost is saved, and the applicability of the scheme is enhanced.

For better understanding, the data processing apparatus provided in the embodiment of the present application is described below with reference to fig. 1. As shown in fig. 1. The data processing apparatus includes: the device comprises an input unit, a first memory, a second memory and a data processing unit. The input unit is respectively connected with the first memory and the second memory, and the data processing unit is respectively connected with the first memory and the second memory.

The input unit is used for writing the received data stream into the first memory and the second memory alternately. The data processing unit is used for reading data from the first memory and the second memory without interruption for preprocessing. Wherein the rate of writing data is greater than the rate of reading data and not greater than twice the rate of reading data. In the embodiment of the application, the two memories are used for alternately storing data to realize ping-pong operation, so that each memory can have a certain time gap to process unprocessed data, and a low-speed processing module is used for processing a high-speed data stream.

The first Memory and the second Memory may be the same, for example, DDR (Double Data Rate SDRAM ), where SDRAM (Synchronous Dynamic Random Access Memory). In the embodiment of the application, the first memory and the second memory can adopt memories with small storage spaces so as to save cost.

In an alternative embodiment, the input unit may include: and a first selector (MUX) respectively connected with the first memory and the second memory, and used for alternately writing the received data stream into the first memory and the second memory according to an input selection signal. The first selector comprises an input end, two output ends and a selection end, wherein the input end is used for receiving a data stream to be processed, the selection end is used for receiving a selection signal, one output end is connected with the first memory, and the other output end is connected with the second memory.

In yet another alternative embodiment, the input unit may include a logic unit, and the logic unit is configured to alternately write the received data stream into the first memory and the second memory. The logic module may be a logic circuit including two controllable switches, the two controllable switches are both connected to the input interface of the input unit and are connected to the two output interfaces in a one-to-one manner, and the received data stream is alternately written into the first memory and the second memory by alternately controlling the on and off of the two controllable switches.

In one embodiment, the data processing unit may include a data processing unit having multiple I/O (input/Output) ports, and may be capable of reading data from the first memory and the second memory simultaneously for preprocessing. Of course, the data processing unit may also include two data processing units, namely a first data processing unit and a second data processing unit, to reduce the requirement on the I/O capability.

The first data processing unit is connected with the first memory and used for reading data from the first memory for preprocessing, and the processing rate of the first data processing unit (namely the rate of reading data from the first memory) is smaller than the rate of writing data into the first memory.

And the second data processing unit is connected with the second memory and used for reading data from the second memory for preprocessing, and the processing rate of the second data processing unit (namely the rate of reading data from the second memory) is smaller than the rate of writing data into the second memory.

The first data processing Unit and the second data processing Unit may be the same, and may be, for example, a module or a Unit with data processing capability, such as a matrix multiplier, an Arithmetic Logic Unit (ALU), a processor, and the like. The data stream described above may be a stream of image pixels, and accordingly, the preprocessing may be convolution processing, pixel matrix calculation processing, or the like. The specific processes of the convolution process and the pixel matrix calculation process are well known to those skilled in the art and will not be described in detail herein.

In another embodiment, the data processing unit may further include: and the input end of the second selector (MUX) is respectively connected with the first data processing unit and the second data processing unit. The second selector is used for alternately outputting the data output by the first data processing unit and the data output by the second data unit according to the input selection signal. The second selector comprises two input ends, an output end and a selection end, wherein one input end is connected with the first data processing unit, and the other input end is connected with the second data processing unit; the selection end is used for receiving the selection signal, and the output end is used for outputting the data output by the first data processing unit or the data output by the second data unit.

It should be noted that the data stream received by the input unit may be a fragmented data stream (i.e., a data stream that has been fragmented according to a preset size). In an embodiment, the data stream input to the data processing apparatus is a fragmented data stream, and of course, the data stream input to the data processing apparatus is a complete data stream, and at this time, the data processing apparatus may further include a data fragmentation module, configured to sequentially fragment the complete data stream to be processed according to a preset size, and send each fragmented data stream to the input unit according to a fragmentation sequence, so that the input unit alternately stores the received data stream in the first memory and the second memory until all fragmented data streams are stored.

For example, in an embodiment, the preset size may be obtained by obtaining a storage space size of the first memory and a storage space size of the second memory, selecting a storage space with a minimum storage space in the first memory and the second memory, and determining the preset size based on the minimum storage space, so that the segmented data stream may be just stored in the memory (which may be the first memory or the second memory) with the minimum storage space.

The data slicing module may be a commonly used module or unit for slicing data, and may also be a processor or a controller.

In addition, to realize the above functions, corresponding timing signals are required, including a selection signal, a write signal required for writing data in the memory, an address signal, and a read signal and an address signal required for reading data, and the timing signals may be input from the outside or generated by the data processing apparatus itself. If the time sequence is generated by the data processing device, the data processing device also comprises a controller used for generating the time sequence correspondingly.

In one embodiment, the structure of the data processing device may be as shown in fig. 2. It should be noted that the configuration shown in fig. 2 is only one of many embodiments of the data processing apparatus, and the configuration shown in fig. 2 is not to be construed as limiting the present application.

For better understanding, how the above-mentioned data processing apparatus can process a high-speed data stream by using a low-speed processing module is described below with reference to specific examples.

Assuming that the image pixels to be processed are 225 (columns) × 225 (rows) and the spatial sizes of the DDR1 and DDR2 are both 8 (columns) × 225 (rows), assuming a buffering period of 10ms for ping-pong operations, there are:

in the first cycle (10ms), the first selector selects to write the incoming data stream (size 8 x 225) to DDR1, assuming that it takes 10ms to write 8 x 225 data.

In the second cycle (10ms), the data flow is switched to the DDR2, 8 × 225 data is written, and in the second cycle, the DDR2 performs a read operation while 8 × 225 data is written, and the DDR1 outputs the read data to the first data processing unit for preprocessing.

In the third cycle (10ms), the data flow switches to DDR1, writing 8 x 225 data. In the third cycle, the DDR2 performs a read operation while 8 × 225 data is written in the DDR1, and outputs the read data to the second data processing unit for preprocessing.

And then, continuously performing loop operation, reading data from the other DDR when writing data to one DDR, and then sending the data to a subsequent data processing unit for convolution calculation until all input writes are completed. In addition, data is written to the DDR1 and DDR2, and data is also read from the DDR1 and DDR 2. In order to better understand the above-mentioned cyclic process, the above-mentioned process is explained below with reference to the timing chart shown in fig. 3. wr _ mode _ a is a write signal of DDR 1; rd _ mode _ a is a read signal of DDR1, wr _ mode _ b is a write signal of DDR2, and rd _ mode _ b is a read signal of DDR 2. The read signal and the write signal shown above are both active high.

Continuing with the above example, assuming that the data writing rate is 100Mbps and the data reading rate is 50Mbps, that is, the data reading rate of the data processing unit is 50Mbps, and if it takes 10ms to write 8 × 225 data, it takes 20ms to read 8 × 225 data, specifically:

from the 6ms of the first cycle, the DDR1 can write data to the address 4 × 225 and read data from the start address at the same time, and by 10ms, the DDR1 has just written 8 × 225 data, and at this time, the DDR1 reads 5ms of data and reads 2 × 225 data.

In the second cycle, 10ms is required for the DDR2 to write 8 × 225 data, and at this time, 10ms of data is read by the DDR1, plus the previous 5ms, 15ms of data is read, and 6 × 225 data is read; in the first 5ms of the third cycle, data can be read from the address 6 x 225 and later while data is written to the start address for 5ms, and at this time, the data stored in the first cycle of the DDR1 is completely read, which takes 20 ms.

From the 6ms of the third cycle, the DDR1 can read data from the start address while writing data to the addresses 4 × 225 and thereafter, and the above-described process is repeated.

Similarly, in the case of the DDR2, from the 6ms of the second cycle, the DDR2 can write data to the address 4 × 225 and read data from the start address at the same time, and by 10ms, the DDR2 has just written 8 × 225 data, and at this time, the DDR2 has read 5ms of data and read 2 × 225 data. In the third cycle, 10ms is required for the DDR1 to write 8 × 225 data, and in this case, 10ms of data is read by the DDR2, plus the previous 5ms, for 15ms of data, and 6 × 225 data is read. In the first 5ms of the fourth cycle, data can be read from the address 6 x 225 and later while data is written to the start address for 5ms, and at this time, the data stored in the second cycle of the DDR2 is completely read, which takes 20 ms. From the 6ms of the fourth cycle, the DDR2 can read data from the start address while writing data to the addresses 4 × 225 and thereafter, and the above-described process is repeated.

By the above example, it can be seen that the present application can process a high-speed data stream by using a low-speed processing module, for example, a processing module with a rate of 50Mbps to process a 100Mbps high-speed data stream.

It should be noted that the above-mentioned cyclic operation can also be reversed, that is: in the first cycle (assumed to be 10ms), the first selector selects to write the incoming data stream (size 8 x 225) to DDR2, assuming that it takes 10ms to write 8 x 225 data. In the second cycle (10ms), the data flow switches to DDR1, writing 8 x 225 data. In the second cycle, the DDR1 is performing a read operation while 8 × 225 data is being written, and the DDR2 outputs the read data to the second data processing unit for preprocessing. In the third cycle (10ms), the data flow switches to DDR2, writing 8 x 225 data. In the third cycle, the DDR1 performs a read operation while 8 × 225 data is written in the DDR2, and outputs the read data to the first data processing unit for preprocessing. And then, continuously performing loop operation, reading data from the other DDR when writing data to one DDR, and then sending the data to a subsequent data processing unit for convolution calculation until all input writes are completed. At this time, wr _ mode _ a is a write signal of DDR 2; rd _ mode _ a is a read signal of DDR2, wr _ mode _ b is a write signal of DDR1, and rd _ mode _ b is a read signal of DDR 2.

Based on the same inventive concept, the embodiment of the present application further provides an integrated circuit, which includes the data processing apparatus and the main controller. The main controller is used for generating the selection signal, and timing signals required by writing data in and reading data out, such as a read signal, a write signal, an address signal and the like, and in addition, the main controller can also be used for sequentially segmenting the complete data stream to be processed according to a preset size, sending each segmented data stream to the input unit according to the segmentation sequence, acquiring the size of the storage space of the first storage and the size of the storage space of the second storage, selecting the minimum storage space of the storage spaces in the first storage and the second storage, and determining the preset size based on the minimum storage space.

The integrated circuit may be an SOC (System on Chip) circuit, such as an FPGA (Field Programmable Gate Array) circuit.

For the sake of brevity, no mention may be made in part of the embodiments of the integrated circuit, and reference may be made to the corresponding contents in the embodiments of the data processing apparatus described above.

Based on the same inventive concept, the embodiment of the present application further provides an electronic device, which may include the data processing apparatus or the integrated circuit described above. The electronic device may be a computer, server, or the like. It should be noted that, in the embodiment of the electronic device, a data processing apparatus or an integrated circuit that is not described is the same as the corresponding embodiment described above in terms of implementation principle and technical effect, and reference may be made to the corresponding content described above in detail.

Based on the same inventive concept, the present application example further provides a data processing method, and the data processing method provided by the present application embodiment will be described below with reference to fig. 4.

S1: and alternately storing the received data stream to be processed into the first memory and the second memory.

The data processing method may be applied to the data processing apparatus described above, and the input unit in the data processing apparatus alternately stores the received data stream to be processed in the first memory and the second memory.

S2: and continuously reading data from the first memory and the second memory for preprocessing.

The data processing unit in the data processing device can continuously read data from the first memory and the second memory for preprocessing, wherein the rate of writing data is greater than the rate of reading data and is not greater than twice of the rate of reading data. The data stream is a pixel stream of an image to be processed, and the preprocessing is convolution processing.

In an embodiment, the to-be-processed data stream may be a fragmented data stream, or may also be a complete data stream, and if the to-be-processed data stream is a complete data stream, the process of alternately storing the received to-be-processed data stream in the first memory and the second memory may be: sequentially fragmenting the data stream to be processed according to a preset size; and alternately storing each fragment data stream into the first memory and the second memory according to the fragment sequence until all fragment data streams are stored. At this time, the data processing apparatus further includes a data slicing module (which may be a processor or a controller), and may use the data slicing module to slice the complete data stream to be processed in sequence according to a preset size, and send each sliced data stream to the input unit according to a slicing sequence, so that the input unit may store the received data streams in the first memory and the second memory alternately until all the sliced data streams are stored.

Optionally, before sequentially slicing the data stream to be processed according to a preset size, the method further includes: acquiring the size of a storage space of the first storage and the size of a storage space of the second storage; selecting the minimum storage space in the first storage and the second storage, and determining the preset size based on the minimum storage space. The data segmentation module can be used for acquiring the size of the storage space of the first storage and the size of the storage space of the second storage; selecting the minimum storage space in the first storage and the second storage, and determining the preset size based on the minimum storage space.

The data processing method provided in the embodiment of the present application has the same implementation principle and technical effect as the data processing apparatus described above, and for the sake of brief description, reference may be made to the corresponding contents in the foregoing data processing apparatus embodiment where no part of the method embodiment is mentioned.

It should be noted that the method described above may be executed by an electronic device in addition to the data processing apparatus described above.

As shown in fig. 5, fig. 5 is a block diagram illustrating a structure of an electronic device 200 according to an embodiment of the present disclosure. The electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230, and a processor 240.

The elements of the transceiver 210, the memory 220, and the processor 240 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, the components may be electrically coupled to each other via one or more communication buses 230 or signal lines. The transceiver 210 is used for transceiving data. The memory 220 is used for storing a computer program for executing the data processing method, and the computer program comprises at least one software functional module which can be stored in the memory 220 in the form of software or Firmware (Firmware) or solidified in an Operating System (OS) of the electronic device 200. The processor 240 is configured to execute the executable modules stored in the memory 220, and the processor 240 is configured to store the received data stream to be processed alternately into the first memory and the second memory; and continuously reading data from the first memory and the second memory for preprocessing, wherein the rate of writing data is greater than the rate of reading data and is not greater than twice the rate of reading data.

The Memory 220 may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Read-Only Memory (EPROM), an electrically Erasable Read-Only Memory (EEPROM), and the like.

The processor 240 may be an integrated circuit chip having signal processing capabilities. The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor 240 may be any conventional processor or the like.

The electronic device 200 includes, but is not limited to, a computer, a server, and the like.

The present embodiment also provides a non-volatile computer-readable storage medium (hereinafter, referred to as a storage medium), where the storage medium stores a computer program, and the computer program is executed by the computer, such as the electronic device 200, to execute the data processing method described above.

It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solutions of the present application, or portions thereof, may be substantially or partially embodied in the form of a software product stored in a computer-readable storage medium, which includes several instructions for causing a computer device (which may be a personal computer, a notebook computer, a server, or an electronic device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned computer-readable storage media comprise: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A data processing method, comprising:

alternately storing the received data stream to be processed into a first memory and a second memory;

and continuously reading data from the first memory and the second memory for preprocessing, wherein the rate of writing data is greater than the rate of reading data and is not greater than twice the rate of reading data.

2. The method of claim 1, wherein storing the received data stream to be processed alternately into the first memory and the second memory comprises:

sequentially fragmenting the data stream to be processed according to a preset size;

and alternately storing each fragment data stream into the first memory and the second memory according to the fragment sequence until all fragment data streams are stored.

3. The method according to claim 2, wherein before sequentially slicing the data stream to be processed according to a preset size, the method further comprises:

acquiring the size of a storage space of the first storage and the size of a storage space of the second storage;

selecting the minimum storage space in the first storage and the second storage, and determining the preset size based on the minimum storage space.

4. A method according to any one of claims 1 to 3, wherein the data stream is a stream of image pixels to be processed and the pre-processing is convolution processing.

5. A data processing apparatus, comprising:

a first memory and a second memory;

an input unit for alternately writing the received data stream into the first memory and the second memory;

and the data processing unit is used for reading data from the first memory and the second memory without interruption for preprocessing, wherein the rate of writing data is greater than the rate of reading data and is not greater than twice the rate of reading data.

6. The data processing apparatus of claim 5, wherein the input unit comprises:

and the first selector is used for alternately writing the received data stream into the first memory and the second memory according to an input selection signal.

7. The data processing apparatus of claim 5, wherein the data processing unit comprises:

the first data processing unit is connected with the first memory and used for reading data from the first memory for preprocessing, and the processing rate of the first data processing unit is smaller than the rate of writing data into the first memory;

and the second data processing unit is connected with the second memory and used for reading data from the second memory for preprocessing, and the processing rate of the second data processing unit is less than the rate of writing data into the second memory.

8. The data processing apparatus of claim 7, wherein the data processing unit further comprises:

and the input end of the second selector is respectively connected with the first data processing unit and the second data processing unit, and the second selector is used for alternately outputting the data output by the first data processing unit and the data output by the second data processing unit according to an input selection signal.

9. An integrated circuit, characterized in that it integrates a data processing device according to any one of claims 5-8.

10. An electronic device, comprising: a device body and a data processing apparatus as claimed in any one of claims 5 to 8, or an integrated circuit as claimed in claim 9.

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