CN114492288A

CN114492288A - Integrated circuit, design method and design device thereof, electronic device, and storage medium

Info

Publication number: CN114492288A
Application number: CN202210128751.6A
Authority: CN
Inventors: 张孝珩; 朴相敏
Original assignee: Beijing Eswin Computing Technology Co Ltd; Hefei Eswin IC Technology Co Ltd
Current assignee: Beijing Eswin Computing Technology Co Ltd; Hefei Eswin IC Technology Co Ltd
Priority date: 2022-02-11
Filing date: 2022-02-11
Publication date: 2022-05-13

Abstract

An integrated circuit, a design method and a design apparatus thereof, an electronic device, and a storage medium, the design method comprising: acquiring an initial design scheme of an integrated circuit; obtaining an application design scheme of the integrated circuit based on the initial design scheme; in this initial design, the integrated circuit includes a first conductive portion including a plurality of first subsections located in different conductive layers and a second conductive portion including a plurality of second subsections located in different conductive layers; the first conductive part and the second conductive part at least pass through the first adjacent conductive layer and the second adjacent conductive layer; in the stacking direction of the conductive layers, the first sub-portion in the first adjacent conductive layer overlaps both the first sub-portion and the second sub-portion in the second adjacent conductive layer, and the second sub-portion in the first adjacent conductive layer overlaps both the first sub-portion and the second sub-portion in the second adjacent conductive layer. The design method is helpful for saving the research and development cost of obtaining the application design scheme based on the initial design scheme.

Description

Integrated circuit, design method and design device thereof, electronic device, and storage medium

Technical Field

Embodiments of the present disclosure relate to a method of designing an integrated circuit, an integrated circuit designing apparatus, an integrated circuit, an electronic device, and a storage medium.

Background

At present, with the continuous development and progress of chip technology, high speed, high integration, low power consumption and low cost have become the main development direction of the integrated circuit industry, and the performance requirements of the market for chip products are also correspondingly improved, so the design scale and complexity of chips are also greatly increased.

Disclosure of Invention

At least one embodiment of the present disclosure provides a method for designing an integrated circuit, the method comprising: acquiring an initial design scheme of an integrated circuit; obtaining an application design scheme of the integrated circuit based on the initial design scheme; the integrated circuit comprises a plurality of conducting layers, wherein the conducting layers are arranged in a stacked mode, and at least one insulating layer is arranged between every two adjacent conducting layers so that the two adjacent conducting layers are spaced and insulated from each other; in the initial design, the integrated circuit includes a first conductive portion and a second conductive portion insulated from each other, the first conductive portion including a plurality of first sub-portions respectively located in different conductive layers and a first connection portion located between the different conductive layers to connect the plurality of first sub-portions, the second conductive portion including a plurality of second sub-portions respectively located in different conductive layers and a second connection portion located between the different conductive layers to connect the plurality of second sub-portions; the plurality of conductive layers comprise a first adjacent conductive layer and a second adjacent conductive layer which are adjacent, the first conductive part at least passes through the first adjacent conductive layer and the second adjacent conductive layer, and the second conductive part at least passes through the first adjacent conductive layer and the second adjacent conductive layer; in the stacking direction of the first adjacent conductive layer and the second adjacent conductive layer, a first sub-portion of the first adjacent conductive layer at least partially overlaps with a first sub-portion and a second sub-portion of the second adjacent conductive layer, and a second sub-portion of the first adjacent conductive layer at least partially overlaps with the first sub-portion and the second sub-portion of the second adjacent conductive layer.

At least one embodiment of the present disclosure also provides an integrated circuit comprising a plurality of conductive layers; the conductive layers are stacked, and at least one insulating layer is arranged between every two adjacent conductive layers so as to enable the two adjacent conductive layers to be spaced and insulated from each other; the integrated circuit includes a first conductive part and a second conductive part insulated from each other, the first conductive part including a plurality of first sub-parts respectively located in different conductive layers and a first connection part located between the different conductive layers to connect the plurality of first sub-parts, the second conductive part including a plurality of second sub-parts respectively located in different conductive layers and a second connection part located between the different conductive layers to connect the plurality of second sub-parts; the plurality of conductive layers comprise a first adjacent conductive layer and a second adjacent conductive layer which are adjacent, the first conductive part at least passes through the first adjacent conductive layer and the second adjacent conductive layer, and the second conductive part at least passes through the first adjacent conductive layer and the second adjacent conductive layer; in the stacking direction of the first adjacent conductive layer and the second adjacent conductive layer, a first sub-portion of the first adjacent conductive layer at least partially overlaps with a first sub-portion and a second sub-portion of the second adjacent conductive layer, and a second sub-portion of the first adjacent conductive layer at least partially overlaps with the first sub-portion and the second sub-portion of the second adjacent conductive layer.

At least one embodiment of the present disclosure also provides an integrated circuit design apparatus including an initial design solution acquisition unit and an application design solution acquisition unit; the initial design scheme acquisition unit is configured to acquire an initial design scheme of the integrated circuit; the application design scheme acquisition unit is configured to obtain an application design scheme of the integrated circuit based on the initial design scheme; the integrated circuit comprises a plurality of conducting layers, wherein the conducting layers are arranged in a stacked mode, and at least one insulating layer is arranged between every two adjacent conducting layers so that the two adjacent conducting layers are spaced and insulated from each other; in the initial design, the integrated circuit includes a first conductive portion and a second conductive portion insulated from each other, the first conductive portion including a plurality of first sub-portions respectively located in different conductive layers and a first connection portion located between the different conductive layers to connect the plurality of first sub-portions, the second conductive portion including a plurality of second sub-portions respectively located in different conductive layers and a second connection portion located between the different conductive layers to connect the plurality of second sub-portions; the plurality of conductive layers comprise a first adjacent conductive layer and a second adjacent conductive layer which are adjacent, the first conductive part at least passes through the first adjacent conductive layer and the second adjacent conductive layer, and the second conductive part at least passes through the first adjacent conductive layer and the second adjacent conductive layer; in the stacking direction of the first adjacent conductive layer and the second adjacent conductive layer, a first sub-portion of the first adjacent conductive layer at least partially overlaps with a first sub-portion and a second sub-portion of the second adjacent conductive layer, and a second sub-portion of the first adjacent conductive layer at least partially overlaps with the first sub-portion and the second sub-portion of the second adjacent conductive layer.

At least one embodiment of the present disclosure also provides an electronic device comprising a memory and a processor; the memory non-transiently stores computer-executable instructions; the processor is configured to execute the computer-executable instructions, which when executed by the processor implement a method of designing an integrated circuit according to any of the embodiments of the present disclosure.

At least one embodiment of the present disclosure also provides a non-transitory computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement a method of designing an integrated circuit according to any one of the embodiments of the present disclosure.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

Fig. 1 is a schematic flow chart of a method for designing an integrated circuit according to some embodiments of the present disclosure;

FIG. 2 is a schematic diagram of an initial design of an integrated circuit according to some embodiments of the present disclosure;

FIG. 3 is a schematic diagram of an initial design and an application design of an integrated circuit according to some embodiments of the present disclosure;

FIG. 4 is a schematic diagram of an initial design and application design of another integrated circuit provided by some embodiments of the present disclosure;

FIG. 5 is a diagram illustrating an example of an implementation of an initial design of an integrated circuit according to some embodiments of the present disclosure;

FIG. 6A is a schematic plan view of the first adjacent conductive layer of FIG. 5;

fig. 6B is a schematic plan view of a second adjacent conductive layer in fig. 5;

FIG. 6C is a schematic plan view of the third adjacent conductive layer of FIG. 5;

fig. 7 is a schematic diagram of a specific example of a conductive layer in an initial design of an integrated circuit according to some embodiments of the present disclosure;

fig. 8 is a schematic diagram illustrating an arrangement position of a first via and a second via in an initial design of an integrated circuit according to some embodiments of the disclosure;

fig. 9 is a schematic diagram of the arrangement positions of the input interfaces of the first signal and the second signal in the initial design of an integrated circuit according to some embodiments of the disclosure;

FIG. 10 is a schematic diagram of a specific example of an initial design of another integrated circuit provided by some embodiments of the present disclosure;

FIG. 11 is a diagram illustrating an example of an implementation of an initial design of yet another integrated circuit according to some embodiments of the present disclosure;

FIG. 12A is a schematic plan view of the first adjacent conductive layer of FIG. 11;

fig. 12B is a schematic plan view of the second adjacent conductive layer in fig. 11;

fig. 12C is a schematic plan view of the third adjacent conductive layer of fig. 11;

FIG. 12D is a schematic plan view of the fourth adjacent conductive layer of FIG. 11;

FIG. 12E is a schematic diagram illustrating the layout of vias in the same insulating layer in the design of the integrated circuit shown in FIG. 11;

fig. 13 is a schematic diagram of the arrangement positions of the input interfaces and the output interfaces of the first signal and the second signal in the initial design scheme of the integrated circuit according to some embodiments of the present disclosure;

FIG. 14 is a schematic diagram of a specific example of an initial design of yet another integrated circuit provided by some embodiments of the present disclosure;

FIG. 15 is a schematic block diagram of an integrated circuit design apparatus provided in some embodiments of the present disclosure;

fig. 16 is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure;

fig. 17 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure; and

fig. 18 is a schematic diagram of a storage medium according to some embodiments of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

With the rapid development of the integrated circuit industry, the scale and complexity of circuit design is increasing. In the process of developing an integrated circuit, a designed original circuit layout is usually required to be modified to meet different practical application requirements or solve possible bad problems in circuit design. However, under the condition that the design scale of the integrated circuit is large and the layout design is complex, the modification process may need to modify the layout design of a plurality of film layers in the integrated circuit, the modification amount is large and the time spent is often large, and meanwhile, a new mask plate for preparing the plurality of film layers may need to be prepared again, thereby greatly increasing the development cost.

At least one embodiment of the present disclosure provides a method for designing an integrated circuit, the method comprising: acquiring an initial design scheme of an integrated circuit; obtaining an application design scheme of the integrated circuit based on the initial design scheme; the integrated circuit comprises a plurality of conductive layers, wherein the conductive layers are mutually stacked, and at least one insulating layer is arranged between every two adjacent conductive layers so as to enable the two adjacent conductive layers to be spaced and insulated from each other; in an initial design, an integrated circuit includes a first conductive portion and a second conductive portion insulated from each other, the first conductive portion including a plurality of first sub-portions respectively located in different conductive layers and a first connection portion located between the different conductive layers to connect the plurality of first sub-portions, the second conductive portion including a plurality of second sub-portions respectively located in the different conductive layers and a second connection portion located between the different conductive layers to connect the plurality of second sub-portions; the plurality of conductive layers comprise a first adjacent conductive layer and a second adjacent conductive layer which are adjacent, the first conductive part at least passes through the first adjacent conductive layer and the second adjacent conductive layer, and the second conductive part at least passes through the first adjacent conductive layer and the second adjacent conductive layer; in the stacking direction of the first adjacent conductive layer and the second adjacent conductive layer, the first sub-portion of the first adjacent conductive layer at least partially overlaps with the first sub-portion and the second sub-portion of the second adjacent conductive layer, and the second sub-portion of the first adjacent conductive layer at least partially overlaps with the first sub-portion and the second sub-portion of the second adjacent conductive layer.

The design method of the integrated circuit provided by the above embodiments of the present disclosure can be applied to the design and development of integrated circuits with different circuit structures or different layout designs, for example, chip design and chip development.

In the method for designing an integrated circuit provided by the above-mentioned embodiments of the present disclosure, by designing the first sub-portion of the first adjacent conductive layer to at least partially overlap with both the first sub-portion and the second sub-portion of the second adjacent conductive layer, and designing the second sub-portion of the first adjacent conductive layer to at least partially overlap with both the first sub-portion and the second sub-portion of the second adjacent conductive layer, in the initial design scheme of the integrated circuit provided, it is possible to reduce the number of conductive layers and insulating layers that need to be modified in the integrated circuit when the manner of connection between the first sub-portion of the first conductive portion and the first connection portion and the manner of connection between the second sub-portion of the second conductive portion and the second connection portion need to be adjusted or modified. Furthermore, the amount of change and the time required to be spent in the process of adjusting or modifying the layout structure in the initial design scheme based on the integrated circuit to obtain the application design scheme can be reduced, so that the research and development cost of the integrated circuit is reduced, and the research and development efficiency is improved.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different figures will be used to refer to the same elements that have been described.

Fig. 1 is a schematic flow chart of a design method of an integrated circuit according to some embodiments of the present disclosure, and fig. 2 is a schematic diagram of an initial design scheme of an integrated circuit according to some embodiments of the present disclosure.

Referring to fig. 1 and fig. 2, a method for designing an integrated circuit according to an embodiment of the present disclosure includes steps S11 and S12.

Step S11: an initial design solution for an integrated circuit is obtained.

Step S12: and obtaining an application design scheme of the integrated circuit based on the initial design scheme.

Taking the initial design of the integrated circuit shown in fig. 2 as an example, the integrated circuit includes a plurality of conductive layers including, for example, a first adjacent conductive layer 101, a second adjacent conductive layer 102, and a third adjacent conductive layer 103 shown in fig. 2, and a plurality of insulating layers including, for example, a first insulating layer 111 between the first adjacent conductive layer 101 and the second adjacent conductive layer 102 and a second insulating layer 112 between the second adjacent conductive layer 102 and the third adjacent conductive layer 103 shown in fig. 2.

As shown in fig. 2, a plurality of conductive layers are stacked on each other, and an insulating layer is disposed between every two adjacent conductive layers to space and insulate the two adjacent conductive layers from each other. For example, the first adjacent conductive layer 101 and the second adjacent conductive layer 102 may be two adjacent conductive layers, or the second adjacent conductive layer 102 and the third adjacent conductive layer 103 may also be two adjacent conductive layers. Taking the first adjacent conductive layer 101 and the second adjacent conductive layer 102 as an example, the first adjacent conductive layer 101 and the second adjacent conductive layer 102 are stacked on each other in a direction R1, that is, the direction R1 is a stacking direction of the first adjacent conductive layer 101 and the second adjacent conductive layer 102; the first insulating layer 111 is located between the first adjacent conductive layer 101 and the second adjacent conductive layer 102 to space and insulate the first adjacent conductive layer 101 and the second adjacent conductive layer 102 from each other.

It should be noted that, the embodiment of the present disclosure takes the initial design scheme of the integrated circuit shown in fig. 2 as an example to describe the design method of the integrated circuit provided in the embodiment of the present disclosure, but the embodiment of the present disclosure includes but is not limited thereto. For example, in the initial design of the integrated circuit shown in fig. 2, three conductive layers and two insulating layers respectively located between two adjacent conductive layers are shown, that is, a first adjacent conductive layer 101, a second adjacent conductive layer 102 and a third adjacent conductive layer 103, and a first insulating layer 111 and a second insulating layer 112; in some other embodiments of the present disclosure, the number of the conductive layers in the initial design of the integrated circuit may also be 2, 4, 5 or more, and accordingly, the number of the insulating layers may also be 1, 3, 4 or more, and the number of the insulating layers between two adjacent conductive layers may also be 2, 3, 4 or more, and the like, which is not particularly limited by the embodiments of the present disclosure.

As shown in fig. 2, in this initial design, the integrated circuit includes a first conductive portion 130 and a second conductive portion 140 that are insulated from each other. The first conductive part 130 includes a plurality of first sub-parts 131 respectively located in different conductive layers and a first connection part 132 located between the different conductive layers to connect the plurality of first sub-parts 131, for example, the first connection part 132 penetrates at least the insulating layer located between the different conductive layers. The second conductive part 140 includes a plurality of second sub-parts 141 respectively located in different conductive layers, and a second connection part 142 located between the different conductive layers to connect the plurality of second sub-parts 141, for example, the second connection part 142 penetrates at least the insulating layer located between the different conductive layers.

For example, regarding step S11 above, taking the first adjacent conductive layer 101 and the second adjacent conductive layer 102 shown in fig. 2 as an example, in the initial design of the integrated circuit 10, the first conductive part 130 passes through at least the first adjacent conductive layer 101 and the second adjacent conductive layer 102, for example, the first conductive part 130 includes at least a first sub-part 131 located in the first adjacent conductive layer 101 and a first sub-part 131 located in the second adjacent conductive layer 102; the second conductive part 140 passes through at least the first adjacent conductive layer 101 and the second adjacent conductive layer 102, for example, the second conductive part 140 includes at least a second sub-part 141 located in the first adjacent conductive layer 101 and a second sub-part 141 located in the second adjacent conductive layer 102; in the stacking direction R1 of the first adjacent conductive layer 101 and the second adjacent conductive layer 102, an overlap is generated between the first sub-portion 131 in the first adjacent conductive layer 101 and the first sub-portion 131 and the second sub-portion 141 in the second adjacent conductive layer 102, and an overlap is generated between the second sub-portion 141 in the first adjacent conductive layer 101 and the first sub-portion 131 and the second sub-portion 141 in the second adjacent conductive layer 102; that is, in the stacking direction R1, an overlap is generated between the first sub-portion 131 of the second adjacent conductive layer 102 and each of the first sub-portion 131 and the second sub-portion 141 of the first adjacent conductive layer 101, and an overlap is generated between the second sub-portion 141 of the second adjacent conductive layer 102 and each of the first sub-portion 131 and the second sub-portion 141 of the first adjacent conductive layer 101.

Therefore, in the case of satisfying the initial design scheme that the first sub-portion 131 of the first adjacent conductive layer 101 overlaps with both the first sub-portion 131 and the second sub-portion 141 of the second adjacent conductive layer 102 in the stacking direction R1, and the second sub-portion 141 of the first adjacent conductive layer 101 overlaps with both the first sub-portion 131 and the second sub-portion 141 of the second adjacent conductive layer 102 in the stacking direction R1, the numbers of the conductive layers and the insulating layers that need to be modified in the integrated circuit can be reduced to obtain a desired application design scheme according to different practical design or application requirements, for example, when the connection manner in the first conductive portion 130 and the second conductive portion 140 needs to be adjusted or modified based on the initial design scheme shown in fig. 2. Furthermore, the amount of change and the time required to be spent in the process of obtaining the application design scheme based on the initial design scheme can be reduced, and the number of corresponding new mask plates which need to be redesigned or prepared can be reduced, so that the research and development cost of the integrated circuit is reduced, and the research and development efficiency is improved.

For example, the obtained new application design may also continue to satisfy the respective arrangement conditions in the first adjacent conductive layer 101, the second adjacent conductive layer 102 and the first insulating layer 111 for the first conductive part 130 and the second conductive part 140 in the initial design, that is, the application design may be the same as the initial design. For example, the application design may include: in the stacking direction R1, the first sub-portion 131 of the first adjacent conductive layer 101 overlaps with the first sub-portion 131 and the second sub-portion 141 of the second adjacent conductive layer 102, and the second sub-portion 141 of the first adjacent conductive layer 101 overlaps with the first sub-portion 131 and the second sub-portion 141 of the second adjacent conductive layer 102.

Therefore, in subsequent design, according to different actual requirements, under the condition that the obtained application design scheme needs to be continuously changed to obtain a new design scheme, the obtained application design scheme can be continuously adjusted as a new initial design scheme. Furthermore, the amount of modification and the time required to be spent in the process of changing for many times based on the initial design scheme can be reduced, and the number of corresponding new mask plates which need to be redesigned or prepared is reduced, so that the research and development cost of the integrated circuit is further reduced, and the research and development efficiency is improved.

For example, the application design scheme may further include the same or similar conditions as those in the initial design scheme for other arrangements of the first conductive part 130 and the second conductive part 140 in the first adjacent conductive layer 101, the second adjacent conductive layer 102, and the first insulating layer 111, and specific contents may refer to corresponding descriptions about the initial design scheme, and repeated parts are not repeated.

For example, the first sub-portion 131 and the second sub-portion 141 of the first adjacent conductive layer 101 are spaced and insulated from each other, and are disposed in a central symmetry manner with respect to the first reference point N1. The first sub-portion 131 and the second sub-portion 141 of the second adjacent conductive layer 102 are spaced and insulated from each other, and are disposed in a central symmetry manner with respect to the second reference point N2.

It should be noted that, in order to clearly show the relative positions and overlapping relationships of the first sub-portion 131 and the second sub-portion 141 in the different conductive layers in the stacking direction R1, the first sub-portion 131 and the second sub-portion 141 in the same layer in the initial design shown in fig. 2 are only divided by the "S" shaped curve, but it should be understood that the first sub-portion 131 and the second sub-portion 141 in the same layer in the initial design shown in fig. 2 are spaced and insulated from each other, and the specific layout implementation manner thereof may refer to the corresponding description in the specific example shown in fig. 5 and fig. 11.

Note that the first reference point N1, the second reference point N2, and other reference points (for example, the third reference point N3, the fourth reference point N4, and the fifth reference point N5) mentioned later are only for clearly explaining the corresponding positional relationships, and do not actually exist in the actual structure of the integrated circuit.

As shown in fig. 2, for the first insulating layer 111 located between the first adjacent conductive layer 101 and the second adjacent conductive layer 102, the first insulating layer 111 includes a first via H1 and a second via H2, and the first via H1 and the second via H2 penetrate through the first insulating layer 111 and are respectively used for providing the first connection portion 132 and the second connection portion 142. For example, in the initial design shown in fig. 2, the first via H1 is used to provide the first connection portion 132, and the second via H2 is used to provide the second connection portion 142. In the first insulating layer 111, the first via hole H1 and the second via hole H2 are disposed in central symmetry with respect to the third reference point N3, that is, the first via hole H1 and the second via hole H2 are located on the same straight line passing through the third reference point N3.

For example, the number of the first vias H1 is the same as the number of the second vias H2. It should be noted that, in the embodiment shown in fig. 2, the number of the first vias H1 and the number of the second vias H2 are both 1; in other embodiments of the present disclosure, the number of the first vias H1 and the number of the second vias H2 may also be 2, 3, 4 or more, and the like, which is not particularly limited by the embodiments of the present disclosure.

The first reference point N1, the second reference point N2, and the third reference point N3 overlap with each other in the stacking direction R1 of the first adjacent conductive layer 101 and the second adjacent conductive layer 102, that is, the first reference point N1, the second reference point N2, and the third reference point N3 are located on the same straight line extending in the stacking direction R1. Therefore, it is possible to reduce the amount of modification required to be made in each of the conductive layers and the insulating layers in the process of obtaining a new application design based on the initial design, and it is also possible to reduce the layout space required to be occupied by the first conductive part 130 and the second conductive part 140 in the first adjacent conductive layer 101, the second adjacent conductive layer 102 and the first insulating layer 111 in the integrated circuit as a whole, thereby facilitating optimization of the structural design of the integrated circuit.

For example, in the embodiment shown in fig. 2, the third adjacent conductive layer 103 is located on a side of the second adjacent conductive layer 102 away from the first adjacent conductive layer 101. The first and second conductive portions 130 and 140 also pass through the third adjacent conductive layer 103, i.e., the first conductive portion 130 also includes a first sub-portion 131 located in the third adjacent conductive layer 103, and the second conductive portion 140 also includes a second sub-portion 141 located in the third adjacent conductive layer 103. In the stacking direction R1 of the first adjacent conductive layer 101, the second adjacent conductive layer 102, and the third adjacent conductive layer 103, the first sub-portion 131 of the second adjacent conductive layer 102 overlaps with the first sub-portion 131 and the second sub-portion 141 of the third adjacent conductive layer 103, the second sub-portion 141 of the second adjacent conductive layer 102 overlaps with the first sub-portion 131 and the second sub-portion 141 of the third adjacent conductive layer 103, that is, the first sub-portion 131 of the third adjacent conductive layer 103 overlaps with the first sub-portion 131 and the second sub-portion 141 of the second adjacent conductive layer 102, and the second sub-portion 141 of the third adjacent conductive layer 103 overlaps with the first sub-portion 131 and the second sub-portion 141 of the second adjacent conductive layer 102.

For example, the first sub-portion 131 and the second sub-portion 141 of the third adjacent conductive layer 103 are spaced and insulated from each other, and are disposed in a central symmetry manner with respect to the fourth reference point N4. For the second insulating layer 112 located between the second adjacent conductive layer 102 and the third adjacent conductive layer 103, the second insulating layer 112 includes a third via H3 and a fourth via H4, and the third via H3 and the fourth via H4 penetrate through the second insulating layer 112 and are used for providing the first connection portion 132 and the second connection portion 142. For example, in the initial design shown in fig. 2, the third via H3 is used to provide the first connection portion 132, and the fourth via H4 is used to provide the second connection portion 142. The third via hole H3 and the fourth via hole H4 are arranged in central symmetry with respect to the fifth reference point N5, that is, the third via hole H3 and the fourth via hole H4 are located on the same straight line passing through the fifth reference point N5. The first reference point N1, the second reference point N2, the third reference point N3, the fourth reference point N4, and the fifth reference point N5 overlap with each other in the stacking direction R1, that is, the first reference point N1, the second reference point N2, the third reference point N3, the fourth reference point N4, and the fifth reference point N5 are located on the same straight line extending in the stacking direction R1.

For the above-mentioned specific arrangement and connection manner of the first sub-portion 131 and the second sub-portion 141 of the second adjacent conductive layer 102 and the third adjacent conductive layer 103, reference may be made to the above corresponding description of the first adjacent conductive layer 101 and the second adjacent conductive layer 102, and repeated points are not repeated herein.

For example, the number of the third vias H3 is the same as the number of the fourth vias H4. It should be noted that, in the embodiment shown in fig. 2, the number of the third vias H3 and the number of the fourth vias H4 are both 1; in some other embodiments of the present disclosure, the number of the third vias H3 and the number of the fourth vias H4 may also be 2, 3, 4 or more, and the like, and the number of the third vias H3 and the number of the fourth vias H4 may be the same as the number of the first vias H1 and the number of the second vias H2, or may be different from the number of the first vias H1 and the number of the second vias H2, which is not limited in this embodiment of the present disclosure.

For example, as shown in fig. 2, in the stacking direction R1, no overlap is generated between the first via H1 in the first insulating layer 111 and the third and fourth vias H3 and H4 in the second insulating layer 112, and no overlap is generated between the second via H2 in the first insulating layer 111 and the third and fourth vias H3 and H4 in the second insulating layer 112. That is, in the stacking direction R1, the first via H1, the second via H2, the third via H3, and the fourth via H4 do not overlap each other.

For example, in some embodiments, the above step S12 includes the following step S121.

Step S121: and selecting any one of the first adjacent conducting layer, the second adjacent conducting layer and the first insulating layer to carry out layout adjustment so as to obtain an application design scheme.

Regarding the step S12, taking the initial design scheme of the integrated circuit shown in fig. 2 as an example, in the case where the initial design scheme is satisfied that the first sub-portion 131 in the first adjacent conductive layer 101 is designed to overlap with both the first sub-portion 131 and the second sub-portion 141 in the second adjacent conductive layer 102 in the stacking direction R1, and the second sub-portion 141 in the first adjacent conductive layer 101 is designed to overlap with both the first sub-portion 131 and the second sub-portion 141 in the second adjacent conductive layer 102 in the stacking direction R1, based on the initial design scheme, only any one of the first adjacent conductive layer 101, the second adjacent conductive layer 102, and the first insulating layer 111 is modified, so as to obtain a corresponding application design scheme. Furthermore, the amount of change and the time required to be spent in the process of obtaining the application design scheme based on the initial design scheme can be reduced, and the number of corresponding new mask plates which need to be redesigned or prepared can be reduced, so that the research and development cost of the integrated circuit is reduced, and the research and development efficiency is improved.

It should be noted that, in some other embodiments of the present disclosure, only the third conductive layer 103 or the second insulating layer 112 shown in fig. 2 may be modified to obtain a corresponding application design, that is, only any one of the first adjacent conductive layer 101, the second adjacent conductive layer 102, the third conductive layer 103, the first insulating layer 111, and the second insulating layer 112 may be modified to obtain a desired application design.

In the following, taking the initial design shown in fig. 2 as an example, an implementation process of obtaining an application design based on the initial design is exemplarily described. However, it should be noted that the embodiments of the present disclosure include but are not limited thereto.

Fig. 3 is a schematic diagram of an initial design scheme and an application design scheme of an integrated circuit according to some embodiments of the present disclosure, and fig. 4 is a schematic diagram of an initial design scheme and an application design scheme of another integrated circuit according to some embodiments of the present disclosure. For example, the initial design of the integrated circuit is shown on the left side of fig. 3, and the application design based on the initial design is shown on the right side; the initial design of the integrated circuit is shown on the left side of fig. 4, and the application design based on this initial design is shown on the right side. It should be noted that the initial design shown in fig. 3 and 4 is substantially the same as the initial design shown in fig. 2 except for including the first input interface inp 1, the first output interface OUTPT1, the second input interface inp 2, and the second output interface OUTPT2, and repeated descriptions are omitted.

For example, as shown in fig. 3 and 4, first conductive portion 130 may be used to transmit a first signal and second conductive portion 140 may be used to transmit a second signal different from the first signal. For example, a first signal may be transmitted from the input interface inp 1 through the first conductive portion 130 to the corresponding output interface OUTPT1, and a second signal may be transmitted from the input interface inp 2 through the second conductive portion 140 to the corresponding output interface OUTPT 2.

For example, the first signal input interface inp 1 and the second signal input interface inp 2 are disposed in the same conductive layer, for example, in the third adjacent conductive layer 103, and the first signal input interface inp 1 and the second signal input interface inp 2 are disposed in central symmetry with respect to the fourth reference point N4, for example. The output interface OUTPT1 for the first signal and the output interface OUTPT2 for the second signal are disposed in the same conductive layer, for example, in the first adjacent conductive layer 101, and the output interface OUTPT1 for the first signal and the output interface OUTPT2 for the second signal are disposed in central symmetry with respect to the first reference point N1, for example.

It should be noted that, in some other examples or embodiments of the present disclosure, the input interface inp 1 for the first signal and the input interface inp 2 for the second signal may also be located in different conductive layers, respectively; the output interface OUTPT1 for the first signal and the output interface OUTPT2 for the second signal may also be located in different conductive layers, respectively; the input interface inp 1 and the output interface OUTPT1 of the first signal and the input interface inp 2 and the output interface OUTPT2 of the second signal may also be located in other conductive layers, for example, other conductive layers in an integrated circuit besides the first adjacent conductive layer 101, the second adjacent conductive layer 102, and the third adjacent conductive layer 103 shown in fig. 3 and fig. 4, which is not limited in this respect by the embodiments of the present disclosure.

For example, taking as an example that the setting positions of the input interface inp 1 for the first signal and the input interface inp 2 for the second signal in the initial design scheme need to be adjusted, for example, the positions are reversed, so as to obtain a new application design scheme, as shown in fig. 3, the first insulating layer 111 may be selected for layout adjustment to obtain a corresponding application design scheme based on the provided initial design scheme. For example, in the example shown in fig. 3, the step S121 may include: based on the original layout structure in the first insulating layer 111, an application layout structure is obtained after planar rotation with respect to the original layout structure of the first insulating layer 111.

For example, as shown in fig. 3, the positions of the first via H1 and the second via H2 in the first insulating layer 111 are adjusted by performing planar rotation on the original layout structure of the first insulating layer 111, so that the connection manner of the first conductive part 130 and the second conductive part 140 in the first adjacent conductive layer 101, the second adjacent conductive layer 102, and the first insulating layer 111 changes. For example, as shown in fig. 3, due to the position change of the first via H1 and the second via H2 in the first insulating layer 111, the first sub-portion 131 and the second sub-portion 141 of the second adjacent conductive layer 102 in the initial design scheme are interchanged, that is, the first sub-portion 131 originally used for transmitting the first signal in the second adjacent conductive layer 102 becomes the second sub-portion 141 used for transmitting the second signal, and the second sub-portion 141 originally used for transmitting the second signal becomes the first sub-portion 131 used for transmitting the first signal. Furthermore, when the positions of the third via H3 and the second via H4 in the second insulating layer 112 are not changed, the first sub-portion 131 and the second sub-portion 141 in the third adjacent conductive layer 103 are also exchanged, that is, the first sub-portion 131 originally used for transmitting the first signal in the third adjacent conductive layer 103 is changed to the second sub-portion 141, and the second sub-portion 141 originally used for transmitting the second signal is changed to the first sub-portion 131, so that the requirement of changing the installation positions of the input interface inp 1 for the first signal and the input interface inp 2 for the second signal can be satisfied.

Therefore, based on the initial design scheme shown in fig. 3, when the arrangement positions of the input interface inp 1 for the first signal and the input interface inp 2 for the second signal need to be adjusted or modified according to actual design or application requirements, the corresponding application design scheme can be obtained by only adjusting the via layout structure in the first insulating layer 111. Furthermore, the number of conducting layers and insulating layers which need to be changed in the integrated circuit can be reduced, the change amount and the time which need to be spent in the process of obtaining the corresponding application design scheme based on the initial design scheme can be reduced, and meanwhile, the number of corresponding new mask plates which need to be redesigned or prepared can be reduced, so that the research and development cost of the integrated circuit is reduced, and the research and development efficiency is improved.

For another example, as shown in fig. 4, the second adjacent conductive layer 102 may be selected for layout adjustment based on the provided initial design to obtain a corresponding application design. For example, in the example shown in fig. 4, the step S121 may include: based on the original layout structure in the second adjacent conductive layer 102, an applied layout structure is obtained after plane inversion relative to the original layout structure of the second adjacent conductive layer 102 or mirror image relative to the original layout structure of the second adjacent conductive layer 102 and plane rotation.

For example, as shown in fig. 4, after performing plane inversion or mirror image and plane rotation on the original layout structure of the second adjacent conductive layer 102, the connection manner of the first conductive part 130 and the second conductive part 140 in the second adjacent conductive layer 102, the third adjacent conductive layer 103 and the second insulating layer 112 can be changed. For example, as shown in fig. 4, due to the change of the positions of the first sub-portion 131 and the second sub-portion 141 in the second adjacent conductive layer 102, the connection function of the third via H3 and the fourth via H4 in the second insulating layer 112 in the initial design is changed, that is, the third via H3 originally used for transmitting the first signal in the second insulating layer 112 is changed to transmit the second signal, and the fourth via H4 originally used for transmitting the second signal is changed to transmit the first signal. Furthermore, when the layout structure of the third adjacent conductive layer 103 is not changed, the first sub-part 131 and the second sub-part 141 in the third adjacent conductive layer 103 are also exchanged, that is, the first sub-part 131 originally used for transmitting the first signal in the third adjacent conductive layer 103 is changed to the second sub-part 141, and the second sub-part 141 originally used for transmitting the second signal is changed to the first sub-part 131, so that the requirement of changing the installation positions of the input interface inp 1 for the first signal and the input interface inp 2 for the second signal can be satisfied.

Therefore, based on the initial design scheme shown in fig. 4, when the arrangement positions of the input interface inp 1 for the first signal and the input interface inp 2 for the second signal need to be adjusted or modified according to actual design or application requirements, the layout structure of the second adjacent conductive layer 102 can be adjusted, so that the corresponding application design scheme can be obtained. Furthermore, the number of conducting layers and insulating layers which need to be changed in the integrated circuit can be reduced, the change amount and the time which need to be spent in the process of obtaining the corresponding application design scheme based on the initial design scheme can be reduced, and meanwhile, the number of corresponding new mask plates which need to be redesigned or prepared can be reduced, so that the research and development cost of the integrated circuit is reduced, and the research and development efficiency is improved.

For example, taking the examples shown in fig. 3 and fig. 4 as an example, the obtained new application design scheme may also continuously satisfy the respective setting conditions in the first adjacent conductive layer 101, the second adjacent conductive layer 102, the third adjacent conductive layer 103, the first insulating layer 111, and the second insulating layer 112 for the first conductive part 130 and the second conductive part 140 in the initial design scheme, that is, the application design scheme may include: in the stacking direction R1, the first sub-portion 131 of the first adjacent conductive layer 101 overlaps with the first sub-portion 131 and the second sub-portion 141 of the second adjacent conductive layer 102, and the second sub-portion 141 of the first adjacent conductive layer 101 overlaps with the first sub-portion 131 and the second sub-portion 141 of the second adjacent conductive layer 102.

For example, the application design may further include: in the stacking direction R1, the first sub-portion 131 of the second adjacent conductive layer 102 overlaps with both the first sub-portion 131 and the second sub-portion 141 of the third adjacent conductive layer 103, and the second sub-portion 141 of the second adjacent conductive layer 102 overlaps with both the first sub-portion 131 and the second sub-portion 141 of the third adjacent conductive layer 103.

Therefore, in subsequent design, according to different actual requirements, under the condition that the obtained application design scheme needs to be continuously changed to obtain a new design scheme, the obtained application design scheme can be continuously adjusted as a new initial design scheme. Furthermore, the amount of change and the time required to be spent in the process of changing for many times based on the initial design scheme can be reduced, and the number of corresponding new mask plates which need to be redesigned or prepared is reduced, so that the research and development cost of the integrated circuit is further reduced, and the research and development efficiency is improved.

For example, the application design scheme may further include the same or similar conditions as those in the initial design scheme for other settings of the first conductive part 130 and the second conductive part 140 in the first adjacent conductive layer 101, the second adjacent conductive layer 102, the third adjacent conductive layer 103, the first insulating layer 111, and the second insulating layer 112, and specific contents may refer to corresponding descriptions about the initial design scheme, and repeated parts are not described again.

In some embodiments of the present disclosure, an orthogonal projection of the first sub-section 131 and the second sub-section 141 in the first adjacent conductive layer 101 as a whole in a reference plane perpendicular to the lamination direction R1 of the first adjacent conductive layer 101 and the second adjacent conductive layer 102 is different from an orthogonal projection of the first sub-section 131 and the second sub-section 141 in the second adjacent conductive layer 102 as a whole in the reference plane. That is, in the stacking direction R1, the pattern formed by the first sub-section 131 and the second sub-section 141 in the first adjacent conductive layer 101 as a whole and the pattern formed by the first sub-section 131 and the second sub-section 141 in the second adjacent conductive layer 102 as a whole do not completely overlap. Therefore, it is possible to facilitate the corresponding application design by only modifying any one of the first adjacent conductive layer 101, the second adjacent conductive layer 102, and the first insulating layer 111.

For example, further, the orthogonal projections of the first sub-section 131 and the second sub-section 141 in the second adjacent conductive layer 102 as a whole in a reference plane, which is perpendicular to the stacking direction R1, and the orthogonal projections of the first sub-section 131 and the second sub-section 141 in the third adjacent conductive layer 103 as a whole in the reference plane are different from each other. That is, in the stacking direction R1, the pattern of the first sub-section 131 and the second sub-section 141 in the second adjacent conductive layer 102 as a whole and the pattern of the first sub-section 131 and the second sub-section 141 in the third adjacent conductive layer 103 as a whole cannot completely overlap each other.

The following specifically describes embodiments of the present disclosure by taking different specific implementations of the initial design schemes of the integrated circuits shown in fig. 5 and fig. 11 as examples. For example, the examples shown in fig. 5 and fig. 11 may be specific implementations of the initial design scheme of the integrated circuit shown in fig. 2, and reference may be made to corresponding contents in the embodiment shown in fig. 2, and repeated descriptions are omitted.

Fig. 5 is a schematic diagram of an implementation example of an initial design scheme of an integrated circuit according to some embodiments of the present disclosure, fig. 6A is a schematic plan view of a first adjacent conductive layer in fig. 5, fig. 6B is a schematic plan view of a second adjacent conductive layer in fig. 5, and fig. 6C is a schematic plan view of a third adjacent conductive layer in fig. 5.

For example, as shown in fig. 5 and fig. 6A to 6C, a first spacing region RG1 is disposed between the first sub-portion 131 and the second sub-portion 141 of the first adjacent conductive layer 101, and the first reference point N1 is a center of the first spacing region RG 1. A second spacing region RG2 is disposed between the first sub-portion 131 and the second sub-portion 141 of the second adjacent conductive layer 102, and a second reference point N2 is a center of the second spacing region RG 2. A third spacing region RG3 is disposed between the first sub-portion 131 and the second sub-portion 141 of the third adjacent conductive layer 103, and a third reference point N3 is a center of the third spacing region RG 3.

For example, an area surrounded by orthogonal projections of the first sub-portion 131 and the second sub-portion 141 in the first adjacent conductive layer 101 in the reference plane has the same size and shape as an area surrounded by orthogonal projections of the first sub-portion 131 and the second sub-portion 141 in the second adjacent conductive layer 101 in the reference plane. For example, the reference plane may be parallel to a plane in which the first adjacent conductive layer 101 or the second adjacent conductive layer 102 is located. For example, the first sub-portion 131 and the second sub-portion 141 of the first adjacent conductive layer 101 form a square profile as a whole in the reference plane, and the first sub-portion 131 and the second sub-portion 141 of the second adjacent conductive layer 102 form a square profile as a whole in the reference plane, and the two square profiles have the same size and shape.

For example, an area surrounded by orthogonal projections of the first sub-portion 131 and the second sub-portion 141 in the second adjacent conductive layer 102 in the reference plane has the same size and shape as an area surrounded by orthogonal projections of the first sub-portion 131 and the second sub-portion 141 in the third adjacent conductive layer 103 in the reference plane. For example, the first sub-portion 131 and the second sub-portion 141 of the second adjacent conductive layer 102 form a square profile as a whole in the reference plane, and the first sub-portion 131 and the second sub-portion 141 of the third adjacent conductive layer 103 form a square profile as a whole in the reference plane, and the two square profiles have the same size and shape.

Thus, in the case where the first reference point N1, the second reference point N2, and the third reference point N3 overlap each other in the stacking direction R1, the layout space required to be occupied in the integrated circuit as a whole by the first sub-section 131 and the second sub-section 141 in the first adjacent conductive layer 101, the second adjacent conductive layer 102, and the third adjacent conductive layer 103 can be reduced, thereby facilitating optimization of the structural design of the integrated circuit.

For example, the size and shape of the area surrounded by the orthographic projection of the first sub-portion 131 in the first adjacent conductive layer 101 in the reference plane are the same as those of the area surrounded by the orthographic projection of the first sub-portion 131 in the second adjacent conductive layer 102 in the reference plane, for example, all of the areas are "L" shaped patterns with the same size. The size and shape of the area surrounded by the orthogonal projection of the second sub-portion 141 in the first adjacent conductive layer 101 in the reference plane are the same as those of the area surrounded by the orthogonal projection of the second sub-portion 141 in the second adjacent conductive layer 102 in the reference plane, for example, the size and shape of the "L" shaped pattern are the same. Therefore, the preparation process of the integrated circuit is facilitated to be simplified, and the research and development cost of the integrated circuit is reduced.

For example, the size and shape of the area surrounded by the orthographic projection of the first sub-portion 131 in the third adjacent conductive layer 103 in the reference plane are the same as those of the area surrounded by the orthographic projection of the first sub-portion 131 in the second adjacent conductive layer 102 in the reference plane, and are all "L" shaped patterns having the same size. The size and shape of the area surrounded by the orthogonal projection of the second sub-portion 141 in the third adjacent conductive layer 103 in the reference plane are the same as those of the area surrounded by the orthogonal projection of the second sub-portion 141 in the second adjacent conductive layer 102 in the reference plane, and are, for example, "L" shaped patterns having the same size.

For example, the overall pattern of the first sub-portion 131 and the second sub-portion 141 of the first adjacent conductive layer 101 is a center-symmetrical double L-shaped pattern, the overall pattern of the first sub-portion 131 and the second sub-portion 141 of the second adjacent conductive layer 102 is a center-symmetrical double L-shaped pattern, and the overall pattern of the first sub-portion 131 and the second sub-portion 141 of the third adjacent conductive layer 103 is a center-symmetrical double L-shaped pattern.

It should be noted that, taking the initial design shown in fig. 5 as an example, the first sub-portion 131 and the second sub-portion 141 of each of the first adjacent conductive layer 101, the second adjacent conductive layer 102, and the third adjacent conductive layer 103 may also adopt other suitable layout designs, and the embodiment of the present disclosure is not particularly limited thereto.

For example, in a case where the overall pattern of the first sub-portion 131 and the second sub-portion 141 in each conductive layer is made to be a double L-shaped pattern having central symmetry, various layout design examples that can be adopted for each conductive layer in the initial design shown in fig. 5 are shown in fig. 7. For example, in the first adjacent conductive layer 101 shown in fig. 6A, the first sub-section 131 and the second sub-section 141 adopt the layout design (B) shown in fig. 7; in other examples, the first sub-portion 131 and the second sub-portion 141 of the first adjacent conductive layer 101 may also adopt other layout designs, such as (a), (C) or (D), in fig. 7. For example, in the second adjacent conductive layer 102 shown in fig. 6B, the first sub-section 131 and the second sub-section 141 adopt the layout design (D) shown in fig. 7; in other examples, the first sub-portion 131 and the second sub-portion 141 of the second adjacent conductive layer 102 may also adopt other layout designs in fig. 7, such as (a), (B), or (C). For example, in the third adjacent conductive layer 103 shown in fig. 6C, the first sub-section 131 and the second sub-section 141 adopt the layout design (B) shown in fig. 7; in other examples, the first sub-portion 131 and the second sub-portion 141 of the third adjacent conductive layer 103 may also adopt other layout designs in fig. 7, such as (a), (C), or (D). It should be noted that the embodiments of the present disclosure include but are not limited thereto.

It should be noted that, taking the initial design shown in fig. 5 as an example, the first via H1 and the second via H2 in the first insulating layer 111 and the third via H3 and the fourth via H4 in the second insulating layer 112 may also adopt other suitable layout designs, and the embodiment of the disclosure is not limited in this respect.

For example, taking the first via H1 and the second via H2 as an example, in the case where the overall pattern of the first sub-portion 131 and the second sub-portion 141 in the first adjacent conductive layer 101 and the second adjacent conductive layer 102 is a double-L-shaped pattern with central symmetry, fig. 8 shows various layout design examples that the first via H1 and the second via H2 can adopt in the initial design shown in fig. 5. For example, referring to fig. 8, the first via H1 and the second via H2 may be disposed at positions P1 to P8, respectively. For example, in the first insulating layer 111 shown in fig. 5, the first via H1 and the second via H2 adopt the layout design (B) shown in fig. 8, that is, are disposed at the position P1 and the position P5, respectively; in other examples, the first via H1 and the second via H2 may have other layout designs, such as (a), (C) or (D), in fig. 8. It should be noted that the embodiments of the present disclosure include but are not limited thereto.

For example, the layout manner of the third via H3 and the fourth via H4 is substantially the same as the layout manner of the first via H1 and the second via H2, and repeated descriptions are omitted. For example, in the second insulating layer 112 shown in fig. 5, the third via H3 and the fourth via H4 adopt the layout design (D) shown in fig. 8, that is, are disposed at the position P2 and the position P6, respectively; in other examples, the third via H3 and the fourth via H4 may have other layout designs, such as (a), (B), or (C), in fig. 8.

For example, taking the initial design shown in fig. 5 as an example, fig. 9 is a schematic diagram of the arrangement positions of the input interfaces of the first signal and the second signal in the initial design of an integrated circuit according to some embodiments of the present disclosure. For example, as shown in fig. 9, the first signal input port inp 1 and the second signal input port inp 2 may be respectively disposed at positions P1 to P8, for example, the layout designs (a), (B), (C) and (D) shown in fig. 9 may be respectively adopted. It should be noted that, besides the layout shown in fig. 9, the input interface inp 1 for the first signal and the input interface inp 2 for the second signal may also adopt other suitable layout designs, and the embodiment of the present disclosure is not limited in this respect.

For example, the layout of the first signal output port OUTPT1 and the second signal output port OUTPT2 is substantially the same as the layout of the first signal input port inp 1 and the second signal input port inp 2, and the description thereof is omitted.

Fig. 10 is a schematic diagram of a specific example of an initial design scheme of another integrated circuit according to some embodiments of the present disclosure. It should be noted that, except that the numbers of the first via H1, the second via H2, the third via H3, and the fourth via H4 are all plural, the initial design scheme of the integrated circuit shown in fig. 10 is substantially the same as or similar to the initial design scheme of the integrated circuit shown in fig. 5, and repeated descriptions are omitted.

For example, as shown in fig. 10, the number of the first vias H1 and the number of the second vias H2 are both 2, and the number of the third vias H3 and the number of the fourth vias H4 are both 2, thereby contributing to improving the electrical connection effect between the first sub-portions 131 in the adjacent conductive layers and the electrical connection effect between the second sub-portions 141 in the adjacent conductive layers.

It should be noted that, in some other embodiments of the present disclosure, the numbers of the first via H1, the second via H2, the third via H3, and the fourth via H4 may also be 3, 4, or more, and the embodiments of the present disclosure are not limited in this respect.

Fig. 11 is a schematic diagram of a specific implementation example of an initial design scheme of yet another integrated circuit according to some embodiments of the present disclosure, where fig. 12A is a schematic plan view of a first adjacent conductive layer in fig. 11, fig. 12B is a schematic plan view of a second adjacent conductive layer in fig. 11, fig. 12C is a schematic plan view of a third adjacent conductive layer in fig. 11, and fig. 12D is a schematic plan view of a fourth adjacent conductive layer in fig. 11.

For example, as shown in fig. 11 and fig. 12A to 12D, the integrated circuit in the initial design further includes a fourth adjacent conductive layer 104 in addition to the first adjacent conductive layer 101, the second adjacent conductive layer 102, and the third adjacent conductive layer 103. For example, the fourth adjacent conductive layer 104 is adjacent to the first adjacent conductive layer 101, the second adjacent conductive layer 102, and the third adjacent conductive layer 103, and is located on a side of the third adjacent conductive layer 103 away from the second adjacent conductive layer 102. The first and second conductive portions 130, 140 are also located in the fourth adjacent conductive layer 104, i.e., the first conductive portion 130 further includes a first sub-portion 131 located in the fourth adjacent conductive layer 104, and the second conductive portion 140 further includes a second sub-portion 141 located in the fourth adjacent conductive layer 104. In the stacking direction R1, the first sub-portion 131 of the fourth adjacent conductive layer 104 overlaps with the first and second sub-portions 131 and 141 of the third adjacent conductive layer 103, the second sub-portion 141 of the fourth adjacent conductive layer 104 overlaps with the first and second sub-portions 131 and 141 of the third adjacent conductive layer 103, that is, the first sub-portion 131 of the third adjacent conductive layer 103 overlaps with the first and second sub-portions 131 and 141 of the fourth adjacent conductive layer 104, and the second sub-portion 141 of the third adjacent conductive layer 103 overlaps with the first and second sub-portions 131 and 141 of the fourth adjacent conductive layer 104.

For specific arrangement of the first sub-portion 131 and the second sub-portion 141 in the fourth adjacent conductive layer 104, and connection manner between the fourth adjacent conductive layer 104 and the third adjacent conductive layer 103 (for example, layout manner of the fifth via H5 and the sixth via H6 for arranging the first connection portion 132 and the second connection portion 142), reference may be made to the corresponding description of the first adjacent conductive layer 101, the second adjacent conductive layer 102, and the third adjacent conductive layer 103, and repeated points are not repeated herein.

For example, as shown in fig. 11 and fig. 12A to 12D, the size and shape of the region surrounded by the orthogonal projection of the first sub-portion 131 in the first adjacent conductive layer 101 in the reference plane are different from the size and shape of the region surrounded by the orthogonal projection of the first sub-portion 131 in the second adjacent conductive layer 102 in the reference plane, and the size and shape of the region surrounded by the orthogonal projection of the second sub-portion 141 in the first adjacent conductive layer 101 in the reference plane are different from the size and shape of the region surrounded by the orthogonal projection of the second sub-portion 141 in the second adjacent conductive layer 102 in the reference plane.

For example, the size and shape of the area surrounded by the orthogonal projection of the first sub-portion 131 in the third adjacent conductive layer 103 in the reference plane are the same as those of the area surrounded by the orthogonal projection of the first sub-portion 131 in the second adjacent conductive layer 102 in the reference plane, and the size and shape of the area surrounded by the orthogonal projection of the second sub-portion 141 in the third adjacent conductive layer 103 in the reference plane are the same as those of the area surrounded by the orthogonal projection of the second sub-portion 141 in the second adjacent conductive layer 102 in the reference plane.

For example, the size and shape of the area surrounded by the orthogonal projection of the first sub-section 131 in the third adjacent conductive layer 103 in the reference plane are different from the size and shape of the area surrounded by the orthogonal projection of the first sub-section 131 in the fourth adjacent conductive layer 104 in the reference plane, and the size and shape of the area surrounded by the orthogonal projection of the second sub-section 141 in the third adjacent conductive layer 103 in the reference plane are different from the size and shape of the area surrounded by the orthogonal projection of the second sub-section 141 in the fourth adjacent conductive layer 104 in the reference plane.

For example, the size and shape of the area surrounded by the orthogonal projection of the first sub-portion 131 in the first adjacent conductive layer 101 in the reference plane are the same as those of the area surrounded by the orthogonal projection of the first sub-portion 131 in the fourth adjacent conductive layer 104 in the reference plane, and the size and shape of the area surrounded by the orthogonal projection of the second sub-portion 141 in the first adjacent conductive layer 101 in the reference plane are the same as those of the area surrounded by the orthogonal projection of the second sub-portion 141 in the fourth adjacent conductive layer 104 in the reference plane.

For example, as shown in fig. 12A, the overall pattern of the first sub-portion 131 and the second sub-portion 141 in the first adjacent conductive layer 101 is a double Z-shaped pattern which is centrosymmetric and is formed by two approximately Z-shaped structures facing each other, the overall pattern of the first sub-portion 131 and the second sub-portion 141 in the second adjacent conductive layer 102 is a double U-shaped pattern which is centrosymmetric and is formed by two U-shaped structures facing each other and crossing each other, the overall pattern of the first sub-portion 131 and the second sub-portion 141 in the third adjacent conductive layer 103 is a double U-shaped pattern which is centrosymmetric and is formed by two approximately Z-shaped structures facing each other and crossing each other, and the overall pattern of the first sub-portion 131 and the second sub-portion 141 in the fourth adjacent conductive layer 104 is a double Z-shaped pattern which is centrosymmetric and is formed by two approximately Z-shaped structures facing each other.

For example, in the embodiment shown in fig. 11 and 12A to 12D, the first sub-portion 131 and the second sub-portion 141 of the first adjacent conductive layer 101, the second adjacent conductive layer 102, the third adjacent conductive layer 103, and the fourth adjacent conductive layer 104 adopt four layout manners shown in fig. 12A to 12D, respectively.

For example, the four layout manners may be divided into two groups, the layout manners shown in fig. 12A and 12C belong to a first group of layout manners, and the layout manners shown in fig. 12B and 12D belong to a second group of layout manners. For example, the first sub-portion 131 and the second sub-portion 141 of two adjacent conductive layers respectively adopt layouts belonging to different groups, so as to avoid the situation that the layouts of the first sub-portion 131 and the second sub-portion 141 of the two adjacent conductive layers are completely the same in the process of performing multiple modifications on the initial design scheme of the integrated circuit. Therefore, according to different actual requirements, the obtained application design scheme can be continuously changed to obtain a new design scheme, so that the change amount and the time required to be spent in the process of changing for many times based on the initial design scheme are reduced, the number of corresponding new mask plates needing to be redesigned or prepared is reduced, the research and development cost of the integrated circuit is further reduced, and the research and development efficiency is improved.

For example, the first sub-portion 131 and the second sub-portion 141 of two non-adjacent conductive layers may adopt a layout belonging to the same group, thereby facilitating the simplification of the manufacturing process of the integrated circuit and reducing the development cost of the integrated circuit.

For example, in the case where a new application design scheme in which the arrangement positions of two input interfaces (or two output interfaces) are interchanged is implemented by modifying any one of the first adjacent conductive layer 101, the second adjacent conductive layer 102, the third adjacent conductive layer 103, and the fourth adjacent conductive layer 104, the layout manner of the first sub-section 131 and the second sub-section 141 in the conductive layer can be modified to belong to another layout manner in the same group of layout manners with respect to the conductive layer selected for modification.

For example, when the modification of the first adjacent conductive layer 101 shown in fig. 12A is selected, the layout manner of the first sub-section 131 and the second sub-section 141 in the first adjacent conductive layer 101 may be modified to the layout manner shown in fig. 12C that belongs to the first group of layout manners; when the modification of the second adjacent conductive layer 102 shown in fig. 12B is selected, the layout manners of the first sub-portion 131 and the second sub-portion 141 in the second adjacent conductive layer 102 may be modified to the layout manner shown in fig. 12D belonging to the second group of layout manners; when the modification of the third adjacent conductive layer 103 shown in fig. 12C is selected, the layout manner of the first sub-section 131 and the second sub-section 141 in the third adjacent conductive layer 103 may be modified to the layout manner shown in fig. 12A that belongs to the first group of layout manners; when the modification of the fourth adjacent conductive layer 104 shown in fig. 12D is selected, the layout manner of the first sub-section 131 and the second sub-section 141 in the fourth adjacent conductive layer 104 may be modified to the layout manner shown in fig. 12B that belongs to the second group of layout manners.

For example, fig. 12E is a schematic diagram illustrating a layout of vias in the same insulating layer in the design of the integrated circuit shown in fig. 11. For example, various layout design examples that can be adopted by two vias located in the same insulating layer in the initial design scheme shown in fig. 11 are shown in fig. 12E. It should be noted that the via H shown in fig. 12E may respectively correspond to the first via H1, the second via H2, the third via H3, the fourth via H4, the fifth via H5, or the sixth via H6 shown in fig. 12A to 12D.

For example, as shown in fig. 11 and fig. 12A to 12E, in the first insulating layer between the first adjacent conductive layer 101 and the second adjacent conductive layer 102, the first via H1 and the second via H2 adopt the layout design (a) shown in fig. 12E; in the second insulating layer located between the second adjacent conductive layer 102 and the third adjacent conductive layer 103, the third via H3 and the fourth via H4 adopt the layout design (C) shown in fig. 12E; in the third insulating layer located between the third adjacent conductive layer 103 and the fourth adjacent conductive layer 104, the fifth via H5 and the sixth via H6 adopt the layout design (B) shown in fig. 12E.

For example, the four via layout approaches shown in fig. 12E can be divided into two groups: the layout patterns shown in (a) and (B) in fig. 12E belong to the first group of layout patterns, and the layout patterns shown in (C) and (D) belong to the second group of layout patterns. For example, the via holes in two adjacent insulating layers respectively adopt layout modes belonging to different groups, so that the situation that the layout modes of the via holes in two adjacent insulating layers are completely the same in the process of modifying the initial scheme of the integrated circuit for many times is avoided. Therefore, according to different actual requirements, the obtained application design scheme can be continuously changed to obtain a new design scheme, so that the change amount possibly generated in the process of changing for many times based on the initial design scheme and the time required to be spent are reduced, the number of corresponding new mask plates needing to be redesigned or prepared is reduced, the research and development cost of the integrated circuit is further reduced, and the research and development efficiency is improved.

For example, the via holes in two non-adjacent insulating layers can adopt a layout mode belonging to the same group, thereby being beneficial to simplifying the preparation process of the integrated circuit and reducing the research and development cost of the integrated circuit.

For example, in the case of modifying any one of the first insulating layer, the second insulating layer, and the third insulating layer to implement a new application design scheme in which the arrangement positions of two input interfaces (or two output interfaces) are interchanged with each other, the layout manner of the via holes in the insulating layer can be modified to another layout manner belonging to the same group of layout manners for the insulating layer selected for modification.

For example, when the layout of the vias in the first insulating layer is selected to be modified, the layout of the vias in the first insulating layer may be modified to the layout (B) shown in fig. 12E, which belongs to the first group of layouts; when the layout mode of the via holes in the second insulating layer is selected to be modified, the layout mode of the via holes in the second insulating layer may be modified to the layout mode (D) shown in fig. 12E which belongs to the second group of layout modes; when the layout manner of the via holes in the third insulating layer is selected to be modified, the layout manner of the via holes in the third insulating layer may be modified to the layout manner (a) shown in fig. 12E which belongs to the first group of layout manners.

For example, taking the second adjacent conductive layer 102 in the initial design shown in fig. 11 as an example, fig. 13 shows the arrangement positions of the input interface inp 1 (or output interface OUTPT1) of the first signal and the input interface inp 2 (or output interface OUTPT2) of the second signal in the case where the first via H1 and the second via H2 respectively adopt four different via design manners shown in fig. 12E, and the input interface inp 1 (or output interface OUTPT1) of the first signal and the input interface inp 2 (or output interface OUTPT2) of the second signal need to be arranged in the first adjacent conductive layer 101 or the second adjacent conductive layer 102.

For example, as shown in fig. 13, taking the input interfaces inp 1 and inp 2 as an example, the input interface inp 1 for the first signal and the input interface inp 2 for the second signal may adopt the layout designs (a), (B), (C), (D), (E) or (F) shown in fig. 13, corresponding to different layouts of the first via H1 and the second via H2, respectively.

For example, as shown in fig. 13, in the stacking direction R1, neither the first signal input interface inp 1 nor the second signal input interface inp 2 overlaps with the first via H1 and the second via H2.

For example, among the eight positions for disposing the first via H1, the second via H2, the input interface inp 1, and the input interface inp 2, the eight positions include four inner positions (e.g., referred to as inner regions) relatively close to the central symmetry point of the first sub-part 131 and the second sub-part 141 and four outer positions (e.g., referred to as outer regions) relatively far from the central symmetry point of the first sub-part 131 and the second sub-part 141. For example, referring to the layout manners (a) and (B) shown in fig. 13, in the case where the first via H1 and the second via H2 are provided in the outside area, the input interfaces inp 1 and inp 2 need to be provided in the inside area; referring to the layout manners (C), (D), (E), and (F) shown in fig. 13, in the case where the first via H1 and the second via H2 are disposed in the inner region, the input interfaces inp 1 and inp 2 need to be disposed in the outer region, thereby ensuring stability and reliability of signal transmission.

It should be noted that, besides the layout shown in fig. 13, the input interface inp 1 and the output interface OUTPT1 for the first signal and the input interface inp 2 and the output interface OUTPT2 for the second signal may also adopt other suitable layout designs, and the embodiment of the present disclosure is not limited in this regard.

Fig. 14 is a schematic diagram of a specific example of an initial design scheme of yet another integrated circuit according to some embodiments of the present disclosure. It should be noted that, except that the numbers of the first via hole H1, the second via hole H2, the third via hole H3, the fourth via hole H4, the fifth via hole H5, and the sixth via hole H6 are all plural, the initial design scheme of the integrated circuit shown in fig. 14 is substantially the same as or similar to the initial design scheme of the integrated circuit shown in fig. 11, and repeated parts are not repeated.

For example, as shown in fig. 14, the number of the first vias H1 and the number of the second vias H2 are both 2, the number of the third vias H3 and the number of the fourth vias H4 are both 2, and the number of the fifth vias H5 and the number of the sixth vias H6 are both 2, thereby contributing to improving the electrical connection effect between the first sub-portions 131 in the adjacent conductive layers and the electrical connection effect between the second sub-portions 141 in the adjacent conductive layers.

It should be noted that, in some other embodiments of the present disclosure, the numbers of the first via H1, the second via H2, the third via H3, the fourth via H4, the fifth via H5, and the sixth via H6 may also be 3, 4, or more, and the like, which is not limited in this embodiment of the present disclosure.

In some embodiments of the present disclosure, each of the conductive layers may be a metal layer. For example, the material of the conductive layer may include a metal material such as aluminum, molybdenum, copper, silver, or an alloy material of these metal materials, such as a silver-palladium-copper Alloy (APC) material.

For example, the material of each insulating layer may be an inorganic insulating material, and the inorganic insulating material may be a transparent material. For example, the inorganic insulating material is an oxide of silicon, a nitride of silicon, or an oxynitride of silicon, such as silicon oxide, silicon nitride, or silicon oxynitride, or an insulating material including a metal oxynitride, such as aluminum oxide or titanium nitride. For example, the material of the insulating layer may also be an organic insulating material to obtain good bending resistance. For example, the organic insulating material is a transparent material. For example, the organic insulating material is OCA optical cement. For example, the organic insulating material may include Polyimide (PI), acrylate, epoxy, Polymethylmethacrylate (PMMA), and the like.

It should be noted that, in the embodiments of the present disclosure, the flows of the design method of the integrated circuit provided in the above embodiments of the present disclosure may include more or less operations, which may be executed sequentially or in parallel. Although the flow of the design method of the integrated circuit described above includes a plurality of operations occurring in a particular order, it should be clearly understood that the order of the plurality of operations is not limited. The above-described design method of the integrated circuit may be performed once or may be performed a plurality of times according to a predetermined condition.

At least one embodiment of the present disclosure also provides an integrated circuit comprising a plurality of conductive layers; the conductive layers are stacked with each other, and at least one insulating layer is arranged between every two adjacent conductive layers so as to enable the two adjacent conductive layers to be spaced and insulated from each other; the integrated circuit comprises a first conductive part and a second conductive part which are insulated from each other, wherein the first conductive part comprises a plurality of first sub-parts respectively positioned in different conductive layers and a first connecting part positioned between the different conductive layers to connect the plurality of first sub-parts, and the second conductive part comprises a plurality of second sub-parts respectively positioned in the different conductive layers and a second connecting part positioned between the different conductive layers to connect the plurality of second sub-parts; the plurality of conductive layers comprise a first adjacent conductive layer and a second adjacent conductive layer which are adjacent, the first conductive part at least passes through the first adjacent conductive layer and the second adjacent conductive layer, and the second conductive part at least passes through the first adjacent conductive layer and the second adjacent conductive layer; in the stacking direction of the first adjacent conductive layer and the second adjacent conductive layer, the first sub-portion of the first adjacent conductive layer at least partially overlaps with the first sub-portion and the second sub-portion of the second adjacent conductive layer, and the second sub-portion of the first adjacent conductive layer at least partially overlaps with the first sub-portion and the second sub-portion of the second adjacent conductive layer.

It should be noted that, in the embodiment of the present disclosure, for specific layout structure, function, technical effect, and the like of the integrated circuit, reference may be made to the description about the initial design scheme and the application design scheme of the integrated circuit in the design method of the integrated circuit, and details are not described here again.

At least one embodiment of the present disclosure also provides an integrated circuit design apparatus that reduces the number of conductive layers and insulating layers that need to be modified in an integrated circuit when a connection pattern between a first sub-portion of a first conductive portion and a first connection portion and a connection pattern between a second sub-portion of a second conductive portion and a second connection portion need to be adjusted or modified by designing the first sub-portion of the first adjacent conductive layer to at least partially overlap both the first sub-portion and the second sub-portion of the second adjacent conductive layer and designing the second sub-portion of the first adjacent conductive layer to at least partially overlap both the first sub-portion and the second sub-portion of the second adjacent conductive layer in an initial design scheme of the integrated circuit that is provided. Furthermore, the amount of change and the time required to be spent in the process of adjusting or modifying the layout structure in the initial design scheme based on the integrated circuit to obtain the application design scheme can be reduced, so that the research and development cost of the integrated circuit is reduced, and the research and development efficiency is improved.

Fig. 15 is a schematic block diagram of an integrated circuit design apparatus provided in some embodiments of the present disclosure.

For example, as shown in fig. 15, the integrated circuit design apparatus 700 includes an initial design solution acquisition unit 701 and an application design solution acquisition unit 702.

The initial design solution acquisition unit 701 is configured to acquire an initial design solution of an integrated circuit. For example, the initial design solution acquisition unit 701 may execute step S11 in the design method of an integrated circuit shown in fig. 1.

The application design scheme acquisition unit 702 is configured to obtain an application design scheme of the integrated circuit based on the initial design scheme. For example, the application design scheme acquisition unit 702 may execute step S12 in the design method of an integrated circuit shown in fig. 1.

The integrated circuit comprises a plurality of conductive layers, wherein the conductive layers are mutually stacked, and at least one insulating layer is arranged between every two adjacent conductive layers so as to enable the two adjacent conductive layers to be spaced and insulated from each other; in an initial design, an integrated circuit includes a first conductive portion and a second conductive portion insulated from each other, the first conductive portion including a plurality of first sub-portions respectively located in different conductive layers and a first connection portion located between the different conductive layers to connect the plurality of first sub-portions, the second conductive portion including a plurality of second sub-portions respectively located in the different conductive layers and a second connection portion located between the different conductive layers to connect the plurality of second sub-portions; the plurality of conductive layers comprise a first adjacent conductive layer and a second adjacent conductive layer which are adjacent, the first conductive part at least passes through the first adjacent conductive layer and the second adjacent conductive layer, and the second conductive part at least passes through the first adjacent conductive layer and the second adjacent conductive layer; in the stacking direction of the first adjacent conductive layer and the second adjacent conductive layer, the first sub-portion of the first adjacent conductive layer at least partially overlaps with the first sub-portion and the second sub-portion of the second adjacent conductive layer, and the second sub-portion of the first adjacent conductive layer at least partially overlaps with the first sub-portion and the second sub-portion of the second adjacent conductive layer.

For example, the initial design solution acquisition unit 701 and the application design solution acquisition unit 702 include codes and programs stored in a memory; the processor may execute the code and program to realize some or all of the functions of the initial design acquisition unit 701 and the application design acquisition unit 702 as described above. For example, the initial design solution acquisition unit 701 and the application design solution acquisition unit 702 may be dedicated hardware devices for implementing some or all of the functions of the initial design solution acquisition unit 701 and the application design solution acquisition unit 702 as described above. For example, the initial design solution acquisition unit 701 and the application design solution acquisition unit 702 may be one circuit board or a combination of a plurality of circuit boards for realizing the functions as described above. In the embodiment of the present application, the one or a combination of a plurality of circuit boards may include: (1) one or more processors; (2) one or more non-transitory memories connected to the processor; and (3) firmware stored in the memory executable by the processor.

Note that the initial design acquisition unit 701 is used to implement step S11 shown in fig. 1, and the application design acquisition unit 702 is used to implement step S12 shown in fig. 1. Thus, for the specific explanation of the initial design solution obtaining unit 701, reference may be made to the description related to step S11 shown in fig. 1 in the embodiment of the integrated circuit design method described above, and for the specific explanation of the application design solution obtaining unit 702, reference may be made to the description related to step S12 shown in fig. 1 in the embodiment of the integrated circuit design method described above. In addition, the integrated circuit design apparatus can achieve the similar technical effects as the design method of the integrated circuit, and the details are not repeated herein.

At least one embodiment of the present disclosure also provides an electronic device that includes a processor, memory, and one or more computer program modules. One or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules including instructions for performing the design method of the integrated circuit provided by any of the embodiments of the present disclosure.

Fig. 16 is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure. As shown in fig. 16, the electronic device 300 includes a processor 310 and a memory 320. Memory 320 is used to non-transitory store computer-executable instructions (e.g., one or more computer program modules). The processor 310 is configured to execute the computer-executable instructions, which when executed by the processor 310 may perform one or more steps of the design method of an integrated circuit described above. The memory 320 and the processor 310 may be interconnected by a bus system and/or other form of connection mechanism (not shown).

For example, the processor 310 may be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or other form of processing unit having data processing capabilities and/or program execution capabilities. For example, the Central Processing Unit (CPU) may be an X86 or ARM architecture or the like. The processor 310 may be a general-purpose processor or a special-purpose processor that may control other components in the electronic device 300 to perform desired functions.

For example, memory 320 may include any combination of one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, Random Access Memory (RAM), cache memory (or the like). The non-volatile memory may include, for example, Read Only Memory (ROM), a hard disk, an Erasable Programmable Read Only Memory (EPROM), a portable compact disc read only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer program modules may be stored on the computer-readable storage medium and executed by the processor 310 to implement the various functions of the electronic device 300. Various applications and various data, as well as various data used and/or generated by the applications, and the like, may also be stored in the computer-readable storage medium.

It should be noted that, in the embodiment of the present disclosure, reference may be made to the above description on the integrated circuit design method and the integrated circuit design apparatus for specific functions and technical effects of the electronic device 300, and details are not described herein again.

Fig. 17 is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure. The electronic device 400 is, for example, suitable for implementing the design method of the integrated circuit provided by the embodiments of the present disclosure. The electronic device 400 may be a terminal device or the like. It should be noted that the electronic device 400 shown in fig. 17 is only an example, and does not bring any limitation to the functions and the scope of use of the embodiments of the present disclosure.

As shown in fig. 17, electronic device 400 may include a processing means (e.g., central processing unit, graphics processor, etc.) 410 that may perform various appropriate actions and processes in accordance with a program stored in a Read Only Memory (ROM)420 or a program loaded from a storage device 480 into a Random Access Memory (RAM) 430. In the RAM 430, various programs and data necessary for the operation of the electronic apparatus 400 are also stored. The processing device 410, the ROM 420, and the RAM 430 are connected to each other by a bus 440. An input/output (I/O) interface 450 is also connected to bus 440.

Generally, the following devices may be connected to the I/O interface 450: input devices 460 including, for example, a touch screen, touch pad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 470 including, for example, a Liquid Crystal Display (LCD), speakers, vibrators, or the like; storage 480 including, for example, magnetic tape, hard disk, etc.; and a communication device 490. The communication device 490 may allow the electronic device 400 to communicate wirelessly or by wire with other electronic devices to exchange data. While fig. 17 illustrates an electronic device 400 having various means, it is to be understood that not all illustrated means are required to be implemented or provided, and that the electronic device 400 may alternatively be implemented or provided with more or less means.

For example, according to an embodiment of the present disclosure, the design method of the integrated circuit described above may be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer readable medium, the computer program comprising program code for performing the design method of the integrated circuit described above. In such embodiments, the computer program may be downloaded and installed from a network through communication device 490, or installed from storage device 480, or installed from ROM 420. When executed by the processing device 410, the computer program may implement the functions defined in the design method of the integrated circuit provided by the embodiments of the present disclosure.

Fig. 18 is a schematic diagram of a storage medium according to some embodiments of the present disclosure. For example, as shown in fig. 18, the storage medium 500 may be a non-transitory computer-readable storage medium, on which one or more computer-readable instructions 501 may be non-temporarily stored on the storage medium 500. For example, the computer readable instructions 501, when executed by a processor, may perform one or more steps in a design method according to an integrated circuit as described above.

For example, the storage medium 500 may be applied to the electronic device described above, and for example, the storage medium 500 may include a memory in the electronic device.

For example, the storage medium may include a memory card of a smart phone, a storage component of a tablet computer, a hard disk of a personal computer, a Random Access Memory (RAM), a Read Only Memory (ROM), an Erasable Programmable Read Only Memory (EPROM), a portable compact disc read only memory (CD-ROM), a flash memory, or any combination of the above, as well as other suitable storage media.

For example, the description of the storage medium 500 may refer to the description of the memory in the embodiment of the electronic device, and repeated descriptions are omitted. The specific functions and technical effects of the storage medium 500 can be referred to the above description of the integrated circuit design method and the integrated circuit design apparatus, which are not described herein again.

For the present disclosure, there are also the following points to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

(2) Thicknesses and dimensions of layers or structures may be exaggerated in the drawings used to describe embodiments of the present invention for clarity. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

(3) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

1. A method of designing an integrated circuit, comprising:

acquiring an initial design scheme of an integrated circuit; and

obtaining an application design scheme of the integrated circuit based on the initial design scheme;

the integrated circuit comprises a plurality of conducting layers, wherein the conducting layers are arranged in a stacked mode, at least one insulating layer is arranged between every two adjacent conducting layers, and therefore the two adjacent conducting layers are spaced and insulated from each other;

in the case of the initial design, it is,

the integrated circuit includes a first conductive portion and a second conductive portion insulated from each other,

the first conductive part includes a plurality of first sub-parts respectively located in different conductive layers and a first connection part located between the different conductive layers to connect the plurality of first sub-parts,

the second conductive part includes a plurality of second sub-parts respectively located in different conductive layers and a second connection part located between the different conductive layers to connect the plurality of second sub-parts;

the plurality of conductive layers comprise a first adjacent conductive layer and a second adjacent conductive layer which are adjacent, the first conductive part at least passes through the first adjacent conductive layer and the second adjacent conductive layer, and the second conductive part at least passes through the first adjacent conductive layer and the second adjacent conductive layer;

in the stacking direction of the first adjacent conductive layer and the second adjacent conductive layer, a first sub-portion of the first adjacent conductive layer at least partially overlaps with a first sub-portion and a second sub-portion of the second adjacent conductive layer, and a second sub-portion of the first adjacent conductive layer at least partially overlaps with the first sub-portion and the second sub-portion of the second adjacent conductive layer.

2. The method of designing an integrated circuit according to claim 1, wherein an application design of the integrated circuit is the same as the initial design.

3. The method of claim 1 or 2, wherein the first sub-portion and the second sub-portion of the first adjacent conductive layer are spaced apart and insulated from each other and are disposed in a central symmetry with respect to the first reference point;

the first sub-part and the second sub-part of the second adjacent conducting layer are spaced and insulated from each other and are arranged in central symmetry relative to the second datum point;

the integrated circuit further comprising a first insulating layer between the first and second adjacent conductive layers, the first insulating layer comprising at least one first via and at least one second via,

the first via hole and the second via hole penetrate through the first insulating layer and are respectively used for arranging the first connecting part and the second connecting part,

the first via hole and the second via hole are arranged in central symmetry relative to a third datum point;

the first reference point, the second reference point, and the third reference point overlap with each other in the stacking direction.

4. The method of claim 3, wherein a first spaced area is disposed between a first sub-portion and a second sub-portion of the first adjacent conductive layer, the first reference point being a center of the first spaced area;

a second spacing area is arranged between the first sub-portion and the second sub-portion of the second adjacent conductive layer, and the second reference point is the center of the second spacing area.

5. The method of designing an integrated circuit according to claim 3, wherein an orthogonal projection of the first and second sub-sections in the first adjacent conductive layer as a whole in a reference plane, which is perpendicular to the stacking direction, and an orthogonal projection of the first and second sub-sections in the second adjacent conductive layer as a whole in the reference plane are different from each other.

6. The method of claim 5, wherein an area defined by orthographic projections of the first and second sub-portions of the first adjacent conductive layer in the reference plane has the same size and shape as an area defined by orthographic projections of the first and second sub-portions of the second adjacent conductive layer in the reference plane.

7. The method of claim 6, wherein the size and shape of the area defined by the orthographic projection of the first sub-portion of the first adjacent conductive layer on the reference plane is the same as the size and shape of the area defined by the orthographic projection of the first sub-portion of the second adjacent conductive layer on the reference plane,

the size and the shape of an area surrounded by orthographic projections of the second sub-portions of the first adjacent conductive layers in the reference plane are the same as those of an area surrounded by orthographic projections of the second sub-portions of the second adjacent conductive layers in the reference plane.

8. The method of claim 6, wherein the overall pattern of the first sub-portion and the second sub-portion of the first adjacent conductive layer is a center-symmetrical double-L pattern, and the overall pattern of the first sub-portion and the second sub-portion of the second adjacent conductive layer is a center-symmetrical double-L pattern.

9. The method of claim 5, wherein the size and shape of the area defined by the orthographic projection of the first sub-portion of the first adjacent conductive layer on the reference plane is different from the size and shape of the area defined by the orthographic projection of the first sub-portion of the second adjacent conductive layer on the reference plane,

the size and the shape of an area surrounded by orthographic projections of the second sub-portions of the first adjacent conducting layers in the reference plane are different from those of an area surrounded by orthographic projections of the second sub-portions of the second adjacent conducting layers in the reference plane.

10. The method of claim 9, wherein the overall pattern of the first sub-portion and the second sub-portion of the first adjacent conductive layer is a center-symmetrical double-U-shaped pattern, and the overall pattern of the first sub-portion and the second sub-portion of the second adjacent conductive layer is a center-symmetrical double-Z-shaped pattern.

11. The method of designing an integrated circuit according to claim 3, wherein the first conductive part is used for transmitting a first signal, and the second conductive part is used for transmitting a second signal different from the first signal, the initial design of the integrated circuit further comprising:

an input interface responding to the first signal and an input interface responding to the second signal are arranged in the same conductive layer, and the input interface responding to the first signal and the input interface responding to the second signal are arranged in central symmetry;

and the output interface responding to the first signal and the output interface responding to the second signal are arranged in the same conductive layer, and the output interface of the first signal and the output interface of the second signal are arranged in central symmetry.

12. The method of designing an integrated circuit according to claim 11, wherein, in the stacking direction, neither the input interface nor the output interface of the first signal overlaps with the first via and the second via in the first insulating layer, and neither the input interface nor the output interface of the second signal overlaps with the first via and the second via in the first insulating layer.

13. The design method of an integrated circuit according to claim 3, wherein, in the initial design scheme,

the plurality of conductive layers further comprise a third adjacent conductive layer, the third adjacent conductive layer is positioned on one side of the second adjacent conductive layer far away from the first adjacent conductive layer, and the first conductive part and the second conductive part at least pass through the third adjacent conductive layer;

in the stacking direction, a first sub-portion of the second adjacent conductive layer at least partially overlaps with both a first sub-portion and a second sub-portion of the third adjacent conductive layer, and a second sub-portion of the second adjacent conductive layer at least partially overlaps with both a first sub-portion and a second sub-portion of the third adjacent conductive layer.

14. The method of claim 13, wherein the first sub-portion and the second sub-portion of the third adjacent conductive layer are spaced apart and insulated from each other and are disposed in a central symmetry with respect to a fourth reference point;

the integrated circuit further comprising a second insulating layer between the second adjacent conductive layer and the third adjacent conductive layer, the second insulating layer comprising at least one third via and at least one fourth via,

the third via hole and the fourth via hole penetrate through the second insulating layer and are used for arranging the first connecting part and the second connecting part,

the third via hole and the fourth via hole are arranged in central symmetry relative to a fifth reference point;

the first reference point, the second reference point, the third reference point, the fourth reference point, and the fifth reference point overlap with each other in the stacking direction;

in the stacking direction, the first via hole in the first insulating layer and the third and fourth via holes in the second insulating layer are not overlapped, and the second via hole in the first insulating layer and the third and fourth via holes in the second insulating layer are not overlapped.

15. The method of designing an integrated circuit according to claim 1 or 2, wherein the integrated circuit further comprises a first insulating layer between the first and second adjacent conductive layers, the first and second connection portions penetrating the first insulating layer,

obtaining an application design scheme of the integrated circuit based on the initial design scheme, including:

and selecting any one of the first adjacent conducting layer, the second adjacent conducting layer and the first insulating layer to carry out layout adjustment so as to obtain the application design scheme.

16. The method of designing an integrated circuit according to claim 15, wherein selecting any one of the first adjacent conductive layer, the second adjacent conductive layer, and the first insulating layer for layout adjustment comprises:

and obtaining an application layout structure which is subjected to plane rotation, turnover or mirror image relative to the original layout structure based on the original layout structure of any one of the first adjacent conducting layer, the second adjacent conducting layer and the first insulating layer.

17. An integrated circuit comprising a plurality of conductive layers;

the conductive layers are stacked, and at least one insulating layer is arranged between every two adjacent conductive layers, so that the two adjacent conductive layers are spaced and insulated from each other;

the integrated circuit includes a first conductive part and a second conductive part insulated from each other, the first conductive part including a plurality of first sub-parts respectively located in different conductive layers and a first connection part located between the different conductive layers to connect the plurality of first sub-parts, the second conductive part including a plurality of second sub-parts respectively located in different conductive layers and a second connection part located between the different conductive layers to connect the plurality of second sub-parts;

18. The integrated circuit of claim 17, wherein the first and second sub-portions of the first adjacent conductive layer are spaced apart and insulated from each other and are disposed in a central symmetry with respect to a first reference point;

19. The integrated circuit of claim 18, wherein an orthogonal projection of the first and second sub-sections of the first adjacent conductive layer as a whole in a reference plane, which is perpendicular to the stacking direction, and an orthogonal projection of the first and second sub-sections of the second adjacent conductive layer as a whole in the reference plane are different from each other.

20. The integrated circuit of claim 19, wherein an area bounded by orthographic projections of the first and second sub-portions of the first adjacent conductive layer in the reference plane is the same size and shape as an area bounded by orthographic projections of the first and second sub-portions of the second adjacent conductive layer in the reference plane;

the size and the shape of an area surrounded by orthographic projections of the first sub-parts in the first adjacent conducting layers in the reference plane are the same as those of an area surrounded by orthographic projections of the first sub-parts in the second adjacent conducting layers in the reference plane;

the size and the shape of an area surrounded by the orthographic projection of the second sub-part in the first adjacent conductive layer in the reference plane are the same as those of an area surrounded by the orthographic projection of the second sub-part in the second adjacent conductive layer in the reference plane.

21. The integrated circuit of claim 19, wherein an orthographic projection of a first subsection of the first adjacent conductive layer in the reference plane defines a region of a different size and shape than an orthographic projection of a first subsection of the second adjacent conductive layer in the reference plane,

22. An integrated circuit design apparatus, comprising:

an initial design scheme acquisition unit configured to acquire an initial design scheme of an integrated circuit; and

an application design scheme acquisition unit configured to obtain an application design scheme of the integrated circuit based on the initial design scheme;

in the case of the initial design, it is,

23. An electronic device, comprising:

a memory non-transiently storing computer executable instructions;

a processor configured to execute the computer-executable instructions,

wherein the computer-executable instructions, when executed by the processor, implement a method of designing an integrated circuit according to any one of claims 1-16.

24. A non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions that, when executed by a processor, implement a method of designing an integrated circuit according to any one of claims 1-16.