CN114492268A

CN114492268A - ASIC prototype verification method, system, equipment and storage medium

Info

Publication number: CN114492268A
Application number: CN202210111426.9A
Authority: CN
Inventors: 曲超; 王奕; 曹蓓
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2022-01-29
Filing date: 2022-01-29
Publication date: 2022-05-13

Abstract

The invention provides a method, a system, equipment and a storage medium for ASIC prototype verification, wherein the method comprises the following steps: reading a design file list corresponding to the ASIC initial complete code and converting the design file list into a design file adding program; establishing an FPGA comprehensive implementation project according to the FPGA model used by the prototype verification platform and the design file adding program; comprehensively realizing an engineering creation project flow integrated program according to the FPGA; and responding to the release of the ASIC new complete code, and executing the project flow integration program to realize the verification of the ASIC new complete code. The project flow of the invention is integrally controlled, the operation difficulty is greatly reduced, the prototype verification development flow is simplified, the working efficiency is greatly improved, and the prototype verification period is shortened.

Description

ASIC prototype verification method, system, equipment and storage medium

Technical Field

The present invention relates to the field of prototyping, and more particularly to a method, system, device and storage medium for ASIC prototyping.

Background

ASIC (Application Specific Integrated Circuit) designs not only include the design of the ASIC chip itself, but also the design of ASIC chip related software solutions. In the ASIC design process, the FPGA (Field Programmable Gate Array) prototype verification is an essential link, which not only can synchronously and rapidly verify the accuracy of the ASIC chip function design, but also can provide a development platform for the design of the ASIC chip software solution earlier, advance the development and design of the software solution, shorten the ASIC design cycle, and accelerate the marketization of the ASIC chip.

FPGA prototype verification is mainly characterized in that FPGA prototype verification technicians transplant ASIC design codes issued by a design team to an FPGA platform with changes as little as possible, replace codes which are specific to ASIC design and are not suitable for an FPGA chip with codes which are suitable for the FPGA chip or IP (Intellectual Property) cores, then complete integration and realization, download generated bit files to the FPGA of the prototype verification platform, verify the functions and the performance of the ASIC design and provide a development platform for software solutions.

In actual work, after an FPGA prototype verification technician completes code migration on an initial complete design code issued by an ASIC design team, although the ASIC design code is subsequently updated and issued many times by the design team, the update reason is mostly Bug repair function, and related code files to be migrated to the FPGA are basically unchanged, and it is not necessary to compare all design code files in each code migration process. The main problem currently exists is that when a design team releases a subsequent new ASIC design code, the FPGA prototype validation technician needs to repeat the work of transplanting related code files, create engineering files on the same validation platform, and synthesize, implement, and bit file generation. The process has strong repeatability, wastes time and labor, is easy to cause the problems of synthesis, realization and bit file generation failure caused by missing items in the transplanting process, wastes time, prolongs the debugging period, increases the verification cost and risks, and cannot effectively serve the purposes of shortening the ASIC design period and accelerating the marketization of an ASIC chip.

Disclosure of Invention

In view of this, embodiments of the present invention provide a method, a system, a computer device, and a computer readable storage medium for ASIC prototype verification, which implement project flow integrated control, and implement prototype verification of a new ASIC code design by jointly calling multiple scripting language programs with one key.

In view of the above, an aspect of the embodiments of the present invention provides a method for ASIC prototype verification, including the following steps: reading a design file list corresponding to the ASIC initial complete code and converting the design file list into a design file adding program; establishing an FPGA comprehensive implementation project according to the FPGA model used by the prototype verification platform and the design file adding program; comprehensively realizing an engineering creation project flow integrated program according to the FPGA; and responding to the release of the ASIC new complete code, and executing the project flow integration program to realize the verification of the ASIC new complete code.

In some embodiments, the building of the FPGA comprehensive implementation project according to the FPGA model used by the prototype verification platform and the design file adding program includes: creating a model selection FPGA project, adding a source file and identifying a replacement design file; and comprehensively realizing by using a preset strategy, building a simulation environment and compiling a basic test case.

In some embodiments, the program for integrating the engineering creation project flow according to the FPGA integrated implementation includes: adding a source file and identifying a replacement design file to be integrated into a first program, integrating a built simulation environment into a second program, integrating a comprehensive implementation into a third program, and integrating the first program, the second program and the third program to obtain an integrated program.

In some embodiments, the program for integrating the engineering creation project flow according to the FPGA integrated implementation includes: drawing an ASIC design file of a specified version, and identifying and converting to generate a tcl file; and setting environment variables uniformly used in the integrated process control process and executing the integrated program.

In another aspect of the embodiments of the present invention, there is provided a system for ASIC prototype verification, including: the reading module is configured to read a design file list corresponding to the ASIC initial complete code and convert the design file list into a design file adding program; the building module is configured for building an FPGA comprehensive implementation project according to the FPGA model used by the prototype verification platform and the design file adding program; the creating module is configured for comprehensively realizing an integrated program of the project flow of engineering creation according to the FPGA; and the execution module is configured to respond to the release of the ASIC new-version complete code and execute the project flow integration program to realize the verification of the ASIC new-version complete code.

In some embodiments, the construction module is configured to: creating a model selection FPGA project, adding a source file and identifying a replacement design file; and comprehensively realizing by using a preset strategy, building a simulation environment and compiling a basic test case.

In some embodiments, the creation module is configured to: adding a source file and identifying a replacement design file to be integrated into a first program, integrating a built simulation environment into a second program, integrating a comprehensive implementation into a third program, and integrating the first program, the second program and the third program to obtain an integrated program.

In some embodiments, the creation module is configured to: drawing an ASIC design file of a specified version, and identifying and converting to generate a tcl file; and setting environment variables uniformly used in the integrated process control process and executing the integrated program.

In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method as above.

In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.

The invention has the following beneficial technical effects:

(1) the method has the advantages that the ASIC design code file list is automatically read, identified, extracted and converted by a program, the FPGA engineering design file list corresponding to the version design and a simulation environment building program are automatically generated, the labor input and the time cost are reduced, the error occurrence rate is reduced, and the efficiency and the accuracy of code transplantation and prototype verification platform generation are improved;

(2) the project flow is integrally controlled, the flow control function is packaged, and a plurality of complicated step flows in the generation process of the verification platform are simplified into one instruction through parameterized transfer, so that the operation difficulty is greatly reduced, the prototype verification development flow is simplified, the working efficiency is greatly improved, and the prototype verification period is shortened.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of an embodiment of a method for ASIC prototype verification provided by the present invention;

FIG. 2 is a flow chart of an embodiment of a method of ASIC prototype verification provided by the present invention;

FIG. 3 is a block diagram of the design of ASIC initial full code in an embodiment of the present invention;

FIG. 4 is a flow chart of engineering construction for comprehensive implementation of a Golden version FPGA in the embodiment of the present invention;

FIG. 5 is a flowchart illustrating an integrated project flow control according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of an embodiment of a system for ASIC prototype verification provided by the present invention;

FIG. 7 is a diagram of a hardware configuration of an embodiment of a computer device for ASIC prototyping provided by the present invention;

FIG. 8 is a schematic diagram of an embodiment of a computer storage medium for ASIC prototype verification provided by the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.

In a first aspect of embodiments of the present invention, embodiments of a method for ASIC prototype verification are presented. Fig. 1 is a schematic diagram of an embodiment of the method for ASIC prototype verification provided by the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:

s1, reading a design file list corresponding to the ASIC initial complete code and converting the design file list into a design file adding program;

s2, building an FPGA comprehensive implementation project according to the FPGA model used by the prototype verification platform and the design file adding program;

s3, comprehensively realizing an integrated program of the project flow of engineering creation according to the FPGA; and

and S4, responding to the release of the ASIC new edition complete code, and executing the project flow integration program to realize the verification of the ASIC new edition complete code.

Fig. 2 is a flowchart of an embodiment of the method for ASIC prototype verification according to the present invention, which is described with reference to fig. 2, and the embodiment of the present invention takes a case where a git version management software and a Vivado design software are used in a Linux system to perform an FPGA engineering acceleration generation of a prototype verification platform.

And reading a design file list corresponding to the ASIC initial complete code and converting the design file list into a design file adding program.

Fig. 3 is a block diagram of ASIC original complete code design, where M1, M2 … … Mm, Mm +1, Mm +2 … … Mm + n are each module in the ASIC design code, including a clock control module, a reset control module, a memory module, an IP core, a high-speed interface module (PCIE, DDR, SRIO, Ethernet) and other functional modules, and L is an on-chip interconnection module. After a design team finishes designing an ASIC initial complete code or a main body frame code, clock resources, reset resources, storage resources, IP resources and a high-speed interface required by the design of the whole ASIC are basically determined, and a design code and a design file list are issued through git version management software.

The method comprises the steps of pulling an ASIC initial complete code and a design file list to a local space through git version management software, writing an automatic reading, recognizing and extracting conversion program by using a script language according to the design file list, reading the design file list line by line and automatically converting the design file list into a design file which can be identified by Vivado design software in real time to add a Tcl program, wherein an add command uses add _ files-nonreturn { File 1 File 2 … … File n }, the execution efficiency of the added file of the Vivado design software is improved, and the version number of a current ASIC code is printed at last in the Tcl program, so that the version of the ASIC design is checked in the execution process, and the work on an error version is prevented.

And establishing an FPGA comprehensive implementation project according to the FPGA model used by the prototype verification platform and the design file adding program.

And according to the FPGA model used by the prototype verification platform, creating a Vivado project of the device, and adding the FPGA project design file by executing the generated Vivado design file adding program. And identifying clock resources, storage resources, IP resources and high-speed interface resources special for ASIC design through in-directory retrieval, and manually completing the replacement of the resources to Xilinx FPGA resources. Adding time sequence constraint, pin constraint and download file requirement constraint, using default strategy to synthesize and implement, solving the problem of failed comprehensive implementation or time sequence non-convergence caused by congestion, overlarge fan-out, overlarge logic level, cross die and overlarge related resource utilization rate in the period by adding related resource use constraint, fan-out constraint, time sequence exception constraint and the suggested comprehensive implementation strategy, and finally converging the time sequence to generate a download file, as shown in fig. 4. Meanwhile, a Testbench designed by an ASIC (application specific integrated circuit) is compiled in Vivado software, the building of a simulation environment is completed, a basic test case is compiled, the simulation of a sanity test is completed, and the building of a Golden version FPGA (field programmable gate array) comprehensive implementation project is completed.

And comprehensively realizing an integrated program of the project flow of engineering creation according to the FPGA.

After the Golden version FPGA comprehensively realizes the successful construction of the project, replacing related design files such as clock resources, storage resources, IP resources, high-speed interface resources and the like and design files added with debugging means in the process as a change folder; saving related time sequence constraint, pin constraint and download file requirement constraint files used in the FPGA comprehensive implementation project as an existing constraint folder; and storing the automatic reading, identifying, extracting and converting program in a program folder, wherein the automatic reading, identifying, extracting and converting program only comprises the function of converting the design file information in the file list file according to the ASIC initial complete design code into the file list information which can be identified by the FPGA engineering design.

Refining the process of newly-built selection type FPGA design engineering into a create _ prj.tcl program; a source. tcl program in the process of adding the FPGA design engineering source file is generated through the steps, an automatic reading, identifying, extracting and converting program needs to be modified, and the identification processing of original clock resources, storage resources, IP resources and high-speed interface resources is filtered; extracting relevant design files such as clock resources, storage resources, IP resources and high-speed interface resources, a process of replacing design files of adding debugging means, a process of adding constraint files, a process of setting engineering parameters and the like into source2.tcl programs; extracting Golden edition FPGA simulation verification environment construction processes (including include files, adding Testbench, setting top layer of simulation files, setting file types, setting simulation parameters and the like) and integrating the extracted Golden edition FPGA simulation verification environment construction processes into an automatic reading, recognizing and extracting conversion program file, wherein at the moment, a source.tcl program and a sim.tcl program can be obtained by executing the automatic reading, recognizing and extracting conversion program in the later period; writing a process Tcl function, realizing the comprehensive process which accords with the Golden version FPGA for comprehensively realizing engineering time sequence convergence, realizing the strategy setting required by the process, establishing a comprehensive realization task, setting parameters and the like, and having the parameter transmission function. And integrating a create _ prj.tcl program, a source.tcl program, a source2.tcl program and a process Tcl function into an FPGA _ all.tcl program, and adding waiting control among the programs.

And (4) integrally controlling the project flow, and compiling a script program with a parameter transmission function. After the new ASIC design code is released, entering the appointed repeatability, setting a uniform environment variable in the integrated control process, and finishing the pull operation of the appointed version design; then copying the version design file list file to a designated folder, executing an automatic reading, identifying, extracting and converting program, copying the generated source.tcl program and sim.tcl program to the designated folder, and displaying the version number for version confirmation; then, an engineering folder displaying the version number is automatically created, Vivado is called in the folder to execute an FPGA _ all.tcl program, so that the automatic creation of prototype verification FPGA design engineering, the automatic addition of the version design file, the automatic replacement of clock resources, storage resources, IP resources, high-speed interface resources and other related design files needing to be added with debugging means, the automatic addition of constraint files, the automatic setting of relevant parameters of engineering operation, the automatic creation of simulation environment, the automatic creation of a plurality of comprehensive implementation strategy tasks meeting the requirement of Golden version FPGA comprehensive implementation engineering time sequence convergence is realized, and only the confirmation and then the selection of the comprehensive implementation strategy tasks are manually needed to generate a download file, as shown in FIG. 5.

And responding to the release of the ASIC new complete code, and executing the project flow integration program to realize the verification of the ASIC new complete code.

According to the embodiment of the invention, the program is adopted to automatically read, identify, extract and convert the ASIC design code file list, the FPGA engineering design file list corresponding to the version design and the simulation environment building program are automatically generated, the human input and the time cost are reduced, the error occurrence rate is reduced, and the efficiency and the accuracy of code transplantation and prototype verification platform generation are improved; the embodiment of the invention adopts project flow integrated control, encapsulates flow control functions, and simplifies a plurality of complex step flows in the generation process of the verification platform into one instruction through parameterized transfer, thereby greatly reducing the operation difficulty, simplifying the prototype verification development flow, greatly improving the working efficiency and shortening the prototype verification period.

It should be particularly noted that, the steps in the embodiments of the method for ASIC prototype verification described above can be mutually intersected, replaced, added, and deleted, so that these methods for ASIC prototype verification with reasonable permutation and combination transformation also belong to the scope of protection of the present invention, and the scope of protection of the present invention should not be limited to the embodiments.

In view of the above objects, a second aspect of the embodiments of the present invention provides a system for ASIC prototype verification. As shown in fig. 6, the system 200 includes the following modules: the reading module is configured to read a design file list corresponding to the ASIC initial complete code and convert the design file list into a design file adding program; the building module is configured for building an FPGA comprehensive implementation project according to the FPGA model used by the prototype verification platform and the design file adding program; the creating module is configured for comprehensively realizing an integrated program of the project flow of engineering creation according to the FPGA; and the execution module is configured to respond to the release of the ASIC new-version complete code and execute the project flow integration program to realize the verification of the ASIC new-version complete code.

In view of the above object, a third aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, reading a design file list corresponding to the ASIC initial complete code and converting the design file list into a design file adding program; s2, building an FPGA comprehensive implementation project according to the FPGA model used by the prototype verification platform and the design file adding program;

s3, comprehensively realizing an integrated program of the project flow of engineering creation according to the FPGA; and S4, responding to the release of the ASIC new edition complete code, executing the project flow integration program to realize the verification of the ASIC new edition complete code.

Fig. 7 is a schematic hardware structure diagram of an embodiment of the computer device for ASIC prototype verification according to the present invention.

Taking the device shown in fig. 7 as an example, the device includes a processor 301 and a memory 302.

The processor 301 and the memory 302 may be connected by a bus or other means, and fig. 7 illustrates a bus connection as an example.

The memory 302 is used as a non-volatile computer readable storage medium for storing non-volatile software programs, non-volatile computer executable programs, and modules, such as program instructions/modules corresponding to the method for ASIC prototype verification in the embodiments of the present application. The processor 301 executes various functional applications of the server and data processing, i.e., implements a method of ASIC prototype verification, by running non-volatile software programs, instructions, and modules stored in the memory 302.

The memory 302 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the method of ASIC prototype verification, and the like. Further, the memory 302 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 302 optionally includes memory located remotely from processor 301, which may be connected to a local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

Computer instructions 303 corresponding to one or more methods of ASIC prototyping are stored in the memory 302 and when executed by the processor 301 perform the method of ASIC prototyping in any of the method embodiments described above.

Any embodiment of a computer device for performing the method of ASIC prototyping described above may achieve the same or similar effects as any of the preceding method embodiments corresponding thereto.

The present invention also provides a computer readable storage medium storing a computer program which, when executed by a processor, performs a method of ASIC prototype verification.

Fig. 8 is a schematic diagram of an embodiment of a computer storage medium for the above ASIC prototype verification according to the present invention. Taking the computer storage medium as shown in fig. 8 as an example, the computer readable storage medium 401 stores a computer program 402 which, when executed by a processor, performs the method as described above.

Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes of the methods of the above embodiments can be implemented by a computer program to instruct related hardware, and the program of the method for ASIC prototype verification can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods as described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims

1. A method of ASIC prototyping comprising the steps of:

reading a design file list corresponding to the ASIC initial complete code and converting the design file list into a design file adding program;

establishing an FPGA comprehensive implementation project according to the FPGA model used by the prototype verification platform and the design file adding program;

comprehensively realizing an engineering creation project flow integrated program according to the FPGA; and

2. The method according to claim 1, wherein the building of the FPGA comprehensive implementation engineering according to the FPGA model used by the prototype verification platform and the design file adding program comprises:

creating a model selection FPGA project, adding a source file and identifying a replacement design file; and

and comprehensively realizing by using a preset strategy, building a simulation environment and compiling a basic test case.

3. The method according to claim 2, wherein said comprehensively implementing an engineering creation project flow integration program according to said FPGA comprises:

adding a source file and identifying a replacement design file to be integrated into a first program, integrating a built simulation environment into a second program, integrating a comprehensive implementation into a third program, and integrating the first program, the second program and the third program to obtain an integrated program.

4. The method of claim 3, wherein said comprehensively implementing an engineering project creation flow integration program according to said FPGA comprises:

drawing an ASIC design file of a specified version, and identifying and converting to generate a tcl file; and

and setting environment variables uniformly used in the integrated process control process and executing the integrated program.

5. A system for ASIC prototyping, comprising:

the reading module is configured to read a design file list corresponding to the ASIC initial complete code and convert the design file list into a design file adding program;

the building module is configured for building an FPGA comprehensive implementation project according to the FPGA model used by the prototype verification platform and the design file adding program;

the creating module is configured for comprehensively realizing an integrated program of the project flow of engineering creation according to the FPGA; and

and the execution module is configured for responding to the release of the ASIC new-version complete code and executing the project flow integration program to realize the verification of the ASIC new-version complete code.

6. The system of claim 5, wherein the building module is configured to:

7. The system of claim 6, wherein the creation module is configured to:

8. The system of claim 7, wherein the creation module is configured to:

9. A computer device, comprising:

at least one processor; and

a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 1 to 4.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 4.