CN114492264B - Gate-level circuit translation method, system, storage medium and equipment - Google Patents
Gate-level circuit translation method, system, storage medium and equipment Download PDFInfo
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Abstract
The invention provides a translation method, a translation system, a storage medium and a device of a gate-level circuit, wherein the method comprises the following steps: generating a VVP file according to the target gate-level netlist file and the process library file; inputting a VVP file name and a top module name of a target gate-level netlist file from a command line, and setting the top module name as a global variable; analyzing the VVP file according to the global variable and the index of each logic keyword and extracting gate-level key information of each node; redefining gate level semantics of the gate level key information of each node according to redefining rules corresponding to each logic keyword to obtain redefined gate level key information of each node; and translating the gate-level key information of each redefined node in a preset general format to obtain a directed graph file, wherein the obtained directed graph file is equivalent to a gate-level circuit in terms of topological structure and circuit semantics and is convenient for secondary development.
Description
Technical Field
The present invention relates to the field of circuit translation, and in particular, to a method, system, storage medium, and device for translating a gate level circuit.
Background
In the high-end digital IC industry, gate level circuit emulation is a critical technology. The original file used for simulating the gate-level circuit is a gate-level netlist file, the gate-level netlist file is a text file which represents a labeled grammar of a connection relation of a bottom-layer circuit and is generated after RTL files are synthesized, the gate-level netlist file cannot be directly simulated in the gate-level circuit simulation process, and the gate-level netlist file needs to be translated into a directed graph file with circuit information.
The existing gate-level circuit translators (such as open source synthesis tools yosys and Icarus Verilog) are poor in universality, lexical and syntactic analyses are adopted in the semantic description conversion process, structural contents of the lexical and syntactic analyses are stored in an abstract syntax tree, so that a third party cannot easily and universally extract translated circuit information, deep research needs to be carried out on internal software architecture if the third party needs to extract the translated circuit information, and the translated contents are difficult to develop secondarily, so that a simple and universal gate-level circuit translation method is urgently needed to solve the problems.
Disclosure of Invention
The present invention is directed to a method, system, storage medium and apparatus for translating a gate level circuit, so as to solve the above-mentioned problems.
The invention provides a translation method of a gate level circuit, which comprises the following steps:
generating a VVP file according to a target gate-level netlist file and a process library file, wherein the target gate-level netlist file is a text file for describing gate-level semantics of connection relations among circuit devices, the process library file comprises logic elements forming the circuit devices, and the VVP file is a text file for describing the gate-level semantics of the connection relations among the logic elements of nodes;
inputting a VVP file name and a top module name of the target gate-level netlist file from a command line and setting the top module name as a global variable;
acquiring a preset logic keyword table, analyzing the VVP file according to the global variable and the index of each logic keyword in the preset logic keyword table, and extracting gate-level key information of a node corresponding to each logic keyword;
redefining gate level semantic meaning of the gate level key information of the nodes corresponding to the logic keywords according to redefining rules corresponding to the logic keywords to obtain redefined gate level key information of the nodes;
and translating the redefined gate-level key information of each node in a preset general format to obtain a directed graph file.
The translation method of the gate level circuit provided by the invention has the following beneficial effects:
the method comprises the steps that firstly, a VVP file is generated according to a target gate-level netlist file and a process library file, the generated VVP file not only comprises a data structure of the target gate-level netlist, but also opens a third-party interface to access a universal logic structure, and therefore the VVP file can be output in a universal file structure mode; inputting a VVP file name and a top module name of the target gate-level netlist file from a command line and setting the top module name as a global variable to prepare for extracting key gate-level information; analyzing the VVP file according to the global variable and the index of each logic keyword in a preset logic keyword table so as to quickly extract gate-level key information of a node corresponding to each logic keyword; redefining gate-level semantics of gate-level key information of each node according to redefining rules corresponding to each logic keyword, which can purposefully solve the problem of insufficient description of circuit semantics to better meet the actual simulation requirement, redefine according to the corresponding redefining rules, enhance the regularity and universality of the redefining process and facilitate the programmed execution of the redefining process; the gate-level key information of each redefined node is translated in a preset general format to obtain a directed graph file, the obtained directed graph file is equivalent to a gate-level circuit in terms of topological structure and circuit semantics, secondary development can be facilitated, and the defect that the EDA industry lacks general digital circuit front-end translation at present is overcome.
In addition, the translation method of the gate level circuit provided by the invention can also have the following additional technical characteristics:
further, the step of analyzing the VVP file according to the global variable and the index of each logical keyword in the preset logical keyword table and extracting the gate-level key information of the node corresponding to each logical keyword specifically includes:
reading each row of information in the VVP file in sequence from the file header of the VVP file and inquiring whether a top module exists in the row information or not;
if the top module does not exist, judging whether a combinational logic udp key word or a sequential logic udp key word exists in the row information in the VVP file;
if the combinational logic udp key word or the sequential logic udp key word exists, analyzing a relevant segment of the combinational logic udp or the sequential logic udp, and extracting and storing a truth table and gate-level key information of a node corresponding to the combinational logic udp key word or the sequential logic udp key word into a first global dictionary.
Further, after the step of sequentially reading each row of information in the VVP file from the file header of the VVP file and querying whether a top module exists in the row information, the method further includes:
and if the top module exists, analyzing all row information behind the top module in the VVP file, extracting and storing gate-level key information corresponding to the logic key according to the logic key in the preset logic key table, wherein the udp logic key in the preset logic key table is an udp logic key except for a combinational logic udp key and a sequential logic udp key.
Further, the step of redefining gate level key information of nodes corresponding to each of the logical keywords according to redefinition rules corresponding to each of the logical keywords to obtain redefined gate level key information of each of the nodes specifically includes:
creating a second global dictionary;
traversing the global list and sequentially acquiring character strings of gate-level key information of all nodes in the global list;
analyzing the character strings of the gate-level key information of each node and extracting the key words of the gate-level key information of each node;
matching and inquiring keywords of the gate-level key information of each node against the preset logic keyword table to find corresponding logic keywords in the preset logic keyword table and determine the type of each node and the redefinition rule of the gate-level key information of each node according to the logic keywords;
and setting keys and values of the second global dictionary according to redefinition rules of the gate-level key information of each node and the gate-level key information of each node.
Further, the step of setting keys and values of the second global dictionary according to the redefinition rule of the gate-level key information of each node and the gate-level key information of each node specifically includes:
and if the node is a basic logic gate node, setting keys and values of the second global dictionary according to a four-input one-output gate level definition rule and gate level key information of the node.
Further, the step of setting the keys and values of the second global dictionary according to a four-input-one-output gate level definition rule and the gate level key information of the node specifically includes:
extracting a node ID, a node type name, a node input ID, a node output ID and a node output bit width from the gate-level key information of the node;
storing the node ID into a key of the second global dictionary;
storing the type name of the node into a type list of the value of the second global dictionary;
sequentially storing the input ID and the constant value of the node into a four-input list of the values of the second global dictionary;
storing the output ID of the node into an output list of values of the second global dictionary;
and storing the output bit width of the node into the bit width list of the value of the second global dictionary.
Further, the step of translating the gate-level key information of each redefined node in a preset general format to obtain a directed graph file includes:
traversing the second global dictionary and converting information in the second global dictionary in a JSON format to obtain a second directed graph file;
traversing the first global dictionary and converting the information in the first global dictionary in a JSON format to obtain a first directed graph file.
The present invention further provides a gate level circuit translation system, including:
a generation module: the system comprises a VVP file, a node selection unit and a node selection unit, wherein the VVP file is used for generating a VVP file according to a target gate-level netlist file and a process library file, the target gate-level netlist is a text file used for describing gate-level semantics of connection relations among circuit devices, the process library file comprises logic elements forming the circuit devices, and the VVP file is a text file used for describing the gate-level semantics of the connection relations among the logic elements of the nodes;
setting a module: the top module name is used for inputting a VVP file name and the target gate-level netlist file from a command line and is set as a global variable;
an extraction module: the VVP file is used for acquiring a preset logic keyword table, analyzing the VVP file according to the global variable and the index of each logic keyword in the preset logic keyword table, and extracting gate-level key information of a node corresponding to each logic keyword;
a definition module: the system comprises a logic key and a semantic database, wherein the logic key is used for redefining gate level semantic meaning of gate level key information of nodes corresponding to the logic keys according to redefining rules corresponding to the logic keys to obtain the redefined gate level key information of the nodes;
the translation module: and the method is used for translating the gate-level key information of each redefined node in a preset general format to obtain a directed graph file.
The present invention also provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor implements the translation method of the gate level circuit described above.
The invention also provides a translation device of the gate level circuit, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor executes the program to realize the translation method of the gate level circuit.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a flowchart of a gate level circuit translation method according to a first embodiment of the present invention;
FIG. 2 is a system block diagram of a translation system for gate level circuits according to a second embodiment of the present invention;
FIG. 3 is a block diagram of a gate level circuit translation apparatus according to a third embodiment of the present invention.
Detailed Description
In order to make the objects, features and advantages of the present invention more comprehensible, embodiments accompanying figures are described in detail below. Several embodiments of the invention are presented in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Example 1
As shown in FIG. 1, a first embodiment of the present invention provides a method for translating a gate level circuit, which includes steps S101 to S105.
S101, generating a VVP file according to a target gate-level netlist file and a process library file, wherein the target gate-level netlist file is a text file for describing gate-level semantics of connection relations among circuit devices, the process library file comprises logic elements forming the circuit devices, and the VVP file is a text file for describing the gate-level semantics of the connection relations among the logic elements of nodes.
It should be noted that the VVP file in the embodiment of the present invention may be generated by an Icarus Verilog simulator, where the Icarus Verilog simulator generates an intermediate file VVP file when simulating a circuit file, and the format of the VVP file is test.
Before the step of generating the VVP file according to the target gate-level netlist file and the process library file, the target gate-level netlist file and the process library file need to be selected, and the format of the selected target gate-level netlist file may be: the format of the selected craft library file can be as follows: smic _13. v. When the VVP file is generated using the Icarus Verilog simulator, the VVP file test.vvp may be generated by inputting the following command "viralog-o test.vvptest.v. smart _13. v".
And S102, inputting a VVP file name and a top module name of the target gate-level netlist file from a command row and setting the top module name as a global variable.
Wherein, the top module name is as follows: top _ module.
S103, acquiring a preset logic keyword table, analyzing the VVP file according to the global variable and the index of each logic keyword in the preset logic keyword table, and extracting gate-level key information of a node corresponding to each logic keyword.
It should be noted that the process device specific to the process library is composed of the following basic logic devices: AND (AND) OR (OR) NOT (NOT), user-defined primitive udp, path delay, device delay, delay unit, AND the like, so that only the key gate level information (gate level language) of the logic devices needs to be sequentially searched AND extracted from the VVP file, AND the logic devices are represented by corresponding logic keywords in the VVP file, so that the key gate level information can be searched AND extracted by the logic keywords.
TABLE 1
Further, the step of analyzing the VVP file according to the global variable and the index of each logical keyword in the preset logical keyword table and extracting the gate-level key information of the node corresponding to each logical keyword specifically includes:
reading each row of information in the VVP file in sequence from the file header of the VVP file and inquiring whether a top module exists in the row information or not;
if the top module does not exist, judging whether a combinational logic udp key word or a sequential logic udp key word exists in the row information in the VVP file;
if the combinational logic udp key word or the sequential logic udp key word exists, analyzing the combinational logic udp or the related segment of the sequential logic udp, and extracting and storing a truth table and gate-level key information of a node corresponding to the combinational logic udp key word or the sequential logic udp key word into a first global dictionary udp _ definitions.
Specifically, if the [ udp ] key appears, the analysis is performed from the line (start line) where the [ udp ] key appears to the line (end line) where the semicolon ends. If the parsed node information includes a specific keyword, UDP/comb (i.e., combinational logic UDP key) or UDP/sequ (i.e., sequential logic UDP key), the parsed node information is correspondingly stored in the first global dictionary UDP _ definitions, and the parsed node information further includes instance names of UDP nodes (i.e., node IDs, such as UDP _ mux 2), type names of UDP nodes (such as UDP _ mux 2), and initial values of UDP nodes (0 represents signal 0, 1 represents signal 1, 2 represents signal X, and 3 represents no-signal value).
It should be noted that, because udp nodes are defined in various ways, logic truth tables thereof are complex and difficult to process, and user-defined udp gate simulation is difficult to implement and cannot ensure correct logic, most of the existing simulators cannot support the situation that user-defined primitives appear in gate-level simulation. The first global dictionary udp _ definitions created in the embodiment of the present invention can store the simulation logic of the user-defined node.
The simulation logic is a key for ensuring the correctness of subsequent simulation, as most of the gate-level netlists are formed by connecting process library devices, and although the devices of different process libraries are different, the bottom layer implementation logic is based on main logic gates (such as AND gates, OR gates and XOR gates) and the like and some user-defined primitive (udp) gates. The main logic gate can be obtained by consulting the relevant digital circuit industry standard, and is not required to be placed in the translation result file, so that the storage pressure of the translation result file can be saved.
Further, after the step of sequentially reading each row of information in the VVP file from the file header of the VVP file and querying whether a top module exists in the row of information, the method further includes:
if the top module exists, analyzing all row information behind the top module in the VVP file, extracting and storing Gate-level key information corresponding to other logic keys according to the other logic keys in the preset logic key table into a global list Gate _ states, wherein the other logic keys are logic keys in the preset logic key table except for a combinational logic udp key and a sequential logic udp key.
And S104, redefining gate level semantic meaning of the gate level key information of the nodes corresponding to the logic keywords according to redefining rules corresponding to the logic keywords to obtain the redefined gate level key information of the nodes.
Further, the step of redefining gate level key information of nodes corresponding to each of the logical keywords according to redefinition rules corresponding to each of the logical keywords to obtain redefined gate level key information of each of the nodes specifically includes:
creating a second global dictionary Gate _ Dict;
traversing the global list Gate _ states and sequentially acquiring character strings of Gate-level key information of each node in the global list Gate _ states;
analyzing the character strings of the gate-level key information of each node and extracting the key words of the gate-level key information of each node;
matching and inquiring keywords of the gate-level key information of each node against the preset logic keyword table to find corresponding logic keywords in the preset logic keyword table and determine the type of each node and the redefinition rule of the gate-level key information of each node according to the logic keywords;
and setting keys and values of the second global dictionary Gate _ Dict according to redefinition rules of the Gate-level key information of each node and the Gate-level key information of each node.
Further, the step of setting keys and values of the second global dictionary according to the redefinition rule of the gate-level key information of each node and the gate-level key information of each node specifically includes:
and if the node is a basic logic Gate node, setting keys and values of the second global dictionary Gate _ Dict according to a four-input one-output Gate level definition rule and Gate level key information of the node.
Further, the step of setting the keys and values of the second global dictionary Gate _ fact according to a four-input one-output Gate level definition rule and the Gate level key information of the node specifically includes:
extracting a node ID, a type name of the node, an input ID of the node, an output ID of the node and an output bit width of the node from the gate-level key information of the node;
storing the node ID into a key of the second global dictionary Gate _ Dict;
storing the type name of the node into a type list of the value of the second global dictionary Gate _ Dict;
sequentially storing the input ID and the constant value of the node into a four-input list of the value of the second global dictionary Gate _ Dict;
storing the output ID of the node into an output list of the value of the second global dictionary Gate _ Dict;
and storing the output bit width of the node into a bit width list of the value of the second global dictionary Gate _ Dict.
It should be noted that, the VVP file includes at least the following node types: the system comprises a signal type node, a logic simulation node and a gate-level signal connection node, wherein the logic simulation node specifically comprises a basic logic gate node and a udp node (user-defined node).
The basic logic gate nodes are common logic gates in a digital circuit, all types are shown in table 2, generally, the basic logic gate nodes are mostly two-input one-output (such as and, or, nor gates), a small number of the basic logic gate nodes are three-input one-output (such as cmos), and some other functions may need to be added in the gate-level simulation process, for example, a debugging interface and a logic lock function need to be added in the gate-level simulation process of the and gate, while the two-input and gate structure cannot meet the simulation requirements, so that the VVP file has the problem of insufficient semantic description of the gate-level circuit for some basic logic gate nodes, and the gate-level key information of the basic logic gate nodes needs to be defined to meet the actual simulation requirements. In order to ensure that the topological structure of input and output is consistent with the gate structure, the embodiment of the invention uniformly defines the basic logic gate nodes as four-input single-output. The unused input gate introduces different constant values, so that the generated logic table has the same meaning as the original two-input logic truth table.
| N_FUNC_AND | N_FUNC_OR | N_FUNC_NAND |
| N_FUNC_NOR | N_FUNC_XNOR | N_FUNC_XOR |
| N_FUNC_NOT | N_FUNC_NOTIF0 | N_FUNC_NOTIF1 |
| N_FUNC_BUFIF0 | N_FUNC_BUFIF1 | N_FUNC_CMOS |
| N_FUNC_NMOS | N_FUNC_PMOS | N_FUNC_RCMOS |
| N_FUNC_RNMOS | N_FUNC_RPMOS | …… |
TABLE 2
The gate-level netlist file is a file which is generated after RTL files are synthesized and used for representing the connection relation of bottom-layer circuits, and because synthesis software cannot synthesize udp grammar, the gate-level netlist file generated by RTL files generally does not contain user-defined primitive udp, udp nodes are often used in process library devices during gate-level simulation, and udp is roughly divided into two types of combination udp and time sequence udp. Because the processing of the udp node is complex, most of the existing simulators cannot support the situation of udp occurring in gate-level simulation, and two major difficulties exist: 1. the udp nodes are defined in various forms, and a logic truth table is complex and difficult to process; 2. the realization difficulty of the user-defined udp gate of the simulation user is large, and the correctness of the combinational logic and the sequential logic cannot be ensured.
The embodiment of the invention refers to the semantic description and the actual simulation condition of the udp node in the VVP file, and the udp node is defined as follows to solve the difficulties: the multi-input single output and input bit width are all 1bit, the number of input ports is udp truth table column number-1, and the rightmost column of the truth table is an output result value after input matching. The definition is as follows:
if the node is an udp node, setting keys and values of the second global dictionary Gate _ Dict according to a multi-input single-output Gate level definition rule and Gate level key information of the node, and specifically comprising the following steps:
extracting a node ID, a node type name, a node input value, a node output value and a truth table column number of the node from gate-level key information of the node;
storing the node ID into a key of the second global dictionary Gate _ Dict;
storing the type name of the node into a type list of the value of the second global dictionary Gate _ Dict;
constructing an input list of the values of the second global dictionary Gate _ Dict according to the truth table column number of the nodes, and sequentially storing the input values of the nodes into the input list of the values of the second global dictionary Gate _ Dict, wherein the column number of the input list of the values of the second global dictionary Gate _ Dict is the truth table column number of the nodes minus 1;
storing the output value of the node into an output list of the value of the second global dictionary Gate _ Dict;
storing 1bit into an input bit width list of values of the second global dictionary Gate _ Dict.
The signal type node mainly plays a role of providing a specified signal and can give an initial value to a circuit. The following three types of nodes are mainly used: n _ VAR, N _ FUNC _ buff, and N _ FUNC _ BUFZ. The signal type node is mainly single-input single-output, normally, a signal with a constant value X in a gate stage circuit is used for N _ VAR, signals with other values are used for N _ FUNC _ BUFT and N _ FUNC _ BUFZ, wherein the N _ FUNC _ BUFT can transmit the strength information of the signal, and the N _ FUNC _ BUFZ ignores the strength information of the signal.
Besides the above-described nodes with emulation functions, the type of node to be redefined in the present invention is also a node that characterizes gate-level connections. The node of this type can play the role of signal connection and selection of each node, including a signal bit selection node (N _ VPART _ SEL) and signal combination nodes (N _ CONCAT8, N _ CONCAT).
The signal combining node mainly plays a role in combining a plurality of signal values, and is a four-input single-output node which can combine multi-bit signals on four inputs, wherein the N _ CONCAT8 signal combining node can transmit signal strength information, and the N _ CONCAT signal combining node can ignore the strength information. The signal bit selection node is a single-input single-output node, and an output signal is determined according to a given bit selection starting subscript and an output bit width.
The definition mode is as follows: if the node is a signal merging node, extracting a node ID, an output bit width of each input signal of the node and an input signal value of the node from gate-level key information of the node;
storing the node ID into a key of the second global dictionary Gate _ Dict;
sequentially storing the input signal values of the nodes into an input list of the values of the second global dictionary Gate _ Dict;
sequentially combining the input signal values of the nodes to obtain output signal values of the nodes, and storing the output signal values of the nodes into an output list of the values of the second global dictionary Gate _ Dict;
and sequentially storing the output bit width of each input signal of the node into a bit width list of the value of the second global dictionary Gate _ Dict.
It should be noted that the created second global dictionary Gate _ fact stores the topology of the redefined Gate-level circuit, so as to ensure the causal order of the subsequent simulation. The topological structure of the redefined gate-level circuit is equivalent to that of the original gate-level netlist gate-level circuit, the problem of insufficient semantic description of some original circuits is solved in a targeted mode, and the actual simulation requirements can be better met.
And S105, translating the gate-level key information of each redefined node in a preset general format to obtain a directed graph file.
The step of translating the gate-level key information of each redefined node in a preset general format to obtain the directed graph file comprises the following steps of:
traversing the first global dictionary udp _ definitions and converting the information in the first global dictionary udp _ definitions in the JSON format to obtain a first directed graph file; traversing the second global dictionary Gate _ Dict and converting the information in the second global dictionary Gate _ Dict in a JSON format to obtain a second directed graph file. No restriction is placed on the translation order between the first global dictionary udp _ definitions and the second global dictionary Gate _ fact. The preset common format may also be a Protocol Buffers format.
It should be noted that, by processing the gate-level key information of each node in the VVP file in the previous stage, each gate has a unique ID, and therefore its corresponding input/output port also has a unique ID. Since the gate-level netlist file itself contains the connection relationships, a directed graph can be formed by the ID of each gate and its input/output ID. Each node in the directed graph behaves as a logic gate and this gate is not a pure digital circuit gate but a previously redefined optimized gate.
The translation result files (the first directed graph file and the second directed graph file) can already represent the circuit as a directed graph, and each graph node represents a gate. Each gate has a unique ID attribute for finding its position in the directed graph. The translation into the JSON file is because the syntax of the JSON file is very easy to use and is lightweight, the response can be performed in a faster manner, and the structural relationship can be clearly expressed. JSON is used as a better internet transmission structured file format, is already used by various networking or stand-alone software, and has extremely strong universality. In addition, the Python is provided with a JSON library, so that the JSON file format is adopted to carry out structured representation on the netlist more conveniently.
The invention firstly carries out structural representation on a gate level netlist to obtain a VVP file, then carries out semantic analysis on the VVP file, obtains information such as nodes, signals, module information, UDP definition content, thread information and process block content contained in the file, redefines the information of some types of nodes (such as signal type nodes, logic simulation nodes and gate level signal connection nodes), and finally outputs a JSON format file which has equivalent semantics and relations among all nodes in a circuit.
In summary, the gate level circuit translation method provided by the present invention has the following beneficial effects: the method comprises the steps that firstly, a VVP file is generated according to a target gate-level netlist file and a process library file, the generated VVP file not only comprises a data structure of the target gate-level netlist, but also opens a third-party interface to access a universal logic structure, and therefore the VVP file can be output in a universal file structure mode; inputting a VVP file name and a top module name of the target gate-level netlist file from a command line, and setting the top module name as a global variable to prepare for extracting key gate-level information; further, analyzing the VVP file according to the global variable and the index of each logical keyword in a preset logical keyword table so as to quickly extract gate-level key information of a node corresponding to each logical keyword; furthermore, the gate level key information of each node is redefined according to the redefining rule corresponding to each logic keyword, so that the problem of insufficient description of circuit semantics can be solved in a targeted manner, the actual simulation requirement can be better met, the redefinition is performed according to the corresponding redefining rule, the regularity and the universality of the redefining process are enhanced, and the programming execution of the redefining process is facilitated; and finally, translating the gate-level key information of each redefined node in a preset general format to obtain a directed graph file, wherein the obtained directed graph file is equivalent to a gate-level circuit in terms of topological structure and circuit semantics, and can be conveniently developed for the second time, so that the defect that the EDA industry lacks general digital circuit front-end translation at present is overcome.
Example 2
Referring to fig. 2, the present embodiment provides a translation system for gate level circuits, including:
a generation module: the system comprises a VVP file, a target gate-level netlist file, a process library file and a node, wherein the VVP file is used for generating the VVP file according to the target gate-level netlist file and the process library file, the target gate-level netlist file is a text file used for describing gate-level semantics of connection relations among circuit devices, the process library file comprises logic elements forming the circuit devices, and the VVP file is a text file used for describing the gate-level semantics of the connection relations among the logic elements of the nodes.
Setting a module: and the top module name is used for inputting the VVP file name and the target gate-level netlist file from a command line and setting the top module name as a global variable.
An extraction module: and the VVP file is used for acquiring a preset logic keyword table, analyzing the VVP file according to the global variable and the index of each logic keyword in the preset logic keyword table, and extracting gate-level key information of a node corresponding to each logic keyword.
The extraction module is further configured to:
reading each row of information in the VVP file in sequence from the file header of the VVP file and inquiring whether a top module exists in the row information or not;
if the top module does not exist, judging whether a combinational logic udp key word or a sequential logic udp key word exists in the row information in the VVP file;
if the combinational logic udp key word or the sequential logic udp key word exists, analyzing a relevant segment of the combinational logic udp or the sequential logic udp, and extracting and storing gate-level key information of a node corresponding to the combinational logic udp key word or the sequential logic udp key word into a first global dictionary udp _ definitions.
The extraction module is further configured to:
if the top module exists, analyzing all row information behind the top module in the VVP file, extracting and storing Gate-level key information corresponding to other logic keys according to the other logic keys in the preset logic key table into a global list Gate _ states, wherein the other logic keys are logic keys in the preset logic key table except for a combinational logic udp key and a sequential logic udp key.
A definition module: and the semantic redefining module is used for redefining the gate level key information of the nodes corresponding to the logic keywords according to the redefining rules corresponding to the logic keywords to obtain the redefined gate level key information of the nodes.
The definition module is further configured to:
creating a second global dictionary Gate _ Dict;
traversing the global list Gate _ states and sequentially acquiring character strings of Gate-level key information of each node in the global list Gate _ states;
analyzing the character strings of the gate-level key information of each node and extracting the key words of the gate-level key information of each node;
matching and inquiring keywords of the gate-level key information of each node against the preset logic keyword table to find corresponding logic keywords in the preset logic keyword table and determine the type of each node and the redefinition rule of the gate-level key information of each node according to the logic keywords;
and setting keys and values of the second global dictionary Gate _ Dict according to redefinition rules of the Gate-level key information of each node and the Gate-level key information of each node.
The definition module is further configured to:
and if the node is a basic logic Gate node, setting keys and values of the second global dictionary Gate _ Dict according to a four-input one-output Gate level definition rule and Gate level key information of the node.
The definition module is further configured to:
extracting a node ID, a type name of the node, an input ID of the node, an output ID of the node and an output bit width of the node from the gate-level key information of the node;
storing the node ID into a key of the second global dictionary Gate _ Dict;
storing the type name of the node into a type list of the value of the second global dictionary Gate _ Dict;
sequentially storing the input ID and the constant value of the node into a four-input list of the value of the second global dictionary Gate _ Dict;
storing the output ID of the node into an output list of the value of the second global dictionary Gate _ Dict;
and storing the output bit width of the node into a bit width list of the value of the second global dictionary Gate _ Dict.
The translation module: and the method is used for translating the gate-level key information of each redefined node in a preset general format to obtain a directed graph file.
The translation module is further to:
traversing the second global dictionary Gate _ Dict and converting information in the second global dictionary Gate _ Dict in a JSON format to obtain a first directed graph file;
and traversing the first global dictionary udp _ definitions and converting the information in the first global dictionary udp _ definitions in a JSON format to obtain a second directed graph file. The preset common format may also be Protocol Buffers format.
Example 3
Referring to fig. 3, the present invention further provides a gate level circuit translation apparatus, which is a gate level circuit translation apparatus according to a third embodiment of the present invention and includes a memory 20, a processor 10 and a computer program 30 stored in the memory and executable on the processor, wherein the processor 10 implements the gate level circuit translation method as described above when executing the computer program 30.
The gate level circuit translation device may be a computer, a server, an upper computer, and the like, and the processor 10 may be a Central Processing Unit (CPU), a controller, a microcontroller, a microprocessor, or other data Processing chip in some embodiments, and is configured to run program codes or process data stored in the memory 20, for example, execute an access restriction program.
The memory 20 includes at least one type of readable storage medium, which includes a flash memory, a hard disk, a multimedia card, a card type memory (e.g., SD or DX memory, etc.), a magnetic memory, a magnetic disk, an optical disk, and the like. The memory 20 may in some embodiments be an internal storage unit of the translation device of the gate level circuit, for example a hard disk of the translation device of the gate level circuit. The memory 20 may also be an external storage device of the door level circuit translation device in other embodiments, such as a plug-in hard disk provided on the door level circuit translation device, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and so on. Further, the memory 20 may also include both internal storage units and external storage devices of the translation apparatus of the gate level circuit. The memory 20 can be used not only for storing application software of the translation apparatus installed in the gate level circuit and various kinds of data, but also for temporarily storing data that has been output or is to be output.
It should be noted that the structure shown in fig. 3 does not constitute a limitation on the translation apparatus of the gate level circuit, which may include fewer or more components than shown, or some components in combination, or a different arrangement of components in other embodiments.
Embodiments of the present invention further provide a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the translation method of the gate level circuit as described above.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for translating gate level circuits, the method comprising:
generating a VVP file according to a target gate-level netlist file and a process library file, wherein the target gate-level netlist file is a text file for describing gate-level semantics of connection relations among circuit devices, the process library file comprises logic elements forming the circuit devices, and the VVP file is a text file for describing the gate-level semantics of the connection relations among the logic elements of nodes;
inputting a VVP file name and a top module name of the target gate-level netlist file from a command line and setting the top module name as a global variable;
acquiring a preset logic keyword table, analyzing the VVP file according to the global variable and the index of each logic keyword in the preset logic keyword table, and extracting gate-level key information of a node corresponding to each logic keyword;
redefining gate level semantic meaning of the gate level key information of the nodes corresponding to the logic keywords according to redefining rules corresponding to the logic keywords to obtain redefined gate level key information of the nodes;
and translating the gate-level key information of each redefined node in a preset general format to obtain a directed graph file.
2. The method of claim 1, wherein the step of parsing the VVP file according to the global variable and the index of each logical key in the preset logical key table and extracting the gate-level key information of the node corresponding to each logical key comprises:
reading each row of information in the VVP file in sequence from the file header of the VVP file and inquiring whether a top module exists in the row information or not;
if the top module does not exist, judging whether a combinational logic udp key word or a sequential logic udp key word exists in the row information in the VVP file;
if the combinational logic udp key word or the sequential logic udp key word exists, analyzing a relevant segment of the combinational logic udp or the sequential logic udp, and extracting and storing a truth table and gate-level key information of a node corresponding to the combinational logic udp key word or the sequential logic udp key word into a first global dictionary.
3. The gate level circuit translation method according to claim 2, wherein the step of reading each row of information in the VVP file in sequence from the file header of the VVP file and querying whether a top module exists in the row of information further comprises:
and if the top module exists, analyzing all row information behind the top module in the VVP file, extracting and storing gate-level key information corresponding to the logic key according to the logic key in the preset logic key table, wherein the udp logic key in the preset logic key table is an udp logic key except for a combinational logic udp key and a sequential logic udp key.
4. The gate level circuit translation method according to claim 3, wherein the step of redefining the gate level key information of the node corresponding to each of the logical keys according to the redefinition rules corresponding to each of the logical keys to obtain the redefined gate level key information of each of the nodes comprises:
creating a second global dictionary;
traversing the global list and sequentially acquiring character strings of gate-level key information of all nodes in the global list;
analyzing the character strings of the gate-level key information of each node and extracting the key words of the gate-level key information of each node;
matching and inquiring keywords of the gate level key information of each node against the preset logic keyword table to find corresponding logic keywords in the preset logic keyword table, and determining the type of each node and the redefinition rule of the gate level key information of each node according to the logic keywords;
and setting keys and values of the second global dictionary according to redefinition rules of the gate-level key information of each node and the gate-level key information of each node.
5. The method for translating gate level circuits according to claim 4, wherein the step of setting keys and values of the second global dictionary according to redefinition rules of gate level key information of each node and gate level key information of each node comprises:
and if the node is a basic logic gate node, setting keys and values of the second global dictionary according to a four-input one-output gate level definition rule and gate level key information of the node.
6. The method for gate level circuit translation of claim 5, wherein said step of setting keys and values of said second global dictionary according to four-input-one-output gate level definition rules and gate level key information of said nodes comprises:
extracting a node ID, a node type name, a node input ID, a node output ID and a node output bit width from the gate-level key information of the node;
storing the node ID into a key of the second global dictionary;
storing the type name of the node into a type list of the value of the second global dictionary;
sequentially storing the input ID and the constant value of the node into a four-input list of the values of the second global dictionary;
storing the output ID of the node into an output list of values of the second global dictionary;
and storing the output bit width of the node into the bit width list of the value of the second global dictionary.
7. The method for translating gate level circuits according to claim 4, wherein the step of translating the gate level key information of each redefined node in a predetermined common format to obtain the directed graph file comprises:
traversing the first global dictionary and converting information in the first global dictionary in a JSON format to obtain a first directed graph file;
traversing the second global dictionary and converting the information in the second global dictionary in a JSON format to obtain a second directed graph file.
8. A translation system for gate level circuitry, comprising:
a generation module: the system comprises a VVP file, a node selection unit and a node selection unit, wherein the VVP file is used for generating a VVP file according to a target gate-level netlist file and a process library file, the target gate-level netlist is a text file used for describing gate-level semantics of connection relations among circuit devices, the process library file comprises logic elements forming the circuit devices, and the VVP file is a text file used for describing the gate-level semantics of the connection relations among the logic elements of the nodes;
setting a module: the device comprises a command line, a target gate-level netlist file, a VVP file name and a top module name, wherein the top module name is used for inputting the VVP file name and the top module name of the target gate-level netlist file from the command line and is set as a global variable;
an extraction module: the VVP file is used for acquiring a preset logic keyword table, analyzing the VVP file according to the global variable and the index of each logic keyword in the preset logic keyword table, and extracting gate-level key information of a node corresponding to each logic keyword;
a definition module: the system comprises a logic key and a semantic database, wherein the logic key is used for redefining gate level semantic meaning of gate level key information of nodes corresponding to the logic keys according to redefining rules corresponding to the logic keys to obtain the redefined gate level key information of the nodes;
the translation module: and the method is used for translating the gate-level key information of each redefined node in a preset general format to obtain a directed graph file.
9. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the translation method of a gate level circuit according to any one of claims 1 to 7.
10. Apparatus for translating gate level circuitry comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor when executing the program implementing a method for translating gate level circuitry as claimed in any one of claims 1 to 7.
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