CN114490461B

CN114490461B - Data transfer control method, storage medium and equipment

Info

Publication number: CN114490461B
Application number: CN202011167579.2A
Authority: CN
Inventors: 刘君
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2020-10-27
Filing date: 2020-10-27
Publication date: 2024-03-29
Anticipated expiration: 2040-10-27
Also published as: CN114490461A

Abstract

The application discloses a data transfer control method, a storage medium and a device, wherein the method comprises the following steps: acquiring a data transfer state corresponding to target data processed by a subsystem; acquiring a number sequence corresponding to the data transfer state from the number sequence set, and acquiring number information sequenced in the first bit from the number sequence; when the number information is the system number corresponding to the subsystem, executing data transfer operation indicated by the data transfer state, and eliminating the system number from the number sequence; when the number information is not the system number corresponding to the subsystem, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be ordered to the first bit in the number sequence, executing the data transfer operation indicated by the data transfer state, and eliminating the system number from the number sequence. By adopting the method and the device, the channels can be decoupled, each channel can be guaranteed to independently perform data transfer operation, the utilization rate of the channel is improved, and then the data transfer efficiency is improved.

Description

Data transfer control method, storage medium and equipment

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a data transfer control method, a storage medium, and a device.

Background

Direct memory access (Direct Memory Access, DMA) modules are one of the important components of modern computers that can transfer data from one address space to another without relying on the significant load of a central processor. Conventional DMA modules are processes for implementing data transfer through a reusable channel, and may include: the method comprises the steps of an instruction transmission channel, an address transmission channel, a data transfer channel and a storage response channel, wherein the channel is a process for realizing data transfer based on a time-sharing multiplexing strategy, when one subsystem in the DMA module occupies the channel to perform data transfer operation, and when another data transfer instruction of the other subsystem exists, the other subsystem can operate the received data transfer instruction to occupy the channel to perform another data transfer operation after the current subsystem finishes data transfer and releases the channel. Because the channels are in a coupled state and have time sequence dependency, the channel utilization rate is low, and the data transfer efficiency is further affected.

Disclosure of Invention

The embodiment of the application provides a data transfer control method, a storage medium and equipment, which can decouple channels, ensure that each channel can independently perform data transfer operation, improve the utilization rate of the channels, and further improve the efficiency of data transfer.

An embodiment of the present application provides a data transfer control method, applied to a DMA, including:

acquiring a data transfer state corresponding to target data processed by a subsystem, wherein the data transfer state is used for representing an execution stage in a data transfer process of the target data;

acquiring a number sequence corresponding to the data transfer state from a number sequence set, and acquiring number information sequenced in the first bit from the number sequence;

when the number information is the system number corresponding to the subsystem, executing the data transfer operation indicated by the data transfer state, and eliminating the system number from the number sequence;

when the number information is not the system number corresponding to the subsystem, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be ordered to the first bit in the number sequence, executing the data transfer operation indicated by the data transfer state, and eliminating the system number from the number sequence;

wherein the system numbers are stored in the same ordering positions in each numbered sequence of the set of numbered sequences, respectively.

A second aspect of the embodiments of the present application provides a data transfer control method, which is applied to DMA, including:

acquiring a number sequence corresponding to the data transfer state from a number sequence set, and storing a system number corresponding to the subsystem into the number sequence;

when the system number is the number information ordered in the first bit in the number sequence, executing the data transfer operation indicated by the data transfer state, and eliminating the system number from the number sequence;

and when the system number is not the number information which is ordered to the first bit in the number sequence, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be ordered to the first bit in the number sequence, executing the data transfer operation indicated by the data transfer state, and eliminating the system number from the number sequence.

A third aspect of the present embodiment provides a data transfer control device, applied to a DMA, including:

the state acquisition unit is used for acquiring a data transfer state corresponding to target data processed by the subsystem, wherein the data transfer state is used for representing an execution stage in a data transfer process of the target data;

The number information acquisition unit is used for acquiring a number sequence corresponding to the data transfer state from a number sequence set and acquiring number information sequenced in the first bit from the number sequence;

the data operation unit is used for executing the data transfer operation indicated by the data transfer state when the number information is the system number corresponding to the subsystem, and eliminating the system number from the number sequence;

the data operation unit is further configured to suspend a data transfer operation indicated by the data transfer state when the number information is not a system number corresponding to the subsystem, wait for the system number to be ordered to a first bit in the number sequence, execute the data transfer operation indicated by the data transfer state, and reject the system number from the number sequence;

A fourth aspect of the present application provides a data transfer control device, applied to a DMA, including:

the system comprises a number storage unit, a number sequence set and a number sequence storage unit, wherein the number storage unit is used for acquiring a data transfer state corresponding to target data processed by a subsystem, acquiring a number sequence corresponding to the data transfer state in the number sequence set, and storing a system number corresponding to the subsystem into the number sequence, wherein the data transfer state is used for representing an execution stage in a data transfer process of the target data;

A data operation unit, configured to execute a data transfer operation indicated by the data transfer state when the system number is number information ordered in a first bit in the number sequence, and reject the system number from the number sequence;

and the data operation unit is further used for suspending the data transfer operation indicated by the data transfer state when the system number is not the number information ordered in the first bit in the number sequence, waiting for the system number to be ordered to the first bit in the number sequence, executing the data transfer operation indicated by the data transfer state, and eliminating the system number from the number sequence.

A fifth aspect of the embodiments of the present application provides a computer device, including a processor, a memory, and an input-output interface;

the processor is respectively connected with the memory and the input/output interface, wherein the input/output interface is used for page interaction, the memory is used for storing program codes, and the processor is used for calling the program codes to execute the steps of the method.

A sixth aspect of the embodiments provides a computer storage medium storing a computer program comprising program instructions which, when executed by a processor, perform the above-described method steps.

In this embodiment of the present application, by acquiring a data transfer state corresponding to target data processed by a subsystem in a DMA module, an execution stage of a data transfer process of current target data may be acquired, and then, by using number information ordered in a first bit indicated by a number sequence corresponding to the data transfer state, a system number corresponding to a subsystem matched with the number information may be acquired, and further, a channel in the current data transfer state may be controlled to execute a data transfer operation process of the subsystem indicated by the system number on the target data, and for non-first bit number information in the number sequence, the current data transfer operation may need to be suspended and waited until the system number becomes the number information ordered in the first bit in the number sequence, and then, the channel may be opened to execute the data transfer operation indicated by the current data transfer state. By setting different number sequences in different data transfer states, each channel can execute data transfer operation of corresponding target data according to system numbers indicated by the number sequences, decoupling of the channels is achieved, each channel can independently execute data transfer operation, channel utilization rate is improved, and data transfer efficiency is further improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a system architecture diagram of a data transfer control provided in an embodiment of the present application;

fig. 2 is a flow chart of a data transfer control method according to an embodiment of the present application;

fig. 3 is a flow chart of a data transfer control method according to an embodiment of the present application;

fig. 4 is a flow chart of a data transfer control method according to an embodiment of the present application;

FIG. 5 is a schematic flow chart of data transfer in an address release state according to an embodiment of the present application;

FIG. 5a is a schematic diagram illustrating data transfer in an address release state according to an embodiment of the present application;

FIG. 6 is a schematic flow chart of data transfer in a data storage state according to an embodiment of the present application;

FIG. 6a is a schematic diagram illustrating data transfer in a data storage state according to an embodiment of the present application;

FIG. 7 is a schematic flow chart of data transfer in a storage response state according to an embodiment of the present application;

FIG. 7a is a schematic diagram illustrating an exemplary data transfer in a storage response state according to an embodiment of the present application;

fig. 8 is a schematic flow chart of data transfer in a data receiving state according to an embodiment of the present application;

FIG. 8a is a schematic diagram illustrating data transfer in a data receiving state according to an embodiment of the present application;

FIG. 8b is a schematic diagram illustrating data transfer in a data receiving state according to an embodiment of the present application;

FIG. 9 is a schematic flow chart of data transfer in a data transfer state according to an embodiment of the present application;

FIG. 9a is a schematic diagram illustrating data transfer in a data transfer state according to an embodiment of the present application;

FIG. 10 is an exemplary schematic diagram of a data transfer control method according to an embodiment of the present disclosure;

FIG. 11 is a flow chart of a data transfer control method according to an embodiment of the present disclosure;

FIG. 12 is a schematic flow chart of data transfer in an address release state according to an embodiment of the present disclosure;

FIG. 12a is a schematic diagram illustrating data transfer in an address release state according to an embodiment of the present application;

FIG. 13 is a schematic flow chart of data transfer in a data storage state according to an embodiment of the present application;

FIG. 13a is a schematic diagram illustrating data transfer in a data storage state according to an embodiment of the present application;

FIG. 14 is a schematic flow chart of data transfer in a storage response state according to an embodiment of the present application;

FIG. 14a is an exemplary diagram of data transfer in a store response state provided by embodiments of the present application;

fig. 15 is a schematic flow chart of data transfer in a data receiving state according to an embodiment of the present application;

FIG. 15a is a schematic diagram illustrating data transfer in a data receiving state according to an embodiment of the present application;

FIG. 16 is a schematic flow chart of data transfer in a data transfer state according to an embodiment of the present application;

FIG. 16a is a schematic diagram illustrating data transfer in a data transfer state according to an embodiment of the present application;

FIG. 17 is an exemplary schematic diagram of a data transfer control method according to an embodiment of the present disclosure;

FIG. 18 is a timing diagram of the execution of channels in a DMA according to an embodiment of the present application;

FIG. 19 is a timing diagram of the execution of channels in a DMA according to an embodiment of the present application;

FIG. 20 is a timing diagram of the execution of channels in a DMA according to an embodiment of the present application;

Fig. 21 is a schematic structural diagram of a data transfer control apparatus according to an embodiment of the present application;

fig. 22 is a schematic structural diagram of a data transfer control apparatus according to an embodiment of the present application;

fig. 23 is a schematic structural diagram of a data transfer control apparatus according to an embodiment of the present application;

FIG. 24 is a schematic diagram of a computer device according to an embodiment of the present disclosure;

fig. 25 is a schematic structural diagram of a data transfer control apparatus according to an embodiment of the present application;

fig. 26 is a schematic structural diagram of a computer device according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

Referring to fig. 1, a system architecture diagram for data transfer control is provided in an embodiment of the present application. As shown in fig. 1, the embodiment of the present application may be applied to a scenario of data transfer of a DMA module, where the data transfer may be represented as data copying, data migration, and the DMA data transfer process may be transferring data from one address space in a source storage module to another address space in a destination storage module, where the source storage module and the destination storage module may be external independent storage devices, a memory in a computer device, and so on, for performing data storage, where the computer device may include, but is not limited to, a personal computer, a notebook computer, smart furniture, a wearable device, a vehicle device, and so on.

Referring to fig. 1 again, fig. 1 also shows a specific architecture of a DMA module, where the DMA module may include an instruction sending module, a subsystem, a data transfer control device, and a channel managed by the data transfer control device, where the instruction sending module is configured to generate a data transfer instruction from a source storage module to a destination storage module, and allocate the data transfer instruction to an idle subsystem for performing data transfer processing, and the subsystem may include multiple subsystems, for example: the subsystem 1, the subsystem 2, the subsystem … and the subsystem N, N are positive integers, and the subsystem is used for analyzing the received data transfer instruction to obtain storage address information carried in the data transfer instruction, wherein the storage address information can comprise a source storage address in a source storage module and a destination storage address in a destination storage module, and the storage address information is used for indicating the current storage position of target data to be transferred and the target storage position to be stored.

The plurality of subsystems can share channels in the DMA module, and the channels can include, but are not limited to, an instruction transmission channel, a source address transmission channel, a data receiving channel, a destination address transmission channel, a data sending channel and a storage response channel according to the execution sequence of the data transfer process, wherein the instruction transmission channel is used for transmitting a data transfer instruction generated by the instruction sending module to a corresponding subsystem, the source address transmission channel is used for sending a source storage address obtained by the subsystem to the source storage module, the data receiving channel is used for receiving target data returned by the source storage module based on the source storage address, the destination address transmission channel is used for sending a destination storage address obtained by the subsystem to the destination storage module, the data sending channel is used for transmitting the target data to an address space of a destination storage address of the destination storage module, and the storage response channel is used for receiving storage response information returned after the destination storage module stores the target data.

The data transfer control device may be configured to select, from the information input by the current channel, information corresponding to the current data transfer processing period to output, and may specifically be configured to select, according to the input information such as the data transfer instruction, the storage address information, the target data, the response signal, and the like, the corresponding information in the current data transfer processing period to output.

It can be appreciated that each subsystem may be pre-assigned a corresponding system number for distinguishing the subsystems; the data transfer state may be used to represent an execution stage in a data transfer process of the target data, optionally, the data transfer state corresponds to the system number, and since the subsystem can only participate in executing a data transfer process indicated by a data transfer instruction at a time, the data transfer state in the current data transfer process is related to the system number of the subsystem, and the data transfer state may be according to an execution sequence of the data transfer process, including, but not limited to, an instruction transmission state, an address release state, a data storage state, a storage response state, and the like, where the instruction transmission state is used to represent that the current execution stage is in an instruction sending module to transmit the data transfer instruction to the subsystem, the address release state is used to represent that the current execution stage is in a state where the data transfer control device receives storage address information sent by the subsystem, and then, after receiving the target data from the source storage module, the target data is transmitted to the destination storage module, and the storage response state is used to represent that the current execution stage is in a state where the response signal is received from the destination storage module.

Alternatively, the data transfer control device may be a module for managing all channels in the DMA, or may include a plurality of data transfer control devices distributed on a plurality of channels in the DMA, where the data transfer control devices may correspond to the channels one by one as shown in fig. 1, where the data transfer control devices may include, but are not limited to, a data transfer control device 10, a data transfer control device 20, a data transfer control device 30, a data transfer control device 40, a data transfer control device 50, and a data transfer control device 60, where the data transfer control device 10, the data transfer control device 20, the data transfer control device 30, the data transfer control device 40, the data transfer control device 50, and the data transfer control device 60 may be connected to each other, and where a plurality of subsystems are connected to each other, and where the data transfer control device 10 is further connected to an instruction sending module.

Specifically, the data transfer control device 10 is configured to set a data transfer state to an instruction transmission state when a data transfer instruction sent by the instruction sending module is obtained, and control the instruction transmission channel to transmit the data transfer instruction to a corresponding subsystem; the data transfer control device 20 is configured to set a data transfer state to an address release state when a source storage address sent by the subsystem is acquired, and control a source address transmission channel to send the source storage address to a source storage module; the data transfer control device 30 is configured to set a data transfer state to a data storage state when the data receiving channel obtains the target data returned by the source storage module, and transmit the target data to the data transfer control device 50 to be ready to be sent to the destination storage module; the data transfer control device 40 is configured to, when a destination storage address sent by the subsystem is obtained, control the destination address transmission channel to send the destination storage address to the destination storage module when the data transfer state is an address release state, or control the destination address transmission channel to send the destination storage address to the destination storage module when the data transfer state is a data storage state, and specifically select a sending opportunity according to actual requirements; the data transfer control device 50 is configured to control the data transmission channel to transmit the obtained target data to the destination storage module when the data transfer state is a data storage state; the data transfer control device 60 acquires a response signal returned by the target storage module from the storage response channel, sets the data transfer state to be a storage response state, and sends the response signal to the subsystem; at this time, the subsystem may send a response signal to the instruction sending module, and the data transfer control device 10 is further configured to obtain the response signal sent by the subsystem, and control the instruction transmission channel to send the response signal to the instruction sending module. Thereby completing a complete data transfer process.

It should be noted that, the data transfer state may be synchronized with the data transfer control device 10, the data transfer control device 20, the data transfer control device 30, the data transfer control device 40, the data transfer control device 50, and the data transfer control device 60, and when one data transfer state is set, the previous data transfer state may be replaced, and after the data transfer process is completed, the data transfer state corresponding to the system number may be removed, or the data transfer state may be reset to an initial value, for example: the data transfer state may be represented by a null value after reset. When the data transfer control apparatus is a module as a whole, all functions of the data transfer control apparatus 10, the data transfer control apparatus 20, the data transfer control apparatus 30, the data transfer control apparatus 40, the data transfer control apparatus 50, and the data transfer control apparatus 60 may be provided, and a mode of selecting a part of apparatuses from a plurality of data transfer control apparatuses for combination or decomposing a certain data transfer control apparatus into a plurality of functional modules is within the scope of protection of the present application.

In the existing DMA data transfer process, because time sequence dependency relationship exists among channels of the DMA, namely, all channels can be released to execute the data transfer process indicated by the next data transfer instruction only after waiting for the completion of the data transfer process indicated by the current data transfer instruction, the channels have empty conditions in the data transfer process, and the utilization rate of the channels and the data transfer efficiency are affected.

In the embodiment of the application, two different data transfer processes are provided, it can be understood that the existing memory module can be divided into a memory module supporting only order preservation or a memory module supporting order preservation and disorder, and for the memory module supporting order preservation, when a plurality of data transfer processes indicated by a plurality of data transfer instructions exist, the data transfer processes need to be used in sequence according to the sending sequence of the data transfer instructions when the same channel is used, so that the memory module cannot be used for correctly processing target data to be transferred due to disorder sending of information corresponding to a system number; for the storage module supporting disorder, when there are multiple data transfer processes indicated by multiple data transfer instructions, when the same channel is used, the data transfer operation of the system number on the channel can be executed first according to the first-in first-out principle, i.e. which information corresponding to the system number is received first, and the storage module can correctly identify the system number so as to ensure that the storage module correctly processes the target data to be transferred.

Based on the system architecture shown in fig. 1, the data transfer control method provided in the embodiment of the present application will be described in detail with reference to fig. 2 to fig. 10, where the embodiment shown in fig. 2 to fig. 10 may be implemented in a data transfer scenario of a storage module supporting order preservation.

Referring to fig. 2, a flow chart of a data transfer control method is provided in an embodiment of the present application. As shown in fig. 2, the method of the embodiment of the present application may include the following steps S101 to S104.

S101, acquiring a data transfer state corresponding to target data processed by a subsystem;

specifically, the data transfer control device may obtain a data transfer state corresponding to the target data processed by the subsystem, where the data transfer state may be used to represent an execution stage in a data transfer process of the target data, and it may be understood that the data transfer state corresponds to the system number, and since the subsystem may only participate in executing a data transfer process indicated by one data transfer instruction at a time, the data transfer state in the current data transfer process may be related to the system number of the subsystem, and the data transfer state may be according to an execution sequence of the data transfer process, including, but not limited to, an address release state, a data storage state, a storage response state, and so on.

S102, acquiring a number sequence corresponding to the data transfer state from a number sequence set, and acquiring number information sequenced in the first bit from the number sequence;

Specifically, the data transfer control device may be preset with a number sequence set, where the number sequence set may include a plurality of number sequences, and may include, but not be limited to, an instruction number sequence, a storage number sequence, and a response number sequence, where in each data transfer state, there may be one number sequence, where the number sequence may be used to instruct the data transfer control device to sequentially execute a data transfer operation indicated by the system number in the current data transfer state according to an arrangement sequence of the system number in the number sequence, where the arrangement sequence of the system number in the number sequence may be specifically determined according to a transmission sequence of a data transfer instruction, and it may be understood that the data transfer instruction is sequentially transmitted to each subsystem by the data transfer control device, where the data transfer control device may obtain a system number corresponding to each of the plurality of subsystems that receive the data transfer instruction, and the data transfer control device may sequentially store the plurality of system numbers in the number sequence according to the transmission sequence of the data transfer instruction. Optionally, the data transfer control device may acquire a number sequence corresponding to the data transfer state from a number sequence set, and acquire number information ordered in a first bit from the number sequence, where the number information ordered in the first bit is used to indicate a system number for executing a data transfer operation indicated by the current data transfer state.

S103, when the number information is the system number corresponding to the subsystem, executing the data transfer operation indicated by the data transfer state, and eliminating the system number from the number sequence;

specifically, when the number information is the system number corresponding to the subsystem, the system number is indicated to be currently in the first bit of the number sequence, the data transfer control device may control the channel to directly perform the data transfer operation indicated by the data transfer state, and at the same time, the data transfer control device may reject the system number from the number sequence, where at this time, the sorting positions of the rest of the number information in the number sequence may be shifted forward by one bit, for example: the system numbers ordered in the second bit may be ordered to the first bit in the sequence of numbers after the system numbers are removed.

S104, when the number information is not the system number corresponding to the subsystem, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be ordered to the first bit in the number sequence, executing the data transfer operation indicated by the data transfer state, and eliminating the system number from the number sequence;

Specifically, when the number information is not the system number corresponding to the subsystem, which indicates that the system number is not currently located in the first bit of the number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state, for example: suspending the data transfer operation, waiting for the system numbers to be sorted to the first bit in the number sequence, and when the system numbers are sorted to the first bit in the number sequence, the data transfer control device can control the channel to continue to execute the data transfer operation indicated by the data transfer state, and meanwhile, the data transfer control device can reject the system numbers from the number sequence because the rest of the system numbers sorted in the number sequence before the system numbers are sequentially subjected to respective data transfer operations and then are rejected from the number sequence.

In this embodiment of the present application, by acquiring a data transfer state corresponding to target data processed by a subsystem in a DMA module, an execution stage of a data transfer process of current target data may be acquired, and then, by using number information ordered in a first bit indicated by a number sequence corresponding to the data transfer state, a system number corresponding to a subsystem matched with the number information may be acquired, and further, a channel in the current data transfer state may be controlled to execute a data transfer operation process of the subsystem indicated by the system number on the target data, and for non-first bit number information in the number sequence, the current data transfer operation may need to be suspended and waited until the system number becomes the number information ordered in the first bit in the number sequence, and then, the channel may be opened to execute the data transfer operation indicated by the current data transfer state. By setting different number sequences in different data transfer states, each channel can execute data transfer operation of corresponding target data according to system numbers indicated by the number sequences, a complete data transfer process can be split into a plurality of data transfer operations corresponding to the data transfer states through a number sequence set, and the data transfer operations of the system numbers can be sequentially executed according to the arrangement sequence of the system numbers in the number sequences in the same data transfer state, so that decoupling of the channels is realized, each channel can independently execute the data transfer operation, and meanwhile, the system numbers are stored in the same ordering positions in the number sequences of the number sequence set, that is, in each data transfer state, the corresponding data transfer operation is executed according to the arrangement sequence of the same system codes, and on the basis of guaranteeing the execution sequence of each data transfer instruction, the channel utilization rate is improved, and further the data transfer efficiency is improved.

In this embodiment, two possible implementations may be included for storing the system number to the same ordering position in each number sequence of the number sequence set, where the first implementation may be to record the system number of the subsystem that receives the data transfer instruction when the data transfer instruction is received, and pre-store the system number to the same ordering position in each number sequence; the second embodiment may be to add the system number to the next number sequence of the current number sequence after each system number is removed from the current number sequence.

Referring to fig. 3, a flow chart of a data transfer control method is provided for an embodiment of the present application. As shown in fig. 3, the method of the embodiment of the present application may include the following steps S111 to S116.

S111, when an instruction sending module sends a data transfer instruction to a subsystem, acquiring a system number corresponding to the subsystem;

specifically, when the instruction sending module sends a data transfer instruction to a subsystem, the data transfer control device may acquire the data transfer instruction, and optionally, the instruction sending module may designate one of the subsystems to receive the data transfer instruction, for example: the instruction sending module records system numbers of a plurality of subsystems, the instruction sending module can send the designated system numbers and the data transfer instructions to the data transfer control equipment, and the data transfer control equipment can send the data transfer instructions to the subsystems corresponding to the system numbers; of course, the data transfer instruction may also be sent to one subsystem by the data transfer control device according to the idle states of the plurality of subsystems. After the data transfer control device receives the data transfer instruction, the data transfer control device may further acquire a system number corresponding to a subsystem that receives the data transfer instruction, and set a data transfer state corresponding to the system number to an instruction transmission state.

S112, storing the system numbers to the same ordering positions in each number sequence of a number sequence set respectively;

specifically, the data transfer control device may store the system number to the same ordering position in each number sequence of the number sequence set, where the number sequence set may include a plurality of number sequences, and may specifically include, but is not limited to, an instruction number sequence, a storage number sequence, and a response number sequence, where it is understood that the ordering position of the system number in each number sequence is related to the sending order of the data transfer instruction, for example: when the data transfer control device receives the first data transfer instruction 1, the data transfer instruction 1 is sent to the subsystem 1, the system number S1 of the subsystem 1 can be obtained, the S1 is stored to the first bit in each number sequence respectively, at the moment, a second data transfer instruction 2 is received again, the data transfer instruction 2 is sent to the subsystem 2, the system number S2 of the subsystem 2 can be obtained, the S2 is stored to each number sequence respectively, at the moment, the S2 is located after the S1 in each number sequence respectively, namely, the second bit and the like; of course, if S2 is stored with S1 in a numbered sequence being deleted, the ordering position of S2 in the numbered sequence is the first bit.

S113, acquiring a data transfer state corresponding to target data processed by the subsystem;

s114, acquiring a number sequence corresponding to the data transfer state from a number sequence set, and acquiring number information sequenced in the first bit from the number sequence;

s115, when the number information is the system number corresponding to the subsystem, executing the data transfer operation indicated by the data transfer state, and eliminating the system number from the number sequence;

s116, when the number information is not the system number corresponding to the subsystem, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be ordered to the first bit in the number sequence, executing the data transfer operation indicated by the data transfer state, and eliminating the system number from the number sequence;

it should be noted that, the steps S113 to S116 in the embodiment of the present application may be respectively referred to the specific descriptions of the steps S101 to S104 in the embodiment shown in fig. 2, and are not described herein.

In this embodiment of the present application, by acquiring a data transfer state corresponding to target data processed by a subsystem in a DMA module, an execution stage of a data transfer process of current target data may be acquired, and then, by using number information ordered in a first bit indicated by a number sequence corresponding to the data transfer state, a system number corresponding to a subsystem matched with the number information may be acquired, and further, a channel in the current data transfer state may be controlled to execute a data transfer operation process of the subsystem indicated by the system number on the target data, and for non-first bit number information in the number sequence, the current data transfer operation may need to be suspended and waited until the system number becomes the number information ordered in the first bit in the number sequence, and then, the channel may be opened to execute the data transfer operation indicated by the current data transfer state. By setting different number sequences in different data transfer states, each channel can execute data transfer operation of corresponding target data according to system numbers indicated by the number sequences respectively, a complete data transfer process can be split into a plurality of data transfer operations corresponding to the data transfer states respectively through a number sequence set, and under the same data transfer state, the data transfer operation of each system number can be sequentially executed according to the arrangement sequence of the system numbers in the number sequences, so that decoupling of the channels is realized, each channel can be ensured to independently execute the data transfer operation, and meanwhile, the system numbers are stored in the same ordering positions in the number sequences of the number sequence set in advance when data transfer instructions are sent, that is, under each data transfer state, the corresponding data transfer operation is executed according to the same arrangement sequence of system codes, and on the basis of guaranteeing the execution sequence of each data transfer instruction, the channel utilization rate is improved, and the data transfer efficiency is further improved.

Referring to fig. 4, a flow chart of a data transfer control method is provided for an embodiment of the present application. As shown in fig. 4, the method of the embodiment of the present application may include the following steps S121 to S125.

S121, acquiring a data transfer state corresponding to target data processed by the subsystem;

s122, acquiring a number sequence corresponding to the data transfer state from a number sequence set, and acquiring number information sequenced in the first bit from the number sequence;

s123, when the number information is the system number corresponding to the subsystem, executing the data transfer operation indicated by the data transfer state, and eliminating the system number from the number sequence;

s124, when the number information is not the system number corresponding to the subsystem, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be ordered to the first bit in the number sequence, executing the data transfer operation indicated by the data transfer state, and eliminating the system number from the number sequence;

it should be noted that, the steps S121 to S124 in the embodiment of the present application may refer to the specific descriptions of the steps S101 to S104 in the embodiment shown in fig. 2, and are not described herein.

S125, storing the system number into the next sequence of the number sequence;

specifically, while the system number is removed from the number sequence, the data transfer control device may store the system number in a next sequence of the number sequence, where the next sequence is a sequence ordered after the number sequence in a number sequence set including an instruction number sequence, a storage number sequence, and a response number sequence according to a transformation order of the data transfer state. For example: if the system number is removed from the instruction number sequence, the system number can be added into a storage number sequence; if the system number is removed from the stored number sequence, the system number can be added to the response number sequence; of course, if the system number is removed from the response number sequence, it indicates that the data transfer process corresponding to the system number has been completed, and it is unnecessary to occupy any channel to perform the data transfer operation, and only the system number is removed from the response number sequence.

The sequence of instruction numbers is related to the order of transmission of the data transfer instructions, for example: when the data transfer control device receives the first data transfer instruction 1, and sends the data transfer instruction 1 to the subsystem 1, the system number S1 of the subsystem 1 can be obtained, and the S1 is stored to the first bit in the instruction number sequence, at this time, a second data transfer instruction 2 is received, and sends the data transfer instruction 2 to the subsystem 2, the system number S2 of the subsystem 2 can be obtained, and the S2 is stored to the instruction number sequence, where the S2 is located after the S1 in each number sequence, that is, the second bit. Therefore, even if the current data transfer operation is executed by S2 before S1 in the data transfer process, and the system number is removed from the current number sequence and stored in the next sequence when the current data transfer operation is executed, the sorting position of S1 in the next sequence is still ordered before S2 and ordered in the first bit, so that the execution sequence of each data transfer instruction is ensured.

In this embodiment of the present application, by acquiring a data transfer state corresponding to target data processed by a subsystem in a DMA module, an execution stage of a data transfer process of current target data may be acquired, and then, by using number information ordered in a first bit indicated by a number sequence corresponding to the data transfer state, a system number corresponding to a subsystem matched with the number information may be acquired, and further, a channel in the current data transfer state may be controlled to execute a data transfer operation process of the subsystem indicated by the system number on the target data, and for non-first bit number information in the number sequence, the current data transfer operation may need to be suspended and waited until the system number becomes the number information ordered in the first bit in the number sequence, and then, the channel may be opened to execute the data transfer operation indicated by the current data transfer state. By setting different number sequences in different data transfer states, each channel can execute data transfer operation of corresponding target data according to the system number indicated by the number sequence, a complete data transfer process can be split into a plurality of data transfer operations corresponding to the data transfer states respectively through a number sequence set, and under the same data transfer state, the data transfer operation of each system number can be sequentially executed according to the arrangement sequence of the system numbers in the number sequence, so that decoupling of the channels is realized, each channel can be ensured to independently execute the data transfer operation, and meanwhile, the system number is removed from the current number sequence and stored in the next sequence when the current data transfer operation is executed and enters the next data transfer state, so that the system number still maintains the ordering position in the current number sequence before the removal in the next sequence, the channel utilization rate is improved on the basis of ensuring the execution sequence of each data transfer instruction, and further the data transfer efficiency is improved.

The embodiments shown in fig. 5 to 7 will describe the data transfer operation in the address release state, the data storage state, and the storage response state in the data transfer state, respectively.

Referring to fig. 5, a flow chart of data transfer in an address release state is provided in the embodiment of the present application. As shown in fig. 5, the process may include:

s131, when the data transfer state is an address release state, acquiring an instruction number sequence corresponding to the address release state from a sequence number set, and acquiring number information sequenced in the first bit from the instruction number sequence;

specifically, when the instruction sending module sends a data transfer instruction to the subsystem, the data transfer control device may obtain a system number of the subsystem, set a data transfer state corresponding to the system number as an instruction transmission state, and store the system number in an instruction number sequence, optionally, when the data transfer control device receives the data transfer instruction sent to the subsystem by the instruction sending module, the data transfer control device may control the instruction transmission channel to send the data transfer instruction to the subsystem, the subsystem may parse the data transfer instruction to obtain storage address information carried in the data transfer instruction, where the storage address information may include a source storage address and a destination storage address of target data requested to be transferred, when the subsystem obtains the source storage address and the destination storage address, the source storage address may be sent to the data transfer control device, when the data transfer control device receives the data transfer instruction sent to the subsystem by the instruction transmission state, the data transfer control device may set a source storage address and a destination storage address, and may also send the data transfer control data to the data transfer control device in a specific state, and may be sent to the data transfer control device according to the actual storage address, and the data transfer control device may be set to the source storage address and the destination storage address. When the data transfer state is an address release state, the data transfer control device may acquire an instruction number sequence corresponding to the address release state, and acquire number information ordered in the first bit in the instruction number sequence.

S132, when the number information is a system number corresponding to the subsystem, acquiring storage address information corresponding to the system number, sending the source storage address to a source storage module, and eliminating the system number from the instruction number sequence;

specifically, when the number information is the system number, that is, the system number is indicated to be currently ordered in the first bit of the instruction number sequence, the data transfer control device may control the source address transmission channel to send the source storage address corresponding to the system number to the source storage module, alternatively, the data transfer control device may also control the destination address transmission channel to send the destination storage address corresponding to the system number to the destination storage module, or may also transmit the destination storage address and the destination data to the destination storage module together in a data storage state, and may specifically be set according to actual requirements. When the source storage address is sent to the source storage module, according to the first embodiment, the data transfer control device may reject the system number from the instruction number sequence, and according to the second embodiment, the data transfer control device may reject the system number from the instruction number sequence and store the system number to the storage number sequence.

S133, when the number information is not the system number corresponding to the subsystem, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sequenced to the first bit in the number sequence, acquiring storage address information corresponding to the system number, sending the source storage address to a source storage module, and eliminating the system number from the instruction number sequence;

specifically, when the number information is not the system number, that is, it indicates that the system number is not currently ordered at the first bit of the instruction number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state and wait for the system number to be ordered to the first bit in the number sequence. Further, when the system number is ordered to the first bit in the instruction number sequence, the data transfer control device may control the source address transmission channel to send a source storage address corresponding to the system number to the source storage module, and when the source storage address is sent to the source storage module, according to the first embodiment, the data transfer control device may reject the system number from the instruction number sequence, and according to the second embodiment, the data transfer control device may reject the system number from the instruction number sequence and store the system number to the storage number sequence.

Referring to fig. 5a, an exemplary schematic diagram of data transfer in the address release state is provided in the embodiment of the present application. As shown in fig. 5a, the instruction sending module sends the data transfer instruction 1 to the data transfer control device 10, where the data transfer control device 10 controls the instruction transmission channel to send the s1_data transfer instruction to the subsystem 1, and considering that the data transfer instruction 1 carries the system number of the subsystem 1, the data transfer instruction 1 may include the system number S1 of the subsystem 1 and the s1_data transfer instruction, and when the system number S1 does not exist in the data transfer instruction 1, the data transfer instruction 1 is equal to the s1_data transfer instruction.

The data transfer control device 10 may store the system number S1 in the instruction number sequence, and set the data transfer state of S1 to the instruction transmission state, when there is the data transfer instruction 2, similarly to the data transfer instruction 1, the instruction sending module may send the data transfer instruction 2 to the data transfer control device 10, and the data transfer control device 10 may control the instruction transmission channel to send the s2_data transfer instruction to the subsystem 2, store the system number S2 of the subsystem 2 in the instruction number sequence, and set the data transfer state of S2 to the instruction transmission state, as can be seen from fig. 5a, the S1 is ordered in the first bit and the S2 is ordered in the second bit in the instruction number sequence.

The data transfer device 10 may synchronize S1 to the data transfer device 20, which means that the current S1 is ordered in the first bit, the subsystem 1 may parse the s1_data transfer instruction to obtain an s1_source storage address and an s1_destination storage address, and send the s1_source storage address to the data transfer control device 20, and similarly, the subsystem 2 may send the s2_source storage address to the data transfer control device 20, when receiving the s1_source storage address, the data transfer control device 20 may set the data transfer state of the S1 to the address release state from the instruction transmission state, the data transfer control device 20 may synchronize the instruction number sequence to obtain the S1 ordered in the first bit, and may control the source address transmission channel to send the s1_source storage address to the source storage module, the data transfer control device 20 may notify the data transfer control device 10 to reject the S1 from the instruction number sequence, and at this time, the data transfer control device 10 may synchronize the S2 ordered in the first bit to the data transfer control device 20, and similarly, the data transfer control device 20 may set the data transfer state of the S2 to the address from the instruction transmission state to the source storage module, and set the data transfer state of the S2 to the source storage address transmission state from the source storage module.

It should be noted that, since the data transfer control device 10 has already synchronized the first bit S1 of the instruction number sequence to the data transfer control device 20, even if the subsystem 1 causes the subsystem 2 to first send the s2_source storage address to the data transfer control device 20 due to the line delay problem, the data transfer control device 20 will not send the s2_source storage address to the source storage module, and can send the s2_source storage address only when the S2 is ordered in the first bit of the instruction number sequence.

In the embodiment of the application, when the data transfer state corresponding to the system number is in the address release state, the source storage addresses sent by different subsystems can be sequentially sent to the source storage module according to the instruction number sequence, so that decoupling of the source address transmission channel is realized, the source address transmission channel can independently perform the sending process of the source storage address, meanwhile, the system number is removed from the current number sequence when the current data transfer operation is performed, and the utilization rate of the source address transmission channel is improved on the basis of ensuring the sending sequence of the source storage address.

Referring to fig. 6, a flow chart of data transfer in a data storage state is provided in an embodiment of the present application. As shown in fig. 6, the process may include:

S141, when the data transfer state is a data storage state, acquiring a storage number sequence corresponding to the data storage state in a sequence set, and acquiring number information sequenced in the first bit in the storage number sequence;

specifically, when the data transfer control device receives the target data returned by the source storage module based on the source storage address based on the data receiving channel, the data transfer control device may set a data transfer state corresponding to the system number from an address release state to a data storage state, and of course, the data transfer control device may also set the data transfer state from the address release state to the data storage state after sending the source storage address, specifically may set the data transfer control device according to actual requirements, and the data transfer control device may obtain a storage number sequence corresponding to the data storage state in a sequence number set, and obtain number information sequenced in the first bit in the storage number sequence.

When the target data is received, the address bits of the target data can be matched with the source storage address, so that the system number of the target data can be determined, and the matching can also be directly performed through the system number described in the target data.

S142, when the number information is a system number corresponding to the subsystem, transferring target data from a source storage address of a source storage module to a destination storage address of a destination storage module based on the system number, and eliminating the system number from the storage number sequence;

specifically, when the number information is the system number, that is, the system number is indicated to be currently ordered at the first bit of the storage number sequence, the data transfer control device may acquire, based on the data receiving channel, the target data sent by the source storage module, and when the target data is received, may match the address bit of the target data with the source storage address, thereby determining the system number to which the target data belongs, or may directly match the system number described in the target data, and when the target data belonging to the system number is acquired, the data transfer control device may send the target data and the target storage address to the target storage module, where the target data may be sent through the data sending channel, and the target storage address may be sent through the target address transmission channel.

Optionally, the data transfer control device may control the destination address transmission channel to send, in advance, the destination storage address corresponding to the system number to the destination storage module in the address release state, or may store the destination storage address and the system number in association in the address release state, and in the data storage state, acquire the destination storage address based on the system number, and transmit the destination storage address and the destination data to the destination storage module together, where the destination storage address and the destination storage module may be specifically set according to actual requirements. When the target data is sent to the target storage module, according to the first embodiment, the data transfer control device may reject the system number from the storage number sequence, and according to the second embodiment, the data transfer control device may reject the system number from the storage number sequence and store the system number to the response number sequence.

S143, when the number information is not the system number corresponding to the subsystem, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be ordered to the first bit in the number sequence, transferring the target data from the source storage address of the source storage module to the destination storage address of the destination storage module based on the system number, and eliminating the system number from the storage number sequence;

Specifically, when the number information is not the system number, that is, it indicates that the system number is not currently ordered at the first bit of the storage number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state and wait for the system number to be ordered to the first bit in the storage number sequence. Further, when the system number is ordered to the first bit in the number sequence, the data transfer control device may acquire, based on a data receiving channel, target data sent by a source storage module, and when the target data is received, may match the address bit of the target data with the source storage address, thereby determining a system number to which the target data belongs, or may directly match the system number described in the target data, and when the target data belonging to the system number is acquired, the data transfer control device may send the target data and the destination storage address to a destination storage module, where the target data may be sent through a data sending channel, and the destination storage address may be sent through a destination address transmission channel. When the target data is sent to the target storage module, according to the first embodiment, the data transfer control device may reject the system number from the storage number sequence, and according to the second embodiment, the data transfer control device may reject the system number from the storage number sequence and store the system number to the response number sequence.

Referring to fig. 6a, an exemplary schematic diagram of data transfer in a data storage state is provided in the embodiment of the present application. As shown in fig. 6a, the data transfer control device 30 obtains the target data corresponding to the system number S1, that is, s1_the target data received by the source storage module, based on the data receiving channel, the data transfer control device 30 may set the data transfer state of S1 to the data storage state, and the data transfer control device 30 is synchronized with S1 in advance, where, as can be seen from fig. 6a, S1 is located in the first bit of the storage number sequence, and the system number S2 is located in the second bit of the storage number sequence.

The data transfer control device 30 may transmit the received s1_target data received by the source storage module to the data transfer control device 50, the data transfer control device 50 may control the data transmission channel to transmit the s1_target data transmitted to the destination storage module, meanwhile, the data transfer control device 50 may agree with the data transfer control device 40 to notify the data transfer control device 40 to control the destination address transmission channel to transmit the s1_destination storage address to the destination storage module synchronously, the destination storage module may store the s1_target data transmitted to the destination storage module in an address space indicated by the s1_destination storage address, and the data transfer control device 30 may reject S1 from the storage number sequence. It should be noted that, the target data received by the source storage module in s1_and the target data sent by s1_to the destination storage module may be the target data corresponding to S1, and this naming method is only used to distinguish the target data received or sent in different channels.

Similarly, when the data transfer control device 30 receives the target data of S2 based on the data receiving channel, that is, s2_the target data received by the source storage module, the data transfer control device 30 may set the data transfer state of S2 to the data storage state, if S1 in the storage number sequence is not removed at this time, the data transfer control device 30 may buffer the target data of s2_the target data received by the source storage module, wait for S1 to be removed from the storage number sequence, the data transfer control device 30 may transmit the received target data of s2_the target data received by the source storage module to the data transfer control device 50, the data transfer control device 50 may control the data transmission channel to transmit the target data of s2_to the destination storage module, and meanwhile, the data transfer control device 50 may agree with the data transfer control device 40 to control the destination address transmission channel to transmit the s2_the destination storage address synchronously, and the destination storage module may store the target data of s2_the target data transmitted to the destination storage module in the destination storage space indicated by the s2_storage address transmission, and may reject the data from the data storage device 30 in the destination storage number sequence. It should be noted that, the target data received by the source storage module in s2_and the target data sent by s2_to the destination storage module may be the target data corresponding to S2, and this naming method is only used to distinguish the target data received or sent in different channels.

It should be noted that, since the first bit S1 of the storage number sequence has been synchronized to the data transfer control device 30, the data transfer control device 40, and the data transfer control device 50, even if the source storage module receives the target data received by the source storage module first by the data transfer control device 30 due to the line delay problem, the data transfer control device 30 will not send the target data received by the source storage module to the data transfer control device 50 by S2, and the target data received by the source storage module by S2 may be sent only when S2 is ordered to the first bit of the storage number sequence.

In the embodiment of the application, when the data transfer state corresponding to the system number is in the data storage state, the target data of different system numbers can be sequentially transferred from the source storage module to the destination storage module according to the storage number sequence, so that decoupling of the data receiving channel, the data transmitting channel and the destination address transmission channel is realized, the processes of data receiving, transmitting and destination address transmitting can be jointly and independently carried out by the data receiving channel, the data transmitting channel and the destination address transmission channel are ensured, meanwhile, when the current data transfer operation is executed, the system number is removed from the current number sequence, and the utilization rate of the data receiving channel, the data transmitting channel and the destination address transmission channel is improved on the basis of ensuring the processing sequence of the data receiving, transmitting and destination address transmitting.

Referring to fig. 7, a flow chart of data transfer in a storage response state is provided in an embodiment of the present application. As shown in fig. 7, the process may include:

s151, when the data transfer state is a storage response state, acquiring a response number sequence corresponding to the data storage state from a sequence number set, and acquiring number information sequenced at the first bit from the response number sequence;

specifically, the data transfer control device may set the data transfer state corresponding to the system number from the data storage state to the storage response state after sending the target data to the target storage module for storage, and of course, the data transfer control device may also set the data transfer state corresponding to the system number from the data storage state to the storage response state when receiving the response signal sent by the target storage module, and may specifically set the data transfer state corresponding to the system number according to the actual requirement.

When the data transfer control device receives the response signal, the data transfer control device can directly perform matching through the system number described in the response signal so as to determine the system number to which the response signal belongs.

S152, when the number information is the system number corresponding to the subsystem, returning a response signal to the subsystem corresponding to the system number, and eliminating the system number from the response number sequence;

specifically, when the number information is the system number, that is, the system number is indicated to be currently ordered at the first bit of the response number sequence, the data transfer control device may send the response signal to the subsystem corresponding to the system number after the response signal returned by the destination storage module after storing the target data is obtained based on the storage response channel, the data transfer control device may reject the system number from the response number sequence, and the subsystem may return the response signal to the instruction sending module through the data transfer control device to respond to the data transfer instruction, thereby completing a data transfer process.

S153, when the number information is not the system number corresponding to the subsystem, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be ordered to the first position in the number sequence, returning a response signal to the subsystem corresponding to the system number, and eliminating the system number from the response number sequence;

Specifically, when the number information is not the system number, that is, it indicates that the system number is not currently ordered at the first bit of the response number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state and wait for the system number to be ordered to the first bit in the number sequence. Further, when the system number is ordered to the first bit in the number sequence, the data transfer control device may acquire, based on the storage response channel, a response signal returned by the destination storage module after storing the target data, and then send the response signal to a subsystem corresponding to the system number, where the data transfer control device may reject the system number from the response number sequence, and the subsystem may return the response signal to the instruction sending module through the data transfer control device, so as to respond to the data transfer instruction, thereby completing a data transfer process.

Referring to fig. 7a, an exemplary schematic diagram of data transfer in a memory response state is provided in the embodiment of the present application. As shown in fig. 7a, the data transfer control device 60 acquires the s1_response signal corresponding to the system number S1 based on the storage response channel, the data transfer control device 60 may set the data transfer state of S1 to the storage response state, and the data transfer control device 60 is synchronized with S1 in advance, where, as can be seen in fig. 7a, S1 is located at the first position of the response number sequence and the system number S2 is located at the second position of the response number sequence.

The data transfer control device 60 may transmit the received s1_response signal to the subsystem 1 corresponding to S1, the subsystem 1 may transmit the s1_response signal to the data transfer control device 10, the data transfer control device 10 controls the instruction transmission channel to receive the s1_response signal, sends the response signal 1 to the instruction sending module in response to the data transfer instruction 1, and the data transfer control device 10 may package the S1 and s1_response signals as the response signal 1 to the instruction sending module in consideration that the s1_response signal does not carry the system number S1 of the subsystem 1, and when the system number S1 exists in the s1_response signal, the response signal 1 is equivalent to the s1_response signal.

Similarly, when the data transfer control device 60 receives the s2_response signal based on the storage response channel, the data transfer control device 60 may set the data transfer state of S2 to the storage response state, if S1 in the response number sequence is not removed at this time, the data transfer control device 60 may buffer the s2_response signal, wait for S1 to be removed from the response number sequence, and then the data transfer control device 60 may transmit the received s2_response signal to the subsystem 2, and the data transfer control device 60 may remove S2 from the response number sequence. The subsystem 2 may transmit the s2_response signal to the data transfer control apparatus 10, and the data transfer control apparatus 10 controls the instruction transmission channel to receive the s2_response signal, and transmits the response signal 2 to the instruction transmission module in response to the data transfer instruction 2.

It should be noted that, since the first bit S1 of the response number sequence is already synchronized to the data transfer control device 60, even if the destination memory module causes the data transfer control device 60 to receive the s2_response signal first due to the line delay problem, the data transfer control device 60 will not send the s2_response signal to the subsystem 2, and can send the s2_response signal only when S2 is ordered in the first bit of the response number sequence.

In the embodiment of the application, when the data transfer state corresponding to the system number is in the storage response state, response signals corresponding to different system numbers sent to the target storage module can be sequentially sent to the corresponding subsystems according to the response number sequence, so that decoupling of the storage response channel is realized, the storage response channel is ensured to be capable of independently sending the response signals, meanwhile, the system number is removed from the current number sequence when the current data transfer operation is executed, and the utilization rate of the storage response channel is improved on the basis of ensuring the sending sequence of the response signals.

In this embodiment of the present application, the DMA module may include at least two working modes, where the first working mode is direct data storage, that is, the target data of the source storage module is directly stored in the target storage module, which may be referred to in the specific description of the embodiment shown in fig. 6; the second working mode is that after the target data is returned from the source storage module, the target data can be sent to the subsystem for data processing, and then the processed target data is sent to the target storage module for storage. It should be noted that, the implementation processes of the first operation mode and the second operation mode are the same when the data transfer state is the instruction transmission state, the address release state and the storage response state, only the difference exists in the data storage state, and the selection of the operation modes can be determined by the data transfer instruction. For the data transfer process in the data storage state for the second mode of operation, please refer to the embodiments shown in fig. 8-9 below.

Referring to fig. 8, a flow chart of data transfer in a data receiving state is provided in an embodiment of the present application. As shown in fig. 8, the process may include:

s161, when the data transfer state is a data receiving state, receiving target data returned by the source storage module based on the source storage address;

specifically, based on the second working mode, the data storage state may further include a data receiving state and a data transferring state, where the data receiving state may be used to indicate that the current execution stage is in a state of sending the target data to the subsystem corresponding to the system number when the target data returned by the source storage module is obtained.

When the data transfer control device receives target data returned by the source storage module based on the source storage address based on the data receiving channel, the data transfer control device can set a data transfer state corresponding to the system number from an address release state to a data receiving state, and of course, the data transfer control device can set the data transfer state from the address release state to the data receiving state after sending the source storage address, and the data transfer control device can be specifically set according to actual requirements. In this embodiment, after the source storage address is sent, the data transfer state is set to be a data receiving state from an address release state, and when the data transfer state is the data receiving state, the data transfer control device may control the data receiving channel to obtain the target data returned by the source storage module based on the source storage address.

S162, acquiring a first storage number sequence corresponding to the data receiving state from a number sequence set, and acquiring number information sequenced in a first bit from the first storage number sequence;

specifically, based on the second working mode, the storage number sequence may further include a first storage number sequence and a second storage number sequence, and the data transfer control device may acquire the first storage number sequence corresponding to the data receiving state in a number sequence set, and acquire the number information sequenced in the first bit in the first storage number sequence.

S163, when the number information is the system number corresponding to the subsystem, the target data is sent to the subsystem corresponding to the system number, and the system number is removed from the first storage number sequence;

specifically, when the number information is the system number, that is, it indicates that the system number is currently ordered in the first bit of the response number sequence, the data transfer control device may send the target data to the subsystem corresponding to the system number after acquiring the target data returned by the source storage module based on the data receiving channel, and when the target data is sent to the destination storage module, according to the first embodiment, the data transfer control device may reject the system number from the first storage number sequence, and according to the second embodiment, the data transfer control device may reject the system number from the first storage number sequence and store the system number to the second storage number sequence, the subsystem may receive the target data and perform data processing on the target data, where the data processing may include data logic operation, data compression, and the like, and the data transfer instruction may further include a data processing signal, where the data processing signal is used to instruct the data transfer control device to send the target data received by the data transfer control device to the subsystem corresponding to the data processing system corresponding to the first storage number.

S164, when the number information is not the system number corresponding to the subsystem, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be ordered to the first position in the number sequence, sending the target data to the subsystem corresponding to the system number, and eliminating the system number from the first storage number sequence;

specifically, when the number information is not the system number, that is, it indicates that the system number is not currently ordered at the first bit of the first storage number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state and wait for the system number to be ordered to the first bit in the number sequence. Further, when the system number is ordered to the first bit in the first storage number sequence, the data transfer control device may send the target data to the subsystem corresponding to the system number after acquiring the target data returned by the source storage module based on the data receiving channel, and when the target data is sent to the destination storage module, according to the first embodiment, the data transfer control device may reject the system number from the first storage number sequence, and according to the second embodiment, the data transfer control device may reject the system number from the first storage number sequence and store the system number to the second storage number sequence. The subsystem receives the target data, can perform data processing on the target data, the data processing can include data logic operation, data compression and other processing, and the data transfer instruction can also include a data processing signal, where the data processing signal is used to instruct the data transfer control device to send the received target data to the subsystem corresponding to the system number, so as to perform corresponding data processing.

Referring to fig. 8a and 8b, an exemplary schematic diagram of data transfer in a data receiving state is provided in the embodiment of the present application. As shown in fig. 8a, the subsystem 1 may parse the s1_data transfer instruction to obtain an s1_source storage address and an s1_destination storage address, and send the s1_source storage address to the data transfer control device 20, and similarly, the subsystem 2 may send the s2_source storage address to the data transfer control device 20, where when receiving the s1_source storage address, the data transfer control device 20 may set the data transfer state of the S1 to the address release state by the instruction transmission state, the data transfer control device 20 synchronizes the S1 in the instruction number sequence to obtain the first order S1, may control the source address transmission channel to send the s1_source storage address to the source storage module, and the data transfer control device 20 may notify the data transfer control device 10 to reject the S1 from the instruction number sequence, and at this time, the data transfer control device 10 may synchronize the S2 in the first order to the data transfer control device 20, and similarly, the data transfer control device 20 may set the data transfer state of the S2 to the address release state by the instruction transmission state, and control the source address transmission channel to send the S2 to the source storage module. As can be seen from fig. 8a, S1 and S2 are pre-stored in the first storage number sequence, the S1 is ordered in the first bit in the first storage number sequence, and the S2 is ordered in the second bit in the first storage number sequence; or after S1 and S2 are removed from the instruction number sequence, they may be added to the first storage number sequence.

As shown in fig. 8b, the data transfer control device 30 obtains the target data corresponding to the system number S1 based on the data receiving channel, that is, s1_target data received by the source storage module, where the data transfer control device 30 may set the data transfer state of S1 to the data receiving state, the data transfer control device 30 may transmit the received s1_target data received by the source storage module to the subsystem 1, at this time, S1 in the first storage number sequence may be removed, when the data transfer control device 30 receives S2 target data based on the data receiving channel, that is, s2_target data received by the source storage module, the data transfer control device 30 may set the data transfer state of S2 to the data receiving state, if S1 in the first storage number sequence is not removed at this time, the data transfer control device 30 may buffer the S2_target data received by the source storage module, and wait for S1 to be removed from the first storage number sequence, the data transfer control device 30 may transmit the received s2_target data received by the source storage module to the subsystem 2, that is known as S2 in the second storage number sequence, and the second storage number sequence is stored in the second ordered sequence 1, and the second ordered sequence is stored in the second sequence 1; or after S1 and S2 are removed from the first storage number sequence, they may be added to the second storage number sequence.

In the embodiment of the application, when the data transfer state corresponding to the system number is in the data receiving state, the target data of different system numbers can be sequentially sent to the corresponding subsystems by the source storage module according to the first storage number sequence to carry out data processing, so that decoupling of the data receiving channels is realized, the data receiving channels can be ensured to independently carry out the data receiving process, meanwhile, the system number is removed from the current number sequence when the current data transfer operation is carried out, and the utilization rate of the data receiving channels is improved on the basis of ensuring the processing sequence of data receiving and sending.

Referring to fig. 9, a flow chart of data transfer in a data transfer state is provided in an embodiment of the present application. As shown in fig. 9, the process may include:

s171, when the data transfer state is a data transfer state, acquiring a second storage number sequence corresponding to the data transfer state in a number sequence set, and acquiring number information sequenced in the first bit in the second storage number sequence;

specifically, the data receiving state may be used to indicate that the current execution stage is in the process of acquiring the target data sent by the subsystem, and send the target storage address and the target data to a target storage module. The subsystem may send the target data after the data processing to the data transfer control device after the data processing, where the data transfer control device may set the data transfer state corresponding to the system number to the data transfer state from the data receiving state, and of course, the data transfer control device may also set the data transfer state corresponding to the system number to the data transfer state from the data receiving state after the target data is sent to the subsystem. In this embodiment of the present application, after target data is sent to a subsystem, setting a data transfer state corresponding to the system number to a data transfer state from a data receiving state, and when the data transfer state is the data transfer state, the data transfer control device may acquire a second storage number sequence corresponding to the data transfer state in a number sequence set, and acquire number information sequenced in a first bit in the second storage number sequence.

S172, when the number information is a system number corresponding to the subsystem, acquiring the target data sent by the subsystem, sending the target storage address and the target data to a target storage module, and eliminating the system number from the second storage number sequence;

specifically, when the number information is the system number, that is, the system number is indicated to be currently ordered in the first bit of the second storage number sequence, the data transfer control device may acquire the target data after the data processing sent by the subsystem, send the target data after the data processing to the target storage module based on the data sending channel, according to the first embodiment, the data transfer control device may reject the system number from the second storage number sequence, and according to the second embodiment, the data transfer control device may reject the system number from the second storage number sequence and store the system number to the response number sequence.

Optionally, the data transfer control device may control the destination address transmission channel to send, in advance, a destination storage address corresponding to the system number to the destination storage module in the address release state, or may store the destination storage address and the system number in association in the address release state, and in the data transfer state, acquire the destination storage address based on the system number, and transmit the destination storage address and the target data after data processing to the destination storage module together, where the destination storage address and the system number may be specifically set according to actual requirements.

S173, when the number information is not the system number corresponding to the subsystem, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sequenced to the first bit in the number sequence, acquiring the target data sent by the subsystem, sending the target storage address and the target data to a target storage module, and eliminating the system number from the second storage number sequence;

specifically, when the number information is not the system number, that is, it indicates that the system number is not currently ordered in the first bit of the second storage number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state and wait for the system number to be ordered to the first bit in the second storage number sequence. Further, when the system number is ordered to the first bit in the second storage number sequence, the data transfer control device may obtain the target data after the data processing sent by the subsystem, send the target data after the data processing to the destination storage module based on the data sending channel, according to the first embodiment, the data transfer control device may reject the system number from the second storage number sequence, and according to the second embodiment, the data transfer control device may reject the system number from the second storage number sequence and store the system number to the response number sequence.

Referring to fig. 9a, an exemplary schematic diagram of data transfer in a data transfer state is provided in the embodiment of the present application. As shown in fig. 9a, after receiving the target data sent to the destination storage module by s1_transmitted by the subsystem 1, the data transfer control device 50 may control the data sending channel to send the target data sent to the destination storage module by s1_to the destination storage module, meanwhile, the data transfer control device 50 may agree with the data transfer control device 40 to notify the data transfer control device 40 to control the destination address transmission channel to send the s1_destination storage address to the destination storage module synchronously, the destination storage module may store the target data sent to the destination storage module by s1_in an address space indicated by the s1_destination storage address, and the data transfer control device 50 may reject S1 from the second storage number sequence. It should be noted that, the target data received by the source storage module in s1_is represented as target data corresponding to S1 acquired by the source storage module, and the target data sent by s1_to the destination storage module is represented as data processed by the subsystem 1 on the target data received by the source storage module in s1_.

Similarly, if S1 in the second storage number sequence is not removed at this time, the data transfer control device 50 may receive the s2_target data received by the source storage module and transmitted by the subsystem 2, cache the s2_target data received by the source storage module, wait for S1 to be removed from the second storage number sequence, and after that, the data transfer control device 50 may control the data transmission channel to send the s2_target data sent to the destination storage module, and meanwhile, the data transfer control device 50 may agree with the data transfer control device 40 to notify the data transfer control device 40 to control the destination address transmission channel to send the s2_target storage address to the destination storage module synchronously, where the destination storage module may store the s2_target data sent to the destination storage module in an address space indicated by the s2_target storage address, and the data transfer control device 50 may remove S2 from the second storage number sequence. It should be noted that, the target data received by the source storage module in s2_is represented as target data corresponding to S2 acquired by the source storage module, and the target data sent by s2_to the destination storage module is represented as data processed by the subsystem 2 on the target data received by the source storage module in s2_. As can be seen from fig. 9a, S1 and S2 are pre-stored in the response-number sequence, wherein S1 is the first bit in the response-number sequence, and S2 is the second bit in the response-number sequence; or after S1 and S2 are removed from the second stored number sequence, they may be added to the response number sequence.

In the embodiment of the application, when the data transfer state corresponding to the system number is in the data transfer state, the target data of the subsystem, which is subjected to data processing, of different system numbers can be sequentially sent to the target storage module for storage according to the second storage number sequence, so that decoupling of the data transmission channel is realized, the process that the data transmission channel can independently perform data transmission is ensured, meanwhile, the system number is removed from the current number sequence when the current data transfer operation is executed, and the utilization rate of the data transmission channel is improved on the basis of ensuring the processing sequence of the data transmission.

The data transfer control method provided in the embodiment of the present application will be described in detail below with reference to the specific example of fig. 10.

Referring to fig. 10, an exemplary schematic diagram of a data transfer control method is provided in an embodiment of the present application. As shown in fig. 10, the instruction sending module sends the data transfer instruction 1 to the data transfer control device 10, where the data transfer control device 10 controls the instruction transmission channel to send the s1_data transfer instruction to the subsystem 1, and considering that the data transfer instruction 1 carries the system number of the subsystem 1, the data transfer instruction 1 may include the system number S1 of the subsystem 1 and the s1_data transfer instruction, and when the system number S1 does not exist in the data transfer instruction 1, the data transfer instruction 1 is equal to the s1_data transfer instruction.

The data transfer control device 10 may store the system number S1 in the instruction number sequence, and set the data transfer state of S1 to the instruction transmission state, when there is the data transfer instruction 2, similarly to the data transfer instruction 1, the instruction sending module may send the data transfer instruction 2 to the data transfer control device 10, and the data transfer control device 10 may control the instruction transmission channel to send the s2_data transfer instruction to the subsystem 2, store the system number S2 of the subsystem 2 in the instruction number sequence, and set the data transfer state of S2 to the instruction transmission state, where S1 is ordered in the first bit in the instruction number sequence, and S2 is ordered in the second bit. The data transfer device 10 may synchronize S1 to the data transfer device 20, the data transfer device 30, the data transfer device 40, the data transfer device 50, and the data transfer device 60, which means that the current S1 is ordered in the first bit, the subsystem 1 may parse the s1_data transfer instruction to obtain an s1_source storage address and an s1_destination storage address, and send the s1_source storage address to the data transfer control device 20, and similarly, the subsystem 2 may send the s2_source storage address to the data transfer control device 20, the data transfer control device 20 may set the data transfer state of the S1 to the address release state from the instruction transmission state when receiving the s1_source storage address, the data transfer control device 20 synchronizes the instruction number sequence to obtain the S1 ordered in the first bit, and may control the source address transmission channel to send the s1_source storage address to the source storage module, the data transfer control device 10 may be notified to reject the S1 from the instruction number sequence, and the data transfer control device 10 may send the S2 to the same device 20 to the data transfer control device to the synchronous state from the source address transmission channel to send the data transfer control device 20, and the data transfer state from the data transfer control device 20 to the synchronous to the source address transmission state is set the data transfer state of the S2 to the data transfer state from the data transfer control device 20.

The data transfer control device 30 obtains the target data corresponding to the system number S1 based on the data receiving channel, that is, s1_target data received by the source storage module, where the data transfer control device 30 may set the data transfer state of S1 to the data receiving state, the data transfer control device 30 may transmit the received s1_target data received by the source storage module to the subsystem 1, at this time, S1 in the first storage number sequence may be removed, when the data transfer control device 30 receives the target data of S2 based on the data receiving channel, that is, s2_target data received by the source storage module, the data transfer control device 30 may set the data transfer state of S2 to the data receiving state, if at this time, S1 in the first storage number sequence is not removed, the data transfer control device 30 may buffer the received s2_target data received by the source storage module, and wait for S1 to be removed from the first storage number sequence, the data transfer control device 30 may transmit the received s2_target data received by the source storage module to the subsystem 2, and store the second storage number sequence in advance and the second storage number sequence in the second storage number sequence and the second storage number sequence in the second order sequence of S1 and the second number sequence is stored in the second order sequence; or after S1 and S2 are removed from the first storage number sequence, they may be added to the second storage number sequence.

After receiving the target data sent to the destination storage module by s1_transmitted by the subsystem 1, the data transfer control device 50 may control the data sending channel to send the target data sent to the destination storage module by s1_to the destination storage module, meanwhile, the data transfer control device 50 may agree with the data transfer control device 40 to notify the data transfer control device 40 to control the destination address transmission channel to send the s1_destination storage address to the destination storage module synchronously, the destination storage module may store the target data sent to the destination storage module by s1_in an address space indicated by the s1_destination storage address, and the data transfer control device 50 may reject S1 from the second storage number sequence. It should be noted that, the target data received by the source storage module in s1_is represented as target data corresponding to S1 acquired by the source storage module, and the target data sent by s1_to the destination storage module is represented as data processed by the subsystem 1 on the target data received by the source storage module in s1_.

Similarly, if S1 in the second storage number sequence is not removed at this time, the data transfer control device 50 may receive the s2_target data received by the source storage module and transmitted by the subsystem 2, cache the s2_target data received by the source storage module, wait for S1 to be removed from the second storage number sequence, and after that, the data transfer control device 50 may control the data transmission channel to send the s2_target data sent to the destination storage module, and meanwhile, the data transfer control device 50 may agree with the data transfer control device 40 to notify the data transfer control device 40 to control the destination address transmission channel to send the s2_target storage address to the destination storage module synchronously, where the destination storage module may store the s2_target data sent to the destination storage module in an address space indicated by the s2_target storage address, and the data transfer control device 50 may remove S2 from the second storage number sequence. It should be noted that, the target data received by the source storage module in s2_is represented as target data corresponding to S2 acquired by the source storage module, and the target data sent by s2_to the destination storage module is represented as data processed by the subsystem 2 on the target data received by the source storage module in s2_. S1 and S2 are prestored in the response number sequence, wherein the S1 is ordered in the first bit in the response number sequence, and the S2 is ordered in the second bit in the response number sequence; or after S1 and S2 are removed from the second stored number sequence, they may be added to the response number sequence.

The data transfer control device 60 obtains an s1_response signal corresponding to the system number S1 based on the storage response channel, the data transfer control device 60 may set the data transfer state of S1 to the storage response state, the data transfer control device 60 is synchronized with S1 in advance, S1 is located at the first bit of the response number sequence, and the system number S2 is located at the second bit of the response number sequence.

It should be noted that, the two data transfer processing procedures of the DMA module shown in the embodiments of the present application are only illustrative, and the two or more data transfer processing procedures can be implemented with reference to the specific description of the above embodiments.

Based on the system architecture shown in fig. 1, the data transfer control method provided in the embodiment of the present application will be described in detail with reference to fig. 11 to 17, where the embodiment shown in fig. 11 to 17 may be implemented in a data transfer scenario supporting an out-of-order memory module.

Referring to fig. 11, a flow chart of a data transfer control method is provided in an embodiment of the present application. As shown in fig. 11, the method of the embodiment of the present application may include the following steps S201 to S203.

S201, acquiring a data transfer state corresponding to target data processed by a subsystem, acquiring a number sequence corresponding to the data transfer state in a number sequence set, and storing a system number corresponding to the subsystem into the number sequence;

The data transfer control device may be preset with a number sequence set, where the number sequence set may include a plurality of number sequences, and specifically may include, but is not limited to, an instruction number sequence, a storage number sequence, and a response number sequence, where in each data transfer state, there may be one number sequence, where the number sequence may be used to instruct the data transfer control device to sequentially execute a data transfer operation indicated by a system number in the number sequence in the current data transfer state, where the arrangement sequence of the system number in the number sequence may be specifically determined according to a receiving sequence of information such as an address, data, a signal, and so on, for example: when the source storage address transmitted by the subsystem is received, the system number corresponding to the subsystem can be acquired, and the system number is stored in the number sequence. The data transfer control device may store a plurality of system numbers in sequence into a number sequence according to a reception order of the information.

S202, when the system number is the number information ordered in the first bit in the number sequence, executing the data transfer operation indicated by the data transfer state, and eliminating the system number from the number sequence;

S203, when the system number is not the number information ordered in the first bit in the number sequence, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be ordered to the first bit in the number sequence, executing the data transfer operation indicated by the data transfer state, and eliminating the system number from the number sequence;

it should be noted that, step S202 and step S203 in the embodiment of the present invention may refer to the specific description of step S102 and step S103 in the embodiment shown in fig. 2, which is not described herein.

In this embodiment of the present application, by acquiring a data transfer state corresponding to target data processed by a subsystem in a DMA module, an execution stage of a data transfer process of current target data may be acquired, and then a system number of a subsystem is stored into the sequence of numbers through a sequence of numbers corresponding to the data transfer state, so as to ensure that the system number of the subsystem enters the system number of the data transfer state first, and may be stored into the sequence of numbers first, to indicate that the system number may firstly execute a data transfer operation indicated by the data transfer state in a channel in the current data transfer state, while for a system number of a non-first bit in the sequence of numbers, the current data transfer operation needs to be suspended and waiting until the system number is ordered in the first bit in the sequence of numbers, and then the channel may be opened to execute the data transfer operation indicated by the current data transfer state.

The embodiments shown in fig. 12 to 14 will describe the data transfer operation in the address release state, the data storage state, and the storage response state in the data transfer state, respectively.

Referring to fig. 12, a flow chart of data transfer in an address release state is provided in the embodiment of the present application. As shown in fig. 12, the process may include:

s211, when a system number corresponding to the subsystem and storage address information corresponding to the system number transmitted by the subsystem are acquired, setting the data transfer state as an address release state, acquiring an instruction number sequence corresponding to the address release state from a coding sequence set, and storing the system number into the instruction number sequence;

specifically, when the instruction sending module sends a data transfer instruction to the subsystem, the data transfer control device may acquire a system number of the subsystem, and set a data transfer state corresponding to the system number to be an instruction transmission state, and optionally, when the data transfer control device receives the data transfer instruction sent to the subsystem by the instruction sending module, the data transfer control device may control the instruction transmission channel to send the data transfer instruction to the subsystem, and the subsystem may parse the data transfer instruction to acquire storage address information carried in the data transfer instruction, where the storage address information may include a source storage address and a destination storage address of target data requested to be transferred.

When the subsystem obtains the source storage address and the destination storage address, the source storage address can be sent to the data transfer control device, when the data transfer control device obtains the source storage address, the data transfer state can be set to an address release state from the instruction transmission state, and optionally, the subsystem can send the source storage address to the data transfer control device and send the destination storage address to the data transfer control device at the same time, and can send the destination storage address to the data transfer control device again when the data storage state is obtained, and the data transfer control device can be specifically set according to actual requirements.

The data transfer control device may acquire an instruction number sequence corresponding to the address release state from a sequence set, and store the system number into the instruction number sequence.

S212, when the system number is the number information which is ordered in the first bit in the number sequence, the system number and the source storage address are sent to a source storage module, and the system number is removed from the instruction number sequence;

Specifically, when the system number is the number information ordered in the first bit in the number sequence, that is, indicates that the system number is currently ordered in the first bit in the instruction number sequence, the data transfer control device may control the source address transmission channel to send the source storage address corresponding to the system number to the source storage module, and when the source storage address is sent to the source storage module, the data transfer control device may reject the system number from the instruction number sequence.

S213, when the system number is not the number information sequenced in the first bit in the number sequence, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sequenced to the first bit in the number sequence, sending the system number and the source storage address to a source storage module, and eliminating the system number from the instruction number sequence;

specifically, when the system number is not the number information ordered in the first bit in the number sequence, that is, the system number is not currently ordered in the first bit in the instruction number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state and wait for the system number to be ordered in the number sequence to the first bit. Further, when the system number is ordered to the first bit in the instruction number sequence, the data transfer control device may control the source address transmission channel to send a source storage address corresponding to the system number to the source storage module, and when the source storage address is sent to the source storage module, the data transfer control device may reject the system number from the instruction number sequence.

Referring to fig. 12a, an exemplary schematic diagram of data transfer in the address release state is provided in the embodiment of the present application. As shown in fig. 12a, the instruction sending module sends the data transfer instruction 1 to the data transfer control device 10, where the data transfer control device 10 controls the instruction transmission channel to send the s1_data transfer instruction to the subsystem 1, and considering that the data transfer instruction 1 carries the system number of the subsystem 1, the data transfer instruction 1 may include the system number S1 of the subsystem 1 and the s1_data transfer instruction, and when the system number S1 does not exist in the data transfer instruction 1, the data transfer instruction 1 is equal to the s1_data transfer instruction.

The data transfer control device 10 may set the data transfer state of S1 to the instruction transmission state, and when there is the data transfer instruction 2, the instruction transmitting module may transmit the data transfer instruction 2 to the data transfer control device 10, similarly to the data transfer instruction 1, and the data transfer control device 10 may control the instruction transmission channel to transmit the s2_data transfer instruction to the subsystem 2 and set the data transfer state of S2 to the instruction transmission state.

The subsystem 1 may parse the s1_data transfer instruction to obtain an s1_source storage address and an s1_destination storage address, and send the s1_source storage address to the data transfer control device 20, and similarly, the subsystem 2 may send the s2_source storage address to the data transfer control device 20, where when receiving the s1_source storage address, the data transfer control device 20 may set the data transfer state of S1 to an address release state from an instruction transmission state, and store S1 to an instruction number sequence, and similarly, the data transfer control device 20 may set the data transfer state of S2 to an address release state from an instruction transmission state, and store S2 to the instruction number sequence.

Further, if the data transfer control device 20 receives the s1_source address first and then receives the s2_source address, in the instruction number sequence, S1 is ordered in the first bit, S2 is ordered in the second bit, otherwise, S2 is ordered in the first bit, and S1 is ordered in the second bit. As shown in fig. 12a, at this time, the data transfer control device 20 receives the s1_source storage address first, and the data transfer control device 20 may store S1 in the first bit of the instruction number sequence, and may control the source address transmission channel to send the S1 and s1_source storage addresses to the source storage module, and then reject S1 from the instruction number sequence. When the data transfer control device 20 receives the s2_source storage address again, S2 may be stored in the instruction number sequence, and if S1 has been removed, then S2 is converted into the first bit of the instruction number sequence, the data transfer control device 20 may control the source address transmission channel to send the S2 and s2_source storage addresses to the source storage module, and then remove S2 from the instruction number sequence; if S1 has not been removed, the data transfer control device 20 may first buffer the s2_source memory address, send the S2 and s2_source memory addresses until S2 is converted into the first bit of the instruction number sequence, and then remove S2 from the instruction number sequence.

In the embodiment of the application, when the data transfer state corresponding to the system number is in the address release state, the source storage addresses sent to different subsystems can be sequentially sent to the source storage module according to the instruction number sequence, so that decoupling of the source address transmission channel is realized, the source address transmission channel can independently perform the sending process of the source storage addresses, meanwhile, the system number is stored into the instruction number sequence according to the receiving sequence of the source storage addresses, the disorder sending process of the source storage addresses is further realized, and the utilization rate of the source address transmission channel is improved.

Referring to fig. 13, a flow chart of data transfer in a data storage state is provided in an embodiment of the present application. As shown in fig. 13, the process may include:

s221, when the target data and the system number sent by the source storage module are acquired, setting the data transfer state into a data storage state, acquiring a storage number sequence corresponding to the data storage state in a numbering sequence set, and storing the system number into the storage number sequence;

specifically, the source storage module may acquire the target data based on the source storage address, and return the target data and the received system number to the data transfer control device, and when the data transfer control device receives the system number and the target data returned by the source storage module based on the data receiving channel, the data transfer control device may set a data transfer state corresponding to the system number from an address release state to a data storage state, acquire a storage number sequence corresponding to the data storage state in the sequence set, and store the system number in the storage number sequence.

S222, when the system number is the number information which is ordered in the first bit in the number sequence, acquiring a target storage address corresponding to the system number, sending the system number, the target data and the target storage address to the target storage module, and eliminating the system number from the storage number sequence;

specifically, when the system number is the number information ordered in the first bit in the number sequence, that is, the system number is currently ordered in the first bit in the storage number sequence, the data transfer control device may acquire a destination storage address corresponding to the system number in a cache, or request to acquire the destination storage address from a subsystem corresponding to the system number, and the data transfer control device may send the system number, the target data and the destination storage address to the destination storage module, and then reject the system number from the storage number sequence. The system number and the target data can be transmitted through the data transmission channel, and the target storage address can be transmitted through the target address transmission channel.

S223, when the system number is not the number information sequenced in the first bit in the number sequence, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sequenced to the first bit in the number sequence, acquiring a destination storage address corresponding to the system number, sending the system number, the target data and the destination storage address to the destination storage module, and eliminating the system number from the storage number sequence;

specifically, when the system number is not the number information ordered in the first bit in the number sequence, that is, it indicates that the system number is not currently ordered in the first bit in the storage number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state and wait for the system number to be ordered in the storage number sequence to the first bit. Further, when the system number is ordered to the first bit in the number sequence, the data transfer control device may acquire a destination storage address corresponding to the storage number in a cache, or request to acquire the destination storage address from a subsystem corresponding to the system number, and the data transfer control device may send the system number, the destination data, and the destination storage address to the destination storage module, and then reject the system number from the storage number sequence. The system number and the target data can be transmitted through the data transmission channel, and the target storage address can be transmitted through the target address transmission channel.

Referring to fig. 13a, an exemplary schematic diagram of data transfer in a data storage state is provided in the embodiment of the present application. As shown in fig. 13a, the data transfer control device 30 acquires the target data corresponding to S1 and S1, that is, s1_target data received by the source storage module, based on the data receiving channel, where the data transfer control device 30 may set the data transfer state of S1 to the data storage state, and store S1 into the storage number sequence; similarly, the data transfer control device 30 may set the data transfer state of S2 to the data storage state and store S2 into the storage number sequence.

Further, if the data transfer control device 30 receives the target data received by the source storage module from s1_first and then receives the target data received by the source storage module from s2_second, in the storage number sequence, S1 is ordered in the first bit, S2 is ordered in the second bit, otherwise, S2 is ordered in the first bit, and S1 is ordered in the second bit. As shown in fig. 13a, when the data transfer control device 30 receives the target data received by the source storage module and s2_is first received by the source storage module, the data transfer control device 30 may store S2 in the first bit of the storage number sequence, the target data received by the source storage module and s2_is transmitted to the data transfer control device 50, the data transfer control device 50 may synchronize with the data transfer control device 40 when receiving the target data received by the source storage module and s2_is received by the source storage module, the data transfer control device 40 may obtain the s2_destination storage address buffered or transmitted by the subsystem 2, the data transfer control device 40 may control the destination address transmission channel to transmit the s2_destination storage address to the destination storage module, the data transfer control device 50 may control the data transmission channel to transmit the target data transmitted by s2_to the destination storage module to the destination storage module, and the data transfer control device 30 may reject S2 from the storage number sequence. The destination memory module may store the destination data sent by s2_to the destination memory module in an address space indicated by the s2_destination memory address. It should be noted that, the target data received by the source storage module in s2_and the target data sent by s2_to the destination storage module may be the target data corresponding to S2, and this naming method is only used to distinguish the target data received or sent in different channels.

When the data transfer control device 30 receives the s1_target data received by the source storage module, S1 may be stored in the storage number sequence, and if S2 has been removed, then S1 is converted into the first bit of the storage number sequence, and the data transfer control device 40 and the data transfer control device 50 may send the S1, s1_target storage address and the target data sent by s1_to the target storage module to the target storage module, and then remove S1 from the storage number sequence; if S2 has not been removed, the data transfer control device 30 may buffer the target data received by the source storage module from s1_until S1 is converted into the first bit of the storage number sequence, and then send the S1, s1_destination storage address and the target data sent by s1_destination storage module to the destination storage module, and then remove S1 from the storage number sequence. It should be noted that, the target data received by the source storage module in s1_and the target data sent by s1_to the destination storage module may be the target data corresponding to S1, and this naming method is only used to distinguish the target data received or sent in different channels.

In the embodiment of the application, when the data transfer state corresponding to the system number is in the data storage state, the target data of different system numbers can be sequentially transferred to the target storage module from the source storage module according to the storage number sequence, so that decoupling of the data receiving channel, the data sending channel and the target address transmission channel is realized, the processes of independently receiving, sending and sending the data by the data receiving channel, the data sending channel and the target address transmission channel are ensured, meanwhile, the system number is stored in the storage number sequence according to the receiving sequence of the target data, and further, the disordered sending process of the target data and the target storage address is realized, and the utilization rate of the data receiving channel, the data sending channel and the target address transmission channel is improved.

Referring to fig. 14, a flow chart of data transfer in a storage response state is provided in an embodiment of the present application. As shown in fig. 14, the process may include:

s231, when the system code and the response signal sent by the target storage module are acquired, setting the data transfer state to be a storage response state, acquiring a response number sequence corresponding to the data storage state in a coding sequence set, and storing the system code into the response number sequence;

specifically, after the destination storage module stores the target data into the address space indicated by the destination storage address, a response signal and the received system number may be returned to the data transfer control device, and when the data transfer control device obtains the system code and the response signal sent by the destination storage module based on the storage response channel, the data transfer control device may set a data transfer state corresponding to the system number from the data storage state to the storage response state, obtain a response number sequence corresponding to the data storage state in the sequence set, and store the system code into the response number sequence.

S232, when the system number is the number information which is ordered in the first bit in the number sequence, returning a response signal to the subsystem corresponding to the system number, and eliminating the system number from the response number sequence;

specifically, when the system number is the number information ordered in the first bit in the number sequence, that is, the number information indicates that the system number is currently ordered in the first bit in the stored number sequence, the data transfer control device may send the response signal to the subsystem corresponding to the system number, and then reject the system number from the response number sequence.

S233, when the system number is not the number information sequenced in the first bit in the number sequence, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sequenced to the first bit in the number sequence, returning a response signal to the subsystem corresponding to the system number, and eliminating the system number from the response number sequence;

specifically, when the system number is not the number information ordered in the first bit in the number sequence, that is, the system number is not currently ordered in the first bit in the response number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state and wait for the system number to be ordered in the response number sequence to the first bit. Further, when the system number is ordered to the first position in the number sequence, the data transfer control device may send the response signal to the subsystem corresponding to the system number, and then reject the system number from the response number sequence.

Referring to fig. 14a, an exemplary schematic diagram of data transfer in a memory response state is provided in the embodiment of the present application. As shown in fig. 14a, the data transfer control device 60 acquires the system number S1 and the s1_response signal corresponding to S1 based on the storage response channel, and the data transfer control device 60 may set the data transfer state of S1 to the storage response state and store S1 into the response number sequence; similarly, the data transfer control device 60 may set the data transfer state of S2 to the data storage state and store S2 into the response-number sequence.

Further, if the data transfer control device 60 receives the s1_response signal first and then receives the s2_response signal, in the response number sequence, S1 is ordered in the first bit and S2 is ordered in the second bit, otherwise, S2 is ordered in the first bit and S1 is ordered in the second bit. As shown in fig. 14a, when the data transfer control device 60 receives the s2_response signal, the data transfer control device 60 may store S2 in the first bit of the response number sequence, may transmit the s2_response signal to the subsystem 2 corresponding to S2, and the data transfer control device 60 may reject S2 from the response number sequence. The subsystem 2 may transmit the s2_response signal to the data transfer control device 10, the data transfer control device 10 controls the instruction transmission channel to receive the s2_response signal, sends the response signal 2 to the instruction sending module to respond to the data transfer instruction 2, and considering that the s2_response signal does not carry the system number S2 of the subsystem 2, the data transfer control device 10 may package the S2 and s2_response signals as the response signal 2 and send the response signal 2 to the instruction sending module, where the response signal 2 is equal to the s2_response signal when the system number S2 exists in the s2_response signal.

When the data transfer control device 60 receives the s1_response signal again, S1 may be stored in the response number sequence, and if S2 has been removed, then S1 is converted into the first bit of the response number sequence, and the data transfer control device 60 may transmit the s1_response signal to the subsystem 1 corresponding to S1, and then remove S1 from the response number sequence; if S2 has not been removed, the data transfer control device 60 may buffer the s1_response signal first until S1 is converted into the first bit of the response number sequence, and then transmit the s1_response signal to the subsystem 1 corresponding to S1, and then remove S1 from the response number sequence. The subsystem 1 may transmit the s1_response signal to the data transfer control device 10, the data transfer control device 10 controls the instruction transmission channel to receive the s1_response signal, sends the response signal 1 to the instruction sending module to respond to the data transfer instruction 1, and considering that the s1_response signal does not carry the system number S1 of the subsystem 1, the data transfer control device 10 may package the S1 and s1_response signals as the response signal 1 and send the response signal 1 to the instruction sending module, where the response signal 1 is equivalent to the s1_response signal when the system number S1 exists in the s1_response signal.

In the embodiment of the application, when the data transfer state corresponding to the system number is in the storage response state, response signals corresponding to different system numbers sent to the target storage module can be sequentially sent to the corresponding subsystems according to the response number sequence, so that decoupling of the storage response channel is realized, the storage response channel can be ensured to independently send the response signals, meanwhile, the system number is stored into the response number sequence according to the receiving sequence of the response signals, the disorder sending process of the response signals is further realized, and the utilization rate of the storage response channel is improved.

In this embodiment of the present application, the DMA module may include at least two working modes, where the first working mode is direct data storage, that is, direct storage of target data of the source storage module into the destination storage module, which may be referred to in the specific description of the embodiment shown in fig. 13; the second working mode is that after the target data is returned from the source storage module, the target data can be sent to the subsystem for data processing, and then the processed target data is sent to the target storage module for storage. It should be noted that, the implementation processes of the first operation mode and the second operation mode are the same when the data transfer state is the instruction transmission state, the address release state and the storage response state, only the difference exists in the data storage state, and the selection of the operation modes can be determined by the data transfer instruction. For the data transfer process in the data storage state for the second mode of operation, please refer to the embodiments shown in fig. 15-16 below.

Referring to fig. 15, a flow chart of data transfer in a data receiving state is provided in the embodiment of the present application. As shown in fig. 15, the process may include:

s241, when the target data and the system number sent by the source storage module are acquired, setting the data transfer state as a data extraction state, acquiring a first storage number sequence corresponding to the data extraction state in a number sequence set, and storing the system number into the first storage number sequence;

The source storage module can acquire target data based on a source storage address, and return the target data and the received system number to the data transfer control device, when the data transfer control device receives the system number and the target data returned by the source storage module based on the data receiving channel, the data transfer control device can set a data transfer state corresponding to the system number from an address release state to a data storage state, acquire a first storage number sequence corresponding to the data receiving state in a programming sequence set, and store the system number in the first storage number sequence.

S242, when the system number is the number information which is ordered in the first bit in the number sequence, the target data is sent to the subsystem corresponding to the system number, and the system number is removed from the first stored number sequence;

Specifically, when the system number is the number information ordered in the first bit in the number sequence, that is, the system number is currently ordered in the first bit in the first storage number sequence, the data transfer control device may send the target data to the subsystem corresponding to the system number, and then reject the system number from the first storage number sequence. The subsystem receives the target data, can perform data processing on the target data, the data processing can include data logic operation, data compression and other processing, and the data transfer instruction can also include a data processing signal, where the data processing signal is used to instruct the data transfer control device to send the received target data to the subsystem corresponding to the system number, so as to perform corresponding data processing.

S243, when the system number is not the number information sequenced in the first bit in the number sequence, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sequenced to the first bit in the number sequence, sending the target data to the subsystem corresponding to the system number, and eliminating the system number from the first stored number sequence;

Specifically, when the system number is not the number information ordered in the first bit in the number sequence, that is, the system number is not currently ordered in the first bit in the first storage number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state and wait for the system number to be ordered to the first bit in the first storage number sequence. Further, when the system number is ordered to the first position in the number sequence, the data transfer control device may send the target data to a subsystem corresponding to the system number, and then reject the system number from the first stored number sequence. The subsystem receives the target data, can perform data processing on the target data, the data processing can include data logic operation, data compression and other processing, and the data transfer instruction can also include a data processing signal, where the data processing signal is used to instruct the data transfer control device to send the received target data to the subsystem corresponding to the system number, so as to perform corresponding data processing.

Referring to fig. 15a, an exemplary schematic diagram of data transfer in a data receiving state is provided in the embodiment of the present application. As shown in fig. 15a, the data transfer control device 30 acquires the target data corresponding to S1 and S1, that is, s1_target data received by the source storage module, based on the data receiving channel, and the data transfer control device 30 may set the data transfer state of S1 to the data receiving state and store S1 into the first storage number sequence; similarly, the data transfer control device 30 may set the data transfer state of S2 to the data reception state and store S2 into the first storage number sequence.

Further, if the data transfer control device 30 receives the target data received by the source storage module in s1_and then receives the target data received by the source storage module in s2_then in the first storage number sequence, S1 is ordered in the first bit, S2 is ordered in the second bit, otherwise, S2 is ordered in the first bit, and S1 is ordered in the second bit. As shown in fig. 15a, at this time, the data transfer control device 30 first receives the target data received by the source storage module S2, the data transfer control device 30 may store S2 in the first bit of the first storage number sequence, may transmit the target data received by the source storage module S2 to the subsystem 2 corresponding to S2, and the data transfer control device 30 may reject S2 from the first storage number sequence.

When the data transfer control device 30 receives the s1_target data received by the source storage module, S1 may be stored in the first storage number sequence, and if S2 has been removed, S1 is converted into the first bit of the first storage number sequence, and the data transfer control device 30 may send the s1_target data received by the source storage module to the subsystem 1 corresponding to S1, and then remove S1 from the first storage number sequence; if S2 has not been removed, the data transfer control device 30 may buffer the target data received by the source storage module from s1_until S1 is converted into the first bit of the first storage number sequence, and then send the target data received by the source storage module from S1 to the subsystem 1 corresponding to S1, and then remove S1 from the first storage number sequence.

In the embodiment of the application, when the data transfer state corresponding to the system number is in the data receiving state, the target data of different system numbers can be sequentially sent to the corresponding subsystems by the source storage module according to the first storage number sequence to perform data processing, so that decoupling of the data receiving channel is realized, the process that the data receiving channel can independently perform data receiving is ensured, meanwhile, the system number is stored into the first storage number sequence according to the receiving sequence of the target data, further, the disorder receiving process of the target data is realized, and the utilization rate of the data receiving channel is improved.

Referring to fig. 16, a flow chart of data transfer in a data transfer state is provided in the embodiment of the present application. As shown in fig. 16, the flow may include:

s251, when the target data sent by the subsystem is acquired, setting the data transfer state into a data transfer state, acquiring a second storage number sequence corresponding to the data transfer state in a sequence number set, acquiring a system number corresponding to the subsystem, and storing the system number into the second storage number sequence;

specifically, the data receiving state may be used to indicate that the current execution stage is in the process of acquiring the target data sent by the subsystem, and send the target storage address and the target data to a target storage module. After the subsystem processes the target data, the target data after the data processing can be sent to a data transfer control device, the data transfer control device can set a data transfer state corresponding to the system number from a data receiving state to a data transfer state, and when the data transfer state is the data transfer state, the data transfer control device can acquire a second storage number sequence corresponding to the data transfer state in a coding sequence set, acquire the system number corresponding to the subsystem, and store the system number in the second storage number sequence.

S252, when the system number is the number information which is ordered in the first bit in the number sequence, a destination storage address corresponding to the system number is obtained, the system number, the target data and the destination storage address are sent to the destination storage module, and the system number is removed from the second storage number sequence;

specifically, when the system number is the number information ordered in the first bit in the number sequence, that is, the system number is currently ordered in the first bit in the second storage number sequence, the data transfer control device may acquire the destination storage address corresponding to the system number in a cache, or request to acquire the destination storage address from the subsystem corresponding to the system number, and the data transfer control device may send the system number, the target data after data processing, and the destination storage address to the destination storage module, and then reject the system number from the second storage number sequence. The system number and the target data can be transmitted through the data transmission channel, and the target storage address can be transmitted through the target address transmission channel.

S253, when the system number is not the number information sequenced in the first bit in the number sequence, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sequenced to the first bit in the number sequence, acquiring a destination storage address corresponding to the system number, sending the system number, the target data and the destination storage address to the destination storage module, and eliminating the system number from the second storage number sequence;

specifically, when the system number is not the number information ordered in the first bit in the number sequence, that is, the system number is not currently ordered in the first bit in the second storage number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state and wait for the system number to be ordered to the first bit in the second storage number sequence. Further, when the system number is ordered to the first bit in the second storage number sequence, the data transfer control device may acquire a destination storage address corresponding to the system number in a cache, or request to acquire the destination storage address from a subsystem corresponding to the system number, and the data transfer control device may send the system number, the target data after data processing, and the destination storage address to the destination storage module, and then reject the system number from the second storage number sequence. The system number and the target data can be transmitted through the data transmission channel, and the target storage address can be transmitted through the target address transmission channel.

Referring to fig. 16a, an exemplary schematic diagram of data transfer in a data transfer state is provided in the embodiment of the present application. As shown in fig. 16a, after receiving the target data sent by s1_to the destination storage module and transmitted by the subsystem 1, the data transfer control device 50 may set the data transfer state of S1 to a data transfer state, and store S1 into the second storage number sequence; similarly, the data transfer control device 50 may set the data transfer state of S2 to the data transfer state, and store S2 into the second storage number sequence.

Further, if the data transfer control device 50 receives the target data sent by s1_to the destination storage module first, and then receives the target data sent by s2_to the destination storage module, in the second storage number sequence, S1 is ordered in the first bit, S2 is ordered in the second bit, otherwise, S2 is ordered in the first bit, and S1 is ordered in the second bit. As shown in fig. 16a, at this time, the data transfer control device 50 receives the target data sent by s2_to the destination storage module first, and may synchronize with the data transfer control device 40, where the data transfer control device 40 may obtain the s2_destination storage address that is cached or transmitted by the subsystem 2, the data transfer control device 40 may control the destination address transmission channel to send the s2_destination storage address to the destination storage module, the data transfer control device 50 may control the data sending channel to transmit the target data sent by s2_to the destination storage module to the destination storage module, and the data transfer control device 50 may reject S2 from the second storage number sequence. The destination memory module may store the destination data sent by s2_to the destination memory module in an address space indicated by the s2_destination memory address. It should be noted that, the target data received by the source storage module in s2_is represented as target data corresponding to S2 acquired by the source storage module, and the target data sent by s2_to the destination storage module is represented as data processed by the subsystem 2 on the target data received by the source storage module in s2_.

When the data transfer control device 50 receives the target data sent by s1_to the destination storage module, S1 may be stored in the second storage number sequence, and if S2 has been removed, then S1 is converted into the first bit of the second storage number sequence, and the data transfer control device 40 and the data transfer control device 50 may send the S1, s1_destination storage address and the target data sent by s1_to the destination storage module to the destination storage module, and then remove S1 from the second storage number sequence; if S2 has not been removed, the data transfer control device 50 may buffer the target data sent from the s1_to the destination storage module, and send the S1, s1_destination storage address and the target data sent from the s1_to the destination storage module until S1 is converted into the first bit of the second storage number sequence, and then remove S1 from the second storage number sequence. It should be noted that, the target data received by the source storage module in s1_is represented as target data corresponding to S1 acquired by the source storage module, and the target data sent by s1_to the destination storage module is represented as data processed by the subsystem 1 on the target data received by the source storage module in s1_.

In the embodiment of the application, when the data transfer state corresponding to the system number is in the data transfer state, the target data which is subjected to data processing by the subsystems and is different in system number can be sequentially sent to the target storage module for storage according to the second storage number sequence, so that decoupling of the data sending channel is realized, the process that the data sending channel can independently send data is ensured, meanwhile, the system number is stored in the second storage number sequence according to the receiving sequence of the target data after data processing, further, the disordered sending process of the target data and the target storage address is realized, and the utilization rate of the data sending channel is improved.

The data transfer control method provided in the embodiment of the present application will be described in detail below with reference to the specific example of fig. 17.

Referring to fig. 17, an exemplary schematic diagram of a data transfer control method is provided in an embodiment of the present application. As shown in fig. 17, the instruction sending module sends the data transfer instruction 1 to the data transfer control device 10, where the data transfer control device 10 controls the instruction transmission channel to send the s1_data transfer instruction to the subsystem 1, and considering that the data transfer instruction 1 carries the system number of the subsystem 1, the data transfer instruction 1 may include the system number S1 of the subsystem 1 and the s1_data transfer instruction, and when the system number S1 does not exist in the data transfer instruction 1, the data transfer instruction 1 is equal to the s1_data transfer instruction.

The data transfer control device 20 receives the s1_source storage address first, and the data transfer control device 20 may store S1 in the first bit of the instruction number sequence, and may control the source address transmission channel to send the S1 and s1_source storage addresses to the source storage module, and then reject S1 from the instruction number sequence. When the data transfer control device 20 receives the s2_source storage address again, S2 may be stored in the instruction number sequence, and if S1 has been removed, then S2 is converted into the first bit of the instruction number sequence, the data transfer control device 20 may control the source address transmission channel to send the S2 and s2_source storage addresses to the source storage module, and then remove S2 from the instruction number sequence; if S1 has not been removed, the data transfer control device 20 may first buffer the s2_source memory address, send the S2 and s2_source memory addresses until S2 is converted into the first bit of the instruction number sequence, and then remove S2 from the instruction number sequence.

The data transfer control device 30 obtains the target data corresponding to S1 and S1, that is, s1_target data received by the source storage module, based on the data receiving channel, where the data transfer control device 30 may set the data transfer state of S1 to the data receiving state, and store S1 into the first storage number sequence; similarly, the data transfer control device 30 may set the data transfer state of S2 to the data reception state and store S2 into the first storage number sequence.

The data transfer control device 30 receives the S2_target data received by the source storage module, the data transfer control device 30 may store S2 in the first bit of the first storage number sequence, may transmit the S2_target data received by the source storage module to the subsystem 2 corresponding to S2, and the data transfer control device 30 may reject S2 from the first storage number sequence.

After receiving the target data sent to the target storage module by s1_transmitted by the subsystem 1, the data transfer control device 50 may set the data transfer state of S1 to a data transfer state, and store S1 into the second storage number sequence; similarly, the data transfer control device 50 may set the data transfer state of S2 to the data transfer state, and store S2 into the second storage number sequence.

The data transfer control device 50 receives the target data sent by the s2_to the destination storage module first, and may synchronize with the data transfer control device 40, where the data transfer control device 40 may obtain the s2_destination storage address that is cached or transmitted by the subsystem 2, the data transfer control device 40 may control the destination address transmission channel to send the s2_destination storage address to the destination storage module, the data transfer control device 50 may control the data transmission channel to transmit the target data sent by the s2_to the destination storage module to the destination storage module, and the data transfer control device 50 may reject S2 from the second storage number sequence. The destination memory module may store the destination data sent by s2_to the destination memory module in an address space indicated by the s2_destination memory address. It should be noted that, the target data received by the source storage module in s2_is represented as target data corresponding to S2 acquired by the source storage module, and the target data sent by s2_to the destination storage module is represented as data processed by the subsystem 2 on the target data received by the source storage module in s2_.

The data transfer control device 60 obtains the system number S1 and the s1_response signal corresponding to the S1 based on the storage response channel, and the data transfer control device 60 may set the data transfer state of S1 to the storage response state, and store S1 into the response number sequence; similarly, the data transfer control device 60 may set the data transfer state of S2 to the data storage state and store S2 into the response-number sequence.

The data transfer control device 60 receives the s2_response signal first, the data transfer control device 60 may store S2 in the first bit of the response number sequence, the s2_response signal may be transmitted to the subsystem 2 corresponding to S2, and the data transfer control device 60 may reject S2 from the response number sequence. The subsystem 2 may transmit the s2_response signal to the data transfer control device 10, the data transfer control device 10 controls the instruction transmission channel to receive the s2_response signal, sends the response signal 2 to the instruction sending module to respond to the data transfer instruction 2, and considering that the s2_response signal does not carry the system number S2 of the subsystem 2, the data transfer control device 10 may package the S2 and s2_response signals as the response signal 2 and send the response signal 2 to the instruction sending module, where the response signal 2 is equal to the s2_response signal when the system number S2 exists in the s2_response signal.

It should be noted that, the two data transfer processing procedures of the DMA module and the information receiving sequences of S1 and S2 shown in the embodiments of the present application are only illustrative, and for more than two data transfer processing procedures, the implementation may be similarly performed with reference to the specific description of the above embodiments.

In this embodiment of the present application, by acquiring a data transfer state corresponding to target data processed by a subsystem in a DMA module, an execution stage of a data transfer process of current target data may be acquired, and then a system number of a subsystem is stored into the sequence of numbers through a sequence of numbers corresponding to the data transfer state, so as to ensure that the system number of the subsystem enters the system number of the data transfer state first, and may be stored into the sequence of numbers first, to indicate that the system number may firstly execute a data transfer operation indicated by the data transfer state in a channel in the current data transfer state, and for a system number of a non-first bit in the sequence of numbers, the current data transfer operation needs to be suspended and waiting until the system number is ordered in the first bit in the sequence of numbers, and then the channel may be opened to execute the data transfer operation indicated by the current data transfer state.

Referring to fig. 18-20, a timing diagram of execution of each channel in a DMA according to an embodiment of the present application is provided, wherein fig. 18 shows a timing diagram of execution of each channel in a DMA according to the prior art; FIG. 19 shows a timing diagram of the execution of channels in a sequential DMA; fig. 20 shows a timing chart of execution of each channel in the out-of-order DMA, and it should be noted that the timing charts of the two data transfer processing procedures shown in fig. 18 to 20 and the information receiving order of S1 and S2 are only illustrative, and the implementation can be similarly performed with reference to the specific description of the above embodiments for more than two data transfer processing procedures.

As shown in fig. 18, the multiple channels in the prior art have timing dependency, so that the multiple channels are released for executing the data transfer process of S2 only after the data transfer process of S1 is executed, and since each channel is called according to the execution sequence of the data transfer, each channel is in an idle state most of the time, for example, an instruction transmission channel, and the instruction transmission channel is in an idle state after sending the s1_data transfer instruction to the subsystem, and the transmission of the s2_data transfer instruction can not be executed until the storage response channel receives the response signal. Therefore, the utilization rate of the channel and the efficiency of data transfer are affected by the prior art.

As shown in fig. 19, the plurality of channels shown in fig. 19 may sequentially complete the data transfer process indicated by each data transfer instruction according to the transmission order of the data transfer instructions, for example: if the s1_data transfer instruction is received first, the S1-related information transmission in each channel needs to be prioritized by S1, and in the embodiment of the present application, decoupling is performed on a plurality of channels on the basis of ordered execution, so that each channel can independently execute the corresponding data transfer operation, and on the basis of ensuring the execution order of each data transfer instruction, the channel utilization rate is improved, and further the data transfer efficiency is improved.

As shown in fig. 20, each of the plurality of channels shown in fig. 20 may perform a corresponding data transfer operation according to an information receiving order, for example: in the instruction transmission channel, although the S1_data transfer instruction is to be transmitted in preference to the S2_data transfer instruction, in the data receiving channel, the S2_target data received by the source storage module can be returned in preference to the S1_target data received by the source storage module and can be preferentially executed, so that the out-of-order execution process of data transfer is realized, the waiting time of each channel when the data transfer operation is executed is further reduced, the channel utilization rate is improved, and the data transfer efficiency is further improved.

Based on the system architecture of fig. 1, the data transfer control device provided in the embodiment of the present application will be described in detail with reference to fig. 21 to 23. It should be noted that, the data transfer control device in fig. 21 to 23 is used to execute the method of the embodiment shown in fig. 2 to 10 of the present application, and for convenience of explanation, only the portion relevant to the embodiment of the present application is shown, and specific technical details are not disclosed, please refer to the embodiment shown in fig. 2 to 10 of the present application.

Referring to fig. 21, a schematic structural diagram of a data transfer control device is provided in an embodiment of the present application. As shown in fig. 21, the data transfer control apparatus 1 of the embodiment of the present application may include: a state acquisition unit 11, a number information acquisition unit 12, and a data operation unit 13.

A state acquisition unit 11, configured to acquire a data transfer state corresponding to target data processed by a subsystem, where the data transfer state is used to represent an execution stage in a data transfer process of the target data;

a number information obtaining unit 12, configured to obtain a number sequence corresponding to the data transfer state from a number sequence set, and obtain number information ordered in the first bit from the number sequence;

A data operation unit 13, configured to execute a data transfer operation indicated by the data transfer state when the number information is a system number corresponding to the subsystem, and reject the system number from the number sequence;

the data operation unit 13 is further configured to suspend the data transfer operation indicated by the data transfer state when the number information is not the system number corresponding to the subsystem, wait for the system number to be ordered to the first bit in the number sequence, execute the data transfer operation indicated by the data transfer state, and reject the system number from the number sequence.

Optionally, the number information obtaining unit 12 is specifically configured to obtain, when the data transfer state is an address release state, an instruction number sequence corresponding to the address release state in a sequence set, and obtain, in the instruction number sequence, number information ordered in a first bit;

the data operation unit 13 is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, the data operation unit is specifically configured to obtain storage address information corresponding to the system number, where the storage address information is a source storage address and a destination storage address for target data, which are obtained by the subsystem after analyzing a data transfer instruction;

And sending the source storage address to a source storage module, and eliminating the system number from the instruction number sequence.

Optionally, the number information obtaining unit 12 is specifically configured to obtain, when the data transfer state is a data storage state, a storage number sequence corresponding to the data storage state in a number sequence set, and obtain, in the storage number sequence, number information ordered in a first bit;

the data operation unit 13 is configured to perform a data transfer operation indicated by the data transfer state, and specifically, is configured to transfer, when the system number is removed from the number sequence, target data from a source storage address of a source storage module to a destination storage address of the destination storage module based on the system number, and remove the system number from the storage number sequence.

Optionally, the number information acquiring unit 12 is specifically configured to receive, when the data transfer state is a data receiving state, target data returned by the source storage module based on the source storage address;

acquiring a first storage number sequence corresponding to the data receiving state from a number sequence set, and acquiring number information sequenced in a first bit from the first storage number sequence;

The data operation unit 13 is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, specifically, send the target data to a subsystem corresponding to the system number, and remove the system number from the first stored number sequence.

Optionally, the number information obtaining unit 12 is specifically configured to obtain, when the data transfer state is a data transfer state, a second storage number sequence corresponding to the data transfer state in a number sequence set, and obtain, in the second storage number sequence, number information ordered in a first bit;

the data operation unit 13 is configured to perform a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, specifically, is configured to obtain the target data sent by the subsystem, send the destination storage address and the target data to a destination storage module, and remove the system number from the second storage number sequence.

Optionally, the number information obtaining unit 12 is specifically configured to obtain, when the data transfer state is a storage response state, a response number sequence corresponding to the data storage state in a sequence set, and obtain, in the response number sequence, number information ordered in a first bit;

The data operation unit 13 is configured to execute a data transfer operation indicated by the data transfer state, and specifically, is configured to return a response signal to the subsystem corresponding to the system number when the system number is removed from the number sequence, and remove the system number from the response number sequence, where the response signal is a response signal returned by the destination storage module after storing the target data.

Referring to fig. 22, a schematic structural diagram of a data transfer control device is provided in an embodiment of the present application. As shown in fig. 22, the data transfer control apparatus 1 of the embodiment of the present application may include: a state acquisition unit 11, a number information acquisition unit 12, a data operation unit 13, a system number acquisition unit 14, and a first number storage unit 15.

A system number obtaining unit 14, configured to obtain a system number corresponding to a subsystem when the instruction sending module sends a data transfer instruction to the subsystem;

a first number storage unit 15, configured to store the system numbers to the same ordering positions in each number sequence of a number sequence set, where the number sequence set includes an instruction number sequence, a storage number sequence, and a response number sequence;

Referring to fig. 23, a schematic structural diagram of a data transfer control device is provided in an embodiment of the present application. As shown in fig. 23, the data transfer control apparatus 1 of the embodiment of the present application may include: a state acquisition unit 11, a number information acquisition unit 12, a data operation unit 13, and a second number storage unit 16.

a second number storage unit 16 for storing the system number into a next sequence of the number sequence;

the next sequence is a sequence sequenced after the number sequence in a number sequence set according to the transformation sequence of the data transfer state, and the number sequence set comprises an instruction number sequence, a storage number sequence and a response number sequence.

Referring to fig. 24, a schematic structural diagram of a computer device is provided in an embodiment of the present application. As shown in fig. 24, the computer device 1000 may include: at least one processor 1001, such as a CPU, at least one network interface 1004, an input output interface 1003, a memory 1005, at least one communication bus 1002. Wherein the communication bus 1002 is used to enable connected communication between these components. The network interface 1004 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface), among others. The memory 1005 may be a high-speed RAM memory or a non-volatile memory (non-volatile memory), such as at least one disk memory. The memory 1005 may also optionally be at least one storage device located remotely from the processor 1001. As shown in fig. 24, an operating system, a network communication module, an input-output interface module, and a transfer control application program may be included in the memory 1005, which is one type of computer storage medium.

In the computer device 1000 shown in fig. 24, the input/output interface 1003 is mainly used for providing an input interface for a user and an access device, and acquiring data input by the user and the access device.

In one embodiment, the processor 1001 may be configured to invoke a transfer control application stored in the memory 1005 and specifically perform the following operations:

Optionally, before executing the data transfer state corresponding to the target data processed by the acquisition subsystem, the processor 1001 further executes the following operations:

when an instruction sending module sends a data transfer instruction to a subsystem, acquiring a system number corresponding to the subsystem;

and respectively storing the system numbers to the same sequencing positions in each number sequence of a number sequence set, wherein the number sequence set comprises an instruction number sequence, a storage number sequence and a response number sequence.

Optionally, after performing the data transfer operation indicated by the data transfer state, the processor 1001 performs the following operations after removing the system number from the number sequence:

storing the system number in a next sequence of the numbered sequence;

Optionally, when the processor 1001 acquires a number sequence corresponding to the data transfer state from the number sequence set, and acquires the number information ordered in the first bit from the number sequence, the following operations are specifically executed:

When the data transfer state is an address release state, acquiring an instruction number sequence corresponding to the address release state from a coding sequence set, and acquiring number information sequenced in the first bit from the instruction number sequence;

the processor 1001, when executing the data transfer operation indicated by the data transfer state and eliminating the system number from the number sequence, specifically executes the following operations:

acquiring storage address information corresponding to the system number, wherein the storage address information is a source storage address and a destination storage address for target data, which are obtained by analyzing a data transfer instruction by the subsystem;

when the data transfer state is a data storage state, a storage number sequence corresponding to the data storage state is obtained in a number sequence set, and number information sequenced in the first bit is obtained in the storage number sequence;

and transferring the target data from the source storage address of the source storage module to the destination storage address of the destination storage module based on the system number, and eliminating the system number from the storage number sequence.

when the data transfer state is a data receiving state, receiving target data returned by the source storage module based on the source storage address;

And sending the target data to a subsystem corresponding to the system number, and eliminating the system number from the first storage number sequence.

when the data transfer state is a data transfer state, acquiring a second storage number sequence corresponding to the data transfer state in a number sequence set, and acquiring number information sequenced in a first bit in the second storage number sequence;

and acquiring the target data sent by the subsystem, sending the target storage address and the target data to a target storage module, and eliminating the system number from the second storage number sequence.

When the data transfer state is a storage response state, acquiring a response number sequence corresponding to the data storage state in a coding sequence set, and acquiring number information sequenced in the first bit in the response number sequence;

optionally, when executing the data transfer operation indicated by the data transfer state, the processor 1001 specifically performs the following operations when eliminating the system number from the number sequence:

and returning a response signal to the subsystem corresponding to the system number, and eliminating the system number from the response number sequence, wherein the response signal is a response signal returned by the target storage module after the target data is stored.

Based on the system architecture of fig. 1, a detailed description will be given below of a data transfer control device provided in an embodiment of the present application with reference to fig. 25. It should be noted that, the data transfer control device in fig. 25 is configured to perform the method of the embodiment shown in fig. 11 to 17, and for convenience of explanation, only a portion relevant to the embodiment of the present application is shown, and specific technical details are not disclosed, please refer to the embodiment shown in fig. 11 to 17 of the present application.

Referring to fig. 25, a schematic structural diagram of a data transfer control device is provided in an embodiment of the present application. As shown in fig. 25, the data transfer control apparatus 2 of the embodiment of the present application may include: a number storage unit 21 and a data operation unit 22.

A number storage unit 21, configured to obtain a data transfer state corresponding to target data processed by a subsystem, obtain a number sequence corresponding to the data transfer state in a number sequence set, and store a system number corresponding to the subsystem into the number sequence, where the data transfer state is used to represent an execution stage in a data transfer process of the target data;

a data operation unit 22, configured to execute a data transfer operation indicated by the data transfer state when the system number is the number information ordered in the first bit in the number sequence, and reject the system number from the number sequence;

The data operation unit 22 is further configured to suspend the data transfer operation indicated by the data transfer state when the system number is not the number information ordered in the first bit in the number sequence, wait for the system number to be ordered in the first bit in the number sequence, execute the data transfer operation indicated by the data transfer state, and reject the system number from the number sequence.

Optionally, the number storage unit 21 is specifically configured to set the data transfer state to an address release state when acquiring a system number corresponding to the subsystem and storage address information corresponding to the system number sent by the subsystem, acquire an instruction number sequence corresponding to the address release state in a sequence set, and store the system number in the instruction number sequence, where the storage address information is a source storage address and a destination storage address for target data obtained by analyzing a data transfer instruction by the subsystem;

the data operation unit 22 is configured to execute a data transfer operation indicated by the data transfer state, and specifically, send the system number and the source storage address to a source storage module when the system number is removed from the sequence of number, and remove the system number from the sequence of instruction numbers.

Optionally, the number storage unit 21 is specifically configured to, when acquiring the target data and the system number sent by the source storage module, set the data transfer state to a data storage state, acquire a storage number sequence corresponding to the data storage state in a sequence set, and store the system number into the storage number sequence;

the data operation unit 22 is configured to perform a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, specifically, is configured to obtain a destination storage address corresponding to the system number, send the system number, the target data, and the destination storage address to the destination storage module, and remove the system number from the storage number sequence.

Optionally, the number storage unit 21 is specifically configured to, when acquiring the target data and the system number sent by the source storage module, set the data transfer state to a data extraction state, acquire a first storage number sequence corresponding to the data extraction state in a number sequence set, and store the system number into the first storage number sequence;

The data operation unit 22 is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, specifically, send the target data to a subsystem corresponding to the system number, and remove the system number from the first stored number sequence.

Optionally, the number storage unit 21 is specifically configured to set the data transfer state to a data transfer state when the target data sent by the subsystem is acquired, acquire a second storage number sequence corresponding to the data transfer state in a number sequence set, acquire a system number corresponding to the subsystem, and store the system number in the second storage number sequence;

the data operation unit 22 is configured to perform a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, specifically, is configured to obtain a destination storage address corresponding to the system number, send the system number, the target data, and the destination storage address to the destination storage module, and remove the system number from the second storage number sequence.

Optionally, the number storage unit 21 is specifically configured to, when acquiring the system code and the response signal sent by the destination storage module, set the data transfer state to a storage response state, acquire a response number sequence corresponding to the data storage state in a sequence set, store the system code in the response number sequence, where the response signal is a response signal corresponding to the system number returned by the destination storage module after storing the target data;

the data operation unit 22 is configured to execute a data transfer operation indicated by the data transfer state, and specifically, is configured to return a response signal to the subsystem corresponding to the system number when the system number is removed from the sequence of numbers, and remove the system number from the sequence of response numbers.

Referring to fig. 24, a schematic structural diagram of a computer device is provided in an embodiment of the present application. As shown in fig. 24, the computer device 2000 may include: at least one processor 2001, such as a CPU, at least one network interface 2004, an input output interface 2003, a memory 2005, at least one communication bus 2002. Wherein a communication bus 2002 is used to enable connected communications between these components. The network interface 2004 may optionally include standard wired interfaces, wireless interfaces (e.g., WI-FI interfaces), among others. The memory 2005 may be a high-speed RAM memory or a non-volatile memory (non-volatile memory), such as at least one disk memory. The memory 2005 may also optionally be at least one storage device located remotely from the aforementioned processor 2001. As shown in fig. 24, an operating system, a network communication module, an input-output interface module, and a transfer control application program may be included in the memory 2005 as one type of computer storage medium.

In the computer device 2000 shown in fig. 24, the input/output interface 2003 is mainly used as an interface for providing input to a user and an access device, and obtains data input by the user and the access device.

In one embodiment, the processor 2001 may be used to invoke a transfer control application stored in the memory 2005 and specifically:

acquiring a data transfer state corresponding to target data processed by a subsystem, acquiring a number sequence corresponding to the data transfer state from a number sequence set, and storing a system number corresponding to the subsystem into the number sequence, wherein the data transfer state is used for representing an execution stage in a data transfer process of the target data;

Optionally, when executing the data transfer state corresponding to the target data processed by the acquisition subsystem, the processor 2001 acquires a number sequence corresponding to the data transfer state from the number sequence set, and stores the system number corresponding to the subsystem in the number sequence, specifically executes the following operations:

When a system number corresponding to the subsystem and storage address information corresponding to the system number transmitted by the subsystem are acquired, setting the data transfer state as an address release state, acquiring an instruction number sequence corresponding to the address release state from a sequence set, and storing the system number into the instruction number sequence, wherein the storage address information is a source storage address and a destination storage address for target data, which are obtained by analyzing a data transfer instruction by the subsystem;

the processor 2001, when executing the data transfer operation indicated by the data transfer state, eliminates the system number from the number sequence, specifically executes the following operations:

and sending the system number and the source storage address to a source storage module, and eliminating the system number from the instruction number sequence.

When the target data and the system number sent by the source storage module are acquired, setting the data transfer state into a data storage state, acquiring a storage number sequence corresponding to the data storage state in a numbering sequence set, and storing the system number into the storage number sequence;

and acquiring a target storage address corresponding to the system number, transmitting the system number, the target data and the target storage address to the target storage module, and eliminating the system number from the storage number sequence.

when the target data and the system number sent by the source storage module are acquired, setting the data transfer state as a data extraction state, acquiring a first storage number sequence corresponding to the data extraction state in a coding sequence set, and storing the system number into the first storage number sequence;

when the target data sent by the subsystem is acquired, setting the data transfer state into a data transfer state, acquiring a second storage number sequence corresponding to the data transfer state in a sequence set, acquiring a system number corresponding to the subsystem, and storing the system number into the second storage number sequence;

And acquiring a target storage address corresponding to the system number, transmitting the system number, the target data and the target storage address to the target storage module, and eliminating the system number from the second storage number sequence.

when the system code and the response signal sent by the target storage module are acquired, setting the data transfer state to be a storage response state, acquiring a response number sequence corresponding to the data storage state in a coding sequence set, and storing the system code into the response number sequence, wherein the response signal is a response signal corresponding to the system number returned by the target storage module after storing target data;

And returning a response signal to the subsystem corresponding to the system number, and eliminating the system number from the response number sequence.

The embodiments of the present application further provide a computer storage medium, where a plurality of program instructions may be stored, where the program instructions are adapted to be loaded by a processor and execute the method steps of the embodiments shown in fig. 2 to 17, and the specific execution process may refer to the specific description of the embodiments shown in fig. 2 to 17, which is not repeated herein.

Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored on a computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), or the like.

The foregoing disclosure is only illustrative of the preferred embodiments of the present application and is not intended to limit the scope of the claims herein, as the equivalent of the claims herein shall be construed to fall within the scope of the claims herein.

Claims

1. A data transfer control method applied to a direct memory access DMA, comprising:

2. The method of claim 1, wherein before the acquiring the data transfer state corresponding to the target data processed by the subsystem, further comprises:

3. The method of claim 1, wherein the performing the data transfer operation indicated by the data transfer state, after the system number is removed from the sequence of numbers, further comprises:

storing the system number in a next sequence of the numbered sequence;

4. The method according to claim 1, wherein the obtaining a number sequence corresponding to the data transfer state in the number sequence set, and obtaining the number information ordered in the first bit in the number sequence, includes:

the executing the data transfer operation indicated by the data transfer state, and removing the system number from the number sequence includes:

5. The method of claim 4, wherein the obtaining a number sequence corresponding to the data transfer state in the number sequence set, and obtaining the number information ordered in the first bit in the number sequence, comprises:

6. The method of claim 4, wherein the obtaining a number sequence corresponding to the data transfer state in the number sequence set, and obtaining the number information ordered in the first bit in the number sequence, comprises:

7. The method of claim 6, wherein the obtaining a number sequence corresponding to the data transfer state in the number sequence set, and obtaining the number information ordered in the first bit in the number sequence, comprises:

8. The method according to claim 5 or 7, wherein the obtaining a number sequence corresponding to the data transfer state in the number sequence set, and obtaining the number information ordered in the first bit in the number sequence, includes:

9. A data transfer control method applied to DMA, comprising:

10. The method according to claim 9, wherein the obtaining the data transfer state corresponding to the target data processed by the subsystem obtains a numbering sequence corresponding to the data transfer state in a numbering sequence set, and stores the system number corresponding to the subsystem in the numbering sequence, including:

11. The method according to claim 10, wherein the obtaining the data transfer state corresponding to the target data processed by the subsystem obtains a numbering sequence corresponding to the data transfer state in a numbering sequence set, and stores the system number corresponding to the subsystem in the numbering sequence, including:

12. The method according to claim 10, wherein the obtaining the data transfer state corresponding to the target data processed by the subsystem obtains a numbering sequence corresponding to the data transfer state in a numbering sequence set, and stores the system number corresponding to the subsystem in the numbering sequence, including:

13. The method according to claim 12, wherein the obtaining the data transfer state corresponding to the target data processed by the subsystem obtains a numbering sequence corresponding to the data transfer state in a numbering sequence set, and stores the system number corresponding to the subsystem in the numbering sequence, including:

14. The method according to claim 11 or 13, wherein the acquiring the data transfer state corresponding to the target data processed by the subsystem acquires a number sequence corresponding to the data transfer state from a sequence set, and stores the system number corresponding to the subsystem into the number sequence, including:

15. A data transfer control apparatus for use in DMA, comprising:

16. The apparatus as recited in claim 15, further comprising:

the system number acquisition unit is used for acquiring a system number corresponding to the subsystem when the instruction sending module sends a data transfer instruction to the subsystem;

the first number storage unit is used for respectively storing the system numbers to the same ordering positions in each number sequence of a number sequence set, and the number sequence set comprises an instruction number sequence, a storage number sequence and a response number sequence.

17. The apparatus as recited in claim 15, further comprising:

a second number storage unit configured to store the system number into a sequence next to the number sequence;

18. The apparatus according to claim 15, wherein the number information acquiring unit is specifically configured to acquire, when the data transfer state is an address release state, an instruction number sequence corresponding to the address release state in a number sequence set, and acquire, in the instruction number sequence, number information ordered in a first bit;

The data operation unit is used for executing the data transfer operation indicated by the data transfer state, and is specifically used for acquiring storage address information corresponding to the system number when the system number is removed from the number sequence, wherein the storage address information is a source storage address and a destination storage address for target data, which are obtained after the subsystem analyzes the data transfer instruction;

19. The apparatus according to claim 18, wherein the number information acquiring unit is specifically configured to acquire, when the data transfer state is a data storage state, a storage number sequence corresponding to the data storage state in a number sequence set, and acquire, in the storage number sequence, number information ordered in a first bit;

the data operation unit is used for executing the data transfer operation indicated by the data transfer state, and particularly is used for transferring target data from a source storage address of a source storage module to a destination storage address of a destination storage module based on the system number when the system number is removed from the number sequence, and removing the system number from the storage number sequence.

20. The apparatus according to claim 18, wherein the number information acquiring unit is specifically configured to receive target data returned by the source storage module based on the source storage address when the data transfer state is a data receiving state;

the data operation unit is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, specifically, is configured to send the target data to a subsystem corresponding to the system number, and remove the system number from the first stored number sequence.

21. The apparatus according to claim 20, wherein the number information obtaining unit is specifically configured to obtain, when the data transfer state is a data transfer state, a second stored number sequence corresponding to the data transfer state in a number sequence set, and obtain, in the second stored number sequence, number information ordered in a first bit;

The data operation unit is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, specifically configured to acquire the target data sent by the subsystem, send the target storage address and the target data to a target storage module, and remove the system number from the second storage number sequence.

22. The apparatus according to claim 19 or 21, wherein the number information acquiring unit is specifically configured to acquire, when the data transfer state is a storage response state, a response number sequence corresponding to the data storage state in a sequence set, and acquire, in the response number sequence, number information ordered in a first bit;

the data operation unit is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, specifically, is configured to return a response signal to the subsystem corresponding to the system number, remove the system number from the response number sequence, where the response signal is a response signal returned by the destination storage module after storing the target data.

23. A data transfer control apparatus for use in DMA, comprising:

24. The apparatus of claim 23, wherein the number storage unit is specifically configured to, when acquiring a system number corresponding to the subsystem and storage address information corresponding to the system number sent by the subsystem, set the data transfer state to an address release state, acquire an instruction number sequence corresponding to the address release state in a sequence set, store the system number in the instruction number sequence, and the storage address information is a source storage address and a destination storage address for target data obtained by the subsystem after analyzing a data transfer instruction;

the data operation unit is used for executing the data transfer operation indicated by the data transfer state, and particularly is used for sending the system number and the source storage address to a source storage module when the system number is removed from the number sequence, and removing the system number from the instruction number sequence.

25. The apparatus according to claim 24, wherein the number storage unit is specifically configured to, when acquiring the target data and the system number sent by the source storage module, set the data transfer state to a data storage state, acquire a storage number sequence corresponding to the data storage state in a number sequence set, and store the system number into the storage number sequence;

The data operation unit is used for executing the data transfer operation indicated by the data transfer state, and is specifically used for acquiring a destination storage address corresponding to the system number when the system number is removed from the number sequence, sending the system number, the target data and the destination storage address to the destination storage module, and removing the system number from the storage number sequence.

26. The apparatus according to claim 24, wherein the number storage unit is specifically configured to, when acquiring the target data and the system number sent by the source storage module, set the data transfer state to a data extraction state, acquire a first storage number sequence corresponding to the data extraction state in a number sequence set, and store the system number in the first storage number sequence;

27. The apparatus according to claim 26, wherein the number storage unit is specifically configured to, when the target data sent by the subsystem is acquired, set the data transfer state to a data transfer state, acquire a second storage number sequence corresponding to the data transfer state in a number sequence set, acquire a system number corresponding to the subsystem, and store the system number in the second storage number sequence;

the data operation unit is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, specifically, is configured to obtain a destination storage address corresponding to the system number, send the system number, the target data, and the destination storage address to the destination storage module, and remove the system number from the second storage number sequence.

28. The apparatus according to claim 25 or 27, wherein the number storage unit is specifically configured to, when acquiring the system code and the response signal sent by the destination storage module, set the data transfer state to a storage response state, acquire a response number sequence corresponding to the data storage state in a number sequence set, store the system code in the response number sequence, and the response signal is a response signal corresponding to the system number returned by the destination storage module after storing the target data;

The data operation unit is used for executing the data transfer operation indicated by the data transfer state, and particularly is used for returning a response signal to the subsystem corresponding to the system number when the system number is removed from the number sequence, and removing the system number from the response number sequence.

29. A computer device, comprising a processor, a memory, and an input-output interface;

the processor is connected to the memory and the input-output interface, respectively, wherein the input-output interface is used for page interaction, the memory is used for storing program code, and the processor is used for calling the program code to execute the method according to any one of claims 1-8 or the method according to any one of claims 9-14.

30. A computer storage medium storing a computer program comprising program instructions which, when executed by a processor, perform the method of any one of claims 1-8 or the method of any one of claims 9-14.