CN114490461A

CN114490461A - Data transfer control method, storage medium and equipment

Info

Publication number: CN114490461A
Application number: CN202011167579.2A
Authority: CN
Inventors: 刘君
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2020-10-27
Filing date: 2020-10-27
Publication date: 2022-05-13
Anticipated expiration: 2040-10-27
Also published as: CN114490461B

Abstract

The application discloses a data transfer control method, a storage medium and a device, wherein the method comprises the following steps: acquiring a data transfer state corresponding to target data processed by a subsystem; acquiring a number sequence corresponding to the data transfer state from the number sequence set, and acquiring number information ordered at the first position from the number sequence; when the number information is a system number corresponding to the subsystem, performing data transfer operation indicated by a data transfer state, and removing the system number from the number sequence; and when the number information is not the system number corresponding to the subsystem, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sequenced to the first position in the number sequence, executing the data transfer operation indicated by the data transfer state, and removing the system number from the number sequence. By the aid of the method and the device, channels can be decoupled, data transfer operation of each channel can be independently carried out, channel utilization rate is improved, and data transfer efficiency is improved.

Description

Data transfer control method, storage medium and equipment

Technical Field

The present application relates to the field of computer technologies, and in particular, to a data transfer control method, a storage medium, and a device.

Background

Direct Memory Access (DMA) modules are one of the important components of modern computers and can transfer data from one address space to another without relying on the heavy load of a central processor. The conventional DMA module is a process for implementing data transfer through a reusable channel, and may include: the DMA module comprises an instruction transmission channel, an address transmission channel, a data transfer channel and a storage response channel, wherein the channels are used for realizing the data transfer process based on a time-sharing multiplexing strategy, when one subsystem in the DMA module occupies the channels to carry out the data transfer operation, and when another data transfer instruction of another subsystem exists, the other subsystem can run the received data transfer instruction after the channels are released after the data transfer of the current subsystem is finished so as to occupy the channels to carry out the another data transfer operation. Because the channels are in a coupled state and have a timing dependence relationship, the utilization rate of the channels is low, and the efficiency of data transfer is influenced.

Disclosure of Invention

The embodiment of the application provides a data transfer control method, a storage medium and a device, which can decouple channels, ensure that each channel can independently perform data transfer operation, improve the utilization rate of the channels and further improve the efficiency of data transfer.

A first aspect of the embodiments of the present application provides a data transfer control method, which is applied to a DMA, and includes:

acquiring a data transfer state corresponding to target data processed by a subsystem, wherein the data transfer state is used for representing an execution stage in a data transfer process of the target data;

acquiring a number sequence corresponding to the data transfer state from a number sequence set, and acquiring number information ordered at a first position from the number sequence;

when the number information is a system number corresponding to the subsystem, executing data transfer operation indicated by the data transfer state, and removing the system number from the number sequence;

when the number information is not the system number corresponding to the subsystem, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sequenced to the first position in the number sequence, executing the data transfer operation indicated by the data transfer state, and removing the system number from the number sequence;

and the system numbers are respectively stored at the same sequencing position in each number sequence of the number sequence set.

A second aspect of the embodiments of the present application provides a data transfer control method, which is applied to a DMA, and includes:

acquiring a numbering sequence corresponding to the data transfer state from a numbering sequence set, and storing a system number corresponding to the subsystem into the numbering sequence;

when the system number is the number information which is sequenced at the first position in the number sequence, executing the data transfer operation indicated by the data transfer state, and removing the system number from the number sequence;

and when the system number is not the number information which is sequenced at the first position in the number sequence, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sequenced at the first position in the number sequence, executing the data transfer operation indicated by the data transfer state, and removing the system number from the number sequence.

A third aspect of the embodiments of the present application provides a data transfer control device, which is applied to a DMA, and includes:

the state acquisition unit is used for acquiring a data transfer state corresponding to target data processed by a subsystem, wherein the data transfer state is used for representing an execution stage in the data transfer process of the target data;

A number information acquisition unit, configured to acquire a number sequence corresponding to the data transfer state from a number sequence set, and acquire number information ordered at a first position from the number sequence;

the data operation unit is used for executing the data transfer operation indicated by the data transfer state when the number information is the system number corresponding to the subsystem, and removing the system number from the number sequence;

the data operation unit is further configured to suspend the data transfer operation indicated by the data transfer state when the number information is not the system number corresponding to the subsystem, wait for the system number to be sorted to the first position in the number sequence, execute the data transfer operation indicated by the data transfer state, and remove the system number from the number sequence;

A fourth aspect of the present embodiment provides a data transfer control device, which is applied to a DMA, and includes:

the system comprises a number storage unit, a number sequence collection unit and a data transfer unit, wherein the number storage unit is used for acquiring a data transfer state corresponding to target data processed by a subsystem, acquiring a number sequence corresponding to the data transfer state from the number sequence collection, and storing a system number corresponding to the subsystem into the number sequence, and the data transfer state is used for representing an execution stage in the data transfer process of the target data;

The data operation unit is used for executing the data transfer operation indicated by the data transfer state when the system number is the number information which is sequenced at the first position in the number sequence, and removing the system number from the number sequence;

the data operation unit is further configured to suspend the data transfer operation indicated by the data transfer state when the system number is not the number information ordered at the first position in the number sequence, wait for the system number ordered at the first position in the number sequence, execute the data transfer operation indicated by the data transfer state, and remove the system number from the number sequence.

A fifth aspect of an embodiment of the present application provides a computer device, including a processor, a memory, and an input/output interface;

the processor is respectively connected with the memory and the input/output interface, wherein the input/output interface is used for page interaction, the memory is used for storing program codes, and the processor is used for calling the program codes to execute the method steps.

A sixth aspect of embodiments of the present application provides a computer storage medium storing a computer program comprising program instructions that, when executed by a processor, perform the above-mentioned method steps.

In the embodiment of the application, by acquiring the data transfer state corresponding to the target data processed by the subsystem in the DMA module, the execution stage of the data transfer process of the current target data can be acquired, and then the system number corresponding to the subsystem matched with the number information can be acquired through the number information which is ordered at the first position and indicated by the number sequence corresponding to the data transfer state, and then the channel in the current data transfer state can be controlled to execute the data transfer operation process of the subsystem indicated by the system number for the target data, for the number information which is not the first bit in the number sequence, the current data transfer operation needs to be suspended and wait until the system number becomes the number information which is ordered at the first bit in the number sequence, and the channel can be opened to execute the data transfer operation indicated by the current data transfer state. By setting different numbering sequences in different data transfer states, each channel can execute data transfer operation of corresponding target data according to the system numbers indicated by the numbering sequences, decoupling of the channels is achieved, independent data transfer operation of each channel is guaranteed, channel utilization rate is improved, and data transfer efficiency is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a system architecture diagram of a data transfer control provided in an embodiment of the present application;

fig. 2 is a schematic flowchart of a data transfer control method according to an embodiment of the present application;

fig. 3 is a schematic flowchart of a data transfer control method according to an embodiment of the present application;

fig. 4 is a schematic flowchart of a data transfer control method according to an embodiment of the present application;

fig. 5 is a schematic flowchart of data transfer in an address release state according to an embodiment of the present application;

fig. 5a is an exemplary schematic diagram of data transfer in an address release state according to an embodiment of the present application;

FIG. 6 is a schematic flow chart illustrating data transfer in a data storage state according to an embodiment of the present application;

FIG. 6a is a schematic diagram illustrating an example of data transfer in a data storage state according to an embodiment of the present application;

FIG. 7 is a schematic flow chart illustrating data transfer in a storage response state according to an embodiment of the present disclosure;

FIG. 7a is a diagram illustrating an example of data transfer in a memory response state according to an embodiment of the present disclosure;

fig. 8 is a schematic flow chart of data transfer in a data receiving state according to an embodiment of the present application;

fig. 8a is a schematic diagram illustrating an example of data transfer in a data receiving state according to an embodiment of the present application;

fig. 8b is a schematic diagram illustrating an example of data transfer in a data receiving state according to an embodiment of the present application;

fig. 9 is a schematic flow chart of data transfer in a data dump state according to an embodiment of the present application;

FIG. 9a is a schematic diagram illustrating an example of data transfer in a data dump state according to an embodiment of the present application;

fig. 10 is a schematic diagram illustrating an example of a data transfer control method according to an embodiment of the present application;

fig. 11 is a schematic flowchart of a data transfer control method according to an embodiment of the present application;

fig. 12 is a schematic flowchart of data transfer in an address release state according to an embodiment of the present application;

fig. 12a is an exemplary diagram of data transfer in an address release state according to an embodiment of the present application;

FIG. 13 is a schematic flow chart illustrating data transfer in a data storage state according to an embodiment of the present application;

FIG. 13a is a schematic diagram illustrating an example of data transfer in a data storage state according to an embodiment of the present application;

FIG. 14 is a schematic flow chart illustrating data transfer in a storage response state according to an embodiment of the present disclosure;

FIG. 14a is a diagram illustrating an example of data transfer in a memory response state according to an embodiment of the present disclosure;

fig. 15 is a schematic flow chart of data transfer in a data receiving state according to an embodiment of the present application;

fig. 15a is a schematic diagram illustrating an example of data transfer in a data receiving state according to an embodiment of the present application;

fig. 16 is a schematic flow chart of data transfer in a data unloading state according to an embodiment of the present application;

FIG. 16a is a schematic diagram illustrating an example of data transfer in a data unloading state according to an embodiment of the present application;

fig. 17 is a schematic diagram illustrating an example of a data transfer control method according to an embodiment of the present application;

FIG. 18 is a timing diagram illustrating the execution of each channel in a DMA according to an embodiment of the present application;

FIG. 19 is a timing diagram illustrating the execution of each channel in a DMA according to an embodiment of the present application;

FIG. 20 is a timing diagram illustrating the execution of each channel in a DMA according to an embodiment of the present application;

Fig. 21 is a schematic structural diagram of a data transfer control device according to an embodiment of the present application;

fig. 22 is a schematic structural diagram of a data transfer control device according to an embodiment of the present application;

fig. 23 is a schematic structural diagram of a data transfer control device according to an embodiment of the present application;

FIG. 24 is a schematic structural diagram of a computer device according to an embodiment of the present application;

fig. 25 is a schematic structural diagram of a data transfer control apparatus according to an embodiment of the present application;

fig. 26 is a schematic structural diagram of a computer device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 1, a system architecture diagram for data transfer control is provided according to an embodiment of the present application. As shown in fig. 1, the embodiment of the present application may be applied to a data transfer scenario of a DMA module, where the data transfer scenario may be represented as data copy and data migration, the DMA data transfer process may be to transfer data from one address space in a source storage module to another address space in a destination storage module, and the source storage module and the destination storage module may be external independent storage devices, memories in computer devices, and other storage devices for data storage, and the computer devices may include, but are not limited to, personal computers, notebook computers, smart furniture, wearable devices, vehicle-mounted devices, and other storage devices.

Referring to fig. 1 again, fig. 1 further shows a specific architecture of the DMA module, where the DMA module may include an instruction sending module, a subsystem, a data transfer control device, and a channel managed by the data transfer control device, the instruction sending module is configured to generate a data transfer instruction from a source storage module to a destination storage module, and allocate the data transfer instruction to an idle subsystem for data transfer processing, and the subsystem may include multiple subsystems, for example: the subsystem 1, the subsystem 2, the subsystem …, and the subsystem N, N are positive integers, and the subsystem is configured to parse a received data transfer instruction to obtain storage address information carried in the data transfer instruction, where the storage address information may include a source storage address in a source storage module and a destination storage address in a destination storage module, and the storage address information is used to indicate a current storage location of target data to be transferred and a target storage location to be stored.

The multiple subsystems may share a channel in the DMA module, the channel may include, but is not limited to, an instruction transmission channel, a source address transmission channel, a data reception channel, a destination address transmission channel, a data transmission channel, and a storage response channel according to an execution sequence of the data transfer process, optionally, the instruction transmission channel is configured to transmit a data transfer instruction generated by the instruction transmission module to a corresponding subsystem, the source address transmission channel is configured to transmit a source storage address obtained by the subsystem to the source storage module, the data reception channel is configured to receive target data returned by the source storage module based on the source storage address, the destination address transmission channel is configured to transmit a destination storage address obtained by the subsystem to the destination storage module, and the data transmission channel is configured to transmit the target data to an address space of the destination storage address of the destination storage module, and the storage response channel is used for receiving the returned storage response information after the target data is stored by the target storage module.

The data transfer control devices may be respectively disposed corresponding to different channels, and may be configured to select, from information input by a current channel, information corresponding to a current data transfer processing cycle for output, and specifically may be configured to select, according to information such as an input data transfer instruction, storage address information, target data, a response signal, and the like, corresponding information in the current data transfer processing cycle for output, and in this embodiment, the data transfer control devices may also be configured to set and record a data transfer state corresponding to target data processed by a subsystem, and the data transfer control devices may further store a corresponding number sequence, where the number sequence may be used to indicate an arrangement order of the data transfer control devices according to system numbers in the number sequence, and sequentially executing the data transfer operation indicated by the system number in the current data transfer state, wherein the system number may be a system number corresponding to the subsystem.

It is understood that each subsystem may be pre-assigned with a corresponding system number for distinguishing the subsystems; the data transfer state may be used to indicate an execution stage in a data transfer process of target data, optionally, the data transfer state is corresponding to the system number, and since the subsystem can only participate in a data transfer process indicated by executing one data transfer instruction at a time, the data transfer state in the current data transfer process is related to the system number of the subsystem, the data transfer state may be according to an execution sequence of the data transfer process, including but not limited to an instruction transmission state, an address release state, a data storage state, a storage response state, and the like, the instruction transmission state is used to indicate that the current execution stage is in a state where the instruction sending module sends the data transfer instruction to the subsystem, the address release state is used to indicate that the current execution stage is in a state where the data transfer control device receives storage address information sent by the subsystem, and respectively sending the storage address information to a source storage module and a destination storage module, wherein the data storage state is used for transmitting target data to the destination storage module after the target data is received from the source storage module in the current execution stage, and the storage response state is used for indicating that a response signal is received from the destination storage module in the current execution stage.

Optionally, the data transfer control device may specifically be a module that manages all channels in the DMA, and may also include a plurality of data transfer control devices that are respectively distributed on a plurality of channels in the DMA, and when the data transfer control device is a plurality of data transfer control devices, the data transfer control device may correspond to the channels one to one, as shown in fig. 1, the data transfer control device may include, but is not limited to, a data transfer control device 10, a data transfer control device 20, a data transfer control device 30, a data transfer control device 40, a data transfer control device 50, and a data transfer control device 60, and the data transfer control device 10, the data transfer control device 20, the data transfer control device 30, the data transfer control device 40, the data transfer control device 50, and the data transfer control device 60 may be respectively connected to each other, and the subsystems are respectively connected to the data transfer control device, the data transfer control device 10 is further connected with an instruction sending module.

Specifically, the data transfer control device 10 is configured to set a data transfer state to an instruction transmission state when acquiring a data transfer instruction sent by an instruction sending module, and control an instruction transmission channel to transmit the data transfer instruction to a corresponding subsystem; the data transfer control device 20 is configured to set a data transfer state to an address release state when a source storage address sent by the subsystem is acquired, and control a source address transmission channel to send the source storage address to a source storage module; the data transfer control device 30 is configured to set a data transfer state as a data storage state when the data receiving channel acquires target data returned by the source storage module, and transmit the target data to the data transfer control device 50 to prepare for sending to the destination storage module; the data transfer control device 40 is configured to, when a destination storage address sent by the subsystem is obtained, control the destination address transmission channel to send the destination storage address to the destination storage module when the data transfer state is the address release state, or control the destination address transmission channel to send the destination storage address to the destination storage module when the data transfer state is the data storage state, where a sending time may specifically be selected according to an actual requirement; the data transfer control device 50 is configured to control a data transmission channel to transmit the acquired target data to a destination storage module when the data transfer state is the data storage state; the data transfer control device 60 acquires a response signal returned by the destination storage module in the storage response channel, sets the data transfer state to the storage response state, and sends the response signal to the subsystem; at this time, the subsystem may send a response signal to the instruction sending module, the data transfer control device 10 is further configured to obtain the response signal sent by the subsystem, and control the instruction transmission channel to send the response signal to the instruction sending module. Thus, a complete data transfer process is completed.

It should be noted that the data transfer states may be synchronized with the data transfer control device 10, the data transfer control device 20, the data transfer control device 30, the data transfer control device 40, the data transfer control device 50, and the data transfer control device 60, and when one data transfer state is set, the previous data transfer state may be replaced, and after the data transfer process is completed, the data transfer state corresponding to the system number may be removed, or the data transfer state may be reset to an initial value, for example: the data transfer state may be represented by a null value after reset. When the data transfer control apparatus is a module as a whole, all functions of the data transfer control apparatus 10, the data transfer control apparatus 20, the data transfer control apparatus 30, the data transfer control apparatus 40, the data transfer control apparatus 50, and the data transfer control apparatus 60 may be provided, and a manner of selecting some apparatuses among a plurality of data transfer control apparatuses to combine them, or dividing a certain data transfer control apparatus into a plurality of functional modules is included in the scope of protection of the present application.

In the existing DMA data transfer process, because a timing dependency exists between the channels of the DMA, that is, all the channels can be released to execute the data transfer process indicated by the next data transfer instruction only after the data transfer process indicated by the current data transfer instruction is completed, the channels are left vacant in the data transfer process, and the utilization rate of the channels and the efficiency of data transfer are affected.

In the embodiment of the application, by acquiring the data transfer state corresponding to the target data processed by the subsystem in the DMA module, the execution stage of the data transfer process of the current target data can be acquired, and then the system number corresponding to the subsystem matched with the number information can be acquired through the number information which is ordered at the first position and indicated by the number sequence corresponding to the data transfer state, and then the channel in the current data transfer state can be controlled to execute the data transfer operation process of the subsystem indicated by the system number for the target data, for the number information which is not the first bit in the number sequence, the current data transfer operation needs to be suspended and wait until the system number becomes the number information which is ordered at the first bit in the number sequence, and the channel can be opened to execute the data transfer operation indicated by the current data transfer state. By setting different numbering sequences in different data transfer states, the channels can execute the data transfer operation of corresponding target data according to the system numbers indicated by the numbering sequences, decoupling of the channels is achieved, independent data transfer operation of each channel is guaranteed, channel utilization rate is improved, and data transfer efficiency is improved.

Two different data transfer processes are provided in the embodiment of the application, and it can be understood that the existing storage module can be divided into a storage module only supporting order preservation or a storage module supporting order preservation and disorder, and for the storage module supporting order preservation, when a plurality of data transfer processes indicated by a plurality of data transfer instructions exist, when the same channel is used, the data transfer processes are sequentially used according to the sending sequence of the data transfer instructions, so as to ensure that the storage module cannot correctly process target data to be transferred due to disorder sending of information corresponding to a system number; for the storage module supporting disorder, when there are multiple data transfer processes indicated by multiple data transfer instructions, when the same channel is used, the data transfer operation of the system number on the channel can be executed first according to the first-in first-out principle, that is, the information corresponding to which system number is received first, and the storage module can correctly identify the system number, so as to ensure that the storage module correctly processes the target data to be transferred.

Based on the system architecture shown in fig. 1, the data transfer control method provided in the embodiment of the present application will be described in detail below with reference to fig. 2 to fig. 10, and the embodiment shown in fig. 2 to fig. 10 may be specifically implemented in a data transfer scenario of a storage module that supports order preservation.

Referring to fig. 2, a flow chart of a data transfer control method is provided in an embodiment of the present application. As shown in fig. 2, the method of the embodiment of the present application may include the following steps S101 to S104.

S101, acquiring a data transfer state corresponding to target data processed by a subsystem;

specifically, the data transfer control device may obtain a data transfer state corresponding to target data processed by the subsystem, where the data transfer state may be used to indicate an execution stage in a data transfer process of the target data, and it may be understood that the data transfer state corresponds to the system number, and since the subsystem can only participate in executing the data transfer process indicated by one data transfer instruction at a time, the data transfer state in the current data transfer process is all related to the system number of the subsystem, and the data transfer state may include, but is not limited to, an address release state, a data storage state, a storage response state, and the like according to an execution sequence of the data transfer process.

S102, acquiring a number sequence corresponding to the data transfer state from a number sequence set, and acquiring number information ordered at a first position from the number sequence;

Specifically, the data transfer control device may be preset with a numbering sequence set, where the numbering sequence set may include a plurality of numbering sequences, and specifically may include but is not limited to an instruction numbering sequence, a storage numbering sequence, and a response numbering sequence, where a numbering sequence may exist in each data transfer state, where the numbering sequence may be used to instruct the data transfer control device to sequentially execute the data transfer operation indicated by the system number in the current data transfer state according to an arrangement sequence of the system number in the numbering sequence, where the arrangement sequence of the system number in the numbering sequence may be specifically determined according to a sending sequence of the data transfer instruction, it may be understood that the data transfer instruction is sequentially sent to each subsystem through the data transfer control device, and the data transfer control device may obtain system numbers corresponding to a plurality of subsystems that receive the data transfer instruction, the data transfer control device may sequentially store a plurality of system numbers in a number sequence according to the transmission order of the data transfer instructions. Optionally, the data transfer control device may obtain a number sequence corresponding to the data transfer state in a number sequence set, and obtain number information ordered at a first position in the number sequence, where the number information ordered at the first position is used to indicate a system number for performing the data transfer operation indicated by the current data transfer state.

S103, when the number information is the system number corresponding to the subsystem, executing the data transfer operation indicated by the data transfer state, and removing the system number from the number sequence;

specifically, when the number information is a system number corresponding to the subsystem, the number information indicates that the system number is currently located at a first bit of the number sequence, the data transfer control device may control a channel to directly perform a data transfer operation indicated by the data transfer state, and meanwhile, the data transfer control device may remove the system number from the number sequence, where sequencing positions of the rest of number information in the number sequence may be shifted forward by one bit, for example: the system number ordered second may be ordered to the first position in the numbering sequence after the system number is culled.

S104, when the number information is not the system number corresponding to the subsystem, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sequenced to the first position in the number sequence, executing the data transfer operation indicated by the data transfer state, and removing the system number from the number sequence;

Specifically, when the number information is not the system number corresponding to the subsystem, it indicates that the system number is not currently located in the first bit of the number sequence, and the data transfer control device may suspend the data transfer operation indicated by the data transfer state, for example: the data transfer control device may control the channel to continue to perform the data transfer operation indicated by the data transfer state when the system number is sorted to the first position in the numbering sequence, and the data transfer control device may simultaneously remove the system number from the numbering sequence.

In the embodiment of the application, by acquiring the data transfer state corresponding to the target data processed by the subsystem in the DMA module, the execution stage of the data transfer process of the current target data can be acquired, and then the system number corresponding to the subsystem matched with the number information can be acquired through the number information which is ordered at the first position and indicated by the number sequence corresponding to the data transfer state, and then the channel in the current data transfer state can be controlled to execute the data transfer operation process of the subsystem indicated by the system number for the target data, for the number information which is not the first bit in the number sequence, the current data transfer operation needs to be suspended and wait until the system number becomes the number information which is ordered at the first bit in the number sequence, and the channel can be opened to execute the data transfer operation indicated by the current data transfer state. By setting different numbering sequences in different data transfer states, each channel can execute the data transfer operation of corresponding target data according to the system number indicated by the numbering sequence, a complete data transfer process can be divided into the data transfer operations corresponding to a plurality of data transfer states by the numbering sequence set, and the data transfer operations of the system numbers can be sequentially executed according to the arrangement sequence of the system numbers in the numbering sequence in the same data transfer state, so that the decoupling of the channels is realized, the data transfer operation can be independently carried out by each channel, meanwhile, the system numbers are stored at the same ordering position in each numbering sequence of the numbering sequence set, namely, the corresponding data transfer operation can be executed according to the arrangement sequence of the same system code in each data transfer state, on the basis of ensuring the execution sequence of each data transfer instruction, the channel utilization rate is improved, and the data transfer efficiency is further improved.

In the embodiment of the present application, the storing of the system number to the same ordering position in each number sequence of the number sequence set may include two possible implementations, where the first implementation may be that, when a data transfer instruction is received, the system number of the subsystem that receives the data transfer instruction is recorded, and the system number is stored in advance to the same ordering position in each number sequence; the second embodiment may be that each system number is removed from the current numbering sequence and added to the next numbering sequence of the current numbering sequence.

Referring to fig. 3, a schematic flow chart of a data transfer control method according to an embodiment of the present application is provided. As shown in fig. 3, the method of the embodiment of the present application may include the following steps S111 to S116.

S111, when the instruction sending module sends a data transfer instruction to the subsystem, obtaining a system number corresponding to the subsystem;

specifically, when the instruction sending module sends a data transfer instruction to a subsystem, the data transfer control device may obtain the data transfer instruction, and optionally, the instruction sending module may specify one of the subsystems to receive the data transfer instruction, for example: the instruction sending module records system numbers of a plurality of subsystems, the instruction sending module can send a specified system number and the data transfer instruction to the data transfer control equipment, and the data transfer control equipment can send the data transfer instruction to the subsystem corresponding to the system number; of course, the data transfer instruction may also be sent to one subsystem by the data transfer control device according to the idle states of multiple subsystems. After the data transfer control device receives the data transfer instruction, the data transfer control device may further obtain a system number corresponding to a subsystem that receives the data transfer instruction, and set a data transfer state corresponding to the system number as an instruction transmission state.

S112, respectively storing the system numbers to the same sequencing positions in each number sequence of the number sequence set;

specifically, the data transfer control device may store the system numbers to the same ordering position in each number sequence of a number sequence set, where the number sequence set may include a plurality of number sequences, specifically, but not limited to, an instruction number sequence, a storage number sequence, and a response number sequence, and it is understood that the ordering position of the system number in each number sequence is related to the sending order of the data transfer instruction, for example: when the data transfer control device receives the first data transfer instruction 1, the data transfer instruction 1 is sent to the subsystem 1, the system number S1 of the subsystem 1 can be obtained, S1 is stored in the first position of each number sequence respectively, at this time, the second data transfer instruction 2 is received, the data transfer instruction 2 is sent to the subsystem 2, the system number S2 of the subsystem 2 can be obtained, S2 is stored in each number sequence respectively, and at this time, S2 is located behind S1, namely, the second position and the like in each number sequence respectively; of course, if S1 in a number sequence is already removed when S2 is stored, the sorting position of S2 in the number sequence is the first bit.

S113, acquiring a data transfer state corresponding to the target data processed by the subsystem;

s114, acquiring a number sequence corresponding to the data transfer state from a number sequence set, and acquiring number information ordered at the first position from the number sequence;

s115, when the number information is the system number corresponding to the subsystem, executing the data transfer operation indicated by the data transfer state, and removing the system number from the number sequence;

s116, when the number information is not the system number corresponding to the subsystem, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sequenced to the first position in the number sequence, executing the data transfer operation indicated by the data transfer state, and removing the system number from the number sequence;

it should be noted that, for steps S113 to S116 in the embodiment of the present application, reference may be made to specific descriptions of steps S101 to S104 in the embodiment shown in fig. 2, which is not repeated herein.

In the embodiment of the application, by acquiring the data transfer state corresponding to the target data processed by the subsystem in the DMA module, the execution stage of the data transfer process of the current target data can be acquired, and then the system number corresponding to the subsystem matched with the number information can be acquired through the number information which is ordered at the first position and indicated by the number sequence corresponding to the data transfer state, and then the channel in the current data transfer state can be controlled to execute the data transfer operation process of the subsystem indicated by the system number for the target data, for the number information which is not the first bit in the number sequence, the current data transfer operation needs to be suspended and wait until the system number becomes the number information which is ordered at the first bit in the number sequence, and the channel can be opened to execute the data transfer operation indicated by the current data transfer state. By setting different numbering sequences in different data transfer states, each channel can execute data transfer operation of corresponding target data according to system numbers indicated by the numbering sequences, a complete data transfer process can be divided into data transfer operations corresponding to a plurality of data transfer states respectively through a numbering sequence set, and the data transfer operations of the system numbers can be sequentially executed according to the arrangement sequence of the system numbers in the numbering sequences in the same data transfer state, so that decoupling of the channels is realized, independent data transfer operation of each channel is ensured, meanwhile, the system numbers are pre-stored at the same ordering position in each numbering sequence of the numbering sequence set when a data transfer instruction is sent, namely, the system numbers in each data transfer state can be arranged according to the same system code sequence, and corresponding data transfer operation is executed, so that the channel utilization rate is improved on the basis of ensuring the execution sequence of each data transfer instruction, and the data transfer efficiency is further improved.

Referring to fig. 4, a flow chart of a data transfer control method according to the embodiment of the present application is schematically shown. As shown in fig. 4, the method of the embodiment of the present application may include the following steps S121 to S125.

S121, acquiring a data transfer state corresponding to target data processed by the subsystem;

s122, acquiring a numbering sequence corresponding to the data transfer state from a numbering sequence set, and acquiring numbering information ordered at a first position from the numbering sequence;

s123, when the number information is the system number corresponding to the subsystem, executing the data transfer operation indicated by the data transfer state, and removing the system number from the number sequence;

s124, when the number information is not the system number corresponding to the subsystem, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sequenced to the first position in the number sequence, executing the data transfer operation indicated by the data transfer state, and removing the system number from the number sequence;

it should be noted that, steps S121 to S124 in the embodiment of the present application may refer to specific descriptions of steps S101 to S104 in the embodiment shown in fig. 2, which are not described herein again.

S125, storing the system number into the next sequence of the number sequence;

specifically, while the system number is removed from the number sequence, the data transfer control device may store the system number in a next sequence of the number sequence, where the next sequence is a sequence ordered after the number sequence in a number sequence set according to a conversion order of the data transfer state, and the number sequence set includes an instruction number sequence, a storage number sequence, and a response number sequence. For example: if the system number is rejected in the instruction number sequence, the system number can be added to a storage number sequence; if the system number is rejected in the stored number sequence, the system number can be added to a response number sequence; of course, if the system number is removed from the response number sequence, it indicates that the data transfer process corresponding to the system number has been completed, and it is not necessary to occupy any channel to perform the data transfer operation, and at this time, it is only necessary to remove the system number from the response number sequence.

The instruction number sequence is related to the order of issue of the data transfer instructions, such as: when the data transfer control device receives the first data transfer instruction 1, the data transfer instruction 1 is sent to the subsystem 1, the system number S1 of the subsystem 1 can be acquired, and S1 is stored to the first bit in the instruction number sequence, at this time, the second data transfer instruction 2 is received, the data transfer instruction 2 is sent to the subsystem 2, the system number S2 of the subsystem 2 can be acquired, and S2 is stored in the instruction number sequence, at this time, S2 is located after S1, namely, the second bit, in each number sequence. Therefore, even if the current data migration operation is executed earlier in the data migration process in S2 than in S1, and the next data migration state is entered, because the system number is already removed from the current number sequence when the current data migration operation is executed and stored in the next sequence, the sorting position of S1 in the next sequence is still sorted before S2 and sorted at the first position, and the execution sequence of each data migration instruction is guaranteed.

In the embodiment of the application, by acquiring the data transfer state corresponding to the target data processed by the subsystem in the DMA module, the execution stage of the data transfer process of the current target data can be obtained, and then the system number corresponding to the subsystem matched with the number information can be obtained through the number information which is ordered at the first position and is indicated by the number sequence corresponding to the data transfer state, and then the channel in the current data transfer state can be controlled to execute the data transfer operation process of the subsystem indicated by the system number for the target data, for the number information which is not the first bit in the number sequence, the current data transfer operation needs to be suspended and wait until the system number becomes the number information which is ordered at the first bit in the number sequence, and the channel can be opened to execute the data transfer operation indicated by the current data transfer state. By setting different numbering sequences in different data transfer states, each channel can execute the data transfer operation of corresponding target data according to the system number indicated by the numbering sequence, a complete data transfer process can be divided into the data transfer operations corresponding to a plurality of data transfer states by a numbering sequence set, and the data transfer operations of the system numbers can be sequentially executed according to the arrangement sequence of the system numbers in the numbering sequence in the same data transfer state, so that the decoupling of the channels is realized, the data transfer operation can be independently carried out for each channel, meanwhile, when the current data transfer operation is executed, the system number is removed from the current numbering sequence and stored in the next sequence, therefore, when the current data transfer operation is executed and enters the next data transfer state, the system number still keeps the sequencing position in the current numbering sequence before elimination in the next sequence, and on the basis of ensuring the execution sequence of each data transfer instruction, the channel utilization rate is improved, and the data transfer efficiency is further improved.

The embodiments shown in fig. 5 to 7 will describe the data transfer operation in the address release state, the data storage state, and the storage response state in the data transfer state, respectively.

Referring to fig. 5, a schematic flow chart of data transfer in an address release state is provided for an embodiment of the present application. As shown in fig. 5, the process may include:

s131, when the data transfer state is an address release state, acquiring an instruction number sequence corresponding to the address release state from a number sequence set, and acquiring number information ordered at a first position from the instruction number sequence;

specifically, when the instruction sending module sends a data transfer instruction to the subsystem, the data transfer control device may obtain a system number of the subsystem, set a data transfer state corresponding to the system number as an instruction transmission state, and store the system number into an instruction number sequence, optionally, when the data transfer control device receives the data transfer instruction sent to the subsystem by the instruction sending module, the data transfer control device may control an instruction transmission channel to send the data transfer instruction to the subsystem, the subsystem may analyze the data transfer instruction to obtain storage address information carried in the data transfer instruction, the storage address information may include a source storage address and a destination storage address of target data requested to be transferred, and when the subsystem obtains the source storage address and the destination storage address, the source storage address can be sent to the data transfer control device, when the data transfer control device obtains the source storage address, the data transfer state can be set to an address release state from the instruction transmission state, optionally, the subsystem can send the source storage address to the data transfer control device, simultaneously, the subsystem can send the destination storage address to the data transfer control device, and also can send the destination storage address to the data transfer control device in the data storage state, and specifically, the destination storage address can be set according to actual requirements. When the data transfer state is the address release state, the data transfer control device may obtain an instruction number sequence corresponding to the address release state, and obtain the number information ordered at the first bit in the instruction number sequence.

S132, when the number information is the system number corresponding to the subsystem, acquiring storage address information corresponding to the system number, sending the source storage address to a source storage module, and removing the system number from the instruction number sequence;

specifically, when the number information is the system number, that is, it indicates that the system number is currently ordered in the first bit of the instruction number sequence, the data transfer control device may control a source address transmission channel to send a source storage address corresponding to the system number to a source storage module, and optionally, the data transfer control device may also control a destination address transmission channel to send a destination storage address corresponding to the system number to a destination storage module, and may also transmit the destination storage address and the destination data to the destination storage module in a data storage state, which may specifically be set according to actual requirements. When the source storage address is sent to the source storage module, according to the first embodiment, the data transfer control device may remove the system number from the instruction number sequence, and according to the second embodiment, the data transfer control device may remove the system number from the instruction number sequence and store the system number in the storage number sequence.

S133, when the serial number information is not the system serial number corresponding to the subsystem, suspending the data transfer operation indicated by the data transfer state, waiting for the system serial number to be sequenced to the first position in the serial number sequence, acquiring storage address information corresponding to the system serial number, sending the source storage address to a source storage module, and removing the system serial number from the instruction serial number sequence;

specifically, when the number information is not the system number, that is, it indicates that the system number is not currently sorted in the first bit of the instruction number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state and wait for the system number to be sorted to the first bit in the number sequence. Further, when the system number is ordered to the first bit in the instruction number sequence, the data transfer control device may control a source address transmission channel to transmit a source storage address corresponding to the system number to a source storage module, and when the source storage address is transmitted to the source storage module, according to the first implementation, the data transfer control device may remove the system number from the instruction number sequence, and according to the second implementation, the data transfer control device may remove the system number from the instruction number sequence and store the system number in a storage number sequence.

Referring to fig. 5a, an exemplary schematic diagram of data transfer in an address release state is provided for an embodiment of the present application. As shown in fig. 5a, an instruction sending module sends a data transfer instruction 1 to the data transfer control device 10, the data transfer control device 10 controls an instruction transmission channel to send an S1_ data transfer instruction to the subsystem 1, considering that the data transfer instruction 1 carries a system number of the subsystem 1, the data transfer instruction 1 may include the system number S1 and an S1_ data transfer instruction of the subsystem 1, and when the system number S1 does not exist in the data transfer instruction 1, the data transfer instruction 1 is equal to the S1_ data transfer instruction.

The data migration control device 10 may store the system number S1 in the instruction number sequence and set the data migration state of S1 as the instruction transfer state, and when there is the data migration instruction 2, similarly to the data migration instruction 1, the instruction sending module may send the data migration instruction 2 to the data migration control device 10, and the data migration control device 10 may control the instruction transfer channel to send the S2_ data migration instruction to the subsystem 2, and store the system number S2 of the subsystem 2 in the instruction number sequence and set the data migration state of S2 as the instruction transfer state, as shown in fig. 5a, S1 is ordered at the first bit in the instruction number sequence, and S2 is ordered at the second bit.

The data transfer device 10 may synchronize S1 to the data transfer device 20 to indicate that S1 is currently ordered in the first place, the subsystem 1 may parse the S1_ data transfer instruction to obtain S1_ source storage address and S1_ destination storage address, and send S1_ source storage address to the data transfer control device 20, similarly, the subsystem 2 may send S2_ source storage address to the data transfer control device 20, the data transfer control device 20 may set the data transfer state of S1 from the instruction transfer state to the address release state when receiving the S1_ source storage address, the data transfer control device 20 synchronizes S1 ordered in the instruction number sequence to obtain S1_ source storage address, and may control the source address transmission channel to send S1_ source storage address to the source storage module, the data transfer control device 20 may notify the data transfer control device 10 to remove S1 from the instruction number sequence, at this time, the data transfer control device 10 synchronizes the first ordered S2 to the data transfer control device 20, and likewise, the data transfer control device 20 may set the data transfer state of S2 from the instruction transfer state to the address release state, and further control the source address transfer channel to send the S2_ source memory address to the source memory module.

It should be noted that, since the data transfer control device 10 has synchronized the first bit S1 of the instruction number sequence to the data transfer control device 20, even if the subsystem 1 causes the subsystem 2 to send the S2_ source storage address to the data transfer control device 20 first due to a line delay problem, the data transfer control device 20 will not send the S2_ source storage address to the source storage module, and can send the S2_ source storage address only when the S2 is sorted in the first bit of the instruction number sequence.

In the embodiment of the application, when the data transfer state corresponding to the system number is in the address release state, the source storage addresses sent by different subsystems can be sequentially sent to the source storage module according to the instruction number sequence, so that decoupling of the source address transmission channel is realized, the source address transmission channel can independently carry out the sending process of the source storage addresses, meanwhile, the system number is removed from the current number sequence when current data transfer operation is executed, and the utilization rate of the source address transmission channel is improved on the basis of ensuring the sending sequence of the source storage addresses.

Referring to fig. 6, a schematic flow chart of data transfer in a data storage state is provided in the present embodiment. As shown in fig. 6, the process may include:

S141, when the data transfer state is a data storage state, acquiring a storage number sequence corresponding to the data storage state from a number sequence set, and acquiring number information ordered at a first position from the storage number sequence;

specifically, when the data transfer control device receives target data returned by the source storage module based on the source storage address based on the data receiving channel, the data transfer control device may set a data transfer state corresponding to the system number from an address release state to a data storage state, and of course, the data transfer control device may also set the data transfer state from the address release state to the data storage state after sending the source storage address, and specifically may set the data transfer state according to an actual requirement, and the data transfer control device may obtain a storage number sequence corresponding to the data storage state in a number sequence set, and obtain number information sorted in a first order in the storage number sequence.

When the target data is received, the address bits of the target data can be matched with the source storage address, so that the system number to which the target data belongs can be determined, and the matching can also be directly performed through the system number described in the target data.

S142, when the number information is the system number corresponding to the subsystem, transferring the target data from the source storage address of the source storage module to the destination storage address of the destination storage module based on the system number, and removing the system number from the storage number sequence;

specifically, when the number information is the system number, that is, when the number information indicates that the system number is currently sorted in the first bit of the storage number sequence, the data transfer control device may obtain the target data sent by the source storage module based on the data receiving channel, upon receipt of the target data, the source storage address may be matched by address bits of the target data, further determining the system number of the target data, or directly matching the system number with the system number described in the target data, when the target data belonging to the system number is acquired, the data transfer control device may send the target data and the destination storage address to a destination storage module, the target data can be sent through a data sending channel, and the target storage address can be sent through a target address transmission channel.

Optionally, when the data transfer control device is in the address release state, the destination address transmission channel may be controlled to transmit the destination storage address corresponding to the system number to the destination storage module in advance, or may perform associated storage on the destination storage address and the system number when the data transfer control device is in the address release state, and when the data transfer control device is in the data storage state, the destination storage address is obtained based on the system number and is transmitted to the destination storage module together with the target data, which may specifically be set according to actual requirements. When the target data is sent to the destination storage module, according to the first embodiment, the data migration control device may remove the system number from the storage number sequence, and according to the second embodiment, the data migration control device may remove the system number from the storage number sequence and store the system number in the response number sequence.

S143, when the number information is not the system number corresponding to the subsystem, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sorted to the first position in the number sequence, transferring the target data from the source storage address of the source storage module to the target storage address of the target storage module based on the system number, and removing the system number from the storage number sequence;

Specifically, when the number information is not the system number, that is, it indicates that the system number is not currently sorted in the first bit of the storage number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state and wait for the system number to be sorted to the first bit in the storage number sequence. Further, when the system number is ordered to the first bit in the number sequence, the data transfer control device may obtain target data sent by a source storage module based on a data receiving channel, and when the target data is received, the address bit of the target data may be matched with the source storage address, so as to determine the system number to which the target data belongs, or may directly perform matching through the system number described in the target data, and when the target data belonging to the system number is obtained, the data transfer control device may send the target data and the target storage address to a target storage module, where the target data may be sent through a data sending channel, and the target storage address may be sent through a target address transmission channel. When the target data is sent to the target storage module, according to the first embodiment, the data transfer control device may remove the system number from the storage number sequence, and according to the second embodiment, the data transfer control device may remove the system number from the storage number sequence and store the system number in the response number sequence.

Referring to fig. 6a, an exemplary schematic diagram of data transfer in a data storage state is provided in the embodiment of the present application. As shown in fig. 6a, the data migration control device 30 acquires the target data corresponding to the system number S1, that is, the target data received by the source storage module at S1_ based on the data receiving channel, the data migration control device 30 may set the data migration state of S1 to the data storage state, and the data migration control device 30 is synchronized with S1 in advance, and as can be seen from fig. 6a, S1 is located at the first bit of the storage number sequence, and the system number S2 is located at the second bit of the storage number sequence.

The data migration control device 30 may transmit the received target data S1_ received by the source storage module to the data migration control device 50, the data migration control device 50 may control the data transmission channel to transmit the target data S1_ sent to the destination storage module, meanwhile, the data migration control device 50 may agree with the data migration control device 40 to notify the data migration control device 40 to control the destination address transmission channel to transmit the S1_ destination storage address to the destination storage module synchronously, the destination storage module may store the target data S1_ sent to the destination storage module in the address space indicated by the S1_ destination storage address, and the data migration control device 30 may remove S1 from the storage number sequence. It should be noted that, in S1, the target data received by the source storage module and the target data sent to the destination storage module in S1 may be the target data corresponding to S1, and this naming method is only used to distinguish the target data received or sent in different channels.

Similarly, when the data migration control device 30 receives the target data of S2 based on the data receiving channel, that is, S2_ the target data received by the source storage module, the data migration control device 30 may set the data migration status of S2 to the data storage status, if S1 in the storage number sequence is not removed at this time, the data migration control device 30 may buffer the target data received by S2_ the source storage module, and wait for S1 to remove from the storage number sequence, the data migration control device 30 may transmit the target data received by S2_ the source storage module to the data migration control device 50, the data migration control device 50 may control the data transmitting channel to transmit the target data transmitted by S2_ to the destination storage module, and at the same time, the data migration control device 50 may agree with the data migration control device 40, the notification data transfer controlling apparatus 40 controls the destination address transfer channel to send the S2_ destination storage address sending synchronization to the destination storage module, the destination storage module may store the target data sent to the destination storage module in S2_ in the address space indicated by the S2_ destination storage address, and the data transfer controlling apparatus 30 may cull S2 from the storage number sequence. It should be noted that, in S2, the target data received by the source storage module and the target data sent to the destination storage module in S2 may be the target data corresponding to S2, and this naming method is only used to distinguish the target data received or sent in different channels.

It should be noted that, since the first bit S1 of the storage number sequence has been synchronized to the data transfer control apparatus 30, the data transfer control apparatus 40, and the data transfer control apparatus 50, even if the source storage module receives the target data received by the source storage module S2 first due to a line delay problem by the data transfer control apparatus 30, the data transfer control apparatus 30 does not transmit the target data received by the source storage module S2 to the data transfer control apparatus 50, and the target data received by the source storage module S2_ can be transmitted only when S2 is sorted at the first bit of the storage number sequence.

In the embodiment of the application, when the data transfer state corresponding to the system number is in the data storage state, the target data of different system numbers can be sequentially transferred from the source storage module to the destination storage module according to the storage number sequence, so that decoupling of the data receiving channel, the data sending channel and the destination address transmission channel is realized, the data receiving channel, the data sending channel and the destination address transmission channel can jointly and independently perform data receiving, sending and destination address sending processes, meanwhile, the system number is removed from the current number sequence when the current data transfer operation is executed, and the utilization rates of the data receiving channel, the data sending channel and the destination address transmission channel are improved on the basis of ensuring the processing sequence of data receiving, sending and destination address sending.

Referring to fig. 7, a schematic flow chart of data transfer in a storage response state is provided for an embodiment of the present application. As shown in fig. 7, the process may include:

s151, when the data transfer state is a storage response state, acquiring a response number sequence corresponding to the data storage state from a number sequence set, and acquiring number information ordered at a first position from the response number sequence;

specifically, after the data transfer control device sends the target data to the destination storage module for storage, setting the data transfer state corresponding to the system number from the data storage state to the storage response state, of course, the data transfer control device may also, upon receiving the response signal sent by the destination storage module, the data transfer state corresponding to the system number is set from the data storage state to the storage response state, and may be specifically set according to actual requirements, in the embodiment of the present application, when a response signal sent by the destination storage module is received, taking the data transfer state corresponding to the system number as the storage response state from the data storage state as an example, the data transfer control device may acquire a response number sequence corresponding to the storage response state in a number sequence set, and acquire number information ordered at a first bit in the response number sequence.

When the data transfer control device receives the response signal, matching can be directly performed through the system number described in the response signal to determine the system number to which the response signal belongs.

S152, when the number information is the system number corresponding to the subsystem, a response signal is returned to the subsystem corresponding to the system number, and the system number is removed from the response number sequence;

specifically, when the number information is the system number, that is, it indicates that the system number is currently sorted in the first bit of the response number sequence, the data transfer control device may obtain, based on the storage response channel, a response signal returned by the destination storage module after storing the target data, and send the response signal to the subsystem corresponding to the system number, the data transfer control device may remove the system number from the response number sequence, and the subsystem may return the response signal to the instruction sending module through the data transfer control device to respond to the data transfer instruction, thereby completing a data transfer process.

S153, when the number information is not the system number corresponding to the subsystem, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sequenced to the first position in the number sequence, returning a response signal to the subsystem corresponding to the system number, and removing the system number from the response number sequence;

Specifically, when the number information is not the system number, that is, it indicates that the system number is not currently sorted in the first bit of the response number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state and wait for the system number to be sorted to the first bit in the number sequence. Further, when the system number is sorted to the first bit in the number sequence, the data transfer control device may obtain, based on a storage response channel, a response signal returned by the destination storage module after storing the target data, and send the response signal to the subsystem corresponding to the system number, the data transfer control device may remove the system number from the response number sequence, and the subsystem may return the response signal to the instruction sending module via the data transfer control device to respond to the data transfer instruction, thereby completing a data transfer process.

Referring to fig. 7a, an exemplary diagram of data transfer in a memory response state is provided for an embodiment of the present application. As shown in fig. 7a, the data migration control device 60 acquires the S1_ response signal corresponding to the system number S1 based on the storage response channel, the data migration control device 60 may set the data migration state of S1 to the storage response state, the data migration control device 60 is synchronized with S1 in advance, and as can be seen from fig. 7a, S1 is located at the first position of the response number sequence, and the system number S2 is located at the second position of the response number sequence.

The data migration control device 60 may transmit the received S1_ response signal to the subsystem 1 corresponding to S1, the subsystem 1 may transmit the S1_ response signal to the data migration control device 10, the data migration control device 10 controls the instruction transmission channel to receive the S1_ response signal, and transmits the response signal 1 to the instruction transmission module in response to the data migration instruction 1, and considering that the S1_ response signal does not carry the system number S1 of the subsystem 1, the data migration control device 10 may encapsulate the S1 and the S1_ response signal as the response signal 1 and transmit the response signal 1 to the instruction transmission module, and when the system number S1 exists in the S1_ response signal, the response signal 1 is equal to the S1_ response signal.

Similarly, when the data migration control device 60 receives the S2_ response signal based on the storage response channel, the data migration control device 60 may set the data migration status of S2 to the storage response status, and if S1 in the response number sequence is not removed at this time, the data migration control device 60 may buffer the S2_ response signal and wait for S1 to be removed from the response number sequence, the data migration control device 60 may transmit the received S2_ response signal to the subsystem 2, and the data migration control device 60 may remove S2 from the response number sequence. The subsystem 2 may transmit an S2_ response signal to the data transfer control apparatus 10, and the data transfer control apparatus 10 controls the instruction transmission channel to receive the S2_ response signal and transmit the response signal 2 to the instruction transmission module in response to the data transfer instruction 2.

It should be noted that, since the first bit S1 of the response number sequence is synchronized to the data transfer control device 60, even if the destination memory module receives the S2_ response signal first due to a line delay problem, the data transfer control device 60 will not send the S2_ response signal to the subsystem 2, and the S2_ response signal can be sent only when the S2 is sorted to the first bit of the response number sequence.

In the embodiment of the application, when the data transfer state corresponding to the system number is in the storage response state, the response signals corresponding to different system numbers sent by the target storage module can be sequentially sent to the corresponding subsystems according to the response number sequence, so that decoupling of the storage response channel is realized, the storage response channel can be ensured to independently send the response signals, meanwhile, the system number is removed from the current number sequence when current data transfer operation is executed, and the utilization rate of the storage response channel is improved on the basis of ensuring the sending sequence of the response signals.

In this embodiment of the present application, the DMA module may include at least two operating modes, where the first operating mode is data direct storage, that is, directly storing target data of the source storage module into the destination storage module, and reference may be made to the detailed description of the embodiment shown in fig. 6; and in the second working mode, after the target data is returned from the source storage module, the target data can be sent to the subsystem for data processing, and then the processed target data is sent to the target storage module for storage. It should be noted that, the first operating mode and the second operating mode are implemented in the same way when the data transfer state is the instruction transmission state, the address release state, and the storage response state, and only when the data storage state is the data storage state, there is a difference, and the selection of the operating mode may be determined by the data transfer instruction. For the data transfer process of the second operation mode in the data storage state, please refer to the following embodiments shown in fig. 8 to fig. 9.

Please refer to fig. 8, which provides a schematic flow chart of data transfer in a data receiving state according to an embodiment of the present application. As shown in fig. 8, the process may include:

s161, when the data transfer state is a data receiving state, receiving target data returned by the source storage module based on the source storage address;

specifically, based on the second operating mode, the data storage state further may include a data receiving state and a data unloading state, where the data receiving state may be used to indicate that the current execution stage is in a state where the target data returned by the source storage module is acquired, and the target data is sent to the subsystem corresponding to the system number.

When the data transfer control device receives target data returned by the source storage module based on the source storage address based on the data receiving channel, the data transfer control device may set the data transfer state corresponding to the system number from the address release state to the data receiving state, and of course, the data transfer control device may also set the data transfer state from the address release state to the data receiving state after sending the source storage address, and may specifically set the data transfer state according to actual requirements. In the embodiment of the application, for example, after a source storage address is sent, the data transfer state is set from an address release state to a data receiving state, and when the data transfer state is the data receiving state, the data transfer control device may control a data receiving channel to obtain target data returned by the source storage module based on the source storage address.

S162, acquiring a first storage serial number sequence corresponding to the data receiving state from a serial number sequence set, and acquiring serial number information sequenced at a first position from the first storage serial number sequence;

specifically, based on the second operation mode, the storage number sequence may further include a first storage number sequence and a second storage number sequence, and the data transfer control device may obtain a first storage number sequence corresponding to the data receiving state in the number sequence set, and obtain the number information ordered at the first position in the first storage number sequence.

S163, when the number information is the system number corresponding to the subsystem, sending the target data to the subsystem corresponding to the system number, and removing the system number from the first storage number sequence;

specifically, when the number information is the system number, that is, it indicates that the system number is currently ordered in the first bit of the response number sequence, the data transfer control device may obtain, based on a data receiving channel, target data returned by a source storage module, and then send the target data to a subsystem corresponding to the system number, and when sending the target data to the destination storage module, according to the first implementation manner, the data transfer control device may remove the system number from the first storage number sequence, and according to the second implementation manner, the data transfer control device may remove the system number from the first storage number sequence and store the system number into a second storage number sequence, and the subsystem receives the target data and may perform data processing on the target data, the data processing may include data logic operation, data compression, and the like, and the data transfer instruction may further include a data processing signal, where the data processing signal is used to instruct the data transfer control device to send the received target data to the subsystem corresponding to the system number, so as to perform corresponding data processing.

S164, when the number information is not the system number corresponding to the subsystem, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sequenced to the first position in the number sequence, sending the target data to the subsystem corresponding to the system number, and removing the system number from the first storage number sequence;

specifically, when the number information is not the system number, that is, it indicates that the system number is not currently sorted in the first bit of the first storage number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state, and wait for the system number to be sorted to the first bit in the number sequence. Further, when the system number is sorted to the first position in the first storage number sequence, the data transfer control device may obtain, based on a data receiving channel, target data returned by a source storage module, and then send the target data to a subsystem corresponding to the system number, and when sending the target data to the destination storage module, according to the first implementation, the data transfer control device may remove the system number from the first storage number sequence, and according to the second implementation, the data transfer control device may remove the system number from the first storage number sequence, and store the system number to the second storage number sequence. The subsystem receives the target data, may perform data processing on the target data, where the data processing may include data logic operation, data compression, and the like, and the data transfer instruction may further include a data processing signal, where the data processing signal is used to instruct the data transfer control device to send the received target data to a subsystem corresponding to the system number, so as to perform corresponding data processing.

Referring to fig. 8a and 8b together, an exemplary schematic diagram of data transfer in a data receiving state is provided for an embodiment of the present application. As shown in fig. 8a, the subsystem 1 may parse the S1_ data transfer instruction to obtain S1_ source storage address and S1_ destination storage address, and send the S1_ source storage address to the data transfer control apparatus 20, and similarly, the subsystem 2 may send the S2_ source storage address to the data transfer control apparatus 20, when the data transfer control apparatus 20 receives the S1_ source storage address, the data transfer state of the S1 may be set to the address release state from the instruction transmission state, the data transfer control apparatus 20 synchronizes the instruction number sequence to obtain the first ordered S1, may control the source address transmission channel to send the S1_ source storage address to the source storage module, the data transfer control apparatus 20 may notify the data transfer control apparatus 10 to remove the S1 from the instruction number sequence, at this time, the data transfer control apparatus 10 synchronizes the first ordered S2 to the data transfer control apparatus 20, also, the data transfer control device 20 may set the data transfer state of S2 from the instruction transfer state to the address release state, thereby controlling the source address transfer channel to send the S2_ source memory address to the source memory module. As can be seen from fig. 8a, S1 and S2 are stored in advance in the first storage number sequence, S1 is sorted to the first bit in the first storage number sequence, and S2 is sorted to the second bit in the first storage number sequence; the sequence numbers may be added to the first storage number sequence after being respectively removed at S1 and S2.

As shown in fig. 8b, the data migration control device 30 acquires the target data corresponding to the system number S1, that is, S1_ target data received by the source storage module, based on the data receiving channel, the data migration control device 30 may set the data migration state of S1 to the data receiving state, the data migration control device 30 may transmit the received target data of S1_ received by the source storage module to the subsystem 1, at which time S1 in the first storage number sequence may be culled, based on the data receiving channel receiving the target data of S2, that is, S2_ target data received by the source storage module, the data migration control device 30 may set the data migration state of S2 to the data receiving state, and if S1 in the first storage number sequence is not culled at this time, the data migration control device 30 may cache the target data of S2_ received by the source storage module, after waiting for S1 to be removed from the first storage number sequence, the data migration control device 30 may transmit the received S2_ target data received by the source storage module to the subsystem 2, as shown in fig. 8b, where S1 and S2 are stored in advance in the second storage number sequence, S1 is sorted to be the first bit in the second storage number sequence, and S2 is sorted to be the second bit in the second storage number sequence; the data is also added to the second storage number sequence after being respectively removed from the first storage number sequence at S1 and S2.

In the embodiment of the application, when the data transfer state corresponding to the system number is in the data receiving state, the target data of different system numbers can be sequentially sent to the corresponding subsystems by the source storage module according to the first storage number sequence for data processing, so that decoupling of the data receiving channel is realized, the data receiving channel can independently perform a data receiving process, meanwhile, the system number is removed from the current number sequence when the current data transfer operation is performed, and the utilization rate of the data receiving channel is improved on the basis of ensuring the processing sequence of data receiving and sending.

Fig. 9 is a schematic flow chart of data transfer in a data dump state according to an embodiment of the present disclosure. As shown in fig. 9, the process may include:

s171, when the data transfer state is the data unloading state, acquiring a second storage number sequence corresponding to the data unloading state from the number sequence set, and acquiring the number information ordered at the first position from the second storage number sequence;

specifically, the data receiving state may be used to indicate that the current execution stage is in a state of sending the destination storage address and the target data to a destination storage module when the target data sent by the subsystem is acquired. After the data processing is performed on the target data, the subsystem may send the target data after the data processing to the data transfer control device, and the data transfer control device may set the data transfer state corresponding to the system number from the data receiving state to the data unloading state. In the embodiment of the application, after the target data is sent to the subsystem, the data transfer state corresponding to the system number is set to be the data transfer state from the data receiving state, and when the data transfer state is the data transfer state, the data transfer control device may acquire a second storage number sequence corresponding to the data transfer state from the number sequence set, and acquire the number information sorted in the first order from the second storage number sequence.

S172, when the number information is a system number corresponding to the subsystem, the target data sent by the subsystem is obtained, the target storage address and the target data are sent to a target storage module, and the system number is removed from the second storage number sequence;

specifically, when the serial number information is the system serial number, that is, it indicates that the system serial number is currently sorted in the first bit of the second storage serial number sequence, the data transfer control device may acquire the processed target data sent by the subsystem, and send the processed target data to the destination storage module based on a data sending channel.

Optionally, when the data transfer control device is in the address release state, the destination address transmission channel may be controlled to transmit the destination storage address corresponding to the system number to the destination storage module in advance, or when the data transfer control device is in the address release state, the destination storage address and the system number may be stored in association, and when the data transfer control device is in the data transfer state, the destination storage address is obtained based on the system number and is transmitted to the destination storage module together with the target data after data processing, which may be specifically set according to actual requirements.

S173, when the serial number information is not the system serial number corresponding to the subsystem, suspending the data transfer operation indicated by the data transfer state, waiting for the system serial number to be sequenced to the first position in the serial number sequence, acquiring the target data sent by the subsystem, sending the target storage address and the target data to a target storage module, and removing the system serial number from the second storage serial number sequence;

specifically, when the number information is not the system number, that is, it indicates that the system number is not currently sorted in the first bit of the second storage number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state and wait for the system number to be sorted to the first bit in the second storage number sequence. Further, when the system number is sorted to the first position in the second storage number sequence, the data transfer control device may acquire the target data after data processing sent by the subsystem, and send the target data after data processing to a destination storage module based on a data sending channel.

Fig. 9a is a schematic diagram of an example of data transfer in a data transfer state according to an embodiment of the present disclosure. As shown in fig. 9a, after receiving the target data transmitted by S1_ to the destination storage module by the subsystem 1, the data migration control device 50 may control the data transmission channel to transmit the target data transmitted by S1_ to the destination storage module, meanwhile, the data migration control device 50 may agree with the data migration control device 40 to notify the data migration control device 40 to control the destination address transmission channel to transmit S1_ destination storage address to the destination storage module synchronously, the destination storage module may store the target data transmitted by S1_ to the destination storage module in the address space indicated by S1_ destination storage address, and the data migration control device 50 may remove S1 from the second storage number sequence. It should be noted that, in S1_ the target data received by the source storage module is represented as the target data corresponding to S1 acquired by the source storage module, and in S1_ the target data sent to the destination storage module is represented as the data processed by the subsystem 1 on the target data received by the source storage module in S1_ step.

Similarly, if S1 in the second storage number sequence is not removed, the data transfer control device 50 may receive S2_ target data received by the source storage module and transmitted by the subsystem 2, buffer S2_ target data received by the source storage module, and wait for S1 to remove from the second storage number sequence, the data transfer control device 50 may control the data transmission channel to transmit S2_ target data transmitted to the destination storage module, and at the same time, the data transfer control device 50 may agree with the data transfer control device 40 to notify the data transfer control device 40 to control the destination address transmission channel to transmit S2_ target storage address to the destination storage module synchronously, and the destination storage module may store the S2_ target data transmitted to the destination storage module in the address space indicated by the S2_ target storage address, the data transfer control device 50 may remove S2 from the second stored number sequence. It should be noted that, in S2_ the target data received by the source storage module is represented as the target data corresponding to S2 acquired by the source storage module, and in S2_ the target data sent to the destination storage module is represented as the target data received by the source storage module in S2_ after being subjected to data processing by the subsystem 2. As can be seen from fig. 9a, S1 and S2 are stored in advance in the response number sequence, S1 is sorted at the first bit in the response number sequence, and S2 is sorted at the second bit in the response number sequence; or after being respectively removed from the second storage number sequence at S1 and S2, the second storage number sequence may be added to the response number sequence.

In the embodiment of the application, when the data transfer state corresponding to the system number is in the data transfer state, the target data after data processing of the subsystems of different system numbers can be sequentially sent to the target storage module for storage according to the second storage number sequence, so that decoupling of the data sending channel is realized, the process that the data sending channel can independently send data is ensured, meanwhile, the system number is removed from the current number sequence when current data transfer operation is executed, and the utilization rate of the data sending channel is improved on the basis of ensuring the processing sequence of data sending.

The data transfer control method provided in the embodiment of the present application will be described in detail below with reference to the specific example of fig. 10.

Referring to fig. 10, an exemplary schematic diagram of a data transfer control method is provided in the present embodiment. As shown in fig. 10, the instruction sending module sends the data transfer instruction 1 to the data transfer control device 10, the data transfer control device 10 controls the instruction transmission channel to send the S1_ data transfer instruction to the subsystem 1, considering that the data transfer instruction 1 carries the system number of the subsystem 1, the data transfer instruction 1 may include the system number S1 and S1_ data transfer instruction of the subsystem 1, and when the system number S1 does not exist in the data transfer instruction 1, the data transfer instruction 1 is equal to the S1_ data transfer instruction.

The data transfer control device 10 may store the system number S1 in the instruction number sequence and set the data transfer state of S1 to the instruction transfer state, and when there is the data transfer instruction 2, the instruction sending module may send the data transfer instruction 2 to the data transfer control device 10, similarly to the data transfer instruction 1, the data transfer control device 10 may control the instruction transfer channel to send the S2_ data transfer instruction to the subsystem 2, and store the system number S2 of the subsystem 2 in the instruction number sequence and set the data transfer state of S2 to the instruction transfer state, S1 is sorted in the first bit in the instruction number sequence, and S2 is sorted in the second bit. The data transfer device 10 may synchronize S1 to the data transfer device 20, the data transfer device 30, the data transfer device 40, the data transfer device 50, and the data transfer device 60, indicating that the current S1 is sorted in the first place, the subsystem 1 may parse the S1_ data transfer instruction to obtain the S1_ source storage address and the S1_ destination storage address, and send the S1_ source storage address to the data transfer control device 20, similarly, the subsystem 2 may send the S2_ source storage address to the data transfer control device 20, the data transfer control device 20 may set the data transfer state of S1 to the address release state when receiving the S1_ source storage address, the data transfer control device 20 synchronizes with the instruction number sequence to obtain the S1 sorted in the first place, may control the source address transmission channel to send the S1_ source storage address to the source storage module, the data transfer control device 20 may notify the data transfer control device 10 to remove S1 from the sequence of instruction numbers, and at this time, the data transfer control device 10 synchronizes S2 ordered at the first bit to the data transfer control device 20, and likewise, the data transfer control device 20 may set the data transfer state of S2 from the instruction transmission state to the address release state, and further, control the source address transmission channel to send S2_ source storage address to the source storage module.

The data migration control device 30 acquires target data corresponding to the system number S1, that is, S1_ target data received by the source storage module, based on the data receiving channel, the data migration control device 30 may set the data migration state of S1 to a data receiving state, the data migration control device 30 may transmit the received target data of S1_ received by the source storage module to the subsystem 1, at this time, S1 in the first storage number sequence may be rejected, when the data migration control device 30 receives the target data of S2 based on the data receiving channel, that is, S2_ target data received by the source storage module, the data migration control device 30 may set the data migration state of S2 to a data receiving state, and if at this time, the S1 in the first storage number sequence is not rejected, the data migration control device 30 may cache the target data of S2_ received by the source storage module, after waiting for S1 to be removed from the first storage number sequence, the data migration control device 30 may transmit the received S2_ target data received by the source storage module to the subsystem 2, where S1 and S2 are stored in advance in the second storage number sequence, S1 is sorted to the first bit in the second storage number sequence, and S2 is sorted to the second bit in the second storage number sequence; the data is also added to the second storage number sequence after being respectively removed from the first storage number sequence at S1 and S2.

After receiving the target data transmitted by S1_ to the destination storage module by the subsystem 1, the data migration control device 50 may control the data transmission channel to transmit the target data transmitted by S1_ to the destination storage module, meanwhile, the data migration control device 50 may agree with the data migration control device 40 to notify the data migration control device 40 to control the destination address transmission channel to transmit S1_ destination storage address to the destination storage module synchronously, the destination storage module may store the target data transmitted by S1_ to the destination storage module in the address space indicated by S1_ destination storage address, and the data migration control device 50 may remove S1 from the second storage number sequence. It should be noted that S1_ represents the target data received by the source storage module as the target data corresponding to S1 acquired by the source storage module, and S1_ represents the target data sent to the destination storage module as the target data received by S1_ by the source storage module is processed by the subsystem 1.

Similarly, if S1 in the second storage number sequence is not removed, the data transfer control device 50 may receive S2_ target data received by the source storage module and transmitted by the subsystem 2, buffer S2_ target data received by the source storage module, and wait for S1 to remove from the second storage number sequence, the data transfer control device 50 may control the data transmission channel to transmit S2_ target data transmitted to the destination storage module, and at the same time, the data transfer control device 50 may agree with the data transfer control device 40 to notify the data transfer control device 40 to control the destination address transmission channel to transmit S2_ target storage address to the destination storage module synchronously, and the destination storage module may store the S2_ target data transmitted to the destination storage module in the address space indicated by the S2_ target storage address, the data transfer control device 50 may remove S2 from the second sequence of storage numbers. It should be noted that, in S2_ the target data received by the source storage module is represented as the target data corresponding to S2 acquired by the source storage module, and in S2_ the target data sent to the destination storage module is represented as the target data received by the source storage module in S2_ after being subjected to data processing by the subsystem 2. The response number sequence is stored with S1 and S2 in advance, S1 is arranged at the first bit in the response number sequence, and S2 is arranged at the second bit in the response number sequence; or after being respectively removed from the second storage number sequence at S1 and S2, the second storage number sequence may be added to the response number sequence.

The data migration control device 60 acquires the S1_ response signal corresponding to the system number S1 based on the storage response channel, the data migration control device 60 may set the data migration state of S1 to the storage response state, the data migration control device 60 synchronizes S1 in advance, S1 is located at the first bit of the response number sequence, and the system number S2 is located at the second bit of the response number sequence.

It should be noted that the two data transfer processing procedures of the DMA module shown in the embodiment of the present application are only examples, and for more than two data transfer processing procedures, the implementation may also be implemented with reference to the detailed description of the foregoing embodiment.

Based on the system architecture shown in fig. 1, the data transfer control method provided in the embodiment of the present application will be described in detail below with reference to fig. 11 to 17, and the embodiment shown in fig. 11 to 17 may be specifically implemented in a data transfer scenario supporting an out-of-order storage module.

Referring to fig. 11, a flow chart of a data transfer control method is provided in an embodiment of the present application. As shown in fig. 11, the method of the embodiment of the present application may include the following steps S201 to S203.

S201, acquiring a data transfer state corresponding to target data processed by a subsystem, acquiring a number sequence corresponding to the data transfer state from a number sequence set, and storing a system number corresponding to the subsystem into the number sequence;

specifically, the data transfer control device may obtain a data transfer state corresponding to target data processed by the subsystem, where the data transfer state may be used to indicate an execution stage in a data transfer process of the target data, and it may be understood that the data transfer state corresponds to the system number, and since the subsystem can only participate in executing a data transfer process indicated by one data transfer instruction at a time, the data transfer state in the current data transfer process is all related to the system number of the subsystem, and the data transfer state may include, but is not limited to, an address release state, a data storage state, a storage response state, and the like according to an execution sequence of the data transfer process.

The data transfer control device may be preset with a numbering sequence set, where the numbering sequence set may include a plurality of numbering sequences, and specifically may include but is not limited to an instruction numbering sequence, a storage numbering sequence, and a response numbering sequence, where one numbering sequence may exist in each data transfer state, the numbering sequence may be used to instruct the data transfer control device to sequentially execute the data transfer operation indicated by the system number in the current data transfer state according to an arrangement order of the system numbers in the numbering sequence, and the arrangement order of the system numbers in the numbering sequence may specifically be determined according to a receiving order of information such as addresses, data, and signals, for example: when a source storage address transmitted by the subsystem is received, a system number corresponding to the subsystem can be obtained, and the system number is stored in a number sequence. The data transfer control device may sequentially store a plurality of system numbers into a number sequence according to a reception order of the information.

S202, when the system number is the number information which is sequenced at the first position in the number sequence, executing the data transfer operation indicated by the data transfer state, and removing the system number from the number sequence;

S203, when the system number is not the number information which is sequenced at the first position in the number sequence, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sequenced at the first position in the number sequence, executing the data transfer operation indicated by the data transfer state, and removing the system number from the number sequence;

it should be noted that step S202 and step S203 in the embodiment of the present invention may refer to the detailed description of step S102 and step S103 in the embodiment shown in fig. 2, and are not repeated herein.

In this embodiment of the present application, an execution stage of a data transfer process of current target data may be obtained by obtaining a data transfer state corresponding to target data processed by a subsystem in a DMA module, and then, by a numbering sequence corresponding to the data transfer state, a system number of the subsystem is stored in the numbering sequence to ensure that a system number that enters the data transfer state first may be stored in the numbering sequence first, which indicates that the system number may perform a data transfer operation indicated by the data transfer state first in a channel in the current data transfer state, and for a system number that is not a first bit in the numbering sequence, the current data transfer operation needs to be suspended for waiting until the system number is sorted in the first bit in the numbering sequence, the channel may be opened to perform the data transfer operation indicated by the current data transfer state, when the data transfer operation is performed, and the system number is removed from the numbering sequence, so that decoupling of the channels is realized, and independent data transfer operation of each channel is ensured, meanwhile, the system number is stored in the numbering sequence according to the information receiving sequence, namely, the system number of the numbering sequence is firstly entered, the data transfer operation indicated by the data transfer state of the system number can be preferentially executed, the out-of-order execution process of data transfer is realized, the waiting time of each channel when executing the data transfer operation is reduced, the channel utilization rate is improved, and the data transfer efficiency is further improved.

The embodiments shown in fig. 12 to 14 will describe the data transfer operation in the address release state, the data storage state, and the storage response state in the data transfer state, respectively.

Referring to fig. 12, a schematic flow chart of data transfer in an address release state is provided for the embodiment of the present application. As shown in fig. 12, the process may include:

s211, when a system number corresponding to the subsystem and storage address information corresponding to the system number, which are sent by the subsystem, are obtained, the data transfer state is set to be an address release state, an instruction number sequence corresponding to the address release state is obtained from a number sequence set, and the system number is stored in the instruction number sequence;

specifically, when the instruction sending module sends a data transfer instruction to the subsystem, the data transfer control device may acquire a system number of the subsystem, and set a data transfer state corresponding to the system number to an instruction transmission state, optionally, when the data transfer control device receives the data transfer instruction sent to the subsystem by the instruction sending module, the data transfer control device may control the instruction transmission channel to send the data transfer instruction to the subsystem, the subsystem may analyze the data transfer instruction to acquire storage address information carried in the data transfer instruction, and the storage address information may include a source storage address and a destination storage address of target data to be transferred.

The subsystem can send the source storage address to the data transfer control equipment when obtaining the source storage address and the destination storage address, the data transfer control equipment can set the data transfer state to an address release state from the instruction transmission state when obtaining the source storage address, optionally, the subsystem can send the source storage address to the data transfer control equipment, and simultaneously send the destination storage address to the data transfer control equipment, and can also send the destination storage address to the data transfer control equipment when in the data storage state, and specifically, the subsystem can set according to actual requirements.

The data transfer control device may obtain an instruction number sequence corresponding to the address release state in a number sequence set, and store the system number in the instruction number sequence.

S212, when the system number is the number information which is sequenced at the first position in the number sequence, the system number and the source storage address are sent to a source storage module, and the system number is removed from the instruction number sequence;

Specifically, when the system number is the number information ordered at the first position in the number sequence, that is, it indicates that the system number is currently ordered at the first position in the instruction number sequence, the data transfer control device may control the source address transmission channel to send the source storage address corresponding to the system number to the source storage module, and when the source storage address is sent to the source storage module, the data transfer control device may remove the system number from the instruction number sequence.

S213, when the system number is not the number information which is sequenced at the first position in the number sequence, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sequenced at the first position in the number sequence, sending the system number and the source storage address to a source storage module, and removing the system number from the instruction number sequence;

specifically, when the system number is not the number information ordered at the first bit in the number sequence, that is, it indicates that the system number is not currently ordered at the first bit in the instruction number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state, and wait for the system number to be ordered at the first bit in the number sequence. Further, when the system number is ordered to the first bit in the sequence of instruction numbers, the data transfer control device may control a source address transmission channel to send a source storage address corresponding to the system number to a source storage module, and when the source storage address is sent to the source storage module, the data transfer control device may remove the system number from the sequence of instruction numbers.

Fig. 12a is a schematic diagram of an example of data transfer in an address release state according to an embodiment of the present disclosure. As shown in fig. 12a, the instruction sending module sends the data transfer instruction 1 to the data transfer control device 10, the data transfer control device 10 controls the instruction transmission channel to send the S1_ data transfer instruction to the subsystem 1, considering that the data transfer instruction 1 carries the system number of the subsystem 1, the data transfer instruction 1 may include the system number S1 and S1_ data transfer instruction of the subsystem 1, and when the system number S1 does not exist in the data transfer instruction 1, the data transfer instruction 1 is equal to the S1_ data transfer instruction.

The data transfer control device 10 may set the data transfer state of S1 to the instruction transmission state, when there is a data transfer instruction 2, the instruction sending module may send the data transfer instruction 2 to the data transfer control device 10 similarly to the data transfer instruction 1, the data transfer control device 10 may control the instruction transmission channel to send the S2_ data transfer instruction to the subsystem 2, and set the data transfer state of S2 to the instruction transmission state.

The subsystem 1 may parse the S1_ data transfer instruction to obtain the S1_ source storage address and the S1_ destination storage address, and send the S1_ source storage address to the data transfer control device 20, and similarly, the subsystem 2 may send the S2_ source storage address to the data transfer control device 20, and when the data transfer control device 20 receives the S1_ source storage address, the data transfer control device 20 may set the data transfer state of the S1 from the instruction transfer state to the address release state, and store the S1 in the instruction number sequence, and similarly, the data transfer control device 20 may set the data transfer state of the S2 from the instruction transfer state to the address release state, and store the S2 in the instruction number sequence.

Further, if the data migration control device 20 receives the S1_ source storage address first and then receives the S2_ source storage address, then in the instruction number sequence, S1 is sorted at the first position and S2 is sorted at the second position, otherwise, S2 is sorted at the first position and S1 is sorted at the second position. As shown in fig. 12a, at this time, when the data transfer control device 20 receives the S1_ source storage address first, the data transfer control device 20 may store S1 in the first bit of the instruction number sequence, may control the source address transmission channel to send the S1 and S1_ source storage address to the source storage module, and then removes S1 from the instruction number sequence. When the data migration control device 20 receives the S2_ source storage address again, S2 may be stored in the instruction number sequence, at this time, if S1 is removed, S2 is converted to the first bit of the instruction number sequence, and the data migration control device 20 may control the source address transmission channel to send the S2 and S2_ source storage address to the source storage module, and then remove S2 from the instruction number sequence; if S1 has not been removed, the data migration control device 20 may first cache the S2_ source storage address until S2 is converted to the first bit of the instruction number sequence, send the S2 and S2_ source storage address, and remove S2 from the instruction number sequence.

In the embodiment of the application, when the data transfer state corresponding to the system number is in the address release state, the source storage addresses sent by different subsystems can be sequentially sent to the source storage module according to the instruction number sequence, so that decoupling of the source address transmission channel is realized, the source address transmission channel is guaranteed to independently carry out the sending process of the source storage addresses, meanwhile, the system number is stored into the instruction number sequence according to the receiving sequence of the source storage addresses, the disorder sending process of the source storage addresses is further realized, and the utilization rate of the source address transmission channel is improved.

Referring to fig. 13, a schematic flow chart of data transfer in a data storage state is provided for an embodiment of the present application. As shown in fig. 13, the process may include:

s221, when the target data and the system number sent by the source storage module are acquired, setting the data transfer state as a data storage state, acquiring a storage number sequence corresponding to the data storage state from a number sequence set, and storing the system number into the storage number sequence;

specifically, the source storage module may obtain target data based on a source storage address, and return the target data and the received system number to the data transfer control device, and when the data transfer control device receives the system number and the target data returned by the source storage module based on a data receiving channel, the data transfer control device may set a data transfer state corresponding to the system number from an address release state to a data storage state, obtain a storage number sequence corresponding to the data storage state in a number sequence set, and store the system number in the storage number sequence.

S222, when the system number is number information which is sequenced at the first position in the number sequence, a target storage address corresponding to the system number is obtained, the system number, the target data and the target storage address are sent to the target storage module, and the system number is removed from the storage number sequence;

specifically, when the system number is the number information ordered at the first position in the number sequence, that is, it indicates that the system number is currently ordered at the first position in the storage number sequence, the data transfer control device may obtain a destination storage address corresponding to the system number in a cache, or request a subsystem corresponding to the system number to obtain the destination storage address, and the data transfer control device may send the system number, the target data, and the destination storage address to the destination storage module, and then remove the system number from the storage number sequence. The system number and the target data can be sent through a data sending channel, and the target storage address can be sent through a target address transmission channel.

S223, when the system number is not the number information which is sequenced at the first position in the number sequence, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sequenced at the first position in the number sequence, acquiring a target storage address corresponding to the system number, sending the system number, the target data and the target storage address to the target storage module, and removing the system number from the storage number sequence;

specifically, when the system number is not the number information ordered at the first bit in the number sequence, that is, it indicates that the system number is not currently ordered at the first bit in the storage number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state, and wait for the system number to be ordered at the first bit in the storage number sequence. Further, when the system number is ordered to the first bit in the number sequence, the data transfer control device may obtain a destination storage address corresponding to the storage number in a cache, or request a subsystem corresponding to the system number to obtain the destination storage address, and the data transfer control device may send the system number, the target data, and the destination storage address to the destination storage module, and then remove the system number from the storage number sequence. The system number and the target data can be sent through a data sending channel, and the target storage address can be sent through a target address transmission channel.

Referring to fig. 13a, an exemplary schematic diagram of data transfer in a data storage state is provided for an embodiment of the present application. As shown in fig. 13a, the data transfer control device 30 acquires the target data corresponding to S1 and S1, that is, the target data S1_ received by the source storage module, based on the data receiving channel, and the data transfer control device 30 may set the data transfer state of S1 as the data storage state, and store S1 in the storage number sequence; likewise, the data transfer control device 30 may set the data transfer state of S2 to the data storage state, and store S2 into the storage number sequence.

Further, if the data migration control device 30 receives S1_ the target data received by the source storage module first and then receives S2_ the target data received by the source storage module, S1 is sorted at the first position and S2 is sorted at the second position in the storage number sequence, otherwise, S2 is sorted at the first position and S1 is sorted at the second position. As shown in fig. 13a, at this time, the data migration control device 30 first receives S2_ the target data received by the source storage module, the data migration control device 30 may store S2 in the first bit of the storage number sequence, may transmit S2_ the target data received by the source storage module to the data migration control device 50, the data migration control device 50 may synchronize with the data migration control device 40 when receiving S2_ the target data received by the source storage module, the data migration control device 40 may obtain S2_ the destination storage address of the cache or transmitted by the subsystem 2, the data migration control device 40 may control the destination address transmission channel to transmit S2_ the destination storage address to the destination storage module, the data migration control device 50 may control the data transmission channel to transmit S2_ the target data transmitted by the destination storage module to the destination storage module, the data transfer control device 30 may remove S2 from the stored number sequence. The destination storage module may store the target data transmitted from S2_ to the destination storage module in the address space indicated by the destination storage address of S2_ destination storage module. It should be noted that, in S2, the target data received by the source storage module and the target data sent to the destination storage module in S2 may both be the target data corresponding to S2, and this naming manner is only used to distinguish the target data received or sent on different channels.

When the data migration control device 30 receives S1_ the target data received by the source storage module again, S1 may be stored in the storage number sequence, at this time, if S2 is removed, S1 is converted to the first bit of the storage number sequence, and the data migration control device 40 and the data migration control device 50 may send the storage addresses of S1 and S1_ and the target data sent by S1_ to the destination storage module, and then remove S1 from the storage number sequence; if S2 has not been removed, the data migration control device 30 may first cache the target data received by the source storage module in S1_ until S1 is converted into the first bit of the storage number sequence, send the target storage addresses in S1 and S1_ and the target data sent to the destination storage module in S1_ and then remove S1 from the storage number sequence. It should be noted that, in S1, the target data received by the source storage module and the target data sent to the destination storage module in S1 may be the target data corresponding to S1, and this naming method is only used to distinguish the target data received or sent in different channels.

In the embodiment of the application, when the data transfer state corresponding to the system number is in the data storage state, the target data of different system numbers can be sequentially transferred from the source storage module to the destination storage module according to the storage number sequence, decoupling of the data receiving channel, the data sending channel and the destination address transmission channel is achieved, and it is ensured that the data receiving channel, the data sending channel and the destination address transmission channel can independently perform data receiving, sending and destination address sending processes.

Referring to fig. 14, a schematic flow chart of data transfer in a storage response state is provided for the embodiment of the present application. As shown in fig. 14, the process may include:

s231, when the system code and the response signal sent by the target storage module are acquired, setting the data transfer state as a storage response state, acquiring a response number sequence corresponding to the data storage state from a number sequence set, and storing the system code into the response number sequence;

specifically, after the target data is stored in the address space indicated by the target storage address by the target storage module, a response signal and a received system number may be returned to the data transfer control device, and when the data transfer control device acquires the system code and the response signal sent by the target storage module based on a storage response channel, the data transfer control device may set the data transfer state corresponding to the system number from the data storage state to the storage response state, acquire a response number sequence corresponding to the data storage state from the number sequence set, and store the system code in the response number sequence.

S232, when the system number is the number information which is sequenced at the first position in the number sequence, a response signal is returned to the subsystem corresponding to the system number, and the system number is removed from the response number sequence;

specifically, when the system number is the number information that is ordered at the first position in the number sequence, that is, the system number is currently ordered at the first position in the storage number sequence, the data transfer control device may send the response signal to the subsystem corresponding to the system number, and then remove the system number from the response number sequence.

S233, when the system number is not the number information ordered at the first position in the number sequence, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be ordered at the first position in the number sequence, returning a response signal to the subsystem corresponding to the system number, and removing the system number from the response number sequence;

specifically, when the system number is not the number information ordered at the first bit in the number sequence, that is, it indicates that the system number is not currently ordered at the first bit in the response number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state, and wait for the system number to be ordered at the first bit in the response number sequence. Further, when the system number is sorted to the first position in the number sequence, the data transfer control device may send the response signal to the subsystem corresponding to the system number, and then remove the system number from the response number sequence.

Referring to fig. 14a, an exemplary diagram of data transfer in a memory response state is provided for an embodiment of the present application. As shown in fig. 14a, the data transfer control device 60 acquires the S1_ response signal corresponding to the system number S1 and S1 based on the storage response channel, and the data transfer control device 60 may set the data transfer state of S1 to the storage response state, and store S1 in the response number sequence; likewise, the data transfer control device 60 may set the data transfer state of S2 to the data storage state, and store S2 in the response number sequence.

Further, if the data migration control device 60 receives the S1_ response signal first and then receives the S2_ response signal, then in the response number sequence, S1 is sorted at the first bit and S2 is sorted at the second bit, otherwise, S2 is sorted at the first bit and S1 is sorted at the second bit. As shown in fig. 14a, when the data transfer control device 60 receives the S2_ response signal first, the data transfer control device 60 may store S2 in the first bit of the response number sequence, may transmit the S2_ response signal to the subsystem 2 corresponding to S2, and the data transfer control device 60 may remove S2 from the response number sequence. The subsystem 2 may transmit an S2_ response signal to the data migration control device 10, the data migration control device 10 controls the instruction transmission channel to receive the S2_ response signal, and transmits the response signal 2 to the instruction transmission module in response to the data migration instruction 2, and considering that the S2_ response signal does not carry the system number S2 of the subsystem 2, the data migration control device 10 may package the S2 and S2_ response signals as the response signal 2 to be transmitted to the instruction transmission module, and when the system number S2 exists in the S2_ response signal, the response signal 2 is equal to the S2_ response signal.

When the data migration control device 60 receives the S1_ response signal again, S1 may be stored in the response number sequence, and if S2 is removed, S1 is converted to the first bit of the response number sequence, and the data migration control device 60 may transmit the S1_ response signal to the subsystem 1 corresponding to S1, and remove S1 from the response number sequence; if S2 has not been removed, the data transfer control device 60 may first buffer the S1_ response signal until S1 is converted to the first bit of the response number sequence, transmit the S1_ response signal to the subsystem 1 corresponding to S1, and remove S1 from the response number sequence. The subsystem 1 may transmit an S1_ response signal to the data migration control device 10, the data migration control device 10 controls the instruction transmission channel to receive the S1_ response signal, and transmits the response signal 1 to the instruction transmission module in response to the data migration instruction 1, and considering that the S1_ response signal does not carry the system number S1 of the subsystem 1, the data migration control device 10 may package the S1 and S1_ response signals as the response signal 1 to transmit to the instruction transmission module, and when the system number S1 exists in the S1_ response signal, the response signal 1 is equal to the S1_ response signal.

In the embodiment of the application, when the data transfer state corresponding to the system number is in the storage response state, the response signals corresponding to different system numbers sent by the target storage module can be sequentially sent to the corresponding subsystems according to the response number sequence, decoupling of the storage response channel is realized, the storage response channel can be guaranteed to independently send the response signals, meanwhile, the system number is stored into the response number sequence according to the receiving sequence of the response signals, the disorder sending process of the response signals is further realized, and the utilization rate of the storage response channel is improved.

In this embodiment of the present application, the DMA module may include at least two working modes, where the first working mode is data direct storage, that is, directly storing the target data of the source storage module into the destination storage module, and reference may be made to the specific description of the embodiment shown in fig. 13; and in the second working mode, the target data can be sent to the subsystem for data processing after being returned from the source storage module, and then the processed target data is sent to the target storage module for storage. It should be noted that, the first operating mode and the second operating mode are implemented in the same way when the data transfer state is the instruction transmission state, the address release state, and the storage response state, and only when the data storage state is the data storage state, there is a difference, and the selection of the operating mode may be determined by the data transfer instruction. Please refer to the embodiment shown in fig. 15-16 below for the data transfer process in the data storage state in the second operation mode.

Fig. 15 is a schematic flow chart of data transfer in a data receiving state according to an embodiment of the present disclosure. As shown in fig. 15, the process may include:

s241, when the target data and the system number sent by the source storage module are acquired, setting the data transfer state as a data extraction state, acquiring a first storage number sequence corresponding to the data extraction state from a number sequence set, and storing the system number into the first storage number sequence;

The source storage module may obtain target data based on a source storage address, and return the target data and the received system number to the data transfer control device, and when the data transfer control device receives the system number and the target data returned by the source storage module based on a data receiving channel, the data transfer control device may set a data transfer state corresponding to the system number from an address release state to a data storage state, obtain a first storage number sequence corresponding to the data receiving state in a number sequence set, and store the system number in the first storage number sequence.

S242, when the system number is the number information which is sequenced at the first position in the number sequence, the target data is sent to the subsystem corresponding to the system number, and the system number is removed from the first storage number sequence;

Specifically, when the system number is the number information that is ordered at the first position in the number sequence, that is, the system number is currently ordered at the first position in the first storage number sequence, the data transfer control device may send the target data to the subsystem corresponding to the system number, and then remove the system number from the first storage number sequence. The subsystem receives the target data, may perform data processing on the target data, and the data processing may include data logic operation, data compression, and the like, and the data transfer instruction may further include a data processing signal, where the data processing signal is used to instruct the data transfer control device to send the received target data to the subsystem corresponding to the system number, so as to perform corresponding data processing.

S243, when the system number is not the number information which is sequenced at the first position in the number sequence, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sequenced at the first position in the number sequence, sending the target data to the subsystem corresponding to the system number, and removing the system number from the first storage number sequence;

Specifically, when the system number is not the number information ordered at the first bit in the number sequence, that is, it indicates that the system number is not currently ordered at the first bit of the first storage number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state, and wait for the system number to be ordered at the first bit in the first storage number sequence. Further, when the system number is ordered to the first place in the number sequence, the data transfer control device may send the target data to a subsystem corresponding to the system number, and then remove the system number from the first storage number sequence. The subsystem receives the target data, may perform data processing on the target data, where the data processing may include data logic operation, data compression, and the like, and the data transfer instruction may further include a data processing signal, where the data processing signal is used to instruct the data transfer control device to send the received target data to a subsystem corresponding to the system number, so as to perform corresponding data processing.

Fig. 15a is a schematic diagram of an example of data transfer in a data receiving state according to an embodiment of the present application. As shown in fig. 15a, the data transfer control device 30 acquires the target data corresponding to S1 and S1, that is, S1_ target data received by the source storage module, based on the data receiving channel, and the data transfer control device 30 may set the data transfer state of S1 as the data receiving state, and store S1 in the first storage number sequence; likewise, the data transfer controlling device 30 may set the data transfer state of S2 to the data reception state, and store S2 in the first storage number sequence.

Further, if the data migration control device 30 receives S1_ the target data received by the source storage module first and then receives S2_ the target data received by the source storage module, S1 is sorted at the first position and S2 is sorted at the second position in the first storage number sequence, otherwise S2 is sorted at the first position and S1 is sorted at the second position. As shown in fig. 15a, at this time, when the data transfer control device 30 first receives S2_ the target data received by the source storage module, the data transfer control device 30 may store S2 in the first bit of the first storage number sequence, may transmit S2_ the target data received by the source storage module to the subsystem 2 corresponding to S2, and the data transfer control device 30 may remove S2 from the first storage number sequence.

When the data migration control device 30 receives S1_ the target data received by the source storage module again, S1 may be stored in the first storage number sequence, at this time, if S2 is removed, S1 is converted into the first bit of the first storage number sequence, and the data migration control device 30 may send S1_ the target data received by the source storage module to the subsystem 1 corresponding to S1, and then remove S1 from the first storage number sequence; if S2 has not been removed, the data migration control device 30 may first cache the target data received from the source storage module in S1_ until S1 is converted into the first bit of the first storage number sequence, send the target data received from the source storage module in S1_ to the subsystem 1 corresponding to S1, and then remove S1 from the first storage number sequence.

In the embodiment of the application, when the data transfer state corresponding to the system number is in the data receiving state, the target data of different system numbers can be sequentially sent to the corresponding subsystems by the source storage module according to the first storage number sequence for data processing, decoupling of the data receiving channel is realized, the data receiving channel can independently perform the data receiving process, meanwhile, the system number is stored in the first storage number sequence according to the receiving sequence of the target data, the out-of-order receiving process of the target data is further realized, and the utilization rate of the data receiving channel is improved.

Fig. 16 is a schematic flow chart of data transfer in a data transfer state according to an embodiment of the present disclosure. As shown in fig. 16, the process may include:

s251, when the target data sent by the subsystem is acquired, setting the data transfer state as a data unloading state, acquiring a second storage number sequence corresponding to the data unloading state from a number sequence set, acquiring a system number corresponding to the subsystem, and storing the system number into the second storage number sequence;

specifically, the data receiving state may be used to indicate that the current execution stage is in a state of sending the destination storage address and the target data to a destination storage module when the target data sent by the subsystem is acquired. After the data processing is performed on the target data, the subsystem may send the target data after the data processing to a data transfer control device, where the data transfer control device may set a data transfer state corresponding to the system number from a data receiving state to a data unloading state, and when the data transfer state is the data unloading state, the data transfer control device may obtain, in a numbering sequence set, a second storage numbering sequence corresponding to the data unloading state, obtain a system number corresponding to the subsystem, and store the system number in the second storage numbering sequence.

S252, when the system number is the number information which is sequenced at the first position in the number sequence, a target storage address corresponding to the system number is obtained, the system number, the target data and the target storage address are sent to the target storage module, and the system number is removed from the second storage number sequence;

specifically, when the system number is the number information ordered at the first position in the number sequence, that is, the system number is currently ordered at the first position in the second storage number sequence, the data transfer control device may obtain a destination storage address corresponding to the system number in a cache, or request a subsystem corresponding to the system number to obtain the destination storage address, and the data transfer control device may send the system number, the target data after data processing, and the destination storage address to the destination storage module, and then remove the system number from the second storage number sequence. The system number and the target data can be sent through a data sending channel, and the target storage address can be sent through a target address transmission channel.

S253, when the system number is not the number information which is sequenced at the first position in the number sequence, suspending the data transfer operation indicated by the data transfer state, waiting for the system number to be sequenced at the first position in the number sequence, acquiring a target storage address corresponding to the system number, sending the system number, the target data and the target storage address to the target storage module, and removing the system number from the second storage number sequence;

specifically, when the system number is not the number information ordered at the first bit in the number sequence, that is, it indicates that the system number is not currently ordered at the first bit of the second storage number sequence, the data transfer control device may suspend the data transfer operation indicated by the data transfer state, and wait for the system number to be ordered at the first bit in the second storage number sequence. Further, when the system number is sorted to the first bit in the second storage number sequence, the data transfer control device may obtain a destination storage address corresponding to the system number in a cache, or request a subsystem corresponding to the system number to obtain the destination storage address, and the data transfer control device may send the system number, the target data after data processing, and the destination storage address to the destination storage module, and then remove the system number from the second storage number sequence. The system number and the target data can be sent through a data sending channel, and the target storage address can be sent through a target address transmission channel.

Referring to fig. 16a, an exemplary diagram of data transfer in a data dump state is provided for an embodiment of the present application. As shown in fig. 16a, after receiving the target data transmitted by S1_ to the destination storage module by the subsystem 1, the data transfer control device 50 may set the data transfer state of S1 to the data dump state, and store S1 in the second storage number sequence; likewise, the data transfer control device 50 may set the data transfer state of S2 to the data dump state, and store S2 into the second storage number sequence.

Further, if the data migration control device 50 receives the target data sent to the destination storage module in S1_ first and then receives the target data sent to the destination storage module in S2_ first, in the second storage number sequence, S1 is sorted in the first place and S2 is sorted in the second place, otherwise, S2 is sorted in the first place and S1 is sorted in the second place. As shown in fig. 16a, at this time, the data transfer control device 50 first receives the target data sent by S2_ to the destination storage module, and may synchronize with the data transfer control device 40, the data transfer control device 40 may obtain the cached or S2_ destination storage address transmitted by the subsystem 2, the data transfer control device 40 may control the destination address transmission channel to send the S2_ destination storage address to the destination storage module, the data transfer control device 50 may control the data transmission channel to transmit the target data sent by S2_ to the destination storage module, and the data transfer control device 50 may remove S2 from the second storage number sequence. The destination storage module may store the target data transmitted from S2_ to the destination storage module in the address space indicated by the destination storage address of S2_ destination storage module. It should be noted that, in S2_ the target data received by the source storage module is represented as the target data corresponding to S2 acquired by the source storage module, and in S2_ the target data sent to the destination storage module is represented as the target data received by the source storage module in S2_ after being subjected to data processing by the subsystem 2.

When the data migration control device 50 receives the target data sent to the destination storage module in S1 again, S1 may be stored in the second storage number sequence, at this time, if S2 is removed, S1 is converted to the first bit of the second storage number sequence, and the data migration control device 40 and the data migration control device 50 may send the storage addresses of S1 and S1_ and the target data sent to the destination storage module in S1_ to the destination storage module, and then remove S1 from the second storage number sequence; if S2 has not been removed, the data migration control device 50 may first cache the target data sent to the destination storage module in S1_ until S1 is converted into the first bit of the second storage number sequence, send the target storage addresses in S1 and S1_ and the target data sent to the destination storage module in S1_ and then remove S1 from the second storage number sequence. It should be noted that, in S1_ the target data received by the source storage module is represented as the target data corresponding to S1 acquired by the source storage module, and in S1_ the target data sent to the destination storage module is represented as the data processed by the subsystem 1 on the target data received by the source storage module in S1_ step.

In the embodiment of the application, when the data transfer state corresponding to the system number is in the data transfer state, the target data after data processing of the subsystems of different system numbers can be sequentially sent to the target storage module for storage according to the second storage number sequence, decoupling of the data sending channel is achieved, the process that the data sending channel can independently send data is guaranteed, meanwhile, the system number is stored into the second storage number sequence according to the receiving sequence of the target data after data processing, the out-of-order sending process of the target data and the target storage address is further achieved, and the utilization rate of the data sending channel is improved.

The data transfer control method provided in the embodiment of the present application will be described in detail below with reference to a specific example of fig. 17.

Fig. 17 is a schematic diagram illustrating an example of a data transfer control method according to an embodiment of the present application. As shown in fig. 17, the instruction sending module sends the data transfer instruction 1 to the data transfer control device 10, the data transfer control device 10 controls the instruction transmission channel to send the S1_ data transfer instruction to the subsystem 1, considering that the data transfer instruction 1 carries the system number of the subsystem 1, the data transfer instruction 1 may include the system number S1 and S1_ data transfer instruction of the subsystem 1, and when the system number S1 does not exist in the data transfer instruction 1, the data transfer instruction 1 is equal to the S1_ data transfer instruction.

The data transfer control device 20 receives the S1_ source storage address first, and the data transfer control device 20 may store S1 in the first bit of the instruction number sequence, may control the source address transmission channel to send the S1 and S1_ source storage address to the source storage module, and then removes S1 from the instruction number sequence. When the data migration control device 20 receives the S2_ source storage address again, S2 may be stored in the instruction number sequence, at this time, if S1 is removed, S2 is converted to the first bit of the instruction number sequence, and the data migration control device 20 may control the source address transmission channel to send the S2 and S2_ source storage address to the source storage module, and then remove S2 from the instruction number sequence; if S1 has not been removed, the data migration control device 20 may first cache the S2_ source storage address until S2 is converted to the first bit of the instruction number sequence, send the S2 and S2_ source storage address, and remove S2 from the instruction number sequence.

The data transfer control device 30 acquires the target data corresponding to S1 and S1, that is, S1_ target data received by the source storage module, based on the data receiving channel, and the data transfer control device 30 may set the data transfer state of S1 to the data receiving state, and store S1 in the first storage number sequence; likewise, the data transfer controlling device 30 may set the data transfer state of S2 to the data reception state, and store S2 in the first storage number sequence.

The data transfer control device 30 first receives S2_ the target data received by the source storage module, the data transfer control device 30 may store S2 in the first bit of the first storage number sequence, may transmit S2_ the target data received by the source storage module to the subsystem 2 corresponding to S2, and the data transfer control device 30 may remove S2 from the first storage number sequence.

When the data migration control device 30 receives S1_ the target data received by the source storage module again, S1 may be stored in the first storage number sequence, at this time, if S2 is removed, S1 is converted into the first bit of the first storage number sequence, and the data migration control device 30 may send S1_ the target data received by the source storage module to the subsystem 1 corresponding to S1, and then remove S1 from the first storage number sequence; if S2 has not been removed, the data migration control device 30 may first cache the target data received by the source storage module in S1_ until S1 is converted into the first bit of the first storage number sequence, send the target data received by the source storage module in S1_ to the subsystem 1 corresponding to S1, and then remove S1 from the first storage number sequence.

After receiving the target data transmitted to the destination storage module in S1_ transmitted by the subsystem 1, the data transfer control device 50 may set the data transfer state in S1 to be the data unloading state, and store S1 in the second storage number sequence; similarly, the data transfer control device 50 may set the data transfer state of S2 to the data dump state, and store S2 in the second storage number sequence.

The data transfer control device 50 receives the target data sent to the destination storage module in S2_ first, and may synchronize with the data transfer control device 40, the data transfer control device 40 may obtain the cached or S2_ destination storage address transmitted by the subsystem 2, the data transfer control device 40 may control the destination address transmission channel to send the S2_ destination storage address to the destination storage module, the data transfer control device 50 may control the data transmission channel to transmit the target data sent to the destination storage module in S2_ to the destination storage module, and the data transfer control device 50 may remove S2 from the second storage number sequence. The destination storage module may store the target data transmitted from S2_ to the destination storage module in the address space indicated by the S2_ destination storage address. It should be noted that, in S2_ the target data received by the source storage module is represented as the target data corresponding to S2 acquired by the source storage module, and in S2_ the target data sent to the destination storage module is represented as the target data received by the source storage module in S2_ after being subjected to data processing by the subsystem 2.

The data transfer control device 60 acquires the S1_ response signals corresponding to the system numbers S1 and S1 based on the storage response channel, and the data transfer control device 60 may set the data transfer state of S1 to the storage response state, and store S1 in the response number sequence; likewise, the data transfer controlling device 60 may set the data transfer state of S2 to the data storage state and store S2 in the response number sequence.

The data transfer control device 60 receives the S2_ response signal first, the data transfer control device 60 may store S2 in the first bit of the response number sequence, may transmit the S2_ response signal to the subsystem 2 corresponding to S2, and the data transfer control device 60 may remove S2 from the response number sequence. The subsystem 2 may transmit an S2_ response signal to the data migration control device 10, the data migration control device 10 controls the instruction transmission channel to receive the S2_ response signal, and transmits the response signal 2 to the instruction transmission module in response to the data migration instruction 2, and considering that the S2_ response signal does not carry the system number S2 of the subsystem 2, the data migration control device 10 may package the S2 and S2_ response signals as the response signal 2 to be transmitted to the instruction transmission module, and when the system number S2 exists in the S2_ response signal, the response signal 2 is equal to the S2_ response signal.

It should be noted that the two data transfer processing procedures of the DMA module and the information receiving sequence of S1 and S2 shown in the embodiment of the present application are only examples, and for more than two data transfer processing procedures, the detailed description of the above embodiment may also be referred to for implementation.

In the embodiment of the present application, an execution phase of a data transfer process of current target data may be obtained by obtaining a data transfer state corresponding to target data processed by a subsystem in a DMA module, and then a numbering sequence corresponding to the data transfer state is used to store a system number of a subsystem in the numbering sequence, so as to ensure that a system number entering the data transfer state first can be stored in the numbering sequence first, which indicates that the system number can perform a data transfer operation indicated by the data transfer state first on a channel in the current data transfer state, and for a system number that is not the first in the numbering sequence, the current data transfer operation needs to be suspended for waiting until the system number is ordered in the first place in the numbering sequence, so that the channel can be opened to perform the data transfer operation indicated by the current data transfer state, and when the data transfer operation is performed, and the system number is removed from the numbering sequence, so that decoupling of the channels is realized, and independent data transfer operation of each channel is ensured, meanwhile, the system number is stored in the numbering sequence according to the information receiving sequence, namely, the system number of the numbering sequence is firstly entered, the data transfer operation indicated by the data transfer state of the system number can be preferentially executed, the out-of-order execution process of data transfer is realized, the waiting time of each system number in the execution of the data transfer process is reduced, the channel utilization rate is improved, and the data transfer efficiency is further improved.

Referring to fig. 18-20, there are shown timing diagrams of executing channels in a DMA according to an embodiment of the present application, in which fig. 18 shows timing diagrams of executing channels in a DMA according to the prior art; FIG. 19 shows an execution timing diagram for each channel in an order-preserving DMA; fig. 20 shows an execution timing diagram of each channel in the out-of-order DMA, it should be noted that the timing diagrams of the two data transfer processing procedures shown in fig. 18-20 and the information receiving sequence of S1 and S2 are only examples, and the detailed description of the above embodiments can be referred to for more than two data transfer processing procedures.

As shown in fig. 18, the multiple channels in the prior art have timing dependencies, and therefore, the multiple channels are released for performing the data transfer process of S2 only after the data transfer process of S1 is completed, and since each channel is called according to the execution sequence of the data transfer, each channel is in an idle state most of the time, such as an instruction transfer channel, and the instruction transfer channel is in an idle state after sending the S1_ data transfer instruction to the subsystem, and can not execute the transfer of the S2_ data transfer instruction until the memory response channel receives the response signal. Therefore, the prior art influences the channel utilization rate and the data transfer efficiency.

As shown in fig. 19, the multiple channels shown in fig. 19 may complete the data transfer process indicated by each data transfer instruction in turn according to the sending order of the data transfer instruction, for example: if the S1_ data transfer instruction is received first, information transmission related to S1 in each channel needs to be prioritized by S1, and in the embodiment of the present application, on the basis of sequential execution, multiple channels are decoupled, so that each channel can independently execute a corresponding data transfer operation, and on the basis of ensuring the execution sequence of each data transfer instruction, the channel utilization rate is improved, and thus the data transfer efficiency is improved.

As shown in fig. 20, each of the plurality of channels shown in fig. 20 may complete the corresponding data transfer operation according to the information receiving sequence, for example: in the instruction transmission channel, although the S1_ data transfer instruction is transmitted in preference to the S2_ data transfer instruction, in the data receiving channel, the target data received by the S2_ source storage module can be returned in preference to the target data received by the S1_ source storage module, and can be preferentially executed, so that the out-of-order execution process of data transfer is realized, the waiting time of each channel when the data transfer operation is executed is further reduced, the channel utilization rate is improved, and the efficiency of data transfer is further improved.

Based on the system architecture of fig. 1, the data transfer control device provided in the embodiment of the present application will be described in detail below with reference to fig. 21 to fig. 23. It should be noted that, the data transfer control apparatus shown in fig. 21-23 is used for executing the method of the embodiment shown in fig. 2-10 of the present application, and for convenience of description, only the portion related to the embodiment of the present application is shown, and details of the specific technology are not disclosed, please refer to the embodiment shown in fig. 2-10 of the present application.

Referring to fig. 21, a schematic structural diagram of a data transfer control device is provided in an embodiment of the present application. As shown in fig. 21, the data transfer control device 1 according to the embodiment of the present application may include: a status acquisition unit 11, a number information acquisition unit 12, and a data operation unit 13.

A state obtaining unit 11, configured to obtain a data transfer state corresponding to target data processed by a subsystem, where the data transfer state is used to indicate an execution stage in a data transfer process of the target data;

a number information obtaining unit 12, configured to obtain a number sequence corresponding to the data transfer state from a number sequence set, and obtain number information ordered at a first position from the number sequence;

A data operation unit 13, configured to, when the number information is a system number corresponding to the subsystem, perform a data transfer operation indicated by the data transfer state, and remove the system number from the number sequence;

the data operation unit 13 is further configured to suspend the data transfer operation indicated by the data transfer state when the number information is not the system number corresponding to the subsystem, wait for the system number to be sorted to the first place in the number sequence, execute the data transfer operation indicated by the data transfer state, and remove the system number from the number sequence.

Optionally, the number information obtaining unit 12 is specifically configured to, when the data transfer state is an address release state, obtain an instruction number sequence corresponding to the address release state in a number sequence set, and obtain number information ordered at a first position in the instruction number sequence;

the data operation unit 13 is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, specifically, is configured to obtain storage address information corresponding to the system number, where the storage address information is a source storage address and a destination storage address of target data obtained after the subsystem parses a data transfer instruction;

And sending the source storage address to a source storage module, and removing the system number from the instruction number sequence.

Optionally, the number information acquiring unit 12 is specifically configured to, when the data transfer state is a data storage state, acquire a storage number sequence corresponding to the data storage state from a number sequence set, and acquire the number information ordered at the first bit from the storage number sequence;

the data operation unit 13 is configured to execute a data transfer operation indicated by the data transfer status, and when the system number is removed from the number sequence, specifically, the data operation unit is configured to transfer target data from a source storage address of a source storage module to a destination storage address of the destination storage module based on the system number, and remove the system number from the storage number sequence.

Optionally, the number information obtaining unit 12 is specifically configured to receive, when the data transfer state is a data receiving state, target data returned by the source storage module based on the source storage address;

acquiring a first storage serial number sequence corresponding to the data receiving state in a serial number sequence set, and acquiring serial number information sequenced in a first position in the first storage serial number sequence;

The data operation unit 13 is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, is specifically configured to send the target data to a subsystem corresponding to the system number, and remove the system number from the first storage number sequence.

Optionally, the number information obtaining unit 12 is specifically configured to, when the data transfer state is a data unloading state, obtain a second storage number sequence corresponding to the data unloading state in a number sequence set, and obtain number information ordered at a first position in the second storage number sequence;

the data operation unit 13 is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, the data operation unit is specifically configured to acquire the target data sent by the subsystem, send the target storage address and the target data to a target storage module, and remove the system number from the second storage number sequence.

Optionally, the number information obtaining unit 12 is specifically configured to, when the data transfer state is a storage response state, obtain a response number sequence corresponding to the data storage state from a number sequence set, and obtain the number information ordered at the first bit from the response number sequence;

The data operation unit 13 is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, specifically, is configured to return a response signal to the subsystem corresponding to the system number, and remove the system number from the response number sequence, where the response signal is a response signal returned by the target storage module after storing the target data.

Referring to fig. 22, a schematic structural diagram of a data transfer control device is provided in an embodiment of the present application. As shown in fig. 22, the data transfer control apparatus 1 according to the embodiment of the present application may include: a status acquisition unit 11, a number information acquisition unit 12, a data operation unit 13, a system number acquisition unit 14, and a first number storage unit 15.

The system number acquiring unit 14 is configured to acquire a system number corresponding to the subsystem when the instruction sending module sends the data transfer instruction to the subsystem;

a first number storage unit 15, configured to store the system numbers to the same ordering position in each number sequence of a number sequence set, where the number sequence set includes an instruction number sequence, a storage number sequence, and a response number sequence;

in the embodiment of the application, by acquiring the data transfer state corresponding to the target data processed by the subsystem in the DMA module, the execution stage of the data transfer process of the current target data can be acquired, and then the system number corresponding to the subsystem matched with the number information can be acquired through the number information which is ordered at the first position and indicated by the number sequence corresponding to the data transfer state, and then the channel in the current data transfer state can be controlled to execute the data transfer operation process of the subsystem indicated by the system number for the target data, for the number information which is not the first bit in the number sequence, the current data transfer operation needs to be suspended and wait until the system number becomes the number information which is ordered at the first bit in the number sequence, and the channel can be opened to execute the data transfer operation indicated by the current data transfer state. By setting different numbering sequences in different data transfer states, each channel can execute the data transfer operation of corresponding target data according to the system number indicated by the numbering sequence, a complete data transfer process can be divided into the data transfer operations corresponding to a plurality of data transfer states by the numbering sequence set, and the data transfer operations of the system numbers can be sequentially executed according to the arrangement sequence of the system numbers in the numbering sequence in the same data transfer state, so that the decoupling of the channels is realized, the data transfer operation can be independently carried out by each channel, meanwhile, the system numbers are pre-stored at the same ordering position in each numbering sequence of the numbering sequence set when a data transfer instruction is sent, namely, the system numbers are arranged according to the same arrangement sequence of the system codes in each data transfer state, and corresponding data transfer operation is executed, so that the channel utilization rate is improved on the basis of ensuring the execution sequence of each data transfer instruction, and the data transfer efficiency is further improved.

Referring to fig. 23, a schematic structural diagram of a data transfer control device is provided in an embodiment of the present application. As shown in fig. 23, the data transfer control apparatus 1 according to the embodiment of the present application may include: a status acquisition unit 11, a number information acquisition unit 12, a data operation unit 13, and a second number storage unit 16.

a data operation unit 13, configured to, when the number information is a system number corresponding to the subsystem, execute a data transfer operation indicated by the data transfer state, and remove the system number from the number sequence;

a second number storage unit 16 for storing the system number in a sequence next to the number sequence;

the next sequence is a sequence after the numbering sequence in a numbering sequence set according to the conversion sequence of the data transfer state, wherein the numbering sequence set comprises an instruction numbering sequence, a storage numbering sequence and a response numbering sequence.

In the embodiment of the application, by acquiring the data transfer state corresponding to the target data processed by the subsystem in the DMA module, the execution stage of the data transfer process of the current target data can be acquired, and then the system number corresponding to the subsystem matched with the number information can be acquired through the number information which is ordered at the first position and indicated by the number sequence corresponding to the data transfer state, and then the channel in the current data transfer state can be controlled to execute the data transfer operation process of the subsystem indicated by the system number for the target data, for the number information which is not the first bit in the number sequence, the current data transfer operation needs to be suspended and wait until the system number becomes the number information which is ordered at the first bit in the number sequence, and the channel can be opened to execute the data transfer operation indicated by the current data transfer state. By setting different numbering sequences in different data transfer states, each channel can execute the data transfer operation of corresponding target data according to the system number indicated by the numbering sequence, a complete data transfer process can be divided into the data transfer operations corresponding to a plurality of data transfer states by a numbering sequence set, and the data transfer operations of the system numbers can be sequentially executed according to the arrangement sequence of the system numbers in the numbering sequence in the same data transfer state, so that the decoupling of the channels is realized, the data transfer operation can be independently carried out for each channel, meanwhile, when the current data transfer operation is executed, the system number is removed from the current numbering sequence and stored in the next sequence, therefore, when the current data transfer operation is executed and enters the next data transfer state, the system number still keeps the sequencing position in the current numbering sequence before elimination in the next sequence, and on the basis of ensuring the execution sequence of each data transfer instruction, the channel utilization rate is improved, and the data transfer efficiency is further improved.

Referring to fig. 24, a schematic structural diagram of a computer device is provided according to an embodiment of the present application. As shown in fig. 24, the computer apparatus 1000 may include: at least one processor 1001, such as a CPU, at least one network interface 1004, input output interfaces 1003, memory 1005, at least one communication bus 1002. Wherein a communication bus 1002 is used to enable connective communication between these components. The network interface 1004 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface), among others. The memory 1005 may be a high-speed RAM memory or a non-volatile memory (non-volatile memory), such as at least one disk memory. The memory 1005 may optionally be at least one memory device located remotely from the processor 1001. As shown in fig. 24, a memory 1005, which is a kind of computer storage medium, may include therein an operating system, a network communication module, an input-output interface module, and a transfer control application program.

In the computer device 1000 shown in fig. 24, the input/output interface 1003 is mainly used as an interface for providing input for the user and the access device, and acquiring data input by the user and the access device.

In one embodiment, processor 1001 may be configured to invoke a transfer control application stored in memory 1005 and specifically perform the following operations:

wherein the system numbers are respectively stored at the same sequencing position in each numbering sequence of the numbering sequence set.

Optionally, before executing the data transition state corresponding to the target data processed by the acquisition subsystem, the processor 1001 further executes the following operations:

when the instruction sending module sends a data transfer instruction to a subsystem, acquiring a system number corresponding to the subsystem;

and respectively storing the system numbers to the same sequencing position in each number sequence of a number sequence set, wherein the number sequence set comprises an instruction number sequence, a storage number sequence and a response number sequence.

Optionally, after executing the data transfer operation indicated by the data transfer state and removing the system number from the number sequence, the processor 1001 further executes the following operations:

storing the system number into a next sequence of the number sequence;

Optionally, when the processor 1001 acquires a number sequence corresponding to the data transfer state from a number sequence set and acquires number information ordered in a first bit from the number sequence, the following operation is specifically performed:

When the data transfer state is an address release state, acquiring an instruction number sequence corresponding to the address release state from a number sequence set, and acquiring number information ordered at a first position from the instruction number sequence;

when the processor 1001 executes the data transfer operation indicated by the data transfer state and removes the system number from the number sequence, the following operation is specifically executed:

acquiring storage address information corresponding to the system number, wherein the storage address information is a source storage address and a target storage address which are obtained by analyzing a data transfer instruction by the subsystem and aim at target data;

when the data transfer state is a data storage state, acquiring a storage number sequence corresponding to the data storage state from a number sequence set, and acquiring number information ordered at a first position from the storage number sequence;

and transferring the target data from the source storage address of the source storage module to the destination storage address of the destination storage module based on the system number, and removing the system number from the storage number sequence.

when the data transfer state is a data receiving state, receiving target data returned by the source storage module based on the source storage address;

And sending the target data to a subsystem corresponding to the system number, and removing the system number from the first storage number sequence.

when the data transfer state is a data transfer state, acquiring a second storage number sequence corresponding to the data transfer state from a number sequence set, and acquiring number information ordered at a first position from the second storage number sequence;

when the processor 1001 executes the data transfer operation indicated by the data transfer state and removes the system number from the number sequence, the following operations are specifically executed:

and acquiring the target data sent by the subsystem, sending the target storage address and the target data to a target storage module, and removing the system number from the second storage number sequence.

When the data transfer state is a storage response state, acquiring a response number sequence corresponding to the data storage state from a number sequence set, and acquiring number information ordered at a first position from the response number sequence;

optionally, when the processor 1001 executes the data transfer operation indicated by the data transfer state and removes the system number from the number sequence, the following operation is specifically executed:

and returning a response signal to the subsystem corresponding to the system number, and removing the system number from the response number sequence, wherein the response signal is a response signal returned by the target storage module after the target data is stored.

In the embodiment of the application, by acquiring the data transfer state corresponding to the target data processed by the subsystem in the DMA module, the execution stage of the data transfer process of the current target data can be acquired, and then the system number corresponding to the subsystem matched with the number information can be acquired through the number information which is ordered at the first position and indicated by the number sequence corresponding to the data transfer state, and then the channel in the current data transfer state can be controlled to execute the data transfer operation process of the subsystem indicated by the system number for the target data, for the number information not in the first order in the number sequence, the current data transfer operation needs to be suspended for waiting until the system number becomes the number information in the first order in the number sequence, and the channel can be opened to execute the data transfer operation indicated by the current data transfer state. By setting different numbering sequences in different data transfer states, each channel can execute the data transfer operation of corresponding target data according to the system number indicated by the numbering sequence, a complete data transfer process can be divided into the data transfer operations corresponding to a plurality of data transfer states by the numbering sequence set, and the data transfer operations of the system numbers can be sequentially executed according to the arrangement sequence of the system numbers in the numbering sequence in the same data transfer state, so that the decoupling of the channels is realized, the data transfer operation can be independently carried out by each channel, meanwhile, the system numbers are stored at the same ordering position in each numbering sequence of the numbering sequence set, namely, the corresponding data transfer operation can be executed according to the arrangement sequence of the same system code in each data transfer state, on the basis of ensuring the execution sequence of each data transfer instruction, the channel utilization rate is improved, and the data transfer efficiency is further improved.

Based on the system architecture of fig. 1, the data transfer control device provided in the embodiment of the present application will be described in detail below with reference to fig. 25. It should be noted that, the data transfer control device in fig. 25 is used for executing the method of the embodiment shown in fig. 11-17 of the present application, and for convenience of description, only the portion related to the embodiment of the present application is shown, and details of the specific technology are not disclosed, please refer to the embodiment shown in fig. 11-17 of the present application.

Referring to fig. 25, a schematic structural diagram of a data transfer control device is provided in an embodiment of the present application. As shown in fig. 25, the data transfer control device 2 according to the embodiment of the present application may include: a number storage unit 21 and a data operation unit 22.

A number storage unit 21, configured to acquire a data transfer state corresponding to target data processed by a subsystem, acquire a number sequence corresponding to the data transfer state from a number sequence set, and store a system number corresponding to the subsystem into the number sequence, where the data transfer state is used to indicate an execution stage in a data transfer process of the target data;

a data operation unit 22, configured to, when the system number is number information ordered at the first position in the number sequence, perform a data transfer operation indicated by the data transfer state, and remove the system number from the number sequence;

The data operation unit 22 is further configured to suspend the data transfer operation indicated by the data transfer state when the system number is not the number information ordered at the first bit in the number sequence, wait for the system number ordered at the first bit in the number sequence, execute the data transfer operation indicated by the data transfer state, and remove the system number from the number sequence.

Optionally, the number storage unit 21 is specifically configured to, when a system number corresponding to the subsystem and storage address information corresponding to the system number, which are sent by the subsystem, are obtained, set the data transfer state to an address release state, obtain an instruction number sequence corresponding to the address release state in a number sequence set, and store the system number in the instruction number sequence, where the storage address information is a source storage address and a destination storage address of target data obtained after the subsystem parses a data transfer instruction;

the data operation unit 22 is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, specifically, is configured to send the system number and the source storage address to a source storage module, and remove the system number from the instruction number sequence.

Optionally, the number storage unit 21 is specifically configured to, when the target data and the system number sent by the source storage module are obtained, set the data transfer state to be a data storage state, obtain a storage number sequence corresponding to the data storage state in a number sequence set, and store the system number in the storage number sequence;

the data operation unit 22 is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, the data operation unit is specifically configured to obtain a destination storage address corresponding to the system number, send the system number, the target data, and the destination storage address to the destination storage module, and remove the system number from the storage number sequence.

Optionally, the number storage unit 21 is specifically configured to, when the target data and the system number sent by the source storage module are obtained, set the data transfer state to be a data extraction state, obtain a first storage number sequence corresponding to the data extraction state in a number sequence set, and store the system number in the first storage number sequence;

The data operation unit 22 is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, is specifically configured to send the target data to a subsystem corresponding to the system number, and remove the system number from the first storage number sequence.

Optionally, the number storage unit 21 is specifically configured to, when the target data sent by the subsystem is obtained, set the data transfer state to a data unloading state, obtain a second storage number sequence corresponding to the data unloading state from a number sequence set, obtain a system number corresponding to the subsystem, and store the system number into the second storage number sequence;

the data operation unit 22 is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, the data operation unit is specifically configured to obtain a destination storage address corresponding to the system number, send the system number, the target data, and the destination storage address to the destination storage module, and remove the system number from the second storage number sequence.

Optionally, the number storage unit 21 is specifically configured to, when the system code and the response signal sent by the destination storage module are obtained, set the data transfer state to a storage response state, obtain a response number sequence corresponding to the data storage state in a number sequence set, and store the system code in the response number sequence, where the response signal is a response signal corresponding to the system code returned by the destination storage module after storing the target data;

the data operation unit 22 is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, specifically, is configured to return a response signal to the subsystem corresponding to the system number, and remove the system number from the response number sequence.

Referring to fig. 24, a schematic structural diagram of a computer device is provided according to an embodiment of the present application. As shown in fig. 24, the computer device 2000 may include: at least one processor 2001, e.g., a CPU, at least one network interface 2004, input output interface 2003, memory 2005, at least one communication bus 2002. The communication bus 2002 is used to implement connection communication between these components. The network interface 2004 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface), among others. Memory 2005 may be a high-speed RAM memory or a non-volatile memory (e.g., at least one disk memory). The memory 2005 may optionally also be at least one memory device located remotely from the aforementioned processor 2001. As shown in fig. 24, the memory 2005 as one type of computer storage medium may include therein an operating system, a network communication module, an input-output interface module, and a transfer control application program.

In the computer device 2000 shown in fig. 24, the input/output interface 2003 is mainly used as an interface for providing input to the user and the access device, and acquiring data input by the user and the access device.

In one embodiment, the processor 2001 may be configured to invoke the transfer control application stored in the memory 2005 and specifically perform the following operations:

acquiring a data transfer state corresponding to target data processed by a subsystem, acquiring a numbering sequence corresponding to the data transfer state from a numbering sequence set, and storing a system number corresponding to the subsystem into the numbering sequence, wherein the data transfer state is used for representing an execution stage in a data transfer process of the target data;

Optionally, when the processor 2001 executes to acquire a data transfer state corresponding to target data processed by a subsystem, acquires a number sequence corresponding to the data transfer state from a number sequence set, and stores a system number corresponding to the subsystem into the number sequence, the following operations are specifically executed:

When a system number corresponding to the subsystem and storage address information corresponding to the system number, which are sent by the subsystem, are acquired, the data transfer state is set to be an address release state, an instruction number sequence corresponding to the address release state is acquired from a number sequence set, the system number is stored in the instruction number sequence, and the storage address information is a source storage address and a destination storage address, which are obtained after the subsystem analyzes a data transfer instruction, for target data;

when the processor 2001 executes the data transfer operation indicated by the data transfer state and removes the system number from the number sequence, the following operations are specifically executed:

and sending the system number and the source storage address to a source storage module, and removing the system number from the instruction number sequence.

When target data and the system number sent by the source storage module are acquired, setting the data transfer state as a data storage state, acquiring a storage number sequence corresponding to the data storage state from a number sequence set, and storing the system number into the storage number sequence;

and acquiring a target storage address corresponding to the system number, sending the system number, the target data and the target storage address to the target storage module, and removing the system number from the storage number sequence.

when target data and the system number sent by the source storage module are acquired, setting the data transfer state as a data extraction state, acquiring a first storage number sequence corresponding to the data extraction state from a number sequence set, and storing the system number into the first storage number sequence;

when the target data sent by the subsystem is acquired, setting the data transfer state as a data unloading state, acquiring a second storage number sequence corresponding to the data unloading state from a number sequence set, acquiring a system number corresponding to the subsystem, and storing the system number into the second storage number sequence;

And acquiring a destination storage address corresponding to the system number, sending the system number, the target data and the destination storage address to the destination storage module, and removing the system number from the second storage number sequence.

when the system code and the response signal sent by the target storage module are acquired, setting the data transfer state as a storage response state, acquiring a response number sequence corresponding to the data storage state from a number sequence set, and storing the system code into the response number sequence, wherein the response signal is a response signal corresponding to the system code returned by the target storage module after the target data is stored;

And returning a response signal to the subsystem corresponding to the system number, and removing the system number from the response number sequence.

An embodiment of the present application further provides a computer storage medium, where the computer storage medium may store a plurality of program instructions, where the program instructions are suitable for being loaded by a processor and executing the method steps in the embodiments shown in fig. 2 to 17, and a specific execution process may refer to specific descriptions of the embodiments shown in fig. 2 to 17, which is not described herein again.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.

The above disclosure is only for the purpose of illustrating the preferred embodiments of the present application and is not to be construed as limiting the scope of the present application, so that the present application is not limited thereto, and all equivalent variations and modifications can be made to the present application.

Claims

1. A data transfer control method is applied to direct memory access DMA, and is characterized by comprising the following steps:

2. The method of claim 1, wherein before obtaining the data transition state corresponding to the target data processed by the subsystem, further comprising:

3. The method of claim 1, wherein after the performing the data transfer operation indicated by the data transfer status and removing the system number from the number sequence, further comprises:

storing the system number into a next sequence of the number sequence;

4. The method according to claim 1, wherein the obtaining the number sequence corresponding to the data transition state in the number sequence set and the number information ordered at the first bit in the number sequence comprises:

the executing the data transfer operation indicated by the data transfer state and removing the system number from the number sequence comprises:

5. The method according to claim 4, wherein the obtaining the number sequence corresponding to the data transition state in the number sequence set and the number information ordered at the first bit in the number sequence comprises:

6. The method according to claim 4, wherein the obtaining the number sequence corresponding to the data transition state in the number sequence set and the number information ordered at the first bit in the number sequence comprises:

7. The method according to claim 6, wherein the obtaining the number sequence corresponding to the data transition state in the number sequence set and the number information ordered at the first bit in the number sequence comprises:

8. The method according to claim 5 or 7, wherein the obtaining of the number sequence corresponding to the data transition state in the number sequence set and the obtaining of the number information ordered at the first bit in the number sequence comprises:

9. A data transfer control method is applied to DMA, and is characterized by comprising the following steps:

10. The method according to claim 9, wherein the obtaining a data transition state corresponding to target data processed by a subsystem, obtaining a numbering sequence corresponding to the data transition state from a numbering sequence set, and storing a system number corresponding to the subsystem into the numbering sequence comprises:

when a system number corresponding to the subsystem and storage address information corresponding to the system number, which are sent by the subsystem, are acquired, the data transfer state is set to be an address release state, an instruction number sequence corresponding to the address release state is acquired from a number sequence set, the system number is stored in the instruction number sequence, and the storage address information is a source storage address and a destination storage address, which are obtained after the subsystem analyzes a data transfer instruction and are aimed at target data;

11. The method according to claim 10, wherein the obtaining a data transition state corresponding to target data processed by the subsystem, obtaining a numbering sequence corresponding to the data transition state from a numbering sequence set, and storing a system number corresponding to the subsystem into the numbering sequence comprises:

12. The method according to claim 10, wherein the obtaining a data transition state corresponding to target data processed by the subsystem, obtaining a numbering sequence corresponding to the data transition state from a numbering sequence set, and storing a system number corresponding to the subsystem into the numbering sequence comprises:

13. The method according to claim 12, wherein the obtaining of the data transition state corresponding to the target data processed by the subsystem, obtaining the numbering sequence corresponding to the data transition state from the numbering sequence set, and storing the system number corresponding to the subsystem into the numbering sequence comprises:

14. The method according to claim 11 or 13, wherein the acquiring a data transition state corresponding to target data processed by the subsystem, acquiring a numbering sequence corresponding to the data transition state from a numbering sequence set, and storing a system number corresponding to the subsystem into the numbering sequence comprises:

15. A data transfer control apparatus applied to a DMA, comprising:

a number information acquiring unit, configured to acquire a number sequence corresponding to the data transfer state in a number sequence set, and acquire number information ordered at a first position in the number sequence;

the data operation unit is used for executing the data transfer operation indicated by the data transfer state and removing the system number from the number sequence when the number information is the system number corresponding to the subsystem;

16. The apparatus of claim 15, further comprising:

the system number acquisition unit is used for acquiring a system number corresponding to the subsystem when the instruction sending module sends a data transfer instruction to the subsystem;

the first number storage unit is used for respectively storing the system numbers to the same sequencing position in each number sequence of a number sequence set, and the number sequence set comprises an instruction number sequence, a storage number sequence and a response number sequence.

17. The apparatus of claim 15, further comprising:

a second number storage unit configured to store the system number in a sequence next to the number sequence;

18. The apparatus according to claim 15, wherein the number information obtaining unit is specifically configured to, when the data transfer state is an address release state, obtain an instruction number sequence corresponding to the address release state in a number sequence set, and obtain number information ordered at a first bit in the instruction number sequence;

The data operation unit is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, the data operation unit is specifically configured to obtain storage address information corresponding to the system number, where the storage address information is a source storage address and a destination storage address of target data obtained after the subsystem parses a data transfer instruction;

19. The apparatus according to claim 18, wherein the number information obtaining unit is specifically configured to, when the data transition state is a data storage state, obtain a storage number sequence corresponding to the data storage state in a number sequence set, and obtain number information ordered at a first bit in the storage number sequence;

the data operation unit is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, the data operation unit is specifically configured to transfer target data from a source storage address of a source storage module to a destination storage address of the destination storage module based on the system number, and remove the system number from the storage number sequence.

20. The device according to claim 18, wherein the number information obtaining unit is specifically configured to receive, when the data transfer state is a data receiving state, target data returned by the source storage module based on the source storage address;

acquiring a first storage serial number sequence corresponding to the data receiving state from a serial number sequence set, and acquiring serial number information sequenced at a first position from the first storage serial number sequence;

the data operation unit is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, the data operation unit is specifically configured to send the target data to a subsystem corresponding to the system number, and remove the system number from the first storage number sequence.

21. The apparatus according to claim 20, wherein the number information obtaining unit is specifically configured to, when the data transfer state is a data unloading state, obtain a second storage number sequence corresponding to the data unloading state in a number sequence set, and obtain the number information ordered at a first bit in the second storage number sequence;

The data operation unit is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, the data operation unit is specifically configured to acquire the target data sent by the subsystem, send the target storage address and the target data to a target storage module, and remove the system number from the second storage number sequence.

22. The apparatus according to claim 19 or 21, wherein the number information obtaining unit is specifically configured to, when the data transition state is a storage response state, obtain a response number sequence corresponding to the data storage state in a number sequence set, and obtain number information ordered at a first bit in the response number sequence;

the data operation unit is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, the data operation unit is specifically configured to return a response signal to the subsystem corresponding to the system number, and remove the system number from the response number sequence, where the response signal is a response signal returned by the destination storage module after the destination storage module stores the target data.

23. A data transfer control apparatus applied to a DMA, comprising:

the system comprises a number storage unit, a number sequence collection unit and a data transfer unit, wherein the number storage unit is used for acquiring a data transfer state corresponding to target data processed by a subsystem, acquiring a number sequence corresponding to the data transfer state from the number sequence collection, and storing a system number corresponding to the subsystem into the number sequence, and the data transfer state is used for representing an execution stage in a data transfer process of the target data;

the data operation unit is used for executing the data transfer operation indicated by the data transfer state and removing the system number from the numbering sequence when the system number is the number information sequenced at the first position in the numbering sequence;

24. The apparatus according to claim 23, wherein the number storage unit is specifically configured to, when acquiring a system number corresponding to the subsystem and storage address information corresponding to the system number, which are sent by the subsystem, set the data transfer state to an address release state, acquire an instruction number sequence corresponding to the address release state from a number sequence set, and store the system number into the instruction number sequence, where the storage address information is a source storage address and a destination storage address for target data, which are obtained after the subsystem parses a data transfer instruction;

the data operation unit is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, the data operation unit is specifically configured to send the system number and the source storage address to a source storage module, and remove the system number from the instruction number sequence.

25. The apparatus according to claim 24, wherein the number storage unit is specifically configured to, when the target data and the system number sent by the source storage module are obtained, set the data transfer state to a data storage state, obtain a storage number sequence corresponding to the data storage state in a number sequence set, and store the system number in the storage number sequence;

The data operation unit is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, the data operation unit is specifically configured to obtain a destination storage address corresponding to the system number, send the system number, the target data, and the destination storage address to the destination storage module, and remove the system number from the storage number sequence.

26. The apparatus according to claim 24, wherein the number storage unit is specifically configured to, when the target data and the system number sent by the source storage module are obtained, set the data transfer state to a data extraction state, obtain a first storage number sequence corresponding to the data extraction state in a number sequence set, and store the system number in the first storage number sequence;

27. The device according to claim 26, wherein the number storage unit is specifically configured to, when the target data sent by the subsystem is acquired, set the data transfer state to a data dump state, acquire a second storage number sequence corresponding to the data dump state in a number sequence set, acquire a system number corresponding to the subsystem, and store the system number in the second storage number sequence;

the data operation unit is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, the data operation unit is specifically configured to obtain a destination storage address corresponding to the system number, send the system number, the target data, and the destination storage address to the destination storage module, and remove the system number from the second storage number sequence.

28. The apparatus according to claim 25 or 27, wherein the number storage unit is specifically configured to, when the system code and the response signal sent by the destination storage module are acquired, set the data transfer state to a storage response state, acquire a response number sequence corresponding to the data storage state in a number sequence set, and store the system code in the response number sequence, where the response signal is a response signal corresponding to the system number returned by the destination storage module after storing the target data;

The data operation unit is configured to execute a data transfer operation indicated by the data transfer state, and when the system number is removed from the number sequence, specifically, is configured to return a response signal to the subsystem corresponding to the system number, and remove the system number from the response number sequence.

29. A computer device comprising a processor, a memory, an input output interface;

the processor is connected to the memory and the input/output interface, respectively, wherein the input/output interface is used for page interaction, the memory is used for storing program code, and the processor is used for calling the program code to execute the method according to any one of claims 1-8 or the method according to any one of claims 9-14.

30. A computer storage medium, characterized in that the computer storage medium stores a computer program comprising program instructions that, when executed by a processor, perform the method of any of claims 1-8 or the method of any of claims 9-14.