CN114490357A - Method and device for generating verification sequence and verification method of function coverage rate - Google Patents

Method and device for generating verification sequence and verification method of function coverage rate Download PDF

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Publication number
CN114490357A
CN114490357A CN202210028932.1A CN202210028932A CN114490357A CN 114490357 A CN114490357 A CN 114490357A CN 202210028932 A CN202210028932 A CN 202210028932A CN 114490357 A CN114490357 A CN 114490357A
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command
commands
database
verification sequence
sequence
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叶子健
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3668—Software testing
    • G06F11/3672—Test management
    • G06F11/3676—Test management for coverage analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/20—Information retrieval; Database structures therefor; File system structures therefor of structured data, e.g. relational data
    • G06F16/21—Design, administration or maintenance of databases
    • G06F16/211—Schema design and management

Abstract

The embodiment of the disclosure relates to the field of semiconductor test, and provides a method and a device for generating a verification sequence and a method for verifying functional coverage rate, wherein the method for generating the verification sequence comprises the following steps: setting the number of commands of the verification sequence as N; building a database, wherein the database comprises a plurality of commands, and the commands are commands required in a verification sequence; randomly picking out N commands from a database in sequence; and checking the N commands, and if the N commands are qualified, generating a verification sequence. The embodiment of the disclosure is at least beneficial to improving the comprehensiveness of the generated verification sequence, avoiding the error-prone and fussy of manually writing the verification sequence and being beneficial to improving the efficiency of generating the verification sequence.

Description

Method and device for generating verification sequence and verification method of function coverage rate
Technical Field
The embodiment of the disclosure relates to the field of semiconductor testing, in particular to a method and a device for generating a verification sequence and a verification method for functional coverage.
Background
With the progress of society and the development of semiconductor technology, memories are more and more widely applied in various fields such as industrial internet, article tracking, information acquisition and the like. The memory generally has the characteristics of various instructions, various states, various scene combinations and large storage capacity, and the characteristics lead the memory to have various scenes during verification, thereby increasing the complexity of verification. Simulation verification is very important in the whole front-end flow of the memory, the product quality can be improved and guaranteed, but the product appearance time can be indirectly influenced, and the problem that how to improve the verification efficiency to shorten the verification time is a key verification concern is solved.
However, the conventional simulation verification method usually requires a verification engineer to construct a large number of verification sequences, and the memory usually has many instructions, many states and diversified scene combinations, which causes difficulty to the verification engineer to construct the verification sequences, and is prone to the problem of incompleteness of the verification scene, and the efficiency of constructing the verification sequences by the verification engineer is not high, which affects the efficiency of verifying the memory by using the verification sequences.
Disclosure of Invention
The embodiment of the disclosure provides a method and a device for generating a verification sequence and a verification method for functional coverage, which are at least beneficial to improving the comprehensiveness of the generated verification sequence and improving the efficiency of generating the verification sequence.
According to some embodiments of the present disclosure, in one aspect, an embodiment of the present disclosure provides a method for generating a verification sequence, including: setting the command number of the verification sequence to be N; building a database, wherein the database comprises a plurality of commands, and the commands are commands required in the verification sequence; randomly picking out N commands from the database in sequence; and checking the N commands, and if the N commands are qualified, generating the verification sequence.
In some embodiments, N is a positive integer greater than or equal to 3, N of the commands including a first command, an intermediate command, and a last command, the intermediate command containing N-2 of the commands; the steps of constructing the database and randomly picking out N commands from the database in sequence comprise: the database comprises a plurality of commands for forming the first command, the intermediate command and the last command; and randomly picking out the first order, the middle order and the last order from the database.
In some embodiments, the step of verifying N of said commands comprises: setting first rule information containing at least one command, and limiting the first command to be any command in the first rule information; setting second rule information, wherein the second rule information comprises limitation information of a command before any intermediate command and limitation information of a command after any intermediate command, and is used for limiting the command before and after any intermediate command; the last bit command is defined as precharging all memory cells.
In some embodiments, N is a positive integer greater than or equal to 3, the N commands include a first command, an intermediate command, and a last command, the intermediate command comprising N-2 commands; the steps of constructing the database and randomly picking out N commands from the database in sequence comprise: the database comprises a plurality of commands for forming the first command and the intermediate command; randomly picking out the first command and the intermediate command from the database in sequence; all memory cells will be precharged as the last bit command.
In some embodiments, the step of verifying N of said commands comprises: setting first rule information containing at least one command, and limiting the first command to be any command in the first rule information; setting second rule information including restriction information of the command preceding any one of the intermediate commands and restriction information of the command succeeding any one of the intermediate commands, for restricting the command preceding and the command succeeding any one of the intermediate commands.
In some embodiments, N is a positive integer greater than or equal to 3, N of the commands including a first command, an intermediate command, and a last command, the intermediate command containing N-2 of the commands; the steps of constructing the database and randomly picking out N commands from the database in sequence comprise: the database comprises a first database and a second database, wherein the number of the commands contained in the second database is larger than the number of the commands contained in the first database; randomly picking the first order from the first database, and sequentially randomly picking the intermediate orders from the second database; all memory cells will be precharged as the last bit command.
In some embodiments, the step of verifying N of said commands comprises: setting second rule information, wherein the second rule information comprises limitation information of a command preceding any one of the intermediate commands and limitation information of a command succeeding any one of the intermediate commands, and is used for limiting the command preceding and the command succeeding any one of the intermediate commands.
In some embodiments, the method of generating a verification sequence further comprises: providing a generation protocol, and setting the second rule information based on the generation protocol and the state machine diagram of the generation protocol.
In some embodiments, the step of verifying N of said commands comprises: after N commands are randomly selected from the database in sequence, generating an initial verification sequence; and sequentially checking the N commands in the initial verification sequence, and if the N commands are qualified, taking the initial verification sequence as the verification sequence.
In some embodiments, the step of verifying N of said commands comprises: and when one command is randomly selected from the database, the command is checked, if the command is not qualified, the subsequent work of randomly selecting the command from the database is not performed, and the command is randomly selected from the first command of the N commands in the database again.
In some embodiments, the N is randomly generated.
According to some embodiments of the present disclosure, in another aspect, there is provided a method for verifying functional coverage, where a verification sequence generated by any one of the methods for generating a verification sequence is applied to a memory to verify the functional coverage of the memory.
In some embodiments, the method for verifying the functional coverage further includes: randomizing bank group information, bank unit information, address selection information, and mode register set information.
According to some embodiments of the present disclosure, there is also provided an apparatus for generating a verification sequence, including: the database construction module is used for constructing a database, the database comprises a plurality of commands, and the commands are commands required in the verification sequence; a randomization module configured to: randomly picking out N commands from the database in sequence; a verification module configured to: and checking the N commands, and if the N commands are qualified, generating the verification sequence.
In some embodiments, N is a positive integer greater than or equal to 3, N of the commands including a first command, an intermediate command, and a last command, the intermediate command containing N-2 of the commands; the database construction module is configured to: and constructing a first database and a second database, wherein the number of the commands contained in the second database is greater than the number of the commands contained in the first database, the first database is used for forming the first commands, and the second database is used for forming the intermediate commands.
In some embodiments, the random module is further configured to: and randomly generating the N.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages:
the commands related to the verification sequence generation are stored in the database, and then N commands are selected from the database in sequence, so that all situations possibly serving as the verification sequence are given out, the comprehensiveness of the generated verification sequence is improved, the commands are automatically selected from the database in sequence, the error easiness and the complexity of manually writing the verification sequence are avoided, the writing efficiency of the verification sequence is improved, and the accuracy of the generated verification sequence is improved by checking the N commands.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
FIG. 1 is a flow chart of a method for generating a verification sequence according to an embodiment of the present application;
fig. 2 is a functional block diagram of an apparatus for generating an authentication sequence according to another embodiment of the present application.
Detailed Description
As known from the background art, in order to realize the simulation verification of the memory, the comprehensiveness of the constructed verification sequence needs to be improved, and the generation efficiency of the verification sequence needs to be improved.
The verification of the memory at present is mainly a verification sequence constructed by a verification engineer in advance, so that in order to improve the function coverage rate when the memory is verified by utilizing the verification sequence subsequently, the verification engineer needs to write a plurality of different verification sequences manually, the condition of writing omission easily occurs, the comprehensiveness of the constructed verification sequence is influenced, the manual writing is complicated, a great deal of energy is consumed, and the generation efficiency of the verification sequence is not improved.
The disclosed implementation provides a method for generating verification sequence and a device thereof, and a verification method of function coverage rate, wherein in the method for generating verification sequence, commands related to the generation of verification sequence are stored in a database, and then N commands are randomly selected from the database in sequence, so that all situations possibly serving as verification sequences are given out, which is favorable for improving the comprehensiveness of the generated verification sequence.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the embodiments of the disclosure, numerous technical details are set forth in order to provide a better understanding of the disclosure. However, the claimed subject matter may be practiced without these specific details or with various changes and modifications based on the following embodiments.
An embodiment of the present application provides a method for generating a verification sequence, which is described in detail below with reference to the accompanying drawings. Fig. 1 is a flowchart of a method for generating a verification sequence according to an embodiment of the present application.
Referring to fig. 1, the method of generating a verification sequence includes the steps of:
s101: the number of commands in the authentication sequence is set to N.
In some embodiments, N is randomly generated. Therefore, the verification sequences containing different numbers of commands can be randomly generated, the diversity of the generated verification sequences is favorably improved, and the omission condition when a verification engineer writes can be avoided.
S102: building a database, wherein the database comprises a plurality of commands, and the commands are commands required in a verification sequence;
s103: sequentially and randomly picking out N commands from a database;
s104: and checking the N commands, and if the N commands are qualified, generating a verification sequence. Three embodiments are provided below to describe the steps of constructing a database, randomly picking N commands from the database in sequence, and checking the N commands in detail.
In some embodiments, N is a positive integer greater than or equal to 3, the N commands include a first command, an intermediate command, and a last command, the intermediate command comprising N-2 commands; the steps of constructing a database and randomly picking out N commands from the database in sequence comprise: the database comprises a plurality of commands for forming a first command, a middle command and a last command; and randomly picking out a first order, a middle order and a last order from the database.
It should be noted that the first command and the last command in the verification sequence are different from the other commands in the verification sequence, i.e. the intermediate commands, and the selectable range of the first command is smaller than that of the intermediate commands, i.e. some commands can be used as intermediate commands but cannot be used as first commands; and the last bit command is usually a fixed specific command, and when the memory is verified subsequently, the last bit command is used for enabling the memory to be restored to a fixed state after the verification is finished, so as to ensure that the state of the memory is the same before the memory is verified each time, avoid the interference caused by the verification of the memory in the previous time on the verification of the memory in the next time, and ensure the accuracy of the verification result of the memory verification each time.
Although the first command, the intermediate command and the last command in the verification sequence are different in selection range, the same command can be used as the first command, the intermediate command and/or the last command, and thus the first command, the intermediate command and the last command in the verification sequence are all selected from the same database, which is beneficial to avoiding the situation that the same command needs to be stored in different databases, and beneficial to avoiding the command from being stored repeatedly so as to save the storage space. Moreover, the N commands are randomly selected from the database in sequence, which can give a poor list of all situations possibly serving as verification sequences, thereby being beneficial to improving the comprehensiveness of the generated verification sequences, and the commands are randomly selected from the database automatically, thereby being beneficial to avoiding the error and complexity of manually writing the verification sequences and improving the writing efficiency of the verification sequences.
Wherein the step of checking the N commands may comprise: setting first rule information containing at least one command, and limiting a first command to be any command in the first rule information; setting second rule information including restriction information of a preceding command of any one of the intermediate commands and restriction information of a succeeding command of any one of the intermediate commands, for restricting the preceding command and the succeeding command of any one of the intermediate commands; the last bit command is defined as precharging all memory cells.
It should be noted that the first rule information specifically refers to: the first command can be specifically which command, and if the command randomly selected from the database conforms to the first rule information, the verification sequence containing the first command is qualified; if the command randomly selected from the database does not accord with the first rule information, the verification sequence containing the first command is unqualified and cannot be used for verifying the memory subsequently.
The method comprises the steps of setting first rule information for a first command, setting second rule information for a middle command and limiting a last command, and screening a command sequence consisting of N commands randomly picked from a database in sequence, so that a verification sequence which cannot verify the functional coverage rate of a memory can be removed, and the accuracy of the generated verification sequence can be improved.
In other embodiments, N is a positive integer greater than or equal to 3, the N commands include a first command, an intermediate command, and a last command, the intermediate command comprising N-2 commands; the steps of constructing a database and randomly picking out N commands from the database in sequence comprise: the database comprises a plurality of commands for forming a first command and an intermediate command; randomly picking out a first command and a middle command from a database in sequence; all memory cells will be precharged as a last bit command.
Therefore, the first N-1 commands in the verification sequence are randomly picked out from the same database, the last command in the verification sequence does not need to be randomly picked out from the database, namely the verification sequence containing the N commands is generated only by carrying out random picking for N-1 times, the steps of randomly picking the commands are favorably reduced, whether the last command meets the requirements or not is not required to be subsequently checked, the checking steps are favorably reduced, and the compiling efficiency of the verification sequence is favorably improved while the comprehensiveness of the generated verification sequence is ensured.
Wherein the step of checking the N commands may comprise: setting first rule information containing at least one command, and limiting a first command to be any command in the first rule information; second rule information is set, the second rule information including restriction information of a command preceding any one of the intermediate commands and restriction information of a command succeeding any one of the intermediate commands, for restricting the command preceding and the command succeeding any one of the intermediate commands.
It should be noted that the first rule information specifically refers to: the first command can be specifically which command, and if the command randomly selected from the database conforms to the first rule information, the verification sequence containing the first command is qualified; if the command randomly selected from the database does not accord with the first rule information, the verification sequence containing the first command is unqualified and cannot be used for verifying the memory subsequently.
The first rule information is set for the first order and the second rule information is set for the intermediate order, the first N-1 orders in the order sequence composed of N orders randomly picked out from the database are screened once, the screening of the last order is not needed, the accuracy of the generated verification sequence is improved, and meanwhile, the efficiency of checking the generated verification sequence is improved.
In still other embodiments, N is a positive integer greater than or equal to 3, the N commands include a first command, an intermediate command, and a last command, the intermediate command comprising N-2 commands; the steps of constructing a database and randomly picking out N commands from the database in sequence comprise: the database comprises a first database and a second database, and the number of commands contained in the second database is greater than that of the commands contained in the first database; randomly picking out a first order from a first database, and sequentially randomly picking out intermediate orders from a second database; all memory cells will be precharged as a last bit command. The first database contains commands which can be used as first-order commands.
Therefore, the first order in the verification sequence is randomly picked out from the first database, the intermediate order in the verification sequence is randomly picked out from the second database, and the number of the orders contained in the first database is smaller than that of the orders contained in the second database, so that the efficiency of randomly picking out the first order from the first database is higher than that of randomly picking out any intermediate order from the second database, and the generated verification sequence is guaranteed to be comprehensive, and the writing efficiency of the verification sequence is further improved.
In some embodiments, the second database contains all commands in the first database and contains commands not present in the first database. For example, the first database may include: ACT commands, PDE commands, REF commands, PDA commands, SREF commands, Cs TRANING commands, Ca TRANING commands, Read Preamble TRANING commands, MPSM commands, and the like; the first database may include: CT commands, PDE commands, REF commands, PDA commands, SREF commands, Cs TRANING commands, Ca TRANING commands, Read Preamble TRANING commands, MPSM commands, WR/WRA commands, RD/RDA commands, PRE commands, PDX (NOP) commands, and the like.
It should be noted that the above-described various specific commands are all DDR standard commands, and the detailed explanation of the various commands may be referred to DDR JEDEC standard. In addition, the database in the foregoing two embodiments may also include the various commands described above.
Wherein the step of checking the N commands may comprise: second rule information is set, the second rule information including restriction information of a command preceding any one of the intermediate commands and restriction information of a command succeeding any one of the intermediate commands, for restricting the command preceding and the command succeeding any one of the intermediate commands.
Because the first order is randomly picked out from the first database, the condition that the picked order cannot be used as the first order does not exist, when the verification sequence is verified, the intermediate order randomly picked out from the second database is only needed to be tested, the first order and the last order do not need to be screened, and the method is beneficial to improving the accuracy of the generated verification sequence and further improving the efficiency of testing the generated verification sequence.
In the above three embodiments, the method for generating the verification sequence may further include: providing a generation protocol, and setting second rule information based on the generation protocol and the state machine diagram of the generation protocol.
It should be noted that the generation protocol is spec specification of standards in the semiconductor industry, and specifies the interaction relationship between some commands frequently used in the memory, such as an activate command, a read command, a write command, a refresh command, a precharge command, and the like; the state machine diagram determined based on the generation protocol contains the interaction between the various commands used in the memory. Therefore, the comprehensiveness of the detection of the intermediate command can be improved based on the second rule information set by the generation protocol and the state machine diagram of the generation protocol, namely, all verification sequences which cannot realize the functional coverage verification of the memory are removed, so that the accuracy of the written verification sequences is ensured.
It should be noted that, in the above three embodiments, the limitation information of the previous command of any intermediate command refers to: for any intermediate command, verifying the information of which commands the command picked one step earlier than the intermediate command in the sequence can be; and, the restriction information of the subsequent command of any intermediate command specifically means: verifying which commands in the sequence that are picked one step later than the intermediate command may be information of which commands.
In addition, in the above three embodiments, the last bit command is a command for precharging all the memory cells, that is, a PERA command, and when the verification sequence is used for verifying the memory, after each verification is completed, the memory can be restored to the initial state, so that it is convenient to subsequently verify the memory by using another verification sequence, which avoids interference between two adjacent verifications and ensures the accuracy of the verification result of each verification of the memory.
The following two embodiments are also provided for the step of verifying the N commands.
In some embodiments, the step of verifying the N commands may comprise: after N commands are sequentially and randomly selected from a database, an initial verification sequence is generated; and sequentially checking the N commands in the initial verification sequence, and if the N commands are qualified, taking the initial verification sequence as the verification sequence. For example, if the randomly generated initial verification sequence is ACT-ACT-WR-REF-REF-ACT-PRE, then when the initial verification sequence is examined, it is determined that if the current command is REF and the last command is WR instead of PRE, which does not meet the rules, then the initial verification sequence is automatically discarded, and a new initial verification sequence is subsequently regenerated from the database.
Therefore, the generated verification sequence can be used for verifying the function coverage rate of the memory, and unnecessary damage and unnecessary power consumption of the memory caused by the wrong verification sequence are avoided. In addition, if the verification is not qualified, the initial verification sequence can be discarded, and the phenomenon that the subsequent unnecessary initial verification sequence occupies a storage space is avoided.
In other embodiments, the step of verifying the N commands may include: when one command is randomly selected from the database, the command is checked, if the command is not qualified, the subsequent work of randomly selecting the command from the database is not performed, and the command is randomly selected from the first command of the N commands in the database again.
Therefore, one command is selected from the database and then is checked, and the N commands do not need to be checked after being selected from the database, so that the incorrect command sorting form can be screened out more timely, and the generation efficiency of the verification sequence is further improved.
It should be noted that, those skilled in the art can understand that all or part of the steps in the method for implementing the various embodiments described above can be implemented by instructing the relevant hardware through a program code, where the program is stored in a storage medium and includes several instructions to make a single chip microcomputer, a chip, or a processor execute all or part of the steps of the method described in the various embodiments of the present disclosure. Further, the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
Various embodiments of the present disclosure are described in detail above, however, the embodiments of the present disclosure are not limited to the specific details in the embodiments described above, and within the technical concept scope of the embodiments of the present disclosure, many simple modifications may be made to the technical solution of the embodiments of the present disclosure, and these simple modifications all belong to the protective scope of the embodiments of the present disclosure. It should be noted that the various technical features described in the above embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the embodiments of the present disclosure do not separately describe various possible combinations.
In addition, any combination between various embodiments of the present disclosure may be made, and the same should be considered as disclosed in the embodiments of the present disclosure, as long as it does not depart from the inventive concept of the embodiments of the present disclosure.
In summary, the commands related to the verification sequence generation are stored in the database, and then the N commands are selected from the database in sequence, so that all situations that may serve as the verification sequence are given out, which is beneficial to improving the comprehensiveness of the generated verification sequence.
Another embodiment of the present application further provides a verification method for functional coverage, where the verification sequence generated by the method for generating a verification sequence provided in the foregoing embodiment is applied to a memory to verify the functional coverage of the memory. The method for verifying the functional coverage provided by another embodiment of the present application will be described in detail below with reference to the accompanying drawings.
The verification method of the functional coverage rate comprises the following steps: the verification sequence generated by the method for generating the verification sequence provided by the foregoing embodiment is applied to the memory to verify the functional coverage of the memory. Because the generated verification sequence has higher comprehensiveness, various functions which can be realized by the memory can be verified based on the verification sequence, thereby being beneficial to improving the function coverage rate of the memory and improving the verification quality of the memory.
The generated verification sequence is input into an interface of the memory for receiving the verification sequence, so that the memory starts to work according to commands in the verification sequence, response parameters of the memory responding to the commands in the verification sequence are collected, and the functional coverage rate of the memory is verified based on the response parameters, so that the memory is ensured to act correctly in an actual environment.
In some embodiments, the method for verifying the functional coverage may further include: randomizing bank group information, bank unit information, address selection information, and mode register set information. Therefore, the verification sequence has higher comprehensiveness, and simultaneously is favorable for improving the comprehensiveness of other control information in the memory, namely further covering various functions which can be realized by the memory, and is favorable for further improving the function coverage rate of the memory, namely improving the probability of verifying all the functions which can be realized by the memory.
It should be noted that, in some embodiments, the randomized BANK GROUP information may be BG, the storage space is divided into two blocks, namely BANK GROUP0 and BANK GROUP1, and one address line is named BG, if BG is pulled high, BANK GROUP p0 is selected, if BG is pulled low, BANK GROUP p1 is selected, in other embodiments, the storage space may be divided into four blocks, and 2 address lines are used for control; the memory unit information can be BA, 1 BANK GROUP is divided into 4 BANKs, namely memory unit bodies, namely BANK0, BANK1, BANK2 and BANK3, 2 address lines are named BA0 and BA1, and the memory unit bodies are encoded for the 4 BANKs; the ADDRESS selection information may be ADDRESS for selecting an ADDRESS line; the mode register set information may be an MRS for programming the mode register.
In summary, the verification sequence generated by the method for generating the verification sequence provided by the foregoing embodiment is applied to the memory, which is beneficial to improving the functional coverage of the memory, so as to improve the verification quality of the memory.
Still another embodiment of the present application further provides an apparatus for generating a verification sequence, which is used to implement the method for generating a verification sequence provided in the foregoing embodiment. An apparatus for generating a verification sequence according to another embodiment of the present application will be described in detail with reference to the accompanying drawings. Fig. 2 is a functional block diagram of an apparatus for generating an authentication sequence according to another embodiment of the present application.
Referring to fig. 2, an apparatus for generating a verification sequence includes: the database construction module 100 is configured to construct a database, where the database includes a plurality of commands, and the commands are commands required in a verification sequence; a stochastic module 101 configured to: randomly picking out N commands from a database in sequence; a verification module 102 configured to: and checking the N commands, and if the N commands are qualified, generating a verification sequence. Therefore, N commands are randomly selected from the database, all situations possibly serving as verification sequences can be given, and therefore comprehensiveness of the generated verification sequences is improved.
In some embodiments, the random module 101 may be further configured to: n is randomly generated. Therefore, the verification sequences containing different numbers of commands can be randomly generated, the diversity of the generated verification sequences is favorably improved, and the omission condition when a verification engineer writes can be avoided.
The database constructed by the database construction module 100 can provide a detailed description of the following three embodiments.
In some embodiments, N is a positive integer greater than or equal to 3, the N commands include a first command, an intermediate command, and a last command, the intermediate command comprising N-2 commands; the database building module is configured to: including the commands required in the authentication sequence. The database is used for randomly forming a first order command, a middle order command and a last order command. Therefore, the first order, the middle order and the last order in the verification sequence are all selected from the same database, the situation that the same order needs to be stored in different databases is avoided, and the order is prevented from being stored repeatedly so as to save storage space.
Wherein the verification module is configured to: setting first rule information containing at least one command, and limiting a first command to be any command in the first rule information; setting second rule information including restriction information of a preceding command of any one of the intermediate commands and restriction information of a succeeding command of any one of the intermediate commands, for restricting the preceding command and the succeeding command of any one of the intermediate commands; the last bit command is defined as precharging all memory cells. Therefore, the verification sequence which cannot be used for verifying the functional coverage rate of the memory can be removed, and the accuracy of the generated verification sequence can be improved.
In other embodiments, N is a positive integer greater than or equal to 3, the N commands include a first command, an intermediate command, and a last command, the intermediate command comprising N-2 commands; the database building module is configured to: including commands required to verify the first command and the intermediate commands in the sequence. The database is used to randomly form a first bit command and intermediate and last bit commands and to precharge all memory cells as a last bit command. Therefore, the verification sequence containing N commands is generated only by carrying out random selection for N-1 times, the steps of randomly selecting the commands are favorably reduced, the follow-up process of checking whether the last command meets the requirements is not needed, the checking steps are favorably reduced, and the comprehensiveness of the generated verification sequence is favorably ensured, and meanwhile, the writing efficiency of the verification sequence is further improved.
Wherein the verification module is configured to: setting first rule information containing at least one command, and limiting a first command to be any command in the first rule information; second rule information is set, the second rule information including restriction information of a command preceding any one of the intermediate commands and restriction information of a command succeeding any one of the intermediate commands, for restricting the command preceding and the command succeeding any one of the intermediate commands. Therefore, the first N-1 commands are only required to be screened once, and the last command is not required to be screened, so that the generated verification sequence is improved in accuracy and the generated verification sequence inspection efficiency.
In still other embodiments, N is a positive integer greater than or equal to 3, the N commands include a first command, an intermediate command, and a last command, the intermediate command comprising N-2 commands; the database building module is configured to: and constructing a first database and a second database, wherein the number of commands contained in the second database is greater than that of the commands contained in the first database, the first database is used for forming the first commands, and the second database is used for forming the intermediate commands. Because the number of the commands contained in the first database is smaller than that of the commands contained in the second database, the efficiency of randomly picking out the first commands from the first database is higher than that of randomly picking out any intermediate command from the second database, and therefore the comprehensiveness of the generated verification sequence is guaranteed, and meanwhile the writing efficiency of the verification sequence is further improved.
Wherein the verification module is configured to: second rule information is set, the second rule information including restriction information of a command preceding any one of the intermediate commands and restriction information of a command succeeding any one of the intermediate commands, for restricting the command preceding and the command succeeding any one of the intermediate commands. Therefore, when the verification sequence is verified, the first order and the last order do not need to be screened, so that the generated verification sequence is more accurately verified, and the verification efficiency of the generated verification sequence is further improved.
In the above three embodiments, the verification module may be further configured to: after N commands are sequentially and randomly selected from a database, an initial verification sequence is generated; and sequentially checking the N commands in the initial verification sequence, and if the N commands are qualified, taking the initial verification sequence as the verification sequence. Alternatively, the verification module may be further configured to: when one command is randomly selected from the database, the command is checked, if the command is not qualified, the subsequent work of randomly selecting the command from the database is not carried out, and the command is randomly selected from the first command in the database again.
In summary, by constructing the database, randomly selecting N commands from the database, all situations that may serve as verification sequences can be given, which is favorable for improving the comprehensiveness of the generated verification sequences, and by automatically randomly selecting commands from the database, it is favorable for avoiding the error-prone and cumbersome nature of manually writing the verification sequences and for improving the writing efficiency of the verification sequences, and moreover, by checking N commands, it is favorable for improving the accuracy of the generated verification sequences.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the embodiments of the present disclosure in practice. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the embodiments of the present disclosure, and it is therefore intended that the scope of the embodiments of the present disclosure be limited only by the terms of the appended claims.

Claims (16)

1. A method of generating a verification sequence, comprising:
setting the number of commands in the verification sequence to be N;
building a database, wherein the database comprises a plurality of commands, and the commands are commands required in the verification sequence;
randomly picking out N commands from the database in sequence;
and checking the N commands, and if the commands are qualified, generating the verification sequence.
2. The method of generating a verification sequence of claim 1, wherein N is a positive integer greater than or equal to 3, the N said commands including a first command, an intermediate command, and a last command, the intermediate command containing N-2 said commands; the steps of constructing the database and randomly picking out N commands from the database in sequence comprise:
the database comprises a plurality of commands for forming the first command, the intermediate command and the last command;
and randomly picking out the first order, the middle order and the last order from the database.
3. The method of generating a verification sequence of claim 2, wherein the step of verifying N of the commands comprises:
setting first rule information containing at least one command, and limiting the first command to be any command in the first rule information;
setting second rule information, wherein the second rule information comprises limitation information of a command before any intermediate command and limitation information of a command after any intermediate command, and is used for limiting the command before and after any intermediate command;
the last bit command is defined as precharging all memory cells.
4. The method of generating a verification sequence of claim 1, wherein N is a positive integer greater than or equal to 3, the N said commands including a first command, an intermediate command, and a last command, the intermediate command containing N-2 said commands; the steps of constructing the database and randomly picking out N commands from the database in sequence comprise:
the database comprises a plurality of commands for forming the first command and the intermediate command;
randomly picking out the first command and the intermediate command from the database in sequence;
all memory cells will be precharged as the last bit command.
5. The method of generating a verification sequence of claim 4, wherein the step of verifying N of the commands comprises:
setting first rule information containing at least one command, and limiting the first command to be any command in the first rule information;
setting second rule information, wherein the second rule information comprises limitation information of a command preceding any one of the intermediate commands and limitation information of a command succeeding any one of the intermediate commands, and is used for limiting the command preceding and the command succeeding any one of the intermediate commands.
6. The method of generating a verification sequence of claim 1, wherein N is a positive integer greater than or equal to 3, the N said commands including a first command, an intermediate command, and a last command, the intermediate command containing N-2 said commands; the steps of constructing the database and randomly picking out N commands from the database in sequence comprise:
the database comprises a first database and a second database, wherein the number of the commands contained in the second database is larger than the number of the commands contained in the first database;
randomly picking the first order from the first database, and sequentially randomly picking the intermediate orders from the second database;
all memory cells will be precharged as the last bit command.
7. The method of generating a verification sequence of claim 6, wherein the step of verifying N of the commands comprises: setting second rule information, wherein the second rule information comprises limitation information of a command preceding any one of the intermediate commands and limitation information of a command succeeding any one of the intermediate commands, and is used for limiting the command preceding and the command succeeding any one of the intermediate commands.
8. The method of generating a verification sequence of any of claims 3, 5 or 7, further comprising: providing a generation protocol, and setting the second rule information based on the generation protocol and the state machine diagram of the generation protocol.
9. The method of generating a verification sequence of claim 1, wherein the step of verifying N of the commands comprises:
after N commands are randomly selected from the database in sequence, generating an initial verification sequence;
and sequentially checking the N commands in the initial verification sequence, and if the N commands are qualified, taking the initial verification sequence as the verification sequence.
10. The method of generating a verification sequence of claim 1, wherein the step of verifying N of the commands comprises:
and when one command is randomly selected from the database, the command is checked, if the command is not qualified, the subsequent work of randomly selecting the command from the database is not performed, and the command is randomly selected from the first command of the N commands in the database again.
11. The method of generating a verification sequence of claim 1, wherein the N is randomly generated.
12. A method for verifying functional coverage, characterized in that a verification sequence generated by the method for generating a verification sequence according to any one of claims 1 to 11 is applied to a memory to verify the functional coverage of the memory.
13. The method for verifying functional coverage according to claim 12, further comprising: randomizing bank group information, bank unit information, address selection information, and mode register set information.
14. An apparatus for generating a verification sequence, comprising:
the database construction module is used for constructing a database, the database comprises a plurality of commands, and the commands are commands required in the verification sequence;
a randomization module configured to: randomly picking out N commands from the database in sequence;
a verification module configured to: and checking the N commands, and if the N commands are qualified, generating the verification sequence.
15. The apparatus of claim 14, wherein N is a positive integer greater than or equal to 3, the N said commands including a first command, an intermediate command, and a last command, the intermediate command containing N-2 said commands;
the database construction module is configured to: and constructing a first database and a second database, wherein the number of the commands contained in the second database is greater than the number of the commands contained in the first database, the first database is used for forming the first commands, and the second database is used for forming the intermediate commands.
16. The apparatus of claim 14, wherein the random module is further configured to: and randomly generating the N.
CN202210028932.1A 2022-01-11 2022-01-11 Method and device for generating verification sequence and verification method of function coverage rate Pending CN114490357A (en)

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