CN114490201A

CN114490201A - Target interface testing method and device

Info

Publication number: CN114490201A
Application number: CN202111553220.3A
Authority: CN
Inventors: 张书锋
Original assignee: Alibaba China Co Ltd
Current assignee: Alibaba China Co Ltd
Priority date: 2021-12-17
Filing date: 2021-12-17
Publication date: 2022-05-13

Abstract

An embodiment of the present specification provides a target interface testing method and apparatus, where the target interface testing method includes: determining at least one initial order-preserving rule test item of a target interface according to a communication interface in the test equipment, determining a target order-preserving rule test item from the at least one initial order-preserving rule test item according to a preset requirement, determining an initial test parameter corresponding to the target order-preserving rule test item and a parameter value of the initial test parameter, sending a test instruction to the test equipment according to the parameter value of the initial test parameter, and receiving a test result of the test equipment on the target order-preserving rule test item of the target interface according to the test instruction. The communication interface of the test equipment is used for determining an initial order-preserving rule test item capable of being tested, the order-preserving rule of the target interface is tested by using lower cost, the test cost of the order-preserving rule of the target interface is reduced, and the test difficulty of the order-preserving rule of the target interface is reduced.

Description

Target interface testing method and device

Technical Field

The embodiments of the present disclosure relate to the field of hardware testing technologies, and in particular, to a target interface testing method, a target interface testing apparatus, a computing device, and a computer-readable storage medium.

Background

PCIe is called the Peripheral Component Interconnect Express, and is a high-speed serial communication standard, PCIe is an important high-speed channel of a server, and PCIe needs to be fully tested in the server production process. Ordering is an order-preserving rule in the PCIe transaction transmission process, and the exception of deadlock, functional error and the like can be avoided when the rule is satisfied. Most PCIe features can be tested by purchasing EP devices with specific functionality or by specialized PCIe protocol analysis instrumentation. However, Ordering is a feature that is completely transparent to the user, and there is no method for testing the feature in a targeted manner.

Disclosure of Invention

In view of this, the present specification provides a target interface testing method. One or more embodiments of the present disclosure also relate to a target interface testing apparatus, a computing device, a computer-readable storage medium, and a computer program, so as to solve the technical problems in the prior art.

According to a first aspect of embodiments of the present specification, there is provided a target interface testing method, including:

determining at least one initial order-preserving rule test item of a target interface according to a communication interface in test equipment;

determining a target order-preserving rule test item from the at least one initial order-preserving rule test item according to a preset requirement;

determining initial test parameters corresponding to the target order-preserving rule test items and parameter values of the initial test parameters;

sending a test instruction to the test equipment according to the parameter value of the initial test parameter;

and receiving a test result of the test equipment for the target order-preserving rule test item of the target interface according to the test instruction.

Optionally, the determining an initial test parameter corresponding to the target order-preserving rule test item and a parameter value of the initial test parameter includes:

and determining a configuration signal of the test equipment corresponding to the target order-preserving rule test item, and setting a first signal value for the configuration signal.

determining a configuration signal and test timeout time of the test equipment corresponding to the target order-preserving rule test item;

setting a first signal value for the configuration signal and determining a timeout value for the test timeout.

Optionally, the sending a test instruction to the test device according to the parameter value of the initial test parameter includes:

sending a memory read instruction to the test equipment through a preset time interval according to the first signal value and the timeout time value of the initial test parameter, wherein the first signal value is used for limiting recovery of a credit value of the test equipment, and the credit value is used for determining whether the test equipment executes the test instruction;

and under the condition that the credit value of the test equipment is exhausted and the current time is less than the timeout time value, sending a memory write instruction to the test equipment and setting a second signal value for the configuration signal, wherein the second signal value is used for recovering the credit value of the test equipment.

sending a configuration write instruction to the test equipment through a preset time interval according to the first signal value of the initial test parameter, wherein the first signal value is used for limiting the recovery of a credit value of the test equipment, and the credit value is used for determining whether the test equipment executes the test instruction;

and under the condition that the credit value of the test equipment is determined to be exhausted, sending a memory write instruction to the test equipment, and setting a second signal value for the configuration signal, wherein the second signal value is used for recovering the credit value of the test equipment.

sending a memory read instruction request to the test equipment according to the first signal value and the timeout time value of the initial test parameter, wherein the first signal value is used for limiting the test equipment from receiving a read completion message;

and returning the read completion message and the memory write instruction to the test equipment and setting a second signal value for the configuration signal when the memory read instruction sent by the test equipment is received and the current time is less than the timeout time value, wherein the second signal value is used for recovering the test equipment from receiving the read completion message.

sending a memory write instruction to the test equipment according to a first signal value of the initial test parameter, wherein the first signal value is used for limiting the test equipment to execute the test instruction;

when a return message of the test equipment for the memory write instruction is not received, sending a memory read instruction request to the test equipment;

and under the condition of receiving the memory read instruction sent by the test equipment, sending a read completion message to the test equipment, and setting a second signal value for the configuration signal, wherein the second signal value is used for recovering the test equipment to execute the test instruction.

sending a memory read instruction to the test equipment according to the first signal value and the timeout time value of the initial test parameter, wherein the first signal value is used for limiting the test equipment to execute the test instruction;

sending a memory read instruction request to the test equipment under the condition that a return message of the test equipment for the memory read instruction is not received and the current time is less than the overtime value;

sending a configuration write instruction to the test equipment according to the first signal value of the initial test parameter, wherein the first signal value is used for limiting recovery of a credit value of the test equipment, and the credit value is used for determining whether the test equipment executes the test instruction;

under the condition that the credit value of the test equipment is determined to be exhausted, sending a memory read instruction request to the test equipment;

and under the condition of receiving the memory reading instruction sent by the test equipment, sending a reading completion message to the test equipment, and setting a second signal value for the configuration signal, wherein the second signal value is used for recovering the credit value of the test equipment.

Optionally, the receiving a test result of the test device for the target order-preserving rule test item of the target interface according to the test instruction includes:

and under the condition that response information returned by the test equipment is received within the test overtime, determining that the test result of the target order-preserving rule test item of the target interface is successful.

Optionally, the receiving a test result of the test device on the target order-preserving rule test item of the target interface according to the test instruction includes:

and under the condition of receiving response information returned by the test equipment, determining that the test result of the target order-preserving rule test item of the target interface is successful.

and under the condition that response information returned by the test equipment is received within the test overtime and the value of the response information meets a preset response condition, determining that the test result of the target order-preserving rule test item of the target interface is successful.

Optionally, the communication interface includes a first communication interface, a second communication interface, a third communication interface, and a fourth communication interface;

the first communication interface is used for transmitting a memory reading instruction or a memory writing instruction from the host machine to the test equipment;

the second communication interface is used for transmitting a memory read completion message from the test equipment to the host machine;

the third communication interface is used for transmitting the memory reading instruction or the memory writing instruction from the test equipment to the host machine;

the fourth communication interface is used for transmitting the memory read completion message from the host to the test equipment.

According to a second aspect of embodiments herein, there is provided a target interface testing apparatus comprising:

the initial item determination module is configured to determine at least one initial order-preserving rule test item of a target interface according to a communication interface in the test equipment;

the target item determination module is configured to determine a target order-preserving rule test item from the at least one initial order-preserving rule test item according to preset requirements;

the parameter determination module is configured to determine an initial test parameter corresponding to the target order-preserving rule test item and a parameter value of the initial test parameter;

the test module is configured to send a test instruction to the test equipment according to the parameter value of the initial test parameter;

and the receiving module is configured to receive a test result of the target order-preserving rule test item of the target interface by the test equipment according to the test instruction.

According to a third aspect of embodiments herein, there is provided a computing device comprising:

a memory and a processor;

the memory is configured to store computer-executable instructions and the processor is configured to execute the computer-executable instructions, which when executed by the processor, implement the steps of the target interface testing method described above.

According to a fourth aspect of embodiments herein, there is provided a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the steps of the target interface testing method.

According to a fifth aspect of embodiments herein, there is provided a computer program, wherein the computer program, when executed on a computer, causes the computer to perform the steps of the target interface testing method of claim.

The target interface testing method provided by the specification comprises the following steps: determining at least one initial order-preserving rule test item of a target interface according to a communication interface in the test equipment, determining a target order-preserving rule test item from the at least one initial order-preserving rule test item according to a preset requirement, determining an initial test parameter corresponding to the target order-preserving rule test item and a parameter value of the initial test parameter, sending a test instruction to the test equipment according to the parameter value of the initial test parameter, and receiving a test result of the test equipment on the target order-preserving rule test item of the target interface according to the test instruction. In the embodiment of the specification, the communication interface of the test equipment is used for determining the initial order-preserving rule test item capable of being tested, and the order-preserving rule of the target interface is tested by using lower cost, so that the test cost of the order-preserving rule of the target interface is reduced, and the test difficulty of the order-preserving rule of the target interface is reduced.

Drawings

Fig. 1 is a scene schematic diagram of an application scenario of a target interface testing method according to an embodiment of the present specification;

FIG. 2 is a flow chart of a target interface testing method provided in one embodiment of the present description;

FIG. 3 is an architecture diagram of a target interface testing method provided in one embodiment of the present description;

FIG. 4 is a schematic diagram of interface signals of a target interface testing method according to an embodiment of the present disclosure;

FIG. 5 is another flowchart of a target interface testing method provided in an embodiment of the present specification;

FIG. 6 is a schematic structural diagram of a target interface testing apparatus according to an embodiment of the present disclosure;

fig. 7 is a block diagram of a computing device according to an embodiment of the present disclosure.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present description. This description may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, as those skilled in the art will be able to make and use the present disclosure without departing from the spirit and scope of the present disclosure.

The terminology used in the description of the one or more embodiments is for the purpose of describing the particular embodiments only and is not intended to be limiting of the description of the one or more embodiments. As used in one or more embodiments of the present specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used in one or more embodiments of the present specification refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, etc. may be used herein in one or more embodiments to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, a first can also be referred to as a second and, similarly, a second can also be referred to as a first without departing from the scope of one or more embodiments of the present description. The word "if," as used herein, may be interpreted as "at … …" or "when … …" or "in response to a determination," depending on the context.

First, the noun terms to which one or more embodiments of the present specification relate are explained.

PCle: is called a universal Component Interconnect Express, and is a high-speed serial communication standard.

Ordering: the order-preserving rule is a rule which limits the order of PCIe transaction transmission and ensures the ordered completion of the transaction, thereby avoiding the problems of deadlock, conflict and the like.

And Credit: a flow control algorithm used by the PCIe bus. The available buffer amount at the receiving end is represented by a credit value, and the transmitting end stops transmitting data when the credit value of the buffer is exhausted.

A CPU: a Central Processing Unit (CPU) is a final execution unit for information processing and program operation, and serves as an operation and control core of a computer system.

RAM: a Random Access Memory (RAM), also called a main Memory, is an internal Memory that directly exchanges data with the CPU. Typically as a temporary data storage medium for the operating system or other program in operation.

In the present specification, a target interface testing method is provided, and the present specification relates to a target interface testing apparatus, a computing device, a computer-readable storage medium, and a computer program, which are described in detail one by one in the following embodiments.

A target interface test apparatus, a computing device, a computer-readable storage medium, and a computer program according to embodiments of the present specification will be described in detail below with reference to the accompanying drawings.

Fig. 1 is a scene schematic diagram of an application scenario of a target interface testing method according to an embodiment of the present specification. The application scenario may include a host machine 102 and a test device 104.

The host 102 may be a device that includes at least hardware such as a processor 1022(CPU), target interface 1026, memory 1024(RAM) and bus, and an operating system. Here, the host 102 may be a computing device such as a Personal Computer (Personal Computer) or a server, or may be a computing device applied to different fields. For example, the host computer 102 may be a personal computer including a target interface 1026, and the personal computer may be connected to the test equipment 104 through the target interface 1026 and transmit test instructions to the test equipment 104 through the operating system.

Test equipment 104 may be a circuit board that supports functionality for communicating with host machine 102. Here, the test device 104 may be an FPGA with a target interface 1026, or may be a device with a target interface 1026 applied in different fields. For example, the test equipment 104 may be an FPGA supporting the target interface 1026.

The host machine 102 may be communicatively coupled to the test equipment 104 via a target interface 1026 to receive or transmit information, etc. Specifically, the host 102 determines at least one initial order-preserving rule test item of the target interface 1026 according to the communication interface in the test device 104, determines a target order-preserving rule test item from the at least one initial order-preserving rule test item according to a preset requirement, determines an initial test parameter and a parameter value of the initial test parameter corresponding to the target order-preserving rule test item, sends a test instruction to the test device 104 according to the parameter value of the initial test parameter, and receives a test result of the test device 104 on the target order-preserving rule test item of the target interface 1026 according to the test instruction, so that the target interface 1026 test method according to the embodiment of the present specification can test the target interface 1026.

It should be noted that the specific type, number, and combination of the host 102, the target interface 1026, and the test device 104 may be adjusted according to the actual requirement of the application scenario, and the embodiment of the present disclosure is not limited thereto.

Fig. 2 is a flowchart illustrating a target interface testing method according to an embodiment of the present disclosure, where the target interface testing method is applied to a host, and includes the following steps.

Step 202: and determining at least one initial order-preserving rule test item of the target interface according to the communication interface in the test equipment.

For a specific explanation of the host, reference may be made to the above embodiments, which are not described herein again; the test equipment can be understood as equipment which is matched with the host machine to complete the test of the target interface; a communication interface may be understood as a channel for signal transmission, such as an interface on a test device; in practical application, the test equipment is connected with the host machine through the communication interface and is communicated with the host machine through the communication interface; the target interface can be understood as an interface to be tested on the host machine.

Order preserving rules (Ordering) can be understood as rules of a target interface in a transaction transmission process, and exceptions such as Deadlock (Deadlock), functional errors and the like can be avoided in the transaction transmission process through the order preserving rules. The deadlock refers to a phenomenon that two or more transactions are blocked due to resource competition or mutual communication during execution, and if no external force is applied, the two or more transactions cannot advance.

The initial order-preserving rule test item may be understood as a test item determined according to the communication interface, and a test item capable of being tested may be determined according to the function of the communication interface.

In practical application, the communication interfaces on the test equipment are different, and the determined initial order-preserving rule test items of the target interface in the host machine are also different, that is, executable instructions can be determined according to the functions of the communication interfaces on the test equipment, and the executable initial order-preserving rule test items can be determined based on the executable instructions. The specific implementation mode is as follows:

in one implementation, the communication interface includes a first communication interface, a second communication interface, a third communication interface, and a fourth communication interface;

Taking the test equipment as the FPGA, and the communication interface on the FPGA comprises a first communication interface, a second communication interface, a third communication interface and a fourth communication interface as an example, at least one initial order-preserving rule test item of the target interface determined according to the communication interface in the test equipment is introduced in detail.

Referring to fig. 3, fig. 3 is an architecture diagram illustrating a target interface testing method according to an embodiment of the present disclosure.

In fig. 3, the test device is an FPGA, the host is a server, and the target interface is a PCIe interface on the server.

The FPGA comprises a PCIe core and four communication interfaces which are cc, cq, rq and rc respectively, wherein the cq is used for transmitting a memory read instruction or a memory write instruction from a host to the FPGA, the cc is used for transmitting a memory read completion message from the FPGA to the host, the rq is used for transmitting a memory read or memory write instruction from the FPGA to the host, and the rc is used for transmitting a memory read completion message from the host to the FPGA.

Then, in the case that the communication interface of the FPGA is cc, cq, rq, rc, the selection of at least one initial order-preserving rule test item of the target interface can be referred to table 1.

TABLE 1

As shown in table 1, the initial order-preserving rule test items that can be determined based on cc, cq, rq, rc interfaces include: a memory write overriding memory read (row 3 a), a memory write overriding another memory write (row 3B), a memory write overriding memory read complete (row 5B a), a memory read complete overriding memory write (row 2B D), a memory read complete overriding memory read request (row 3D), and a memory read complete overriding another memory read complete test item (row 5D).

The target interface testing method provided by the embodiment of the specification can realize the testing of the order-preserving rule of the target interface only by using the four communication interfaces of the FPGA, so that the testing of the order-preserving rule of the target interface becomes feasible, the testing cost is low, and the testing difficulty is reduced.

Step 204: and determining a target order-preserving rule test item from at least one initial order-preserving rule test item according to a preset requirement.

The preset requirement may be set according to actual application, for example, two initial order-preserving rule test items, namely, a memory write overriding memory read completion and a memory read completion overriding memory read request, may be selected according to the preset requirement as a target order-preserving rule test item.

The target order-preserving rule test item may be understood as one, two or more initial order-preserving rule test items selected from the initial order-preserving rule test items according to a preset requirement, that is, the initial order-preserving rule test items to be tested subsequently.

In practical application, all the test items of the initial order-preserving rule are not necessarily required to be tested, and the test items required to be tested can be determined from the initial order-preserving rule according to preset requirements and used as target order-preserving rule test items to be tested.

The target interface test method provided in the embodiment of the present specification may determine, according to a preset requirement, a target order-preserving rule test item to be tested from a plurality of initial order-preserving rule test items, so as to implement customizability of a test scheme, and select different target order-preserving rule test items for different test purposes, thereby increasing diversity of the scheme and improving universality.

Step 206: and determining initial test parameters corresponding to the target order-preserving rule test items and parameter values of the initial test parameters.

The initial test parameters may be initial parameters set for different target order-preserving rule test items before performing the test.

In practical application, different test methods required to be performed on different target order-preserving rule test items are different, so in order to perform subsequent test steps, each target order-preserving rule test item needs to set an initial test parameter and a corresponding parameter value so as to ensure that the current target order-preserving rule test item can be smoothly performed.

Specifically, according to different target order-preserving rule test items, the initial test parameters and the corresponding parameter values which need to be set for each target order-preserving rule test item are also different. The specific implementation mode is as follows:

the determining of the initial test parameters corresponding to the target order-preserving rule test items and the parameter values of the initial test parameters includes:

The configuration signal may be understood as a signal for setting the test device, and may be pulled high or pulled low, where pulling low refers to setting a value of the configuration signal to 0, and pulling high refers to setting a value of the configuration signal to 1.

The first signal value may be 0, and in case the first signal value is 0, setting the first signal value for the configuration signal is to set the configuration signal to a low level.

In practical application, some target order-preserving rule test items need to send a configuration signal to the test equipment and set a first signal value, so that subsequent test steps are performed.

For example, when it is determined that the memory write-override memory read is completed as the target order-preserving rule test item, the server searches the configuration of the test item, which is required to be performed before the test, of the memory write-override memory read from the database, determines the configuration signal of the test equipment corresponding to the target order-preserving rule test item according to the configuration required to be performed, and sets a first signal value for the configuration signal.

The target interface testing method provided by the embodiment of the specification determines the initial testing parameters and the parameter values of the initial testing parameters according to the target order-preserving rule testing items, can customize the testing of the target interface, determines different testing environments according to different situations of the target interface, and improves the accuracy of the testing result.

In another implementation example, when the target order-preserving rule test items are different, not only the configuration signal of the target order-preserving rule test item needs to be set, but also the test timeout time needs to be set. The specific implementation mode is as follows:

For a specific explanation of the configuration signal and the first signal value, reference may be made to the description of the above embodiments, which is not repeated herein.

The test timeout may be understood as a maximum waiting time calculated from the sending of the test instruction, and a value greater than or equal to the timeout value triggers the occurrence of a timeout event (completion timeout).

In practical use, some order preserving rule test items not only need to send a configuration signal to the test equipment and set a first signal value, but also need to perform a timeout value for determining the test timeout.

For example, when it is determined that the memory write override memory read is completed as the target order-preserving rule test item, first a first signal value is set for the configuration signal, and further, a test timeout time needs to be set, where the timeout time value may range from 4 seconds to 64 seconds, and the timeout time value of the test timeout time may be a fixed value set according to actual application experience, or may be a different value set according to different target order-preserving rule test items, which is not limited in this embodiment of the specification.

The embodiment of the specification determines the initial test parameters and the parameter values of the initial test parameters according to the target order-preserving rule test items, can customize the test of the target interface, determines different test environments according to different conditions of the target interface, and improves the accuracy of the test result. The test overtime time is set to reserve time for sending other test instructions, so that the test feasibility is ensured.

Step 208: and sending a test instruction to the test equipment according to the parameter value of the initial test parameter.

The test instruction may be an instruction for testing sent by a host to a test device, and the form of the test instruction may be set according to the type of the test device, or may be a self-defined instruction, such as devmem and setpci, which is not limited in the embodiments of this specification.

In practical application, the target order-preserving rule test item is tested, and the test item can be understood as sending a test instruction to the test equipment based on the host machine, so that the host machine and the test equipment communicate with each other, and the test of the target interface is completed.

In the above example, when the target order-preserving rule test item is a test item in which memory writing exceeds memory reading, a specific implementation manner of sending a test instruction to the test equipment according to the parameter value of the initial test parameter is as follows:

the sending of the test instruction to the test equipment according to the parameter value of the initial test parameter includes:

sending a memory read instruction to the test equipment through a preset time interval according to the first signal value and the timeout time value of the initial test parameter, wherein the first signal value is used for limiting recovery of a credit value of the test equipment, and the credit value is used for determining whether the test equipment executes the memory read instruction;

Wherein the first signal value is used to limit credit recovery of the test device may be understood as prohibiting credit recovery in case the configuration signal is the first signal value. The credit value is used to determine whether the test device executes the memory read instruction, which may be understood as the credit value is used to determine whether the test device receives the test instruction.

For example, referring to fig. 4, fig. 4 shows an interface signal diagram of a target interface testing method, a configuration signal may be a Pcie _ cq _ np _ req signal, a first signal value may be 0 (low level), the Pcie _ cq _ np _ req signal is used to prohibit credit update of a memory read command or a configuration write command, when the value of the Pcie _ cq _ np _ req signal is 0, a credit value (credit) is exhausted according to the number of times of executing a test command, so that the test command is suspended, and the Pcie _ cq _ np _ req signal is mapped in a Pcie bar space, and may be subjected to read-write control by a host. For example, the target order-preserving rule test item may be a test item in which memory writing exceeds memory reading, the host sets the value of the Pcie _ cq _ np _ req signal to 0 in a memory writing manner, and sets the timeout value to 4 seconds, the host sends a memory reading instruction to the test device at an interval of one second, and the test device consumes a credit value each time the test device executes the memory reading instruction sent by the host, where an initial value of the credit value may be 32, and a data size of the memory reading instruction may be 8 bits to 64 bits; under the condition that the credit value is exhausted, the memory read instruction is suspended and is not executed by the test equipment any more, and the host machine cannot receive a read completion message returned by the test equipment, the host machine does not send the memory read instruction to the test equipment any more, the time is counted from the memory read instruction sent by the last host machine, under the condition that the counted time is less than the overtime value, the host machine sends a memory write instruction to the test equipment, the value of the Pcie _ cq _ np _ req signal is set to be a second signal value through a memory write mode, the second signal value can be 1 (high level), and when the value of the Pcie _ cq _ np _ req signal is set to be 1, the credit value is returned, namely the credit value is recovered to 32, so that the suspended memory read instruction is executed continuously.

The embodiment of the specification can test the test items of the memory write-over-memory read based on the two test instructions between the host machine and the test equipment, so that the test program is simple, and the test efficiency is improved.

In the above example, when the target order-preserving rule test item is a test item in which the memory write overrides another memory write, a specific implementation manner of sending the test instruction to the test device according to the parameter value of the initial test parameter is as follows:

sending a first memory write instruction to the test equipment according to the first signal value of the initial test parameter, wherein the first signal value is used for limiting the test equipment to execute the first memory write instruction;

when a return message of the test equipment for the first memory write instruction is not received, sending a second memory write instruction to the test equipment, and setting a second signal value for the configuration signal, where the second signal value is used to recover the test equipment to execute the first memory write instruction.

For example, the host sets the value of the M _ axis _ cq _ linear signal to 0 by means of configuration writing, specifically, the manner of configuration writing may be to access an MSI MASK field of an ECAM space of the test device, a change in the MSI MASK field reflects that an interface signal to the test device is a cfg _ interrupt _ MSI _ data signal, and the cfg _ interrupt _ MSI _ data signal is used to control the test logic to set the M _ axis _ cq _ linear signal to 0, thereby preventing the first memory write operation from passing through. That is, the memory write operation used to control the MSIX interrupt generation fails, the first memory write instruction is locked (block), and the test equipment does not generate an MSIX interrupt. And then sending a second memory write instruction to the test equipment, wherein the address and the data carried by the write instruction are both special values, analyzing the address and the data field of the M _ axi _ cq _ tdata in the test logic, setting the M _ axi _ cq _ linear to be 1 after obtaining an expected special value, judging whether the MSIX is generated, and if the MISX is generated, indicating that the second memory write successfully surpasses the first memory write.

The embodiment of the specification can test the test item of the memory write exceeding the other memory write based on the two test instructions between the host machine and the test equipment, so that the test program is simple, and the test efficiency is improved.

In the above example, when the target order-preserving rule test item is a test item in which memory writing is completed and memory reading is completed, a specific implementation manner of sending a test instruction to the test device according to the parameter value of the initial test parameter is as follows:

Specifically, the configuration signal may be an M _ axis _ rc _ linear signal, and the first signal value may be 0. For example, the target order-preserving rule test item may be a test item in which memory write overrides memory read completion, the host sets the value of the M _ axis _ rc _ linear signal to 0 by means of memory write, and sets the timeout value to 4 seconds, the host sends a memory read command request to the test device, the test device sends a memory read command to the host after receiving the memory read command request, because the M _ axis _ rc _ linear signal is set to 0, after the memory read command is executed by the host, the read completion message sent by the host is locked, the test device cannot receive the read completion message returned by the host, the test device does not send a memory read command to the host any more, starts timing from the memory read command sent by the test device, the host sends a memory write command to the test device when the timing time is less than the timeout value, and sets the value of the M _ axis _ rc _ linear signal to the second signal value by means of memory write, the second signal value may be 1 so that the test device receives the read complete message.

The embodiment of the specification can test the test items of the memory write-over-memory read completion based on the two test instructions between the host machine and the test equipment, so that the test program is simple, and the test efficiency is improved.

In the above example, when the target order-preserving rule test item is a test item in which the memory read is completed and the memory write is surpassed, a specific implementation manner of sending the test instruction to the test equipment according to the parameter value of the initial test parameter is as follows:

sending a memory write instruction to the test equipment according to a first signal value of the initial test parameter, wherein the first signal value is used for limiting the test equipment to execute the memory write instruction;

when the return message of the test equipment for the memory write instruction is not received, sending a memory read instruction request to the test equipment;

and under the condition of receiving the memory read instruction sent by the test equipment, sending a read completion message to the test equipment, and setting a second signal value for the configuration signal, wherein the second signal value is used for recovering the test equipment to execute the memory write instruction.

Specifically, the configuration signal may be an M _ axis _ rc _ linear signal, and the first signal value may be 0. For example, the target order-preserving rule test item may be a test item in which memory read is completed and memory write is surpassed, the host sets the value of the M _ axi _ rc _ linear signal to 0 by means of memory write, the host sends a memory write command to the test device, the memory write command triggers the test device to generate MSIX interrupt, because the value of the M _ axi _ rc _ linear signal is 0, the memory write command is locked, the memory write command is no longer executed by the test device, so MSIX interrupt does not occur, the test device sends a memory read command to a preset address of the host, the host sends a read completion message with a preset load message (payload) to the test device after receiving the memory read command, and the host sets the value of the M _ axi _ rc _ linear signal to a second signal value in the case of receiving the read completion message with the preset load message, the second signal value may be 1, so that the test equipment may execute the memory write instruction to generate the MSIX interrupt.

The embodiment of the specification can test the test items of the memory read completion exceeding the memory write based on the two test instructions between the host machine and the test equipment, so that the test program is simple, and the test efficiency is improved.

In the above example, when the target order-preserving rule test item is a test item in which the memory read completion exceeds the memory read request, a specific implementation manner of sending the test instruction to the test device according to the parameter value of the initial test parameter is as follows:

sending a first memory read instruction to the test equipment according to the first signal value and the timeout time value of the initial test parameter, wherein the first signal value is used for limiting the test equipment to execute the first memory read instruction;

sending a memory read instruction request to the test equipment under the condition that a return message of the test equipment for the first memory read instruction is not received and the current time is less than the timeout value;

and under the condition of receiving a second memory read instruction sent by the test equipment, sending a read completion message to the test equipment, and setting a second signal value for the configuration signal, wherein the second signal value is used for recovering the test equipment to execute the first memory read instruction.

Specifically, the configuration signal may be an M _ axis _ cq _ linear signal, and the first signal value may be 0. For example, the target order-preserving rule test item may be a test item in which memory read completion exceeds a memory read request, the host sets the value of the M _ axi _ cq _ linear signal to 0 by means of memory write, and sets the timeout value to 4 seconds, the host sends a memory read command to the test device, the memory read command triggers the test device to generate MSIX interrupt, because the value of the M _ axi _ cq _ linear signal is 0, the memory read command is locked, the memory read command is no longer executed by the test device, and the host cannot receive a read completion message returned by the test device, the memory read command sent from the host starts timing, the test device sends the memory read command to a preset address of the host in the case that the timing time is less than the timeout value, the host sends the read completion message with a preset load message to the test device after receiving the memory read command, when the test device receives the read completion message with the preset load message, the host sets the value of the M _ axis _ cq _ linear signal to a second signal value, where the second signal value may be 1, so that the test device may execute the memory read instruction.

The embodiment of the specification can test the test items of which the memory reading is finished beyond the memory reading request based on the two test instructions between the host machine and the test equipment, so that the test program is simple, and the test efficiency is improved.

In the above example, when the target order-preserving rule test item is a test item in which the memory read completion exceeds another memory read completion, a specific implementation manner of sending the test instruction to the test device according to the parameter value of the initial test parameter is as follows:

sending a first memory read instruction request to the test equipment according to the first signal value and the timeout time value of the initial test parameter, wherein the first signal value is used for limiting the test equipment from receiving a first read completion message;

under the condition that a first memory read instruction sent by the test equipment is received and the current time is less than the overtime value, returning the first read completion message to the test equipment and sending a second memory read instruction request;

and sending a second read completion message to the test equipment under the condition of receiving a second memory read instruction sent by the test equipment, and setting a second signal value for the configuration signal, wherein the second signal value is used for recovering the test equipment from receiving the first read completion message.

In an actual situation, the test device sends two memory read commands to the host, where the two memory read commands are both specific memory addresses, and the specific addresses are both written with specific values in advance, and the writing mode may be, but is not limited to, devmem. According to the first signal value and the timeout value of the initial test parameter, the host machine returns a first read completion message to the test equipment, data and an address carried by the first memory read completion message can trigger a test logic to generate MSIX interruption, the test equipment is controlled to send a second memory read instruction to a specific memory address under the condition that the first read completion message aiming at the first memory read instruction of the test equipment is not received and the current time is less than the timeout value, a second read completion message aiming at the second memory read instruction returned by the host machine can set a configuration signal to be a second signal value, and the second signal value is used for allowing the test equipment to receive the first read completion message aiming at the first memory read instruction. And the test logic sets the configuration signal to be a second signal value after analyzing the address and data fields of the second read completion message and obtaining an expected result.

Specifically, the configuration signal may be an M _ axis _ rc _ linear signal, and the first signal value may be 0. For example, the target order-preserving rule test item may be a test item for a memory read completion overriding another memory read completion read request, the host may, but is not limited to, trigger the test logic to set the value of the M _ axis _ rc _ linear signal to 0 and set the timeout value to 4 seconds by configuring the write cfg _ interrupt _ msi _ data, and then the test device sends a first memory read complete instruction to the host, where the first memory read complete instruction triggers the test device to generate the MSIX interrupt because the value of the M _ axis _ rc _ linear signal is 0 and the first memory read complete instruction is locked, so that the MSIX interrupt cannot be generated. The method comprises the steps that timing is started from a first memory read instruction sent by test equipment, the test equipment sends a second memory read instruction to a host machine under the condition that timing time is smaller than a timeout time value, the host machine sends a second read completion message with a preset load message to the test equipment, and the host machine sets the value of an M _ axis _ rc _ linear signal to be a second signal value which can be 1 under the condition that the test equipment receives the read completion message with the preset load message, so that the test equipment can receive the first read completion message, and MSIX interruption is triggered successfully.

The embodiment of the specification can test the test item of which the memory reading is finished and is beyond the test item of which the memory reading is finished based on the two test instructions between the host machine and the test equipment, so that the test program is simple, and the test efficiency is improved.

Step 210: and receiving a test result of the test equipment for the target order-preserving rule test item of the target interface according to the test instruction.

Specifically, after sending the test instruction to the test equipment according to the parameter value of the initial test parameter, the host machine may receive the test result of the target order-preserving rule test item of the target interface by the test equipment according to the test instruction.

In the above example, when the target order-preserving rule test item is a memory write override memory read completion, a memory read completion override memory read request, and a memory read completion override another memory read completion, after sending a test instruction to the test equipment according to the parameter value of the initial test parameter, the host receives a test result of the target order-preserving rule test item of the target interface by the test equipment according to the test instruction, and the specific implementation manner is as follows:

the receiving a test result of the test equipment on the target order-preserving rule test item of the target interface according to the test instruction includes:

The response information may be a signal or data sent by the test device, and the response information may be actively acquired by the host computer or actively sent by the test device, which is not limited in the embodiments of the present specification.

Specifically, the target order-preserving rule test item may be a test item in which memory writing overrides memory reading, after the corresponding test step is performed, the test device receives a read completion message returned by the host for the memory read instruction under the condition that the timing time is less than 4 seconds, and the host monitors MSIX interruption under the condition that the timing time is less than 4 seconds, and determines that memory writing overrides memory reading, thereby determining that the test result of the target order-preserving rule test item is successful.

Further, the target order-preserving rule test item may be a test item in which the memory read completion overrides the memory read request, after the corresponding test step is performed, the host receives a read completion message returned by the test device for the memory read instruction under the condition that the timing time is less than 4 seconds, and determines that the memory read completion overrides the memory write request, thereby determining that the test result of the target order-preserving rule test item is successful. The test result is determined according to whether the response message is received within the test timeout time, so that the test flow is simple.

Further, the target order-preserving rule test item may be a test item in which the memory reading completion exceeds another memory reading completion, and after the corresponding test step is performed, if the test device generates the MSIX interrupt under the condition that the timing time is less than 4 seconds, the host receives the information that the test device generates the MSIX interrupt, and determines that the memory reading completion exceeds another memory reading completion, thereby determining that the test result of the target order-preserving rule test item is successful. And determining the test result according to whether the response message is received or not, so that the test flow is simple.

In the above example, after sending a test instruction to the test device according to the parameter value of the initial test parameter under the condition that the target order-preserving rule test item is a memory write overriding another memory write and a memory read finishes overriding the memory write, the host receives the test result of the target order-preserving rule test item of the target interface according to the test instruction, and the specific implementation manner is as follows:

Specifically, the target order-preserving rule test item may be a test item in which the memory write overrides another memory write, after the corresponding test step is performed, if the test device is interrupted by the MSIX, the MSIMASK field of the ECAM space of the test device is also changed, and the host receives a message indicating that the memory write overrides another memory write, thereby determining that the test result of the target order-preserving rule test item is successful.

Further, the target order-preserving rule test item can be a test item for completing memory reading and overriding memory writing, after the corresponding test steps are performed, the host receives the information that the test equipment generates MSIX interruption, and judges that the memory reading and overriding memory writing are completed, so that the test result of the target order-preserving rule test item is determined to be successful.

In the above example, after sending the test instruction to the test device according to the parameter value of the initial test parameter under the condition that the target order-preserving rule test item is memory write-transcendental memory read, the host machine receives the test result of the test device on the target order-preserving rule test item of the target interface according to the test instruction, and the specific implementation manner is as follows:

the receiving a test result of the test equipment for the target order-preserving rule test item of the target interface according to the test instruction comprises:

Specifically, the target order-preserving rule test item may be a test item for memory write-override memory read, after the corresponding test step is performed, the host receives a read completion message returned by the test device for the last memory read instruction sent when the timing time is less than 4 seconds, and if the read completion message is a preset read completion message, it is determined that the memory write-override memory read is performed, thereby determining that the test result of the target order-preserving rule test item is successful. And determining the test result according to whether the response message is received or not and whether the response message is a preset response condition or not, so that the accuracy of the test result is improved.

The following describes the target interface testing method further by taking an application of the target interface testing method provided in this specification to a server as an example, with reference to fig. 5. Fig. 5 shows another flowchart of a target interface testing method provided in an embodiment of the present specification, which specifically includes the following steps.

Step 502: and determining at least one initial order-preserving rule test item of the PCIe interface according to the communication interface in the FPGA.

Specifically, the FPGA includes a PCIe core, a communication interface of the FPGA includes cc, cq, rq, and rc, and the initial order-preserving rule test item can be determined through the cc, cq, rq, and rc interfaces, and includes: the memory write overrides the test items of the memory read completion, the memory read completion overrides the memory read request, the memory write completes the super configuration write, the memory read completion overrides the memory write, the memory write overrides the configuration write and the memory write overrides the memory read.

Step 504: and determining a target order-preserving rule test item from at least one initial order-preserving rule test item according to a preset requirement.

Specifically, the preset requirement may be two target order-preserving rule test items for performing the memory write overriding memory read completion and the memory read overriding memory read completion requests.

Step 506: determining a configuration signal and test timeout time of the FPGA corresponding to the target order-preserving rule test item, setting a first signal value for the configuration signal, and determining the timeout time value of the test timeout time.

Specifically, the target order-preserving rule test item may be a test item in which the memory write overrides the memory read completion, and the server searches the configuration signal, the first signal value, and the timeout time value of the test timeout time of the test item in which the memory write overrides the memory read completion from the database. The database may be local or remote.

Step 508: and sending a test instruction to the FPGA according to the first signal value and the timeout time value of the initial test parameter.

Step 510: and receiving a test result of the target order-preserving rule test item of the PCIe interface by the FPGA according to the test instruction within the test overtime.

Specifically, a test item in which memory writing is completed over memory reading is performed: the server sets the value of the M _ axis _ rc _ linear signal to 0 in a memory writing mode, and sets the timeout value to 4 seconds, the server sends a memory read instruction request to the FPGA, the FPGA sends a memory read instruction to the server after receiving the memory read instruction request, because the M _ axis _ rc _ linear signal is set to 0, after the memory read instruction is executed by the server, the read completion sent by the server is locked, the FPGA cannot receive a read completion message returned by the server, the FPGA no longer sends the memory read instruction to the server, timing is started from the memory read instruction sent by the FPGA, the server sends a memory write instruction to the FPGA under the condition that the timing time is less than the timeout value, and sets the value of the M _ axis _ rc _ linear signal to a second signal value in a memory writing mode, and the second signal value can be 1, so that the FPGA receives the read completion message. And the FPGA receives a read completion message returned by the server aiming at the memory read instruction under the condition that the timing time is less than 4 seconds, the server monitors MSIX interruption under the condition that the timing time is less than 4 seconds, and the memory write-override memory read completion is judged, so that the test result of the target order-preserving rule test item is determined to be successful.

In specific implementation, the test items of the memory read completion surpassing the memory read request are carried out: the method includes the steps that a server sets the value of an M _ axis _ cq _ linear signal to be 0 in a memory writing mode, and sets a timeout value to be 4 seconds, the server sends a memory reading instruction to an FPGA, the memory reading instruction can trigger the FPGA to generate MSIX interruption, because the value of the M _ axis _ cq _ linear signal is 0, the memory reading instruction is locked, the memory reading instruction is not executed by the FPGA any more, and the server cannot receive a read completion message returned by the FPGA, the FPGA sends the memory reading instruction to a preset address of the server, the server sends the read completion message with a preset load message to the FPGA after receiving the memory reading instruction, and under the condition that the FPGA receives the read completion message with the preset load message, the server sets the value of the M _ axis _ cq _ linear signal to be a second signal value, and the second signal value can be 1, so that the FPGA can execute the memory reading instruction. And under the condition that the timing time is less than 4 seconds, the server receives a read completion message returned by the FPGA aiming at the memory read instruction, and judges that the memory read completion exceeds the memory write request, thereby determining that the test result of the target order-preserving rule test item is successful.

It should be noted that, the order of testing each target order-preserving rule test item is not sequential, a test for overriding a memory read request may be completed by a memory read first, a test for overriding a memory read completion may also be performed by a memory write first, and an embodiment of the present specification is not limited.

In the embodiment of the specification, the order-preserving rule of the PCIe interface can be tested only by using four communication interfaces of the FPGA, so that the test of the order-preserving rule of the PCIe interface becomes feasible, the test cost is low, and the test difficulty is reduced.

Corresponding to the above method embodiment, the present specification further provides an embodiment of a target interface testing apparatus, and fig. 6 shows a schematic structural diagram of a target interface testing apparatus provided in an embodiment of the present specification. As shown in fig. 6, the apparatus includes:

an initial item determination module 602 configured to determine at least one initial order-preserving rule test item of a target interface according to a communication interface in the test device;

a target item determination module 604 configured to determine a target order-preserving rule test item from the at least one initial order-preserving rule test item according to a preset requirement;

a parameter determining module 606 configured to determine an initial test parameter corresponding to the target order-preserving rule test item and a parameter value of the initial test parameter;

a test module 608 configured to send a test instruction to the test device according to a parameter value of the initial test parameter;

the receiving module 610 is configured to receive a test result of the test device on the target order-preserving rule test item of the target interface according to the test instruction.

Optionally, the parameter determining module 606 is further configured to:

Optionally, the testing module 608 is further configured to:

and when a return message of the test equipment for the first memory write instruction is not received, sending a second memory write instruction to the test equipment, and setting a second signal value for the configuration signal, wherein the second signal value is used for recovering the test equipment to execute the first memory write instruction.

Optionally, the testing module 608 is further configured to:

Optionally, the receiving module 610 is further configured to:

The foregoing is a schematic diagram of a target interface testing apparatus according to an embodiment of the present disclosure. It should be noted that the technical solution of the target interface testing apparatus and the technical solution of the target interface testing method belong to the same concept, and details that are not described in detail in the technical solution of the target interface testing apparatus can be referred to the description of the technical solution of the target interface testing method.

FIG. 7 illustrates a block diagram of a computing device 700 provided in accordance with one embodiment of the present description. The components of the computing device 700 include, but are not limited to, memory 710 and a processor 720. Processor 720 is coupled to memory 710 via bus 730, and database 750 is used to store data.

Computing device 700 also includes access device 740, access device 740 enabling computing device 700 to communicate via one or more networks 760. Examples of such networks include the Public Switched Telephone Network (PSTN), a Local Area Network (LAN), a Wide Area Network (WAN), a Personal Area Network (PAN), or a combination of communication networks such as the internet. Access device 740 may include one or more of any type of network interface, e.g., a Network Interface Card (NIC), wired or wireless, such as an IEEE802.11 Wireless Local Area Network (WLAN) wireless interface, a worldwide interoperability for microwave access (Wi-MAX) interface, an ethernet interface, a Universal Serial Bus (USB) interface, a cellular network interface, a bluetooth interface, a Near Field Communication (NFC) interface, and so forth.

In one embodiment of the present description, the above-described components of computing device 700, as well as other components not shown in FIG. 7, may also be connected to each other, such as by a bus. It should be understood that the block diagram of the computing device architecture shown in FIG. 7 is for purposes of example only and is not limiting as to the scope of the present description. Those skilled in the art may add or replace other components as desired.

Computing device 700 may be any type of stationary or mobile computing device, including a mobile computer or mobile computing device (e.g., tablet, personal digital assistant, laptop, notebook, netbook, etc.), a mobile phone (e.g., smartphone), a wearable computing device (e.g., smartwatch, smartglasses, etc.), or other type of mobile device, or a stationary computing device such as a desktop computer or PC. Computing device 700 may also be a mobile or stationary server.

Wherein the processor 720 is configured to execute computer-executable instructions that, when executed by the processor, implement the steps of the target interface testing method described above.

The foregoing is a schematic representation of a computing device in accordance with embodiments of the present disclosure. It should be noted that the technical solution of the computing device and the technical solution of the target interface testing method belong to the same concept, and details that are not described in detail in the technical solution of the computing device can be referred to the description of the technical solution of the target interface testing method.

An embodiment of the present specification also provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the steps of the target interface testing method described above.

The foregoing is an illustrative version of a computer-readable storage medium of the embodiments of the present specification. It should be noted that the technical solution of the storage medium belongs to the same concept as the technical solution of the target interface testing method, and details that are not described in detail in the technical solution of the storage medium can be referred to the description of the technical solution of the target interface testing method.

An embodiment of the present specification further provides a computer program, wherein when the computer program is executed in a computer, the computer program is used to make the computer execute the steps of the target interface testing method.

The foregoing is an illustrative version of a computer program that is embodied by the present description. It should be noted that the technical solution of the computer program and the technical solution of the target interface testing method belong to the same concept, and details that are not described in detail in the technical solution of the computer program can be referred to the description of the technical solution of the target interface testing method.

The foregoing description has been directed to specific embodiments of this disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

The computer instructions comprise computer program code which may be in source code form, object code form, an executable file or some intermediate form, or the like. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice.

It should be noted that, for the sake of simplicity, the foregoing method embodiments are described as a series of acts, but those skilled in the art should understand that the present embodiment is not limited by the described acts, because some steps may be performed in other sequences or simultaneously according to the present embodiment. Further, those skilled in the art should also appreciate that the embodiments described in this specification are preferred embodiments and that acts and modules referred to are not necessarily required for an embodiment of the specification.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The preferred embodiments of the present specification disclosed above are intended only to aid in the description of the specification. Alternative embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the embodiments and the practical application, to thereby enable others skilled in the art to best understand and utilize the embodiments. The specification is limited only by the claims and their full scope and equivalents.

Claims

1. A target interface test method is applied to a host machine and comprises the following steps:

2. The method of claim 1, wherein the determining initial test parameters corresponding to the target order-preserving rule test items and parameter values of the initial test parameters comprises:

3. The method of claim 1, wherein the determining initial test parameters corresponding to the target order-preserving rule test items and parameter values of the initial test parameters comprises:

4. The method of claim 3, the sending test instructions to the test device according to the parameter values of the initial test parameters comprising:

5. The method of claim 2, the sending test instructions to the test device according to the parameter values of the initial test parameters comprising:

6. The method of claim 3, the sending test instructions to the test device according to the parameter values of the initial test parameters comprising:

7. The method of claim 2, the sending test instructions to the test device according to the parameter values of the initial test parameters comprising:

8. The method of claim 3, the sending test instructions to the test device according to the parameter values of the initial test parameters comprising:

9. The method of claim 3, the sending test instructions to the test device according to the parameter values of the initial test parameters comprising:

10. The method of any one of claims 4, 6, 8, and 9, wherein the receiving a test result of the test device testing an item of a target order-preserving rule of the target interface according to the test instruction comprises:

11. The method according to any one of claims 5 and 7, wherein the receiving of the test result of the test device on the target order-preserving rule test item of the target interface according to the test instruction comprises:

12. A target interface test apparatus, comprising:

the testing module is configured to send a testing instruction to the testing equipment according to the parameter value of the initial testing parameter;

13. A computing device, comprising:

a memory and a processor;

the memory is configured to store computer-executable instructions and the processor is configured to execute the computer-executable instructions, which when executed by the processor implement the steps of the target interface testing method of any one of claims 1 to 11.

14. A computer readable storage medium storing computer executable instructions which, when executed by a processor, perform the steps of the target interface testing method of any one of claims 1 to 11.