CN114489802A

CN114489802A - Data processing device, data processing method and related product

Info

Publication number: CN114489802A
Application number: CN202011272683.8A
Authority: CN
Inventors: 不公告发明人
Original assignee: Cambricon Technologies Corp Ltd
Current assignee: Cambricon Technologies Corp Ltd
Priority date: 2020-11-13
Filing date: 2020-11-13
Publication date: 2022-05-13

Abstract

The present disclosure discloses a data processing apparatus, a data processing method, and a related product. The data processing apparatus may be implemented as a computing apparatus included in a combined processing apparatus, which may also include interface apparatus and other processing apparatus. The computing device interacts with other processing devices to jointly complete computing operations specified by a user. The combined processing device may further comprise a storage device connected to the computing device and the other processing device, respectively, for storing data of the computing device and the other processing device. Aspects of the present disclosure provide an instruction system involving tensor data that may increase processing flexibility and improve processing efficiency of a machine.

Description

Data processing device, data processing method and related product

Technical Field

The present disclosure relates to the field of processors, and in particular, to a data processing apparatus, a data processing method, a chip, and a board card.

Background

The instruction system is an interface for the interaction of computer software and hardware, and is a very important part in the structure of a computer system. With the continuous development of artificial intelligence technology, the amount of data and the data dimension which need to be processed are increasing. Therefore, how to reasonably and scientifically design the instruction can not only provide enough information, but also save the storage space, shorten the instruction fetching time and improve the performance of the machine, which is an important problem in the instruction design.

Disclosure of Invention

To address one or more of the technical problems mentioned above, the present disclosure proposes, in various aspects, an instruction system involving tensor data. By the instruction system of the present disclosure, processing flexibility may be increased, thereby increasing the processing efficiency of the machine.

In a first aspect, the present disclosure provides a data processing apparatus comprising a control unit, an address calculation unit, and an execution unit, wherein: the control unit is configured to obtain a decoded processing instruction, where the processing instruction includes an opcode and an operand that includes at least one flag bit for indicating a source of information for calculating a data address during execution of the processing instruction; the address calculation unit is configured to calculate the data address using a corresponding information source according to the indication of the flag bit; and the execution unit is configured to execute the processing instruction according to the data address and the operation code.

In a second aspect, the present disclosure provides a chip comprising the data processing apparatus of any of the embodiments of the first aspect.

In a third aspect, the present disclosure provides a board card comprising the chip of any of the embodiments of the second aspect.

In a fourth aspect, the present disclosure provides a data processing method, the method comprising: obtaining a decoded processing instruction, wherein the processing instruction comprises an operation code and an operand, and the operand comprises at least one flag bit and is used for indicating an information source of a calculation data address during the execution of the processing instruction; calculating the data address by using a corresponding information source according to the indication of the flag bit; and executing the processing instruction according to the data address and the operation code.

By the data processing device, the data processing method, the chip and the board card, the embodiment of the disclosure adds at least one instruction field in the instruction to identify the source of address calculation in the instruction execution process, so that the flexibility of processing can be increased, thereby improving the processing efficiency of the machine.

Drawings

The above and other objects, features and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:

FIG. 1 shows a schematic diagram of a data storage space according to an embodiment of the present disclosure;

FIG. 2 shows a schematic diagram of data chunking in a data storage space, according to an embodiment of the present disclosure;

FIG. 3 shows a schematic block diagram of a data processing apparatus according to an embodiment of the present disclosure;

FIG. 4 shows a schematic flow chart diagram of a data processing method according to an embodiment of the present disclosure;

FIG. 5 shows a block diagram of a combined treatment device according to an embodiment of the disclosure; and

fig. 6 shows a schematic structural diagram of a board card according to an embodiment of the disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, not all embodiments of the present disclosure. All other embodiments, which can be derived by one skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the scope of protection of the present disclosure.

It should be understood that the terms "first," "second," "third," and "fourth," etc. as may be used in the claims, the specification, and the drawings of the present disclosure, are used for distinguishing between different objects and not for describing a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

Computers process various data by executing instructions. To indicate the source of the data, the destination of the operation results, and the operation performed, an instruction typically contains the following information:

(1) the Operation Code (OP) is used to indicate the Operation (e.g., add, subtract, multiply, divide, data transfer, etc.) to be performed by the instruction, and specifies the nature and function of the Operation. A computer may have tens to hundreds of instructions, each with a corresponding opcode, which the computer recognizes to perform different operations.

(2) And the operand is used for describing the operation object of the instruction. Operands may relate to the data type, memory access address, addressing mode, etc. of the operated-on object. The operand may be directly given to the operated-on object, or indicate a memory address or a register address (i.e., a register name) of the operated-on object.

The instructions of conventional processors are designed to perform basic single data scalar operations. Here, a single data scalar operation refers to an instruction where each operand is a scalar datum. However, with the development of artificial intelligence technology, in tasks such as image processing and pattern recognition, the oriented operands are often data types of multidimensional vectors (i.e., tensor data), and the use of only scalar operations does not make hardware efficiently complete the operation task. In addition, due to the multi-dimensional nature of tensor data, sometimes only a portion of the data in the tensor data needs to be manipulated, rather than for the entire tensor data. Therefore, how to efficiently execute multidimensional tensor data processing is also an urgent problem to be solved in the current computing field.

In an embodiment of the present disclosure, an instruction system is provided in which at least one instruction field is added to an operand of a processing instruction to indicate a source of information for calculating a data address during execution of the processing instruction. By adding an instruction field to indicate the source of information used to compute the data address, the data object on which the processing instruction operates can be indicated more flexibly. For example, whether the operated-on data is the entire tensor data or the partial data of the tensor data may be indicated by the instruction field. Therefore, by configuring a new instruction domain, the programming mode of the software side can be more flexible and more efficient.

The instruction field may be a flag bit indicating the source of any of the following information: a parameter of the processing instruction; or a parameter of a descriptor in the processing instruction, wherein the descriptor is used to indicate information of tensor data associated with the processing instruction. In other words, the flag bit may identify whether the address calculation employs information in the instruction (parameters of the instruction) or information in the descriptor (parameters of the descriptor) during execution of the instruction. The value of the flag bit may be "0" or "1". For example, the flag bit takes a value of "0", indicating that the parameter of the instruction is adopted; the flag bit takes the value of '1', and indicates the parameters of the adopted descriptors; and vice versa.

In some embodiments of the present disclosure, the flag bits may indicate the source of information used to compute the data address at different granularities. Due to the multidimensional characteristic of tensor data, sometimes the whole tensor data needs to be operated, and sometimes only part of the tensor data needs to be operated, so that information sources for calculating data addresses can be indicated according to operation needs and different granularities. In embodiments of the present disclosure, the granularity may be the entire tensor data, one or more dimensions of the tensor data, parameters of the entire tensor, or parameters of one or more dimensions of the tensor data, among others.

The following description is given by taking tensor plus operation instructions as examples, and examples of flag bit indications of various granularities are given. The decoded tensor plus operation instruction includes an opcode Add and operands, the operands relating to at least three tensors: input tensor 1, input tensor 2, and output tensors, which are three-dimensional data, may be indicated by corresponding descriptors. The information for calculating the data addresses of the tensors may include various parameters, which are not assumed to be a parameter a and a parameter B. These parameters may be included in the processing instruction as parameters of the processing instruction or may be included in the corresponding descriptor of the processing instruction as parameters of the descriptor.

In one possible implementation, the flag bits may indicate the source of information for the data address used to compute the entire tensor data. In this implementation, the flag bits may indicate, for example, the source of information for the data addresses of the various tensor data involved in processing the instruction.

Taking the above tensor plus operation instruction as an example, in the present implementation, the tensor plus operation instruction may add the following instruction fields:

inputting a tensor 1 flag bit; inputting a tensor 2 flag bit; and outputting tensor flag bits.

These flag bits are used to indicate the source of information for computing the data addresses of the various tensors. For example, the address calculation is to use tensor plus information in the operation instruction (parameters of the instruction) or information in respective descriptors (for example, parameters of a descriptor of input tensor 1, parameters of a descriptor of input tensor 2, and parameters of a descriptor of output tensor).

In another possible implementation, the flag bits may indicate the source of information for calculating the data addresses for the various dimensions of the tensor data. Still taking the above tensor plus operation instruction as an example, in the present implementation, the tensor plus operation instruction may add the following instruction fields:

inputting a flag bit of 1 dimension 1 of tensor; inputting a flag bit of 1 dimension 2 of tensor; inputting a flag bit of 1 dimension 3 of tensor;

inputting a flag bit of tensor 2 dimension 1; inputting a flag bit of tensor 2 dimension 2; inputting a flag bit of tensor 2 and dimension 3;

outputting a flag bit of tensor dimension 1; outputting a flag bit of tensor dimension 2; and outputting a flag bit of the tensor dimension 3.

These flag bits are used to indicate the source of information for computing the data addresses for each dimension of each tensor. By using flag bits at this granularity of tensor dimensions, data operated on by instructions can also be accessed based on this granularity of dimensions, thereby increasing processing flexibility.

In yet another possible implementation, the flag bits may indicate the source of information for calculating different parameters of the data address. The parameters used for calculating the data address may include different forms of parameters, which may include, for example, at least one of: an offset of the entire or partial storage area of tensor data; and the size of the entire or partial storage area of the tensor data. The meaning of each parameter will be described in detail later with reference to the accompanying drawings.

inputting a flag bit of a parameter A in tensor 1; inputting a flag bit of a parameter B in tensor 1;

inputting a flag bit of a parameter A in tensor 2; inputting a flag bit of a parameter B in tensor 2;

outputting a flag bit of a parameter A in the tensor; and outputting a flag bit of the parameter B in the tensor.

These flag bits are used to indicate the source of information for the various parameters for calculating the data addresses for the various tensors. In these implementations, the objects of the instruction operation can be flexibly set according to the parameters for calculating the data address. In the above example, the parameter a may be an offset, for example, and the parameter B may be a size, for example.

In yet another possible implementation, the flag bits may indicate the source of information for different parameters of the data addresses used to compute the dimensions of the tensor data. In this implementation, the information source for computing the data address can be set from both the tensor data dimension and the parameter for computing the address.

inputting a flag bit of a parameter A in dimension 1 of tensor 1; inputting a flag bit of a parameter B in dimension 1 of tensor 1;

inputting a flag bit of a parameter A in a dimension 2 of tensor 1; inputting a flag bit of a parameter B in dimension 2 of tensor 1;

inputting a flag bit of a parameter A in dimension 3 of tensor 1; inputting a flag bit of a parameter B in dimension 3 of tensor 1;

inputting a flag bit of a parameter A in dimension 1 of tensor 2; inputting a flag bit of a parameter B in dimension 1 of tensor 2;

inputting a flag bit of a parameter A in dimension 2 of tensor 2; inputting a flag bit of a parameter B in a dimension 2 of tensor 2;

inputting a flag bit of a parameter A in dimension 3 of tensor 2; inputting a flag bit of a parameter B in dimension 3 of tensor 2;

outputting a flag bit of the parameter A in the tensor dimension 1; outputting a flag bit of a parameter B in a tensor dimension 1;

outputting a flag bit of the parameter A in the tensor dimension 2; outputting a flag bit of a parameter B in the tensor dimension 2;

outputting a flag bit of a parameter A in a tensor dimension 3; and outputting a flag bit of the parameter B in the tensor dimension 3.

Those of ordinary skill in the art will appreciate that although individual features are described in various implementations in a separate manner, various combinations of such features may be made without conflict and still be within the scope of the present disclosure. For example, the flag bits of the above granularities may be used in any combination, such as identifying the information sources of the data addresses of its respective dimensions for the input tensor 1 and the input tensor 2, respectively, and the information sources of the data addresses of its entirety for the output tensor. Those skilled in the art can construct various combination embodiments based on the disclosure of the present disclosure.

As can be seen from the above description, embodiments of the present disclosure provide an instruction system, in which at least one flag bit is included in an operand of an instruction, and by which a source of information for calculating a data address during instruction execution can be flexibly set, so that a data object operated by a processing instruction can be more flexibly indicated, which facilitates a more flexible and efficient programming manner on a software side. Various possible implementations of descriptors for indicating tensor data information are described in detail below in conjunction with the figures.

Tensors may contain multiple forms of data composition. The tensors may be of different dimensions, e.g. a scalar may be regarded as a 0-dimensional tensor, a vector may be regarded as a 1-dimensional tensor, and a matrix may be a 2-or higher-than-2-dimensional tensor. The shape of the tensor includes information such as the dimensions of the tensor, the sizes of the dimensions of the tensor, and the like. For example, for a three-dimensional tensor:

x₃＝[[[1，2，3]，[4，5，6]]；[[7，8，9]，[10，11，12]]]

the shape or dimension of the tensor can be expressed as X₃That is, the tensor is expressed as a three-dimensional tensor by three parameters, and the size of the tensor in the first dimension is 2, the size of the tensor in the second dimension is 2, and the size of the tensor in the third dimension is 3. When storing tensor data in a memory, the shape of the tensor data cannot be determined according to the data address (or the storage area), and further, related information such as the correlation among a plurality of tensor data cannot be determined, which results in low access efficiency of the processor to the tensor data.

In one possible implementation, the shape of the N-dimensional tensor data may be indicated by a descriptor, N being a positive integer, e.g., N ═ 1, 2, or 3, or zero. The three-dimensional tensor in the above example can be represented by descriptor (2,2, 3). It should be noted that the present disclosure is not limited to the way the descriptors indicate the tensor shape.

In one possible implementation, the value of N may be determined according to the dimension (also referred to as the order) of the tensor data, or may be set according to the usage requirement of the tensor data. For example, when the value of N is 3, the tensor data is three-dimensional tensor data, and the descriptor may be used to indicate the shape (e.g., offset, size, etc.) of the three-dimensional tensor data in three dimensional directions. It should be understood that the value of N can be set by those skilled in the art according to practical needs, and the disclosure does not limit this.

Although tensor data can be multidimensional, there is a correspondence between tensors and storage on memory because the layout of memory is always one-dimensional. Tensor data is typically allocated in contiguous memory space, i.e., the tensor data can be one-dimensionally expanded (e.g., line first) for storage on memory.

This relationship between the tensor and the underlying storage may be represented by an offset of a dimension (offset), a size of a dimension (size), a step size of a dimension (stride), and so on. The offset of a dimension refers to the offset in that dimension from a reference position. The size of a dimension refers to the size of the dimension, i.e., the number of elements in the dimension. The step size of a dimension refers to the interval between adjacent elements in the dimension, for example, the step size of the above three-dimensional tensor is (6,3,1), that is, the step size of the first dimension is 6, the step size of the second dimension is 3, and the step size of the third dimension is 1.

FIG. 1 shows a schematic diagram of a data storage space according to an embodiment of the present disclosure. As shown in fig. 1, the data storage space 21 stores a two-dimensional data in a line-first manner, which can be represented by (X, Y) (wherein the X-axis is horizontally to the right and the Y-axis is vertically to the bottom). The size in the X-axis direction (the size of each row, or the total number of columns) is ori _ X (not shown), the size in the Y-axis direction (the total number of rows) is ori _ Y (not shown), and the starting address PA _ start (base address) of the data storage space 21 is the physical address of the first data block 22. The data block 23 is partial data in the data storage space 21, and its offset amount 25 in the X-axis direction is denoted as offset _ X, the offset amount 24 in the Y-axis direction is denoted as offset _ Y, the size in the X-axis direction is denoted as size _ X, and the size in the Y-axis direction is denoted as size _ Y.

In a possible implementation manner, when the descriptor is used to define the data block 23, the data reference point of the descriptor may use the first data block of the data storage space 21, and the reference address of the descriptor may be agreed as the starting address PA _ start of the data storage space 21. The content of the descriptor of the data block 23 may then be determined in combination with the size ori _ X of the data storage space 21 in the X axis, the size ori _ Y in the Y axis, and the offset amount offset _ Y of the data block 23 in the Y axis direction, the offset amount offset _ X in the X axis direction, the size _ X in the X axis direction, and the size _ Y in the Y axis direction.

In one possible implementation, the content of the descriptor can be represented using the following formula (1):

it should be understood that although the content of the descriptor is represented by a two-dimensional space in the above examples, a person skilled in the art can set the specific dimension of the content representation of the descriptor according to practical situations, and the disclosure does not limit this.

In one possible implementation manner, a reference address of the data reference point of the descriptor in the data storage space may be appointed, and based on the reference address, the content of the descriptor of the tensor data is determined according to the positions of at least two vertexes located at diagonal positions in the N dimensional directions relative to the data reference point.

For example, a reference address PA _ base of a data reference point of the descriptor in the data storage space may be agreed. For example, one data (for example, data with position (2, 2)) may be selected as a data reference point in the data storage space 21, and the physical address of the data in the data storage space may be used as the reference address PA _ base. The content of the descriptor of the data block 23 in fig. 1 can be determined from the positions of the two vertices of the diagonal position relative to the data reference point. First, the positions of at least two vertices of the diagonal positions of the data block 23 relative to the data reference point are determined, for example, the positions of the diagonal position vertices relative to the data reference point in the top-left-to-bottom-right direction are used, wherein the relative position of the top-left vertex is (x _ min, y _ min), and the relative position of the bottom-right vertex is (x _ max, y _ max), and then the content of the descriptor of the data block 23 can be determined according to the reference address PA _ base, the relative position of the top-left vertex (x _ min, y _ min), and the relative position of the bottom-right vertex (x _ max, y _ max).

In one possible implementation, the content of the descriptor (with reference to PA _ base) can be represented using the following equation (2):

it should be understood that although the above examples use the vertex of two diagonal positions of the upper left corner and the lower right corner to determine the content of the descriptor, the skilled person can set the specific vertex of at least two vertices of the diagonal positions according to the actual needs, and the disclosure does not limit this.

In one possible implementation, the content of the descriptor of the tensor data can be determined according to the reference address of the data reference point of the descriptor in the data storage space and the mapping relation between the data description position and the data address of the tensor data indicated by the descriptor. For example, when tensor data indicated by the descriptor is three-dimensional space data, the mapping relationship between the data description position and the data address may be defined by using a function f (x, y, z).

In one possible implementation, the content of the descriptor can be represented using the following equation (3):

in one possible implementation, the descriptor is further used to indicate an address of the N-dimensional tensor data, wherein the content of the descriptor further includes at least one address parameter representing the address of the tensor data, for example, the content of the descriptor may be the following formula (4):

where PA is the address parameter. The address parameter may be a logical address or a physical address. When the descriptor is analyzed, the PA may be used as any one of a vertex, a middle point, or a preset point of the vector shape, and the corresponding data address may be obtained by combining the shape parameters in the X direction and the Y direction.

In one possible implementation, the address parameter of the tensor data comprises a reference address of a data reference point of the descriptor in a data storage space of the tensor data, and the reference address comprises a start address of the data storage space.

In one possible implementation, the descriptor may further include at least one address parameter representing an address of the tensor data, for example, the content of the descriptor may be the following equation (5):

wherein PA _ start is a reference address parameter, which is not described again.

It should be understood that, the mapping relationship between the data description location and the data address can be set by those skilled in the art according to practical situations, and the disclosure does not limit this.

In a possible implementation manner, a default base address can be set in a task, the base address is used by descriptors in instructions in the task, and shape parameters based on the base address can be included in the descriptor contents. This base address may be determined by setting an environmental parameter for the task. The relevant description and usage of the base address can be found in the above embodiments. In this implementation, the contents of the descriptor can be mapped to the data address more quickly.

In one possible implementation, the reference address may be included in the content of each descriptor, and the reference address of each descriptor may be different. Compared with the mode of setting a common reference address by using the environment parameters, each descriptor in the mode can describe data more flexibly and use a larger data address space.

In one possible implementation, the data address of the data in the data storage space corresponding to the operand of the processing instruction may be determined from the contents of the descriptor. The calculation of the data address is automatically completed by hardware, and the calculation methods of the data address are different when the content of the descriptor is represented in different ways. The present disclosure does not limit the specific calculation method of the data address.

For example, the content of the descriptor in the operand is expressed by formula (1), the amount of shift of the tensor data indicated by the descriptor in the data storage space is offset _ x and offset _ y, respectively, and the size is size _ x × size _ y, then the starting data address PA1 of the tensor data indicated by the descriptor in the data storage space is_(x,y)The following equation (6) may be used to determine:

PA1_(x,y)＝PA_start+(offset_y-1)*ori_x+offset_x (6)

the data start address PA1 determined according to the above equation (6)_(x,y)In combination with the offsets offset _ x and offset _ y and the sizes size _ x and size _ y of the storage area, the storage area of the tensor data indicated by the descriptor in the data storage space can be determined.

In a possible implementation manner, when the operand further includes a data description location for the descriptor, a data address of data corresponding to the operand in the data storage space may be determined according to the content of the descriptor and the data description location. In this way, a portion of the data (e.g., one or more data) in the tensor data indicated by the descriptor may be processed.

For example, the content of the descriptor in the operand is expressed by formula (2), the tensor data indicated by the descriptor are respectively offset by offset _ x and offset _ y in the data storage space, the size is size _ x × size _ y, and the data description position for the descriptor included in the operand is (x)_q，y_q) Then, the data address PA2 of the tensor data indicated by the descriptor in the data storage space_(x,y)The following equation (7) may be used to determine:

PA2_(x,y)＝PA_start+(offset_y+y_q-1)*ori_x+(offset_x+x_q) (7)

in one possible implementation, the descriptor may indicate the data of the block. The data partitioning can effectively accelerate the operation speed and improve the processing efficiency in many applications. For example, in graphics processing, convolution operations often use data partitioning for fast arithmetic processing.

FIG. 2 shows a schematic diagram of data chunking in a data storage space according to an embodiment of the present disclosure. As shown in FIG. 2, the data storage space 200 also stores two-dimensional data in a row-first manner, which may be represented by (X, Y) (where the X-axis is horizontally to the right and the Y-axis is vertically down). The dimension in the X-axis direction (the dimension of each row, or the total number of columns) is ori _ X (not shown), and the dimension in the Y-axis direction (the total number of rows) is ori _ Y (not shown). Unlike the tensor data of fig. 1, the tensor data stored in fig. 2 includes a plurality of data blocks.

In this case, the descriptor requires more parameters to represent the data blocks. Taking the X axis (X dimension) as an example, the following parameters may be involved: ori _ x, x.tile.size (size in tile 202), x.tile.stride (step size in tile 204, i.e. the distance between the first point of the first tile and the first point of the second tile), x.tile.num (number of tiles, shown as 3 tiles in fig. 2), x.stride (overall step size, i.e. the distance from the first point of the first row to the first point of the second row), etc. Other dimensions may similarly include corresponding parameters.

In one possible implementation, the descriptor may also indicate compression information of the relevant tensor data. For example, the descriptor may include a compression flag, such as compress _ en, that is used to mark whether the associated tensor data is compressed. Alternatively or additionally, the descriptor may also indicate the compression or encoding employed. For example, the descriptor may record the compression mode compress _ base.

In one possible implementation, the descriptor may include an identification of the descriptor and/or the content of the descriptor. The identifier of the descriptor is used to distinguish the descriptor, for example, the identifier of the descriptor may be its number; the content of the descriptor may include at least one shape parameter representing a shape of the tensor data. For example, the tensor data is 3-dimensional data, of three dimensions of the tensor data, in which shape parameters of two dimensions are fixed, the content of the descriptor thereof may include a shape parameter representing another dimension of the tensor data.

In one possible implementation, the identity and/or content of the descriptor may be stored in a descriptor storage space (internal memory), such as a register, an on-chip SRAM or other media cache, or the like. The tensor data indicated by the descriptors may be stored in a data storage space (internal or external memory), such as an on-chip cache or an off-chip memory, etc. The present disclosure does not limit the specific locations of the descriptor storage space and the data storage space.

In one possible implementation, the identity, content, and tensor data indicated by the descriptors may be stored in the same block of internal memory, e.g., a contiguous block of on-chip cache may be used to store the relevant content of the descriptors at addresses ADDR0-ADDR 1023. The addresses ADDR0-ADDR63 can be used as a descriptor storage space to store the identifier and content of the descriptor, and the addresses ADDR64-ADDR1023 can be used as a data storage space to store tensor data indicated by the descriptor. In the descriptor memory space, the identifiers of the descriptors may be stored with addresses ADDR0-ADDR31, and addresses ADDR32-ADDR 63. It should be understood that the address ADDR is not limited to 1 bit or one byte, and is used herein to mean one address, which is a unit of one address. The descriptor storage space, the data storage space, and their specific addresses may be determined by those skilled in the art in practice, and the present disclosure is not limited thereto.

In one possible implementation, the identity of the descriptors, the content, and the tensor data indicated by the descriptors may be stored in different areas of internal memory. For example, a register may be used as a descriptor storage space, the identifier and the content of the descriptor may be stored in the register, an on-chip cache may be used as a data storage space, and tensor data indicated by the descriptor may be stored.

In one possible implementation, where a register is used to store the identity and content of a descriptor, the number of the register may be used to represent the identity of the descriptor. For example, when the number of the register is 0, the identifier of the descriptor stored therein is set to 0. When the descriptor in the register is valid, an area in the buffer space can be allocated for storing the tensor data according to the size of the tensor data indicated by the descriptor.

In one possible implementation, the identity and content of the descriptors may be stored in an internal memory and the tensor data indicated by the descriptors may be stored in an external memory. For example, the identification and content of the descriptors can be stored on-chip, and the tensor data indicated by the descriptors can be stored off-chip.

In one possible implementation, the data address of the data storage space corresponding to each descriptor may be a fixed address. For example, separate data storage spaces may be divided for tensor data, each of which has a one-to-one correspondence with descriptors at the start address of the data storage space. In this case, a circuit or module (e.g., an entity external to the disclosed computing device) responsible for parsing the computation instruction may determine the data address in the data storage space of the data corresponding to the operand from the descriptor.

In one possible implementation, when the data address of the data storage space corresponding to the descriptor is a variable address, the descriptor may be further used to indicate an address of the N-dimensional tensor data, wherein the content of the descriptor may further include at least one address parameter indicating the address of the tensor data. For example, the tensor data is 3-dimensional data, when the descriptor points to an address of the tensor data, the content of the descriptor may include one address parameter indicating the address of the tensor data, such as a starting physical address of the tensor data, or may include a plurality of address parameters of the address of the tensor data, such as a starting address of the tensor data + an address offset, or the tensor data is based on the address parameters of each dimension. The address parameters can be set by those skilled in the art according to practical needs, and the disclosure does not limit this.

In one possible implementation, the address parameter of the tensor data may include a reference address of a data reference point of the descriptor in a data storage space of the tensor data. Wherein the reference address may be different according to a variation of the data reference point. The present disclosure does not limit the selection of data reference points.

In one possible implementation, the base address may comprise a start address of the data storage space. When the data reference point of the descriptor is the first data block of the data storage space, the reference address of the descriptor is the start address of the data storage space. When the data reference point of the descriptor is data other than the first data block in the data storage space, the reference address of the descriptor is the address of the data block in the data storage space.

In one possible implementation, the shape parameters of the tensor data include at least one of: the size of the data storage space in at least one direction of the N dimensional directions, the size of the storage area in at least one direction of the N dimensional directions, the offset of the storage area in at least one direction of the N dimensional directions, the positions of at least two vertexes located at diagonal positions of the N dimensional directions relative to the data reference point, and the mapping relationship between the data description position of the tensor data indicated by the descriptor and the data address. Where the data description position is a mapping position of a point or a region in the tensor data indicated by the descriptor, for example, when the tensor data is 3-dimensional data, the descriptor may represent a shape of the tensor data using three-dimensional space coordinates (x, y, z), and the data description position of the tensor data may be a position of a point or a region in the three-dimensional space to which the tensor data is mapped, which is represented using three-dimensional space coordinates (x, y, z).

It should be understood that shape parameters representing tensor data can be selected by one skilled in the art based on practical considerations, which are not limited by the present disclosure. By using the descriptor in the data access process, the association between the data can be established, thereby reducing the complexity of data access and improving the instruction processing efficiency.

FIG. 3 shows a schematic block diagram of a data processing apparatus according to an embodiment of the present disclosure. As shown in fig. 3, the data processing apparatus 300 includes a control unit 310, an address calculation unit 320, and an execution unit 330.

The control unit 310 may be configured to control the operation of the data processing apparatus 300, such as reading a memory or an externally incoming instruction, decoding (decoding) the instruction, issuing a micro-operation control signal to the corresponding component, and the like. Specifically, the control unit 310 may be configured to control the address calculation unit 320 to calculate a corresponding data address according to the received processing instruction, and control the execution unit 330 to execute corresponding processing according to the data address. The instructions may include, but are not limited to, data access instructions, arithmetic instructions, descriptor management instructions, synchronization instructions, and the like. The present disclosure is not limited to a particular type of instruction and a particular manner of decoding.

The decoded processing instruction includes an opcode and an operand including at least one flag bit for indicating a source of information for calculating a data address during execution of the processing instruction.

The address calculation unit 320 may be configured to calculate the corresponding data address using the corresponding information source according to the indication of the flag bit. The flag bit may indicate any of the following sources of information: a parameter of the processing instruction; or a parameter of a descriptor in the processing instruction, wherein the descriptor is used to indicate information of tensor data associated with the processing instruction.

In some embodiments, the flag bits may indicate the source of information used to compute the data address at different granularities. In one implementation, the flag bits may indicate the source of information for the data address used to compute the entire tensor data. In another implementation, the flag bits may indicate the source of information for calculating the data addresses for the various dimensions of the tensor data. In yet another implementation, the flag bits may indicate the source of information used to calculate different parameters of the data address. In yet another implementation, the flag bits may indicate the source of information for different parameters of the data addresses used to compute the dimensions of the tensor data. The address calculation unit 320 may obtain corresponding parameters directly from the processing instruction or from a descriptor of the processing instruction according to the indication of the flag bit, and calculate the corresponding data address based on the parameters.

Depending on the particular implementation, the calculation of the data address may depend on different parameters. In some implementations, these parameters may include, but are not limited to: an offset of the entire or partial storage area of tensor data; and the size of the entire or partial storage area of the tensor data.

The execution unit 330 may be configured to execute specific instructions under the control of the control unit 310. In particular, the execution unit 330 may be configured to execute the processing instruction according to the data address calculated by the address calculation unit 320 and an opcode in the decoding instruction. The execution unit 330 may include, but is not limited to, an Arithmetic and Logic Unit (ALU), a Memory Access Unit (MAU), a Neural Functional Unit (NFU), and the like. The present disclosure is not limited to a particular type of hardware for the execution unit.

Alternatively or additionally, the data processing apparatus 300 may further include a Tensor Interface Unit (TIU) 340, which may be configured to implement operations associated with the descriptors under the control of the control Unit 310. These operations may include, but are not limited to, registration, modification, deregistration, resolution of descriptors; reading and writing descriptor content, etc. The present disclosure does not limit the specific hardware type of tensor interface unit. In this way, the operation associated with the descriptor can be realized by dedicated hardware, and the access efficiency of tensor data is further improved.

Although the control unit 310, the address calculation unit 320, and the tensor interface unit 340 are illustrated as separate modules in fig. 3, those skilled in the art will appreciate that these three units may also be implemented as one module or recombined and split into more modules, and the present disclosure is not limited in this respect.

Alternatively or additionally, the data processing device 300 may further comprise a storage unit 350. The storage unit 350 may be configured to store various information including, but not limited to, instructions, descriptor-associated information, tensor data, and the like. The storage unit 350 may include various storage resources including, but not limited to, an internal memory and an external memory. The internal memory may include, for example, registers, on-chip SRAM, or other media cache. The external memory may comprise, for example, off-chip memory. The present disclosure is not limited to a particular implementation of the memory cell.

The data processing device 300 may be implemented using a general purpose processor (e.g., a central processing unit CPU, a graphics processing unit GPU) and/or a special purpose processor (e.g., an artificial intelligence processor, a scientific computing processor, or a digital signal processor, etc.), and the present disclosure is not limited to a particular type of data processing device.

FIG. 4 illustrates an exemplary flow diagram of a data processing method 400 according to an embodiment of the disclosure. The data processing method 400 may be implemented, for example, by the data processing apparatus 300 of fig. 3.

As shown in FIG. 4, the method 400 begins in step S410 by fetching a decoded processing instruction. This step may be performed, for example, by control unit 310 of fig. 3.

In an embodiment of the disclosure, a decoded processing instruction includes an opcode and an operand including at least one flag bit for indicating a source of information for calculating a data address during execution of the processing instruction.

Next, in step S420, the data address is calculated by using the corresponding information source according to the indication of the flag bit. This step may be performed, for example, by address calculation unit 320 of fig. 3. The specific implementation of the flag bit can refer to the foregoing description, and is not described herein again.

Finally, in step S430, the processing instruction is executed according to the data address and the operation code. This step may be performed, for example, by execution unit 330 of fig. 3.

The data processing method performed by the data processing apparatus of the embodiment of the present disclosure has been described above with reference to the flowchart. It is noted that while for simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present disclosure is not limited by the order of acts, as some steps may, in accordance with the present disclosure, occur in other orders and concurrently. Further, those skilled in the art will also appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules referred to are not necessarily required by the disclosure.

It should be further noted that, although the steps in the flowchart of fig. 4 are shown in sequence as indicated by the arrows, the steps are not necessarily executed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 4 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

Fig. 5 is a block diagram illustrating a combined processing device 500 according to an embodiment of the present disclosure. As shown in fig. 5, the combined processing device 500 includes a computing processing device 502, an interface device 504, other processing devices 506, and a storage device 508. Depending on the application scenario, one or more computing devices 510 may be included in the computing device, and may be configured as the data processing device 300 shown in fig. 3 to perform the operations described herein in conjunction with fig. 4.

In various embodiments, the computing processing device of the present disclosure may be configured to perform user-specified operations. In an exemplary application, the computing processing device may be implemented as a single-core artificial intelligence processor or a multi-core artificial intelligence processor. Similarly, one or more computing devices included within a computing processing device may be implemented as an artificial intelligence processor core or as part of a hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as artificial intelligence processor cores or as part of a hardware structure of an artificial intelligence processor core, computing processing devices of the present disclosure may be considered to have a single core structure or a homogeneous multi-core structure.

In an exemplary operation, the computing processing device of the present disclosure may interact with other processing devices through an interface device to collectively perform user-specified operations. Other Processing devices of the present disclosure may include one or more types of general and/or special purpose processors, such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), and artificial intelligence processors, depending on the implementation. These processors may include, but are not limited to, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic, discrete hardware components, etc., and the number may be determined based on actual needs. As previously mentioned, the computing processing device of the present disclosure may be considered to have a single core structure or an isomorphic multi-core structure only. However, when considered together, a computing processing device and other processing devices may be considered to form a heterogeneous multi-core structure.

In one or more embodiments, the other processing device can interface with external data and controls as a computational processing device of the present disclosure (which can be embodied as an artificial intelligence, e.g., a computing device associated with neural network operations), performing basic controls including, but not limited to, data handling, starting and/or stopping of the computing device, and the like. In further embodiments, other processing devices may also cooperate with the computing processing device to collectively perform computational tasks.

In one or more embodiments, the interface device may be used to transfer data and control instructions between the computing processing device and other processing devices. For example, the computing processing device may obtain input data from other processing devices via the interface device, and write the input data into a storage device (or memory) on the computing processing device. Further, the computing processing device may obtain the control instruction from the other processing device via the interface device, and write the control instruction into the control cache on the computing processing device slice. Alternatively or optionally, the interface device may also read data in the memory device of the computer processing device and transmit the data to the other processing device.

Additionally or alternatively, the combined processing device of the present disclosure may further include a storage device. As shown in the figure, the storage means is connected to the computing processing means and the further processing means, respectively. In one or more embodiments, the storage device may be used to hold data for the computing processing device and/or the other processing devices. For example, the data may be data that is not fully retained within internal or on-chip storage of a computing processing device or other processing device.

In some embodiments, the present disclosure also discloses a chip (e.g., chip 602 shown in fig. 6). In one implementation, the Chip is a System on Chip (SoC) and is integrated with one or more combinatorial processing devices as shown in fig. 5. The chip may be connected to other associated components through an external interface device, such as external interface device 606 shown in fig. 6. The relevant component may be, for example, a camera, a display, a mouse, a keyboard, a network card, or a wifi interface. In some application scenarios, other processing units (e.g., video codecs) and/or interface modules (e.g., DRAM interfaces) and/or the like may be integrated on the chip. In some embodiments, the disclosure also discloses a chip packaging structure, which includes the chip. In some embodiments, the present disclosure also discloses a board card including the above chip packaging structure. The board will be described in detail below with reference to fig. 6.

Fig. 6 is a schematic diagram illustrating a structure of a board card 600 according to an embodiment of the disclosure. As shown in fig. 6, the board includes a memory device 604 for storing data, which includes one or more memory cells 610. The memory device may be coupled to and communicate data with control device 608 and chip 602 described above, for example, via a bus. Further, the board card further includes an external interface device 606 configured for data relay or transfer function between the chip (or the chip in the chip package structure) and an external device 612 (such as a server or a computer). For example, the data to be processed may be transferred to the chip by an external device through an external interface. For another example, the calculation result of the chip may be transmitted back to an external device via the external interface device. According to different application scenarios, the external interface device may have different interface forms, for example, it may adopt a standard PCIE interface or the like.

In one or more embodiments, the control device in the disclosed card may be configured to regulate the state of the chip. Therefore, in an application scenario, the control device may include a single chip Microcomputer (MCU) for controlling the operating state of the chip.

From the above description in conjunction with fig. 5 and 6, it will be understood by those skilled in the art that the present disclosure also discloses an electronic device or apparatus, which may include one or more of the above boards, one or more of the above chips and/or one or more of the above combination processing devices.

According to different application scenarios, the electronic device or apparatus of the present disclosure may include a server, a cloud server, a server cluster, a data processing apparatus, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a PC device, a terminal of the internet of things, a mobile terminal, a mobile phone, a vehicle recorder, a navigator, a sensor, a camera, a video camera, a projector, a watch, an earphone, a mobile storage, a wearable device, a visual terminal, an autopilot terminal, a vehicle, a household appliance, and/or a medical device. The vehicle comprises an airplane, a ship and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph. The electronic device or apparatus of the present disclosure may also be applied to the fields of the internet, the internet of things, data centers, energy, transportation, public management, manufacturing, education, power grid, telecommunications, finance, retail, construction site, medical, and the like. Further, the electronic device or apparatus disclosed herein may also be used in application scenarios related to artificial intelligence, big data, and/or cloud computing, such as a cloud end, an edge end, and a terminal. In one or more embodiments, a computationally powerful electronic device or apparatus according to the present disclosure may be applied to a cloud device (e.g., a cloud server), while a less power-consuming electronic device or apparatus may be applied to a terminal device and/or an edge-end device (e.g., a smartphone or a camera). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and/or the edge device are compatible with each other, so that appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and/or the edge device according to the hardware information of the terminal device and/or the edge device, and uniform management, scheduling and cooperative work of end-cloud integration or cloud-edge-end integration can be completed.

It is noted that for the sake of brevity, the present disclosure describes some methods and embodiments thereof as a series of acts and combinations thereof, but those skilled in the art will appreciate that the aspects of the present disclosure are not limited by the order of the acts described. Accordingly, one of ordinary skill in the art will appreciate that certain steps may be performed in other sequences or simultaneously, in accordance with the disclosure or teachings of the present disclosure. Further, those skilled in the art will appreciate that the embodiments described in this disclosure are capable of alternative embodiments, in which acts or modules are involved, which are not necessarily required to practice one or more aspects of the disclosure. In addition, the present disclosure may focus on the description of some embodiments, depending on the solution. In view of the above, those skilled in the art will understand that portions of the disclosure that are not described in detail in one embodiment may also be referred to in the description of other embodiments.

In particular implementation, based on the disclosure and teachings of the present disclosure, one skilled in the art will appreciate that the several embodiments disclosed in the present disclosure may be implemented in other ways not disclosed herein. For example, as for the units in the foregoing embodiments of the electronic device or apparatus, the units are divided based on the logic functions, and there may be other dividing manners in actual implementation. Also for example, multiple units or components may be combined or integrated with another system or some features or functions in a unit or component may be selectively disabled. The connections discussed above in connection with the figures may be direct or indirect couplings between the units or components in terms of connectivity between the different units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection utilizing an interface, where the communication interface may support electrical, optical, acoustic, magnetic, or other forms of signal transmission.

In the present disclosure, units described as separate parts may or may not be physically separate, and parts shown as units may or may not be physical units. The aforementioned components or units may be co-located or distributed across multiple network elements. In addition, according to actual needs, part or all of the units can be selected to achieve the purpose of the solution of the embodiment of the present disclosure. In addition, in some scenarios, multiple units in embodiments of the present disclosure may be integrated into one unit or each unit may exist physically separately.

In some implementation scenarios, the integrated units may be implemented in the form of software program modules. If implemented in the form of software program modules and sold or used as a stand-alone product, the integrated units may be stored in a computer readable memory. In this regard, when aspects of the present disclosure are embodied in the form of a software product (e.g., a computer-readable storage medium), the software product may be stored in a memory, which may include instructions for causing a computer device (e.g., a personal computer, a server, or a network device, etc.) to perform some or all of the steps of the methods described in embodiments of the present disclosure. The Memory may include, but is not limited to, a usb disk, a flash disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.

In other implementation scenarios, the integrated unit may also be implemented in hardware, that is, a specific hardware circuit, which may include a digital circuit and/or an analog circuit, etc. The physical implementation of the hardware structure of the circuit may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors and like devices. In view of this, the various devices described herein (e.g., computing devices or other processing devices) may be implemented by suitable hardware processors, such as CPUs, GPUs, FPGAs, DSPs, ASICs, and the like. Further, the aforementioned storage unit or storage device may be any suitable storage medium (including magnetic storage medium or magneto-optical storage medium, etc.), and may be, for example, a variable Resistive Memory (RRAM), a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), an Enhanced Dynamic Random Access Memory (EDRAM), a High Bandwidth Memory (HBM), a Hybrid Memory Cube (HMC), a ROM, a RAM, or the like.

The foregoing may be better understood in light of the following clauses:

clause 1. a data processing apparatus including a control unit, an address calculation unit, and an execution unit, wherein:

the control unit is configured to obtain a decoded processing instruction, where the processing instruction includes an opcode and an operand that includes at least one flag bit for indicating a source of information for calculating a data address during execution of the processing instruction;

the address calculation unit is configured to calculate the data address using a corresponding information source according to the indication of the flag bit; and

the execution unit is configured to execute the processing instruction according to the data address and the operation code.

Clause 2. the data processing apparatus of clause 1, wherein the flag indicates any one of the following sources of information:

a parameter of the processing instruction; or

Parameters of a descriptor in the processing instruction, wherein the descriptor is for information indicative of tensor data associated with the processing instruction.

Clause 3. the data processing apparatus of clause 2, wherein the flag indicates a source of information for computing the data address at different granularities.

Clause 4. the data processing apparatus according to any of clauses 2-3, wherein the flag indicates a source of information for a data address used to calculate the entire tensor data.

Clause 5. the data processing apparatus according to any of clauses 2-4, wherein the flag indicates a source of information for calculating data addresses for the dimensions of the tensor data.

Clause 6. the data processing apparatus of any of clauses 2-5, wherein the flag indicates a source of information for calculating different parameters of the data address.

Clause 7. the data processing apparatus according to any of clauses 2-6, wherein the flag indicates a source of information for calculating different parameters of data addresses for the dimensions of the tensor data.

Clause 8. the data processing apparatus according to any of clauses 2-7, wherein the parameter comprises at least one of:

an offset of the entire or partial storage area of tensor data; and

the size of the whole or part of the storage area of the tensor data.

Clause 9 the data processing apparatus according to any of clauses 2-8, wherein the descriptor indicates shape information of the tensor data, the shape information of the tensor data including at least one shape parameter representing a shape of N-dimensional tensor data, N being a positive integer, the shape parameter of the tensor data including at least one of:

the size of a data storage space where the tensor data are located in at least one of N dimensional directions, the size of a storage area of the tensor data in at least one of the N dimensional directions, the offset of the storage area in at least one of the N dimensional directions, the positions of at least two vertexes located at diagonal positions of the N dimensional directions relative to a data reference point, and the mapping relation between the data description position of the tensor data and a data address.

Clause 10. a chip, characterized in that it comprises a data processing device according to any of clauses 1 to 9.

Clause 11, a board, wherein the board includes the chip of clause 10.

Clause 12. a data processing method, the method comprising:

obtaining a decoded processing instruction, wherein the processing instruction comprises an operation code and an operand, and the operand comprises at least one flag bit and is used for indicating an information source of a calculation data address during the execution of the processing instruction;

calculating the data address by using a corresponding information source according to the indication of the flag bit; and

and executing the processing instruction according to the data address and the operation code.

Clause 13. the data processing method of clause 12, wherein the flag indicates any one of the following sources of information:

a parameter of the processing instruction; or

Clause 14. the data processing method of clause 13, wherein the flag indicates a source of information for computing the data address at different granularities.

Clause 15. the data processing method according to any of clauses 13-14, wherein the flag indicates a source of information for a data address used to calculate the entire tensor data.

Clause 16. the data processing method according to any of clauses 13-15, wherein the flag indicates a source of information for calculating data addresses for the dimensions of the tensor data.

Clause 17. the data processing method of any of clauses 13-16, wherein the flag indicates a source of information for calculating different parameters of the data address.

Clause 18. the data processing method according to any of clauses 13-17, wherein the flag indicates the source of information for different parameters of the data addresses used to compute the dimensions of the tensor data.

Clause 19. the data processing method of any of clauses 13-18, wherein the parameters include at least one of:

an offset of the entire or partial storage area of tensor data; and

the size of the whole or part of the storage area of the tensor data.

Clause 20. the data processing method according to any of clauses 13-19, wherein the descriptor indicates shape information of the tensor data, the shape information of the tensor data including at least one shape parameter representing a shape of N-dimensional tensor data, N being a positive integer, the shape parameter of the tensor data including at least one of:

Claims

1. A data processing apparatus comprising a control unit, an address calculation unit, and an execution unit, wherein:

2. The data processing apparatus according to claim 1, wherein the flag bit indicates any one of the following information sources:

a parameter of the processing instruction; or

3. A data processing apparatus as claimed in claim 2, wherein the flag bits indicate the source of information used to calculate the data address at different granularities.

4. A data processing apparatus as claimed in any of claims 2 to 3, wherein the flag bit indicates the source of information for the data address used to calculate the entire tensor data.

5. A data processing apparatus as claimed in any of claims 2 to 4, wherein the flag bit indicates the source of information for calculating the data address for each dimension of tensor data.

6. A data processing apparatus as claimed in any of claims 2 to 5, wherein the flag bit indicates the source of information for calculating different parameters of the data address.

7. A data processing apparatus as claimed in any of claims 2 to 6, wherein the flag bits indicate the source of information for different parameters of the data addresses used to calculate the dimensions of the tensor data.

8. The data processing apparatus according to any of claims 2-7, wherein the parameter comprises at least one of:

an offset of the entire or partial storage area of tensor data; and

the size of the whole or part of the storage area of the tensor data.

9. The data processing apparatus according to any one of claims 2 to 8, wherein the descriptor indicates shape information of the tensor data, the shape information of the tensor data includes at least one shape parameter representing a shape of N-dimensional tensor data, N being a positive integer, the shape parameter of the tensor data including at least one of:

10. A chip, characterized in that it comprises a data processing device according to any one of claims 1-9.

11. A card comprising the chip of claim 10.

12. A method of data processing, the method comprising:

13. The data processing method of claim 12, wherein the flag bit indicates any one of the following information sources:

a parameter of the processing instruction; or

14. A data processing method as claimed in claim 13, wherein the flag bits indicate the source of information used to calculate the data address at different granularities.

15. A data processing method as claimed in any of claims 13 to 14, wherein the flag bit indicates the source of information for the data address used to calculate the entire tensor data.

16. A data processing method as claimed in any of claims 13 to 15, wherein the flag bit indicates the source of information for calculating the data address for each dimension of the tensor data.

17. A data processing method as claimed in any of claims 13 to 16, wherein the flag bit indicates the source of information for calculating different parameters of the data address.

18. A data processing method as claimed in any of claims 13 to 17, wherein the flag bits indicate the source of information for different parameters of the data addresses used to calculate the dimensions of the tensor data.

19. A data processing method as claimed in any of claims 13 to 18, wherein said parameters comprise at least one of:

an offset of the entire or partial storage area of tensor data; and

the size of the whole or part of the storage area of the tensor data.

20. The data processing method of any of claims 13-19, wherein the descriptor indicates shape information of the tensor data, the shape information of the tensor data includes at least one shape parameter representing a shape of N-dimensional tensor data, N being a positive integer, the shape parameter of the tensor data including at least one of: