CN114488903A - Communication optical fiber communication composite coding system and method for high-voltage frequency converter unit - Google Patents
Communication optical fiber communication composite coding system and method for high-voltage frequency converter unit Download PDFInfo
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- G05B19/00—Programme-control systems
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Abstract
The invention relates to a communication optical fiber communication composite coding system and method for a high-voltage frequency converter unit, which comprises the following steps: the system comprises a plurality of integrated frequency conversion units, an FPGA controller and a DSP processor; the integrated frequency conversion units are respectively connected with the FPGA controller through optical fibers; the FPGA controller is connected with the DSP processor through a bus; the integrated frequency conversion unit comprises a power unit and a control unit; the power unit comprises an IGBT module; the control unit comprises an MCU module and a CPLD module; the MCU module is electrically connected with the IGBT module and is used for acquiring non-real-time state data and real-time control data and sending the data to the CPLD module; the CPLD module is electrically connected with the MCU module and is used for moving the non-real-time state data to the real-time control data to obtain the composite data. The invention directly transmits the composite data to the FPGA controller through the integrated frequency conversion unit, thereby improving the working efficiency of the whole system.
Description
Technical Field
The invention relates to the technical field of information communication, in particular to a high-voltage frequency converter unit communication optical fiber communication composite coding system and method.
Background
The voltage type high-voltage frequency converter topological structure adopts an integrated frequency conversion unit series connection structure, each integrated frequency conversion unit is connected with a main controller through an optical fiber, an IGBT (insulated gate bipolar transistor) is mainly controlled to work through an optical fiber high-speed data frame, the data state and the fault state of the integrated frequency conversion unit need to be collected in time, relevant data packets in the optical fiber have strict time sequence requirements, relevant data processing is realized through relevant programmable logic chips such as an FPGA (field programmable gate array) or a CPLD (complex programmable logic device) and the like, and the data synchronization and the time sequence of fault linkage of a plurality of integrated frequency conversion units are ensured.
The programmable logic chip has limited internal resources and is advantageous in processing real-time control data, but as the data collected in the integrated frequency conversion unit is increased and mostly is state data, the requirement on real-time performance is not high, and if the data is uniformly packed into an optical fiber serial data string, a plurality of adverse results occur, (1) the programmable unit and a main control program need to be rewritten, hardware descriptive programs are incompatible, and the development and test process is complex; (2) the non-real-time data occupy effective bandwidth when the data packet is changed in length, and the real-time data acquisition frequency is reduced; (3) the hardware resources of the FPGA and the CPLD occupy a large amount, a chip with larger capacity is needed, and the cost is increased.
In order to prevent the adverse result, the non-real-time state data can be transmitted only when the transmission of the real-time control data is finished; the non-real-time state data and the real-time control data can not be transmitted simultaneously, so that the working efficiency of the whole system is low.
Disclosure of Invention
The invention aims to provide a high-voltage frequency converter unit communication optical fiber communication composite coding system and method, which solve the problem that the working efficiency of the whole system is low because non-real-time state data and real-time control data cannot be transmitted simultaneously.
According to a first aspect of embodiments of the present invention, there is provided a high-voltage frequency converter unit communication optical fiber communication composite coding system, including:
the system comprises a plurality of integrated frequency conversion units, an FPGA controller and a DSP processor;
the integrated frequency conversion units are respectively connected with the FPGA controller through optical fibers;
the FPGA controller is connected with the DSP processor through a bus;
the integrated frequency conversion unit comprises a power unit and a control unit;
the power unit comprises an IGBT module;
the control unit comprises an MCU module and a CPLD module;
the MCU module is electrically connected with the IGBT module and is used for acquiring non-real-time state data and real-time control data and sending the non-real-time state data and the real-time control data to the CPLD module;
the CPLD module is electrically connected with the MCU module and is used for receiving the non-real-time state data and the real-time control data and moving the non-real-time state data to the real-time control data to obtain the composite data.
Preferably, the integrated frequency conversion units are respectively connected with the FPGA controller through optical fibers, specifically:
the CPLD modules in the integrated frequency conversion units are respectively connected with the FPGA controller through optical fibers and are used for transmitting modulated signals obtained by modulating high-frequency carriers by composite data to the FPGA controller through the optical fibers.
According to a second aspect of the embodiments of the present invention, there is provided a high-voltage frequency converter unit communication optical fiber communication composite coding method, including:
the MCU module collects non-real-time state data and real-time control data and sends the non-real-time state data and the real-time control data to the CPLD module;
the CPLD module receives the non-real-time state data and the real-time control data, and moves the non-real-time state data to the real-time control data to obtain composite data;
the CPLD module modulates the high-frequency carrier wave by using the composite data to obtain a modulated signal, and transmits the modulated signal to the FPGA controller through an optical fiber;
the FPGA controller receives and demodulates the modulated signal to obtain composite data;
the DSP processor reads the composite data from the FPGA controller;
the DSP processor separates non-real-time state data and real-time control data from the composite data.
Preferably, the first and second electrodes are formed of a metal,
the non-real-time status class data comprises: the temperature of the IGBT module and the voltage of each group of capacitors in the power unit;
the format of the non-real-time state data is as follows: a binary data string;
the rate of the non-real-time status class data is 1 Kbps.
Preferably, the first and second electrodes are formed of a metal,
the real-time control class data comprises: bus voltage in the power unit, and fault linkage information in the power unit;
the frame format of the real-time control data is as follows: 16BIT data in total, BIT 0-BIT 9 are power unit direct-current voltages, BIT 10-BIT 14 are power unit states, BIT15 is a low-speed signal modulation BIT;
the rate of the real-time control type data frames is 40K frames per second.
Preferably, the moving the non-real-time status data to the real-time control data to obtain the composite data specifically includes:
the duration of each 1-BIT non-real-time state data is 1ms, the 1ms comprises 40 frames of real-time control data, the 1-BIT non-real-time state data is moved to BIT15 BITs of the 40 frames of real-time control data, and 40 frames of composite data are obtained;
and by analogy, moving the non-real-time state data to the real-time control data to obtain composite data, wherein the transmission rate of the composite data is 40K frames per second.
Preferably, the high-frequency carrier specifically includes:
the frequency is 5 MHz.
Preferably, the FPGA controller receives and demodulates the modulated signal to obtain the composite data, specifically:
the composite data is stored in a dual-port RAM of the FPGA controller.
Preferably, the DSP processor reads the composite data from the FPGA controller, specifically:
the DSP processor reads the composite data from the dual-port RAM of the FPGA controller;
a read rate of 10K frames per second is used.
Preferably, the DSP processor separates the non-real-time status data and the real-time control data from the composite data, specifically:
the DSP processor comprises data processing software, and the data processing software separates non-real-time state data and real-time control data from the composite data.
The technical scheme provided by the embodiment of the invention can have the following beneficial effects:
the method comprises the steps that non-real-time state data and real-time control data are collected through an MCU module, and the non-real-time state data are moved to the real-time control data through a CPLD module to form composite data; the integrated frequency conversion unit directly transmits the composite data to the FPGA controller, so that the working efficiency of the whole system is improved, and the problem of low working efficiency of the whole system caused by the fact that non-real-time state data and real-time control data cannot be transmitted simultaneously is solved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic block diagram illustrating a high voltage converter unit communication fiber optic communication composite encoding system in accordance with an exemplary embodiment;
FIG. 2 is a schematic flow chart diagram illustrating a high voltage converter unit communication fiber optic communication composite encoding method in accordance with an exemplary embodiment;
FIG. 3 is an inverter information collection architecture diagram, shown in accordance with an exemplary embodiment;
fig. 4 is a timing diagram illustrating a low speed data modulation sequence according to an exemplary embodiment.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the invention, as detailed in the appended claims.
Fig. 1 is a schematic block diagram illustrating a high-voltage converter unit communication fiber optic communication composite encoding system 100 according to an exemplary embodiment, as shown in fig. 1, the system comprising:
the system comprises a plurality of integrated frequency conversion units 101, an FPGA controller 102 and a DSP processor 103;
the integrated frequency conversion units 101 are respectively connected with the FPGA controller 102 through optical fibers;
the FPGA controller 102 is connected with the DSP processor 103 through a bus;
the integrated frequency conversion unit 101 comprises a power unit 1011 and a control unit 1012;
the power unit 1011 includes an IGBT module 10111;
the control unit 1012 comprises an MCU module 10121 and a CPLD module 10122;
the MCU module 10121 is electrically connected to the IGBT module 10111, and the MCU module 10121 is configured to collect non-real-time status data and real-time control data, and send the non-real-time status data and the real-time control data to the CPLD module 10122;
the CPLD module 10122 is electrically connected to the MCU module 10121, and the CPLD module 10122 is configured to receive the non-real-time status data and the real-time control data, and move the non-real-time status data to the real-time control data to obtain the composite data.
The IGBT module is a modular semiconductor product formed by bridge-packaging an IGBT (Insulated Gate Bipolar Transistor) and a FWD (free wheeling diode) by a specific circuit; the packaged IGBT module is directly applied to devices such as a frequency converter, an UPS (Uninterruptible Power Supply), and the like.
It can be understood that, in the embodiment, the MCU module collects the non-real-time status data and the real-time control data, and the CPLD module moves the non-real-time status data to the real-time control data to form composite data; the integrated frequency conversion unit directly transmits the composite data to the FPGA controller, so that the working efficiency of the whole system is improved, and the problem of low working efficiency of the whole system caused by the fact that non-real-time state data and real-time control data cannot be transmitted simultaneously is solved.
The communication between the integrated frequency conversion unit 101 and the FPGA controller 102 needs to be performed by a specific module in the integrated frequency conversion unit 101.
In a specific practice, the integrated frequency conversion units 101 are respectively connected with the FPGA controller 102 through optical fibers, specifically:
the CPLD modules 10122 in the multiple integrated frequency conversion units 101 are respectively connected to the FPGA controller 102 through optical fibers, and are configured to transmit modulated signals obtained by modulating a high-frequency carrier with composite data to the FPGA controller 102 through optical fibers.
It is understood that the CPLD module in the integrated inverter unit performs communication of the integrated inverter unit with the FPGA controller.
Fig. 2 is a schematic flow chart illustrating a method for communication optical fiber communication composite encoding of a high-voltage frequency converter unit according to an exemplary embodiment, where the method includes:
step S21, the MCU module collects non-real time state data and real time control data, and sends the non-real time state data and real time control data to the CPLD module;
step S22, the CPLD module receives the non-real-time state data and the real-time control data, and moves the non-real-time state data to the real-time control data to obtain composite data;
step S23, the CPLD module modulates the high-frequency carrier wave by the composite data to obtain a modulated signal, and transmits the modulated signal to the FPGA controller through the optical fiber;
step S24, the FPGA controller receives the modulated signal and demodulates the modulated signal to obtain composite data;
step S25, the DSP processor reads the composite data from the FPGA controller;
in step S26, the DSP processor separates the non-real-time status data and the real-time control data from the composite data.
It should be noted that the method provided by this embodiment is applied to the optical fiber communication composite coding system for high-voltage frequency converter unit communication.
It can be understood that the method moves the non-real-time state data to the real-time control data to form composite data, and the composite data is transmitted to the FPGA controller through the optical fiber, so that the working efficiency of the whole system is improved, and the problem of low working efficiency of the whole system caused by the fact that the non-real-time state data and the real-time control data cannot be transmitted simultaneously is solved.
The non-real-time status data is described mainly in terms of what types can be included, what format is used, and how high the transmission rate is.
In the specific practice of the method, the material is,
the non-real-time status class data comprises: the temperature of the IGBT module and the voltage of each group of capacitors in the power unit;
the format of the non-real-time state data is as follows: a binary data string;
the rate of the non-real-time status class data is 1 Kbps.
It will be appreciated that the duration of each 1bit state class data is 1 ms.
It should be noted that the non-real-time status data is mainly used for monitoring the working status (temperature, voltage, etc.) of the frequency converter, and has low requirement on real-time performance and does not need high transmission rate.
The real-time control data is mainly described in terms of what types can be contained, what frame format is adopted, and how high the transmission rate is.
In the specific practice of the method, the material is,
the real-time control class data comprises: bus voltage in the power unit, and fault linkage information in the power unit;
the frame format of the real-time control data is as follows: 16BIT data in total, BIT 0-BIT 9 are power unit direct-current voltages, BIT 10-BIT 14 are power unit states, BIT15 is a low-speed signal modulation BIT;
the rate of the real-time control type data frames is 40K frames per second.
It will be appreciated that the real-time control class data is 25us in duration per frame.
It should be noted that the DSP performs control operation by using real-time control type data, and if the operation result is a stop instruction, the DSP rapidly notifies each integrated frequency conversion unit to stop working immediately through the FPGA controller, otherwise, an accident may occur in the entire frequency converter.
The composite coding method mainly aims to solve the problem of how to move non-real-time state data to real-time control data.
In a specific practice, the moving of the non-real-time state data to the real-time control data to obtain the composite data specifically includes:
the duration of each 1-BIT non-real-time state data is 1ms, the 1ms comprises 40 frames of real-time control data, the 1-BIT non-real-time state data is moved to BIT15 BITs of the 40 frames of real-time control data, and 40 frames of composite data are obtained;
and by analogy, moving the non-real-time state data to the real-time control data to obtain composite data, wherein the transmission rate of the composite data is 40K frames per second.
It is understood that moving the 1-BIT non-real-time status class data to the BIT15 BITs of the 40 frames of real-time control class data will make the BIT15 BITs of the 40 frames of real-time control class data all the same, or all 0's, or all 1's.
It can be understood that, by using the modulation method, low-speed non-real-time status data is carried on high-speed real-time control data.
The high frequency carrier is generally selected from common carriers in the industry.
In a specific practice, the high-frequency carrier specifically is:
high-speed optical fiber data with a baud rate of 5MHz takes 3.2us when 16 bits of data are transmitted per frame, and one packet of data is transmitted every 25us (40 Kbps).
A specific storage unit is required in the FPGA controller to store the composite data obtained after demodulation.
In a specific practice, the FPGA controller receives and demodulates a modulated signal to obtain composite data, specifically:
the composite data is stored in a dual-port RAM of the FPGA controller.
It should be noted that the biggest characteristic of the dual-port RAM is memory data sharing, and one memory is equipped with two sets of independent address, data and control lines, allowing two independent CPUs or controllers to simultaneously and asynchronously access the memory cells.
And the DSP processor reads the composite data from the FPGA controller, wherein the reading speed is higher than the speed of the non-real-time state data.
In specific practice, the DSP processor reads the composite data from the FPGA controller, specifically:
the DSP processor reads the composite data from the dual-port RAM of the FPGA controller;
a read rate of 10K frames per second is used.
It can be understood that the sampling frequency of 10K frames per second is adopted to recover the non-real-time state data of 1Kbps, so that the time sequence requirement is completely met, and the non-real-time state data of the integrated frequency conversion unit can be correctly received.
The separation of the composite data requires the use of data processing software.
In a specific practice, the DSP processor separates non-real-time status data and real-time control data from the composite data, specifically:
the DSP processor comprises data processing software, and the data processing software separates non-real-time state data and real-time control data from the composite data.
It will be appreciated that the data processing software separates the non-real time status class data, assembles it into 8-bit bytes of data according to the rules of the serial bus, and then assembles the individual bytes of data into a serial data frame.
The unit communication optical fiber communication composite coding technology in the invention is explained below by taking a high-voltage frequency converter used in engineering practice as an example, and mainly comprises an inverter information acquisition system architecture (see fig. 3) and a low-speed data modulation timing sequence principle (see fig. 4).
Fig. 3 is a block diagram illustrating an inverter information acquisition system according to an exemplary embodiment, the system comprising, as shown in fig. 3:
the system comprises a DSP processor, an FPGA controller, an A group inverter, a B group inverter, a C group inverter, an A phase optical fiber interface, a B phase optical fiber interface and a C phase optical fiber interface;
the group a inverter includes 9 inverter units (a1 inverter … … a9 inverter);
the group B inverter includes 9 inverter units (B1 inverter … … B9 inverter);
the group C inverter includes 9 inverter units (C1 inverter … … C9 inverter);
the A group of inverters are electrically connected with the A phase optical fiber interface;
the group B inverter is electrically connected with the phase B optical fiber interface;
the group C inverter is electrically connected with the phase C optical fiber interface;
the phase A optical fiber interface, the phase B optical fiber interface and the phase C optical fiber interface are electrically connected with the FPGA controller;
the FPGA controller is electrically connected with the DSP processor;
each inverter unit comprises an MCU module and a CPLD module.
The MCU module collects the temperature of the IGBT and the voltage on each group of capacitors, and transmits the collected data to the CPLD module by using the Tx end of the UART which is arranged outside the MCU module, the CPLD module transmits a data packet to the FPGA controller through an optical fiber, the FPGA controller processes the data packet and then transmits the data packet to the DSP processor, the DSP processor processes 16-bit serial port data, the data packet is analyzed into 8-bit bytes according to the serial bus rule, and then the bytes are combined into a serial data frame.
The size of the data packet sent by each inverter unit is 16BIT, wherein BIT 0-BIT 9 are unit direct-current voltages, BIT 10-BIT 14 unit states, and BIT15 reserves BITs for special data. The whole data packet is serially sent to the FPGA controller, synchronous chain control of a plurality of units is realized by one data packet per 25us, and a controller DSP reads a 16-bit data packet at regular time (100us period) through a parallel bus, which is a real-time partial data transmission process.
The other aspect of the composite coding is BIT15 in the data packet, the serial port of the MCU module in the inverter unit sends non-real-time data at a baud rate of 1kbps, and a TX signal of the MCU module is moved to BIT15 of the 25us data packet through the CPLD module to complete the design of the composite coding. The length change of the non-real-time data does not need to modify an optical fiber protocol and a hardware description program, and only needs program adjustment of an MCU module and a DSP processor. The data expansion is convenient, the period of real-time data is not influenced, and the data separation transmission of two baud rates is realized in one path of high-speed optical fiber.
Fig. 4 is a schematic diagram illustrating a timing diagram for low speed data modulation according to an exemplary embodiment, as shown in fig. 4, the schematic diagram including:
BIT stream after low-speed demodulation, low-speed modulation clock and high-speed data packet.
The low-speed demodulated BIT stream is theoretically consistent with the non-real-time data BIT stream.
The low-speed modulation clock is used for sampling the BIT stream of the non-real-time data, and the sampling result is put into BIT15 BITs of the high-speed data packet (real-time data packet).
The duration of each 1-BIT non-real-time data is 1000us, 1000us comprises 40 real-time data packets (the period is 25us), and the 1-BIT non-real-time data is moved to BIT15 BITs of the 40 real-time data packets to obtain 40 composite data packets.
As can be seen from the figure, the first BIT data of the non-real-time data is 0, and the BIT15 BITs of the corresponding first group of high-speed packets (the first group [ P1] to [ P40]) are all 0;
the second BIT data of the non-real-time data is 1, and the BIT15 BITs of the corresponding second group of high-speed data packets (the second group [ P1] to [ P40]) are all 1;
the third BIT data of the non-real time data is 0, and BIT15 BITs of the corresponding third group of high speed packets (the third group [ P1] to [ P40]) are all 0.
It can be understood that the rate of sending the non-real-time data by the MCU module is 1Kbps, the duration of each 1bit of the non-real-time data is 1000us, the period of the real-time data packet sent by the CPLD module is 25us, which is equivalent to that the non-real-time data is sent out at a rate 40 times, and the error at the receiving end is 25us, i.e. 5% edge error, does not affect the serial data receiving logic timing.
The composite data packet is transmitted into a buffer area of the FPGA controller, the DSP processor reads the composite data packet evenly at a time interval of 100us, namely, the composite data packet is sampled at a sampling frequency of 10K to recover 1K data stream, so that the time sequence requirement is completely met, and the non-real-time data sent by the MCU module can be correctly received.
On the basis of receiving UART serial data at the bottom layer, the data of the inverter unit can be received by sending a plurality of bytes in the data channel, and the communication data is increased without modifying programs of the FPGA controller and the CPLD module, so that the data expansion is facilitated.
The receiving end of the DSP processor is used as a receiving clock of a 1Kbps serial port through a time interval of reading parallel port data, internal software simulates the extraction of a UART data byte stream, and the read data of each inverter unit is extracted in a time-sharing manner.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.
It should be noted that the terms "first," "second," and the like in the description of the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present invention, the meaning of "a plurality" means at least two unless otherwise specified.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (10)
1. The utility model provides a high-voltage inverter unit communication optical fiber communication composite coding system which characterized in that includes:
the system comprises a plurality of integrated frequency conversion units, an FPGA controller and a DSP processor;
the integrated frequency conversion units are respectively connected with the FPGA controller through optical fibers;
the FPGA controller is connected with the DSP processor through a bus;
the integrated frequency conversion unit comprises a power unit and a control unit;
the power unit comprises an IGBT module;
the control unit comprises an MCU module and a CPLD module;
the MCU module is electrically connected with the IGBT module and is used for acquiring non-real-time state data and real-time control data and sending the non-real-time state data and the real-time control data to the CPLD module;
the CPLD module is electrically connected with the MCU module and is used for receiving the non-real-time state data and the real-time control data and moving the non-real-time state data to the real-time control data to obtain the composite data.
2. The system of claim 1, wherein the plurality of integrated frequency conversion units are respectively connected to the FPGA controller via optical fibers, specifically:
the CPLD modules in the integrated frequency conversion units are respectively connected with the FPGA controller through optical fibers and are used for transmitting modulated signals obtained by modulating high-frequency carriers by composite data to the FPGA controller through the optical fibers.
3. A high-voltage frequency converter unit communication optical fiber communication composite coding method applied to the high-voltage frequency converter unit communication optical fiber communication composite coding system of any one of claims 1 to 2, which is characterized by comprising the following steps:
the MCU module collects non-real-time state data and real-time control data and sends the non-real-time state data and the real-time control data to the CPLD module;
the CPLD module receives the non-real-time state data and the real-time control data, and moves the non-real-time state data to the real-time control data to obtain composite data;
the CPLD module modulates the high-frequency carrier wave by using the composite data to obtain a modulated signal, and transmits the modulated signal to the FPGA controller through an optical fiber;
the FPGA controller receives and demodulates the modulated signal to obtain composite data;
the DSP processor reads the composite data from the FPGA controller;
the DSP processor separates non-real-time state data and real-time control data from the composite data.
4. The method of claim 3,
the non-real-time status class data comprises: the temperature of the IGBT module and the voltage of each group of capacitors in the power unit;
the format of the non-real-time state data is as follows: a binary data string;
the rate of the non-real-time status class data is 1 Kbps.
5. The method of claim 4,
the real-time control class data comprises: bus voltage in the power unit, and fault linkage information in the power unit;
the frame format of the real-time control data is as follows: 16BIT data in total, BIT 0-BIT 9 are power unit direct-current voltages, BIT 10-BIT 14 are power unit states, BIT15 is a low-speed signal modulation BIT;
the rate of the real-time control type data frames is 40K frames per second.
6. The method according to claim 5, wherein the moving of the non-real-time status data to the real-time control data to obtain the composite data comprises:
the duration of each 1-BIT non-real-time state data is 1ms, the 1ms comprises 40 frames of real-time control data, the 1-BIT non-real-time state data is moved to BIT15 BITs of the 40 frames of real-time control data, and 40 frames of composite data are obtained;
and by analogy, moving the non-real-time state data to the real-time control data to obtain composite data, wherein the transmission rate of the composite data is 40K frames per second.
7. The method according to claim 3, characterized in that the high frequency carriers are in particular:
the frequency is 5 MHz.
8. The method according to claim 3, wherein the FPGA controller receives and demodulates the modulated signal to obtain the composite data, specifically:
the composite data is stored in a dual-port RAM of the FPGA controller.
9. The method of claim 8, wherein the DSP processor reads the composite data from the FPGA controller, specifically:
the DSP processor reads the composite data from the dual-port RAM of the FPGA controller;
a read rate of 10K frames per second is used.
10. The method of claim 3, wherein the DSP processor separates the non-real-time status data and the real-time control data from the composite data, specifically:
the DSP processor comprises data processing software, and the data processing software separates non-real-time state data and real-time control data from the composite data.
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