CN114488760A - Re-quantization time-to-digital converter based on double-multipath gate-controlled ring oscillator - Google Patents
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Abstract
A requantization time-to-digital converter based on a dual-multipath gate-controlled ring oscillator belongs to the field of digital-to-analog hybrid circuits. The time-to-digital converter comprises a pulse generating circuit, a first gate-controlled ring oscillator, a second gate-controlled ring oscillator, a requantization circuit and a data correction circuit, wherein the requantization circuit comprises a decoder, a first multiplexer, a second multiplexer, a third multiplexer, a comparator and a common mode detection circuit, and the data correction circuit comprises a first order difference circuit, a delay circuit and an adder. The invention adds the outputs of two mismatched time-to-digital converters based on a multi-channel gate-controlled ring oscillator, quantizes the sum of the quantization errors of the two time-to-digital converters again and eliminates the quantization errors, thereby enabling the time-to-digital converters to be equivalent to a time-to-digital converter with half of the original minimum resolvable time.
Description
Technical Field
The invention belongs to the field of digital-analog hybrid circuits, and particularly relates to a requantization time-to-digital converter based on a double-multi-channel gated ring oscillator.
Background
Digital Phase Locked Loops (DPLLs) are an attractive alternative to traditional analog phase locked loops in radio frequency synthesizer and wired application clock recovery designs, can be scaled down to the required chip size and can be used for digitally intensive calibration and modulation. Usually, the digital phase-locked loop adopts partial digital or full digital, and uses a Time-to-digital converter (TDC) instead of the phase detector, and the in-band noise of the digital phase-locked loop is mainly the quantization noise introduced by the Time-to-digital converter. Therefore, how to reduce quantization noise becomes one of the keys of the low noise digital phase locked loop, and the common methods include increasing time resolution and increasing linearity.
The academics proposed in 2007 time-to-digital converters based on Gated-ring oscillators (GROs), which only allowed the oscillator to oscillate during a given measurement and tried to freeze the ring oscillator state between measurements, measuring the number of delayed cell transitions within one measurement interval. In view of the need for improving the time resolution, in 2008, a time-to-digital converter based on a Multi-gate ring oscillator (Multi-path GRO) was proposed, and since an inverter with multiple inputs is used, the delay of each stage is reduced, so that the time resolution of picosecond order can be realized. However, for low noise digital phase locked loops, the quantization error in picoseconds still remains to be reduced.
Disclosure of Invention
The invention aims to provide a requantization time-to-digital converter based on a dual-multipath gated ring oscillator, aiming at the defects in the prior art. The invention realizes the improvement of the time resolution by quantizing the quantization errors of the two multi-channel gate-controlled ring oscillators again.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a double-multi-channel gated ring oscillator-based requantization time-to-digital converter comprises a pulse generation circuit (PG), a first gated ring oscillator (GRO1), a second gated ring oscillator (GRO2), a requantization circuit and a data modification circuit, wherein the requantization circuit consists of a Decoder (Decoder), a first multiplexer (MUX1), a second multiplexer (MUX2), a third multiplexer (MUX3), a Comparator (CMP) and a common mode detection Circuit (CMD), and the data modification circuit consists of a differential circuit (Diff), a delay circuit (delay) and an adder;
the Start signal Start and the Stop signal Stop are input to a pulse generating circuit, and the pulse generating circuit converts an input time difference Tin of rising edges of the Start signal Start and the Stop signal Stop into a high-level pulse EN whose pulse width is equal to Tin and a low-level pulse EN _ n whose pulse width is equal to Tin; a high-level pulse EN is input into a second NMOS tube M2 and a fourth NMOS tube M4, a low-level pulse is input into a first PMOS tube M1 and a third PMOS tube M3, a first gated ring oscillator is connected with a power signal VDD through a first PMOS tube M1 and grounded through a second NMOS tube M2, and a second gated ring oscillator is connected with the power signal VDD through a third PMOS tube M3 and grounded through a fourth NMOS tube M4; the first gate-controlled ring oscillator starts to oscillate when the enable signal EN is at a high level and EN _ N is at a low level, and outputs N first oscillation waveforms V1[ N:1] which are continuously inverted between the high level and the low level; the second gate-controlled ring oscillator starts to oscillate when the enable signal EN is at a high level and EN _ N is at a low level, and outputs N second oscillation waveforms V2[ N:1] which are continuously inverted between the high level and the low level; the first oscillation waveform V1[ N:1] is inputted to a Decoder (Decoder) and a first multiplexer (MUX1), respectively, and the second oscillation waveform V2[ N:1] is inputted to the Decoder (Decoder) and a second multiplexer (MUX2), respectively; the reset end of the decoder is connected with the Start signal Start, the decoder resets all outputs to 0 when the Start signal Start rises, counts the turnover times of all waveforms in the first oscillation waveform V1[ N:1] to obtain an output D1, and counts the turnover times of all waveforms in the second oscillation waveform V2[ N:1] to obtain an output D2; when the first gated ring oscillator and the second gated ring oscillator are in a pause state, outputting a first selection signal SEL1[ N:1] to control the first multiplexer, outputting a second selection signal SEL2[ N:1] to control the second multiplexer, and outputting a third selection signal SEL3[1:0] to control the third multiplexer according to the states of adjacent inverters, which are not inverted, of the first gated ring oscillator and the second gated ring oscillator; the first multiplexer selects and outputs signals of corresponding addresses in the first oscillation waveform V1[ N:1] according to a first selection signal SEL1[ N:1], and the signals are marked as V1; the second multiplexer selects and outputs signals of corresponding addresses in the second oscillation waveform V2[ N:1] according to a second selection signal SEL2[ N:1], and the signals are marked as V2; the common mode detection Circuit (CMD) detects the common mode voltage of the input signals V1 and V2, if the common mode voltage is higher than a preset threshold voltage Vth, the output signal XCMD is at a high level, otherwise, the output signal XCMD is at a low level; the comparator compares the voltages of the input signals V1 and V2, and if V1 is higher than V2, the output signal XCMP is at a high level, otherwise XCMP is at a low level; the third multiplexer selects and outputs XCMD or XCMP or inverts XCMP according to a third selection signal SEL3[1:0], and the selected signal is marked as an output signal X; the delay circuit (delay) delays the Stop signal Stop and inputs the delayed Stop signal Stop as a clock signal to the first-order difference circuit (Diff); the first-order difference circuit carries out first-order difference on the output signal X to obtain an output SX; the adder adds the outputs D1 and D2 from the decoder, and then subtracts the output SX, so that the final output signal ReQ can be obtained.
Further, when the first gated ring oscillator and the second gated ring oscillator are in a pause state, two adjacent inverters which output in-phase levels exist in the first gated ring oscillator and the second gated ring oscillator, the output levels of the two adjacent inverters are both low levels or both high levels, and the corresponding gated ring oscillator is respectively marked as a 0 state (both low levels) or a 1 state (both high levels); the voltages of two adjacent inverters outputting the same phase level in the first gated ring oscillator are respectively marked as V1iAnd V1i+1The voltages of two adjacent inverters outputting the same phase level in the second gated ring oscillator are respectively marked as V2iAnd V2i+1(ii) a When the first gated ring oscillator is in the 0 state and the second gated ring oscillator is in the 0 state, the output signal V1 of the first multiplexer is V1iThe output signal V2 of the second multiplexer is V2i+1The output signal X of the third multiplexer is XCMP negation; when the first gated ring oscillator is in 0 state and the second gated ring oscillator is in 1 state, the output signal V1 of the first multiplexer is V1i+1The output signal V2 of the second multiplexer is V2iThe output signal X of the third multiplexer is XCMD; when the first gated ring oscillator is in the 1 state and the second gated ring oscillator is in the 0 state, the output signal V1 of the first multiplexer is V1iThe output signal V2 of the second multiplexer is V2i+1The output signal X of the third multiplexer is XCMD; when the first gated ring oscillator is in 1 state, the second gated ring oscillatorWhen the oscillator is in 1 state, the output signal V1 of the first multiplexer is V1iThe output signal V2 of the second multiplexer is V2i+1And the output signal X of the third multiplexer is XCMP. The details are shown in the following table:
| GRO1, GRO2 states | MUX1, MUX2 outputs V1, V2 | MUX3 outputs X |
| GRO 10 state, GRO 20 state | V1i，V2i+1 | XCMP negation |
| GRO 10 state, GRO 21 state | V1i+1，V2i | XCMD |
| GRO 11 state, GRO 20 state | V1i，V2i+1 | XCMD |
| GRO 11 state, GRO 21 state | V1i，V2i+1 | XCMP |
Furthermore, the first gated ring oscillator and the second gated ring oscillator are multi-channel gated ring oscillators with completely identical circuit structures, and the delay of the phase inverters of the first gated ring oscillator and the second gated ring oscillator is different by controlling the width-length ratio of transistors of the internal phase inverters.
Further, the first multiplexer and the second multiplexer are analog multiplexers, and the third multiplexer is a digital multiplexer.
The invention provides a requantization time-to-digital converter based on a double-multipath gate-controlled ring oscillator, which has the working principle that: the input time difference Tin respectively generates two quantization errors Q1 and Q2 contained in the output waveform of the oscillator after passing through the first gated ring oscillator and the second gated ring oscillator, and two integers D1 and D2 generated by a decoder; the quantization error information of each gated ring oscillator comprises the output voltage waveform V of two adjacent inverters at the same output phase leveli、Vi+1In the above two inverters, the output levels are both low or high, and the corresponding gated ring oscillator is respectively marked as 0 state or 1 state, as shown in fig. 2 and 3, the quantization error can be expressed as:
(0 state) or
(1 state);
when the input time error is Tin[n]Each inverter stage of the first gated ring oscillator is delayed by
Each inverter stage of the second gated ring oscillator is delayed by
The number of level flips D of the first gated ring oscillator occurring within the measurement time1[n]Is equal to Tin[n]Divided by its per-stage inverter delay, and subtracted by the quantization error Q1[n]First-order reshaping; number of level flips D of second gated ring oscillator occurring within measurement time2[n]Is equal to Tin[n]Divided by its per-stage inverter delay, and subtracted by the quantization error Q2[n]First order reshaping:
D1[n]＝(K-Δk)*Tin[n]-Q1[n]+Q1[n-1]
D2[n]＝(K+Δk)*Tin[n]-Q2[n]+Q2[n-1]
the preliminary data D [ n ] obtained by adding the two is:
D[n]＝2K*Tin[n]-(Q1[n]+Q2[n])+(Q1[n-1]+Q2[n-1])
due to D [ n ]]Is about D1[n]And D2[n]Twice, which can be seen approximately as a doubling of the temporal resolution; but the quantization error is doubled at the moment, the effective resolution is not doubled, and a requantization circuit and a data correction circuit are needed to eliminate half of the quantization error;
at the nth measurement, the quantization errors of the first gated ring oscillator and the second gated ring oscillator are:
the integer X [ n ] obtained by the re-quantization circuit through re-quantization is as follows:
finally, X [ n ]]From the preliminary data D n after a first order difference]Subtraction, the overall quantization error drops to
And Q1[n]、Q2[n]The variance of (a) is 1/12; thereby making its minimum resolvable time half that of a conventional single multi-gated ring oscillator based time-to-digital converter, the number of significant bits is increased by one.
The invention has the beneficial effects that:
the invention adds the outputs of two mismatched time-to-digital converters based on a multi-channel gate-controlled ring oscillator, quantizes the sum of the quantization errors of the two time-to-digital converters again and eliminates the quantization errors, thereby enabling the time-to-digital converters to be equivalent to a time-to-digital converter with half of the original minimum resolvable time. Compared with the current time-to-digital converter based on a single multi-way gated ring oscillator, the delay time of each stage of the ring oscillator is close to the design limit; the invention can improve the time resolution to twice of the original time resolution by a mode of quantization again on the premise of not reducing the delay time of each level of phase inverter of the ring oscillator.
Drawings
FIG. 1 is a schematic diagram of a requantization time-to-digital converter based on a dual-gated ring oscillator according to the present invention;
FIG. 2 is a diagram of quantization error in the 0 state when the gated ring oscillator is paused;
FIG. 3 is a diagram of quantization error in the 1 state when the gated ring oscillator is paused;
FIG. 4 is a schematic diagram of a double-gated ring oscillator based requantization time-to-digital converter and corresponding test circuitry according to embodiment 1 of the present invention;
fig. 5 is a partial timing diagram of internal signals according to embodiment 1 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described with reference to the following embodiments and the accompanying drawings.
The following non-limiting examples are presented to enable those of ordinary skill in the art to more fully understand the present invention and are not intended to limit the invention in any way.
Example 1
The present embodiment provides a requantization time-to-digital converter based on a dual-gated ring oscillator. As shown in fig. 1, the apparatus includes a pulse generating circuit (PG), a first gated ring oscillator (GRO1), a second gated ring oscillator (GRO2), a Decoder (Decoder), a first multiplexer (MUX1), a second multiplexer (MUX2), a third multiplexer (MUX3), a Comparator (CMP), a common mode detection Circuit (CMD), a first-order differential circuit (Diff), a delay circuit (delay), and an adder;
the delay of each stage of inverter of the first gated ring oscillator is 1/0.955ps, the delay of each stage of inverter of the second gated ring oscillator is 1/1.045ps, and the two stages can be regarded as being generated by a gated oscillator with the delay of 1ps of each stage of inverter through fine adjustment in positive and negative directions during design;
a requantization circuit consisting of a Decoder (Decoder), a first multiplexer (MUX1), a second multiplexer (MUX2), a third multiplexer (MUX3), a Comparator (CMP) and a common mode detection Circuit (CMD) carries out corresponding processing according to four different states of the first gated ring oscillator and the second gated ring oscillator when the gated ring oscillator is paused, and an output X is obtained;
finally, the first-order difference circuit performs first-order difference on the output X to obtain SX; d1 and D2 are added and then SX is subtracted, so that the integral quantization error is eliminated to be half of the original value, and the time resolution is doubled;
fig. 4 is a schematic diagram of a requantization time-to-digital converter based on a dual-gated ring oscillator and a corresponding test circuit according to embodiment 1 of the present invention; the input time error was 233.3ps, the gain of GRO1 was 0.955T LSB/ps, the gain of GRO2 was 1.045T LSB/ps, and the gain of GRO3 in the test circuit was 2 TLSB/ps. As shown in fig. 5, the measured data and quantization errors generated by GRO1, GRO2, GRO3 are D1, D2, DK and Q1, Q2, QK, respectively, the integer obtained by quantization again is X, after first order difference, SX is obtained, and finally the final data ReQ obtained by subtracting SX from D1+ D2 is completely equal to DK.
Therefore, the requantization time-to-digital converter based on the dual multi-channel gated ring oscillator is equivalent to a time-to-digital converter with the minimum resolvable time of 0.5ps/LSB, and compared with the time-to-digital converter based on the single multi-channel gated ring oscillator with the minimum resolvable time of about 1ps/LSB, the requantization time-to-digital converter based on the dual multi-channel gated ring oscillator can improve the time resolution to twice of the original time resolution by a requantization mode on the premise of not reducing the delay time of each stage of inverters of the ring oscillator.
Claims (4)
1. A requantization time-to-digital converter based on a dual multi-channel gated ring oscillator comprises a pulse generation circuit (PG), a first gated ring oscillator (GRO1), a second gated ring oscillator (GRO2), a requantization circuit and a data modification circuit, wherein the requantization circuit comprises a Decoder (Decoder), a first multiplexer (MUX1), a second multiplexer (MUX2), a third multiplexer (MUX3), a Comparator (CMP) and a common mode detection Circuit (CMD), and the data modification circuit comprises a first order difference circuit (Diff), a delay circuit (delay) and an adder;
the Start signal Start and the Stop signal Stop are input to a pulse generating circuit, and the pulse generating circuit converts an input time difference Tin of rising edges of the Start signal Start and the Stop signal Stop into a high-level pulse EN whose pulse width is equal to Tin and a low-level pulse EN _ n whose pulse width is equal to Tin; the high-level pulse EN is input into a second NMOS tube (M2) and a fourth NMOS tube (M4), the low-level pulse EN is input into a first PMOS tube (M1) and a third PMOS tube (M3), the first gated ring oscillator is connected with a power supply signal through a first PMOS tube (M1) and is grounded through a second NMOS tube (M2), and the second gated ring oscillator is connected with the power supply signal through a third PMOS tube (M3) and is grounded through a fourth NMOS tube (M4); the first gated ring oscillator outputs N first oscillation waveforms which are continuously inverted between high and low levels after oscillation; the second gate-controlled ring oscillator outputs N second oscillation waveforms which are continuously inverted between high and low levels after oscillation; the first oscillation waveform is respectively input into a Decoder (Decoder) and a first multiplexer (MUX1), and the second oscillation waveform is respectively input into the Decoder (Decoder) and a second multiplexer (MUX 2); the reset end of the decoder is connected with the Start signal Start, the decoder resets all outputs to 0 when the Start signal Start rises, counts the turnover times of all waveforms in the first oscillating waveform to obtain an output D1, and counts the turnover times of all waveforms in the second oscillating waveform to obtain an output D2; when the first gated ring oscillator and the second gated ring oscillator are in a pause state, outputting a first selection signal to control the first multiplexer, outputting a second selection signal to control the second multiplexer and outputting a third selection signal to control the third multiplexer according to the states of the adjacent inverters, which are not inverted, of the first gated ring oscillator and the second gated ring oscillator; the first multiplexer selects and outputs a signal of a corresponding address in the first oscillating waveform according to the first selection signal, and the signal is marked as V1; the second multiplexer selects and outputs a signal of a corresponding address in the second oscillating waveform according to the second selection signal, and the signal is marked as V2; the common mode detection circuit detects the common mode voltage of the input signals V1 and V2, if the common mode voltage is higher than a preset threshold voltage Vth, the output signal XCMD is at a high level, otherwise, the output signal XCMD is at a low level; the comparator compares the voltages of the input signals V1 and V2, and if V1 is higher than V2, the output signal XCMP is at a high level, otherwise XCMP is at a low level; the third multiplexer selects and outputs XCMD or XCMP or inverts XCMP according to the third selection signal and records as an output signal X; the delay circuit (delay) delays the Stop signal Stop and inputs the delayed Stop signal Stop as a clock signal to the first-order difference circuit (Diff); the first-order difference circuit carries out first-order difference on the output signal X to obtain an output SX; the adder adds the outputs D1 and D2 from the decoder, and then subtracts the output SX, so that the final output signal ReQ can be obtained.
2. The double-multi-gated ring oscillator-based requantization time-to-digital converter of claim 1, wherein when the first gated ring oscillator and the second gated ring oscillator are in a pause state, two adjacent inverters outputting in-phase levels are both present in the first gated ring oscillator and the second gated ring oscillator, when the output levels of the two adjacent inverters are at a low level, the corresponding gated ring oscillator is in a 0 state, and when the output levels of the two adjacent inverters are at a high level, the corresponding gated ring oscillator is in a 1 state; voltage division of two adjacent inverters outputting in-phase levels in a first gated ring oscillatorIs marked as V1iAnd V1i+1The voltages of two adjacent inverters outputting the same phase level in the second gated ring oscillator are respectively marked as V2iAnd V2i+1(ii) a When the first gated ring oscillator is in the 0 state and the second gated ring oscillator is in the 0 state, the output signal V1 of the first multiplexer is V1iThe output signal V2 of the second multiplexer is V2i+1The output signal X of the third multiplexer is XCMP negation; when the first gated ring oscillator is in 0 state and the second gated ring oscillator is in 1 state, the output signal V1 of the first multiplexer is V1i+1The output signal V2 of the second multiplexer is V2iThe output signal X of the third multiplexer is XCMD; when the first gated ring oscillator is in the 1 state and the second gated ring oscillator is in the 0 state, the output signal V1 of the first multiplexer is V1iThe output signal V2 of the second multiplexer is V2i+1The output signal X of the third multiplexer is XCMD; when the first gated ring oscillator is in 1 state and the second gated ring oscillator is in 1 state, the output signal V1 of the first multiplexer is V1iThe output signal V2 of the second multiplexer is V2i+1And the output signal X of the third multiplexer is XCMP.
3. The dual multi-gated ring oscillator-based requantization time-to-digital converter of claim 1, wherein the first and second gated ring oscillators are identical multi-gated ring oscillators, and wherein the inverters of the first and second gated ring oscillators have different delays by controlling the width-to-length ratios of the internal inverter transistors.
4. The double gated ring oscillator based requantization time to digital converter of claim 1, wherein the first and second multiplexers are analog multiplexers and the third multiplexer is a digital multiplexer.
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| CN114488760B (en) | 2022-11-01 |
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