CN114488637B - Array substrate and display device - Google Patents
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- CN114488637B CN114488637B CN202210142255.6A CN202210142255A CN114488637B CN 114488637 B CN114488637 B CN 114488637B CN 202210142255 A CN202210142255 A CN 202210142255A CN 114488637 B CN114488637 B CN 114488637B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1339—Gaskets; Spacers; Sealing of cells
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
Abstract
The invention discloses an array substrate and a display device, which comprise a display area and a non-display area, wherein the non-display area comprises a GOA area, and a first metal layer, an insulating layer and a second metal layer are sequentially arranged in the GOA area; the first metal layer comprises a plurality of peripheral scanning signal lines, one peripheral scanning signal line which is farthest from the display area in the non-display area is a first high-level signal line, and the first high-level signal line is a signal line connected with a high-level signal end; the insulating layer is provided with a plurality of through holes which penetrate through the insulating layer and are arranged along the extending direction of each peripheral scanning signal line at the corresponding position of each peripheral scanning signal line, and at least part of the peripheral scanning signal lines are electrically connected with the second metal layer through the corresponding through holes. The invention can improve the problem of via corrosion of the low-level via under the high-temperature high-humidity experimental environment, thereby preventing the display panel from having failure modes such as abnormal display and the like and improving the production yield and the service performance of the display panel.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to an array substrate and a display device.
Background
In order to meet the requirements of customers on narrow frames, the array substrate row driving (Gate driver On Array, GOA) technology has become a mainstream technical scheme, the GOA technology utilizes the thin film transistor display (Thin Film Transistor, TFT) process to manufacture a gate driving circuit on the array substrate, and utilizes time sequence control to realize the purpose of scanning and driving the gates row by row, so as to achieve the effect of narrow frames.
However, due to the complex structure of the GOA, the defects of the TFT manufacturing process, the influence of external environment and other factors, poor split-screen transverse lines caused by GOA failure often occur, especially in the high-temperature and high-humidity environment test process, corrosion of ITO in a GOA circuit area can occur due to the problem of water absorption or adhesiveness, and finally, failure modes such as abnormal display and the like of a display panel are caused, so that the production yield and the service performance of the display panel are affected.
Disclosure of Invention
The invention mainly aims to provide an array substrate and a display device, which are used for solving the problems that in the prior art, the ITO of a GOA circuit area is corroded, so that failure modes such as abnormal display and the like of a display panel are finally caused, and the production yield and the service performance of the display panel are affected.
In view of the above problems, the present invention provides an array substrate, including a display area and a non-display area, where the non-display area includes a GOA area, and the GOA area is sequentially provided with a first metal layer, an insulating layer, and a second metal layer;
the first metal layer comprises a plurality of peripheral scanning signal lines, one peripheral scanning signal line farthest from the display area in the non-display area is a first high-level signal line, and the first high-level signal line is a signal line connected with a high-level signal end;
the insulating layer is provided with a plurality of through holes which penetrate through the insulating layer and are arranged along the extending direction of each peripheral scanning signal line at the corresponding position of each peripheral scanning signal line, and at least part of the peripheral scanning signal lines are electrically connected with the second metal layer through the corresponding through holes.
Further, in the above array substrate, the first high-level signal line is electrically connected to the second metal layer through a corresponding via hole.
Further, the array substrate further includes a ground signal line;
the ground signal line is disposed on a side of the first high-level signal line away from the display region.
Further, in the above array substrate, the first high-level signal line is not electrically connected to the second metal layer through a corresponding via hole.
Further, the array substrate further comprises a ground signal line;
the ground signal line is disposed on a side of the first high-level signal line near the display region.
Further, the array substrate further comprises a ground signal line;
the grounding signal line is arranged between the first high-level signal line and the ith peripheral scanning signal line;
the ith peripheral scanning signal line is a peripheral scanning signal line connected with the second metal layer, wherein the ith peripheral scanning signal line is a first peripheral scanning signal line connected with the second metal layer in the plurality of peripheral scanning signal lines.
Further, in the above-mentioned array substrate, the peripheral scanning signal lines other than the first high-level signal line among the plurality of peripheral scanning signal lines include a second high-level signal line, a pulse signal line, and a low-level signal line; the second high-level signal line is a signal line connected with the high-level signal end, the pulse signal line is a signal line connected with the pulse signal end, and the low-level signal line is a signal line connected with the low-level signal end;
the second high-level signal line, the pulse signal line, and the low-level signal line are sequentially arranged in a direction from a distance from the non-display region to a distance from the display region.
Further, in the above array substrate, the high-level signal sent by the high-level signal end and received by the first high-level signal line is a high-level signal with adjustable potential.
Further, in the above-mentioned array substrate, the levels of the plurality of peripheral scanning signal lines are from high to low in a direction from the non-display region to the display region.
The invention also provides a display device comprising the array substrate as described in any one of the above.
One or more embodiments of the above-described solution may have the following advantages or benefits compared to the prior art:
according to the array substrate and the display device, one peripheral scanning signal line farthest from the display area is connected with the high-level signal end in the non-display area, so that the outermost peripheral scanning signal line of all the peripheral scanning signal lines is the first high-level signal line. Thus, after water vapor permeates the display panel, generated anions are attracted by the high-level signal line, so that anions are gathered around the first peripheral scanning signal line, cations are further attracted by the anions, the cations are effectively blocked from moving to the peripheral scanning signal line with low-level signals inside, the low-level through holes inside can be effectively protected, the reduction reaction rate and strength of the electrolytic cell are reduced, the problem of corrosion of the through holes of the low-level through holes in a high-temperature and high-humidity experimental environment is solved, the display panel is prevented from being in failure modes such as abnormal display, and the production yield and the service performance of the display panel are improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention, without limitation to the invention. In the drawings:
FIG. 1 is a top view of an array substrate according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view taken along the X-X direction in FIG. 1;
fig. 3 is a top view of an array substrate according to another embodiment of the present invention.
Detailed Description
The following will describe embodiments of the present invention in detail with reference to the drawings and examples, thereby solving the technical problems by applying technical means to the present invention, and realizing the technical effects can be fully understood and implemented accordingly. It should be noted that, as long as no conflict is formed, each embodiment of the present invention and each feature of each embodiment may be combined with each other, and the formed technical solutions are all within the protection scope of the present invention.
Through carrying out deep analysis on the horizontal stripe defect of the high-temperature high-humidity split screen, the root cause of the defect is confirmed that water vapor continuously permeates into the display panel under the high-temperature high-humidity environment, so that impurity ions in liquid crystal around the display panel are ionized, meanwhile, a large amount of impurity ions can enter along with the water vapor, different through holes of the GOA circuit have different potentials when the GOA circuit works, the impurity ions directionally move to form a passage under the action of a high potential difference, and when the potential difference reaches a threshold voltage, electrolytic cell reaction (cations in the electrolytic cell move to low-level through holes, anions move to the high-level through holes, and the low-level through holes accept or release electrons to become neutral atoms or molecules) occurs. In some embodiments, the low level is negative voltage, the voltage value is typically-12 to-14 v, and the high level is positive voltage, typically +12 to +14v.
The high-level via hole refers to a via hole always connected with a high-level signal in the GOA working process (each frame of display time does not include blank time), and comprises a via hole corresponding to a signal line such as GCH/VDS, and the low-level via hole refers to a via hole with a low-level signal in the GOA working process (each frame of display time does not include blank time), and comprises a via hole corresponding to a signal line such as CLK/STV/VGL/VSD.
Because the electrolytic cell reaction is forced oxidation-reduction reaction, the low-level cation Kong Xiyin undergoes reduction reaction:
In 2 O 3 conversion to In by reduction reaction&O2(：In 2 O 3 →2In+3/2O 2 )。
In on low-level via after reduction reaction 2 O 3 The low-level via hole impedance is obviously increased and can not be conducted after the low-level via hole impedance is reduced to In, and the output of the GOA circuit is affected to form split-screen transverse stripes.
The main direction of improving the transverse stripes of the high-temperature high-humidity split screen is to inhibit the reduction reaction of the low-level via holes, so that the corrosion of the low-level via holes is improved, and the application provides the following solutions:
firstly, a sealant material with better capability of isolating water vapor is adopted to slow down the water vapor from entering the display panel, so that the ionization degree of impurity ions in liquid crystal around the display panel is reduced, and the quantity of the impurity ions entering the display panel along with the water vapor is also reduced; but this solution is limited by the sealant material manufacturer.
Secondly, the concentration of impurity ions near the low-level via holes is reduced, and then the channel current between the corresponding high-low voltage GOA via holes is reduced, so that the reaction intensity of an electrolytic cell is reduced, and the corrosion rate and degree of the 2ITO via holes are improved;
thirdly, reducing the potential difference of each through hole of the GOA by reducing the voltage of a high-level signal or the voltage of a low-level signal, wherein the smaller the potential difference is, the weaker the electrolytic cell reaction is; however, in this scheme, the voltage drop of the high-level signal may cause charge-related defects, and the voltage drop of the low-level signal may cause leakage-related defects.
Fourth, promote the corrosion resistance of second ITO layer, lengthen the time that second ITO layer via hole corrodes to lose efficacy, for example increase the thickness of second ITO layer. But the scheme has higher cost and lower productivity.
To sum up the advantages and disadvantages of the 4 solutions, the present invention is described in detail with respect to the second solution:
fig. 1 is a top view of an array substrate according to an embodiment of the present invention, and fig. 2 is a cross-sectional view of fig. 1 along the X-X direction. As shown in fig. 1 to 2, the array substrate of the present embodiment may include a display area 1 and a non-display area 2, where the non-display area 2 includes a GOA area, and a first metal layer 21, an insulating layer 22, and a second metal layer 23 sequentially disposed in the GOA area. The non-display area 2 is disposed outside the display area 1, and in this embodiment, the non-display area 2 is disposed around the display area 1.
In a specific implementation process, the first metal layer 21 includes a plurality of peripheral scan signal lines 211, the insulating layer 22 is provided with a plurality of vias C extending through the insulating layer 22 along the extending direction of each peripheral scan signal line 211 at positions corresponding to each peripheral scan signal line 211, at least a portion of the peripheral scan signal lines 211 are electrically connected to the second metal layer 23 through the corresponding vias C, and the second metal layer 23 is connected to the GOA.
In a specific implementation process, a peripheral scan signal line 211 farthest from the display area 1 in the non-display area 2 is connected to a high-level signal terminal (not shown in the figure), so that a peripheral scan signal line 211 farthest from the display area 1 is a first high-level signal line, and a via hole C corresponding to the peripheral scan signal line 211 is a high-level via hole C, where the high-level via hole C may attract anions.
According to the formation mechanism of the electrolytic cell, after water vapor permeates into the display panel, liquid crystal impurities are ionized to generate impurity ions, the impurity ions directionally move between the short-distance high-level through holes and the short-distance low-level through holes to form a passage, and when the passage current is larger than a threshold voltage, the electrolytic cell reaction occurs, wherein anions move to the high-level through holes C, and cations move to the low-level through holes.
In this embodiment, since the first high-level signal line is a high-level signal line, and the corresponding via hole C is a high-level via hole, at this time, anions move to the first high-level signal line, and are collected around the first high-level signal line, and the anions further can attract cations, so that the cations also move to the first high-level signal line as much as possible, and thus, the cations are effectively blocked from moving to the peripheral scanning signal line 211 with a low-level signal inside, so that the low-level via hole inside can be effectively protected, the reduction reaction rate and strength of the electrolytic cell can be reduced, the corrosion problem of the via hole C of the low-level via hole in the high-temperature and high-humidity experimental environment can be improved, and further, the failure modes such as abnormal display of the display panel can be prevented, and the production yield and the service performance of the display panel can be improved.
Fig. 3 is a top view of an array substrate according to another embodiment of the present invention.
As shown in fig. 1 to 3, the array substrate may further include a ground signal line GND. The first high-level signal line may be an active peripheral scan signal line 211 (see GCH signal line in fig. 1) or an inactive peripheral scan signal line 211, and the inactive peripheral scan signal line 211 may be referred to as an auxiliary signal line (see Dummy signal line in fig. 3).
When the first high-level signal line is the active peripheral scan signal line 211, the first high-level signal line is electrically connected to the second metal layer 23 through the corresponding via hole C. In this case, the ground signal line GND is provided on a side of the first high-level signal line distant from the display area 1 so as to electrostatically protect the GOA circuit.
When the first high-level signal line is the inactive peripheral scan signal line 211, the first high-level signal line is not electrically connected to the second metal layer 23 through the corresponding via hole C. In this case, the ground signal line GND may be provided on the side of the first high-level signal line close to the display area 1, or the ground signal line GND may be provided between the first high-level signal line and the i-th peripheral scanning signal line 211. The ith peripheral scan signal line 211 is a peripheral scan signal line 211 connected to the second metal layer 23, which is a first peripheral scan signal line 211 in the plurality of peripheral scan signal lines 211, and in fig. 3, the ith peripheral scan signal line 211 may be a GCH signal line. In this way, the ground signal line GND can be ensured to be located at the periphery of the effective peripheral scanning signal line 211 so as to electrostatically protect the GOA circuit.
In one specific implementation, the peripheral scan signal lines other than the first high-level signal line in the plurality of peripheral scan signal lines 211 include a second high-level signal line (GCH signal line, VDS signal line, and Dummy signal line in fig. 1 to 3), a pulse signal line (CLK signal line in fig. 1 to 3), and a low-level signal line (VGL signal line in fig. 1 to 3); the second high-level signal line is a signal line connected with the high-level signal end, the pulse signal line is a signal line connected with the pulse signal end, and the low-level signal line is a signal line connected with the low-level signal end.
In a direction from the distance from the non-display area 2 to the approach to the display area 1, the second high-level signal line, the pulse signal line, and the low-level signal line are sequentially arranged, as shown in fig. 1, and the other peripheral scanning signal lines 211 may be arranged in an arrangement of VDS signal lines, CLK signal lines, and VGL signal lines, as shown in fig. 3, and the other peripheral scanning signal lines 211 may be arranged in an arrangement of VGL signal lines, VDS signal lines, CLK signal lines, and VGL signal lines. That is, one peripheral scanning signal line 211 farthest from the display area 1 is arranged at the outermost periphery as a first high-level signal line, and the other peripheral scanning signal lines 211 are arranged in the order of the second high-level signal line, the pulse signal line and the low-level signal line, so that the peripheral scanning signal line 211 with the low-level signal is as far away from the cutting line (the line indicated by B in fig. 1 and 3) of the array substrate as possible, and approaches the display area, and thus, even if a small amount of cations enter the display panel, the water vapor concentration and the cation concentration around the low-level via hole are relatively reduced, thereby achieving the purpose of improving the corrosion of the via hole C.
In a specific implementation process, considering the influence of GOA wiring line width and via hole C size in an a-Si Mobile product, after each peripheral scanning signal line 211 is arranged in an upward arrangement mode, the distance from a low-level via hole to a cutting line can be increased by more than 26 mu m, the water vapor concentration around the low-level via hole after the position adjustment of the via hole C is relatively reduced, the cation concentration is relatively reduced, the reduction reaction rate of an electrolytic cell is relatively reduced, and the corrosion degree of the low-level via hole under the same experimental condition/time is relatively reduced, so that the corrosion problem of the via hole C under the high-temperature high-humidity experimental environment of the GOA via hole C is improved.
In a specific implementation process, the high-level signal sent by the high-level signal end received by the first high-level signal line is a high-level signal with adjustable potential. Thus, the second scheme and the third scheme can be combined with each other, and the purpose of improving low-level via corrosion is achieved.
In the present embodiment, the thickness of the second metal layer 23 is appropriately increased, so that the second scheme and the fourth scheme are combined with each other to achieve the purpose of improving the low-level via corrosion.
The invention also provides a display device which comprises the array substrate of the embodiment. The display device may be a display panel, a display, or the like.
In one implementation, the display device may further include a frame and a sealant. The rubber frame surrounds the array substrate; the sealant is arranged between the sealant frame and the array substrate, and is used for sealing the side face of the display panel and fixedly connecting the sealant frame and the array substrate; wherein, the performance value of the sealant for isolating water vapor is larger than a preset threshold value. Thus, the first scheme and the second scheme can be combined with each other, and the purpose of improving low-level via corrosion is achieved.
It is to be understood that the same or similar parts in the above embodiments may be referred to each other, and that in some embodiments, the same or similar parts in other embodiments may be referred to.
It should be noted that in the description of the present invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "plurality" means at least two.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although the embodiments of the present invention are disclosed above, the embodiments are only used for the convenience of understanding the present invention, and are not intended to limit the present invention. Any person skilled in the art can make any modification and variation in form and detail without departing from the spirit and scope of the present disclosure, but the scope of the present disclosure is still subject to the scope of the present disclosure as defined by the appended claims.
Claims (10)
1. The array substrate comprises a display area and a non-display area, wherein the non-display area comprises a GOA area, and the array substrate is characterized in that a first metal layer, an insulating layer and a second metal layer are sequentially arranged in the GOA area;
the first metal layer comprises a plurality of peripheral scanning signal lines, one peripheral scanning signal line farthest from the display area in the non-display area is a first high-level signal line, and the first high-level signal line is a signal line connected with a high-level signal end;
the insulating layer is provided with a plurality of through holes which penetrate through the insulating layer and are arranged along the extending direction of each peripheral scanning signal line at the corresponding position of each peripheral scanning signal line, and at least part of the peripheral scanning signal lines are electrically connected with the second metal layer through the corresponding through holes;
the high-level signal refers to a signal which is always high in the GOA working process, and the low-level signal refers to a signal which is low in the GOA working process;
the plurality of peripheral scanning signal lines comprise low-level signal lines, the low-level signal lines are positioned between the first high-level signal lines and the display area, and the low-level signal lines are electrically connected with the second metal layer through corresponding through holes.
2. The array substrate of claim 1, wherein the first high-level signal line is electrically connected to the second metal layer through a corresponding via.
3. The array substrate of claim 2, further comprising a ground signal line;
the ground signal line is disposed on a side of the first high-level signal line away from the display region.
4. The array substrate of claim 1, wherein the first high-level signal line is not electrically connected to the second metal layer through a corresponding via.
5. The array substrate of claim 4, further comprising a ground signal line;
the ground signal line is disposed on a side of the first high-level signal line near the display region.
6. The array substrate of claim 4, further comprising a ground signal line;
the grounding signal line is arranged between the first high-level signal line and the ith peripheral scanning signal line;
the ith peripheral scanning signal line is a peripheral scanning signal line connected with the second metal layer, wherein the ith peripheral scanning signal line is a first peripheral scanning signal line connected with the second metal layer in the plurality of peripheral scanning signal lines.
7. The array substrate according to claim 1, wherein other peripheral scanning signal lines of the plurality of peripheral scanning signal lines than the first high-level signal line include a second high-level signal line, a pulse signal line, and a low-level signal line; the second high-level signal line is a signal line connected with the high-level signal end, the pulse signal line is a signal line connected with the pulse signal end, and the low-level signal line is a signal line connected with the low-level signal end;
the second high-level signal line, the pulse signal line, and the low-level signal line are sequentially arranged in a direction from a distance from the non-display region to a distance from the display region.
8. The array substrate of claim 1, wherein the high-level signal transmitted from the high-level signal terminal received by the first high-level signal line is a high-level signal with adjustable potential.
9. The array substrate according to claim 1, wherein the levels of the plurality of peripheral scan signal lines are from high to low in a direction from a distance from the non-display region to a distance from the display region.
10. A display device comprising an array substrate according to any one of claims 1 to 9.
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| CN202210142255.6A CN114488637B (en) | 2022-02-16 | 2022-02-16 | Array substrate and display device |
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| CN202210142255.6A CN114488637B (en) | 2022-02-16 | 2022-02-16 | Array substrate and display device |
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| CN114488637B true CN114488637B (en) | 2023-07-21 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN203895097U (en) * | 2014-05-29 | 2014-10-22 | 合肥鑫晟光电科技有限公司 | Circuit capable of eliminating shutdown ghost shadows and display device |
| CN105096871A (en) * | 2015-08-11 | 2015-11-25 | 京东方科技集团股份有限公司 | Array substrate driving circuit, array substrate, display panel and display device |
| CN107966860A (en) * | 2017-11-24 | 2018-04-27 | 深圳市华星光电技术有限公司 | A kind of GOA circuits, display panel and display device |
| CN111725278A (en) * | 2020-06-11 | 2020-09-29 | 武汉华星光电半导体显示技术有限公司 | OLED display panel |
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- 2022-02-16 CN CN202210142255.6A patent/CN114488637B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203895097U (en) * | 2014-05-29 | 2014-10-22 | 合肥鑫晟光电科技有限公司 | Circuit capable of eliminating shutdown ghost shadows and display device |
| CN105096871A (en) * | 2015-08-11 | 2015-11-25 | 京东方科技集团股份有限公司 | Array substrate driving circuit, array substrate, display panel and display device |
| CN107966860A (en) * | 2017-11-24 | 2018-04-27 | 深圳市华星光电技术有限公司 | A kind of GOA circuits, display panel and display device |
| CN111725278A (en) * | 2020-06-11 | 2020-09-29 | 武汉华星光电半导体显示技术有限公司 | OLED display panel |
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