CN114464596A

CN114464596A - Semiconductor device and method of forming a semiconductor device

Info

Publication number: CN114464596A
Application number: CN202110923202.3A
Authority: CN
Inventors: 杨挺立; 蔡柏豪; 吴逸文; 杨胜斌; 刘浩君
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2021-01-21
Filing date: 2021-08-12
Publication date: 2022-05-10
Also published as: US11855028B2; DE102021113437B4; KR20220106013A; DE102021113437A1; TW202230670A; TWI817308B; KR102580566B1; US20220230978A1; US20230369269A1

Abstract

A semiconductor device is disclosed that includes a substrate; an interconnect structure located over the substrate; a first passivation layer over the interconnect structure; a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to the conductive features of the interconnect structure; a conformal second passivation layer over and extending along the upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump and a second conductive bump over the first conductive pad and the second conductive pad, respectively, wherein the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and a dummy bump over the conductive line, wherein the dummy bump is spaced apart from the conductive line by a conformal second passivation layer. Embodiments of the invention also relate to another semiconductor device and a method of forming a semiconductor device.

Description

Semiconductor device and method of forming a semiconductor device

Technical Field

The embodiment of the invention relates to the field of semiconductors. More particularly, embodiments of the present invention relate to semiconductor devices and methods of forming semiconductor devices.

Background

High-density integrated circuits such as Very Large Scale Integration (VLSI) circuits are typically formed with interconnect structures (also referred to as interconnects) that serve as three-dimensional wiring structures. The purpose of the interconnect structure is to accurately connect densely packed devices together to form a functional circuit. As the integration increases, the parasitic capacitance effects between the metal lines of the interconnects that cause RC delay and crosstalk increase accordingly. To reduce parasitic capacitance and increase the conduction speed of interconnects, low-k dielectric materials are often used to form inter-layer dielectric (ILD) layers and inter-metal dielectric (IMD) layers.

Metal lines and vias are formed in the IMD layer. The forming process may include forming an etch stop layer over the first conductive feature and forming a low-k dielectric layer over the etch stop layer. The low-k dielectric layer and the etch stop layer are patterned to form trench and via openings. The trench and via openings are then filled with a conductive material, and a planarization process is then performed to remove excess conductive material, thereby forming metal lines and vias. Conductive bumps such as micro-bumps (μ -bumps) and controlled collapse chip connections (C4 bumps) are formed over the interconnect structure for connection with other devices.

Disclosure of Invention

Some embodiments of the present invention provide a semiconductor device, including a substrate; an interconnect structure located over the substrate; a first passivation layer over the interconnect structure; a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to the conductive features of the interconnect structure; a conformal second passivation layer over and extending along the upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump and a second conductive bump respectively over the first conductive pad and the second conductive pad, wherein the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and a dummy bump over the conductive line, wherein the dummy bump is spaced apart from the conductive line by a conformal second passivation layer.

Other embodiments of the present invention provide a semiconductor device comprising an interconnect structure located over a substrate; a first conductive pad, a second conductive pad, and a wire over and electrically coupled to the interconnect structure; a passivation layer over the first conductive pad, the second conductive pad, and the conductive line, wherein the passivation layer is conformal with and extends along the outer surfaces of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump, a second conductive bump and a dummy bump respectively located above the first conductive pad, the second conductive pad and the wire, wherein a first width of the first conductive bump is smaller than a second width of the second conductive bump; and first and second bump vias respectively located under the first and second conductive bumps, wherein the first bump via extends through the passivation layer and contacts the first conductive pad, wherein the second bump via extends through the passivation layer and contacts the second conductive pad, wherein the dummy bump is separated from the conductive line by the passivation layer, and the dummy bump is electrically isolated from the conductive line.

Still further embodiments of the present invention provide a method of forming a semiconductor device comprising forming an interconnect structure over a substrate; forming a first conductive pad, a second conductive pad, and a wire over the interconnect structure and electrically coupled to the interconnect structure, wherein a width of the second conductive pad is greater than a width of the first conductive pad; conformally forming a passivation layer over the first conductive pad, the second conductive pad, and the conductive line; forming a first opening and a second opening in the passivation layer to expose the first conductive pad and the second conductive pad, respectively, while keeping the conductive line covered by the passivation layer; forming a first conductive bump, a second conductive bump and a dummy bump over the first conductive pad, the second conductive pad and the wire, respectively; and forming a first bump via under the first conductive bump and a second bump via under the second conductive bump, wherein the first and second bump vias extend through the passivation layer and electrically couple the first and second conductive bumps to the first and second conductive pads, respectively, wherein the dummy bump is electrically isolated.

Drawings

Aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1A, 1B, 2-7, and 8A-8D illustrate cross-sectional views of a semiconductor device at various stages of fabrication according to one embodiment.

Fig. 9 and 10 illustrate cross-sectional views of a semiconductor device at various stages of fabrication, in accordance with another embodiment.

Fig. 11-14 illustrate cross-sectional views of a semiconductor device at various stages of fabrication, according to another embodiment.

Fig. 15 shows a cross-sectional view of a semiconductor device according to yet another embodiment.

Fig. 16A and 16B illustrate cross-sectional views of semiconductor devices having different processing sequences in accordance with some embodiments.

Fig. 17 illustrates a flow diagram of a method of forming a semiconductor device according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include examples in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component (or elements) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Throughout the description herein, unless otherwise noted, the same or similar reference numbers in different figures refer to the same or similar elements formed by the same or similar forming methods using the same or similar materials. Further, unless otherwise noted, figures having the same reference numerals and different letters (e.g., fig. 8A and 8B) show different views (e.g., along different cross-sections) of the same semiconductor device at the same stage of fabrication.

According to an embodiment, a plurality of conductive pads and conductive lines are formed over the interconnect structure and electrically coupled to the interconnect structure. A conformal passivation layer is formed over the conductive pads and conductive lines. Conductive bumps, such as micro-bumps (μ -bumps) and controlled collapse chip connections (C4 bumps), are formed over the passivation layer and electrically coupled to the underlying conductive pads. A dummy bump is formed over the conductive line, and the dummy bump is isolated from the conductive line. By forming dummy bumps over the wires, dummy conductive pads are no longer required and the saved space can be used to route other functional components, such as wires. In some embodiments, a dielectric layer is formed over the passivation layer prior to forming the conductive bump. The dielectric layer fills gaps between the conductive pads and between the conductive lines, thereby making it easier to form a seed layer for forming the conductive bumps. The present invention allows different types of conductive bumps, such as C4 bumps and μ -bumps, to be mixed together (e.g., interposed between each other) in the same area of a semiconductor device. This hybrid bump scheme allows for greater flexibility in the design of the conductive bumps to accommodate different design requirements.

Fig. 1A, 1B, 2-7, and 8A-8D illustrate cross-sectional views of a semiconductor device 100 at various stages of fabrication, according to an embodiment. The semiconductor device 100 may be a device wafer including active devices (e.g., transistors, etc.) and/or passive devices (e.g., capacitors, inductors, resistors, etc.). In some embodiments, semiconductor device 100 is an interposer wafer that may or may not include active and/or passive devices. According to yet another embodiment of the present invention, the semiconductor device 100 is a package substrate tape, which may be a package substrate having a core therein or may also be a coreless package substrate. In the discussion that follows, a device wafer is used as an example of the semiconductor device 100. As those skilled in the art will readily appreciate, the teachings of the present invention may also be applied to interposer wafers, package substrates, or other semiconductor structures.

As shown in fig. 1A, the semiconductor device 100 includes a semiconductor substrate 101 and electronic components 103 (e.g., active devices, passive devices) formed on or in the semiconductor substrate 101 (which may also be referred to as the substrate 101). The semiconductor substrate 101 may include a doped or undoped semiconductor material such as silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 101 may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

In the example of fig. 1A, the electronic component 103 is formed on the semiconductor substrate 101 or in the semiconductor substrate 101. Examples of electronic components 103 include transistors (e.g., Complementary Metal Oxide Semiconductor (CMOS) transistors), resistors, capacitors, diodes, and the like. The electronic component 103 may be formed using any suitable method, details of which are not discussed herein.

In some embodiments, after forming the electronic component 103, an interlayer dielectric (ILD) layer is formed over the semiconductor substrate 101 and over the electronic component 103. The ILD layer may fill the spaces between the gate stacks of the transistors (not shown) of the electronic component 103. According to some embodiments, the ILD layer comprises silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), fluorine doped silicate glass (FSG), Tetraethylorthosilicate (TEOS), and the like. The ILD layer may be formed using spin coating, Flowable Chemical Vapor Deposition (FCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), and the like.

Contact plugs are formed in the ILD layer that electrically couple the electronic components 103 to conductive features (e.g., metal lines, vias) of a subsequently formed interconnect structure 106. Note that in the present invention, unless otherwise specified, the conductive member refers to a conductive member that uses electricity, and the conductive material refers to a conductive material that uses electricity. According to some embodiments, the contact plug is formed of a conductive material such as tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and/or multilayers thereof. Forming the contact plug may include forming a contact opening in the ILD layer, forming one or more conductive materials in the contact opening, and performing a planarization process such as Chemical Mechanical Polishing (CMP) to make a top surface of the contact plug flush with a top surface of the ILD layer.

Still referring to fig. 1A, an interconnect structure 106 is formed over the ILD layer and over the electronic component 103. The interconnect structure 106 includes a plurality of dielectric layers 109 and conductive features (e.g., metal lines, vias) formed in the dielectric layers 109. In some embodiments, interconnect structures 106 interconnect electronic components 103 to form functional circuitry of semiconductor device 100.

In some embodiments, each dielectric layer 109, which may also be referred to as an inter-metal dielectric (IMD) layer, is formed of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. According to some embodiments, the dielectric layer 109 is formed of a low-k dielectric material having a dielectric constant (k value) below 3.0, such as about 2.5, about 2.0, or even lower. Dielectric layer 109 may include Black Diamond (a registered trademark of applied materials), carbon containing low-k dielectric materials, Hydrogen Silsesquioxane (HSQ), Methyl Silsesquioxane (MSQ), and the like. As an example, forming each dielectric layer 109 may include depositing a porogen-containing dielectric material over the ILD layer and then performing a curing process to drive off the porogen to form porous dielectric layer 109. Other suitable methods may also be used to form dielectric layer 109.

As shown in fig. 1A, conductive features, such as conductive lines 105 and vias 107, are formed in dielectric layer 109. In an exemplary embodiment, the conductive feature may include a diffusion barrier layer and a conductive material (e.g., copper or a copper-containing material) over the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum nitride, and the like, and may be formed by CVD, Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), and the like. After forming the diffusion barrier layer, a conductive material is formed over the diffusion barrier layer. The formation of the conductive features may include a single damascene process, a dual damascene process, and the like.

Next, a plurality of passivation layers 111 are formed over the interconnect structure 106, and a plurality of metal-insulator-metal (MIM) capacitors 113 are formed in the passivation layers 111. The passivation layer 111 may be formed of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics such as carbon-doped oxides, very low-k dielectrics such as porous carbon-doped silicon dioxide, combinations of these, and the like. Each passivation layer 111 may be formed by a process such as Chemical Vapor Deposition (CVD), FVCD, but any suitable process may be utilized.

A MIM capacitor 113 is formed in the passivation layer 111. Fig. 1B shows an enlarged view of region 102 in fig. 1A to show details of MIM capacitor 113. As shown in fig. 1B, each MIM capacitor 113 includes two metal layers 113M (e.g., copper layers) and a dielectric layer 113I (e.g., a high-k dielectric layer) located between the metal layers 113M. Each layer (e.g., 113M, 113I, and 113M) of the MIM capacitor 113 is formed in a respective passivation layer (e.g., 111B, 111C, or 111D). As an example, the upper metal layer 113M and the lower metal layer 113M of the MIM capacitor 113 may be connected to the overlying via 119V and the underlying via 108, respectively, wherein the overlying via 119V and the underlying via 108 are formed in the

passivation layers

111E and 111A, respectively. As another example, the upper metal layer 113M and the lower metal layer 113M of the MIM capacitor 113 may be connected to the first overlying via 119V1 and the second overlying via 119V2, respectively. In the example of fig. 1B, the second overlying via 119V2 extends through the passivation layer 111D and the dielectric layer 113I to connect with the lower metal layer 113M. Note that the second overlying via 119V2 extends through an opening in the upper metal layer 113M of the MIM capacitor, and thus the first overlying via 119V2 is separated from (e.g., does not contact) the upper metal layer 113M of the MIM capacitor by a portion of the passivation layer 111D.

Referring back to fig. 1A, the lower metal layer of the MIM capacitor 113 may be electrically coupled to the conductive component of the interconnect structure 106, for example, by vias extending from the lower metal layer of the MIM capacitor 113 to the conductive component of the interconnect structure 106. Additionally, multiple MIM capacitors 113 may be electrically coupled in parallel to provide a large capacitance value. For example, upper metal layers of the MIM capacitor 113 may be electrically coupled together and lower metal layers of the MIM capacitor 113 may be electrically coupled together. In some embodiments, MIM capacitor 113 is omitted.

Referring next to fig. 2, an opening 112 is formed in the passivation layer 111. Some openings 112 extend through the passivation layer 111 to expose the conductive features of the interconnect structure 106. In some embodiments, some of the openings 112 extend partially through the passivation layer 111 to expose an upper metal layer of the MIM capacitor 113. The openings 112 may be formed in one or more etching processes (e.g., an anisotropic etching process).

After forming the opening 112, a barrier layer 115 is conformally formed over the upper surface of the passivation layer 111 and along the sidewalls and bottom of the opening 112. The barrier layer 115 may have a multi-layer structure and may include a diffusion barrier layer (e.g., a TiN layer) and a seed layer (e.g., a copper seed layer) formed over the diffusion barrier layer. The barrier layer 115 may be formed using any suitable formation method, such as CVD, PVD, ALD, combinations thereof, and the like.

Next, in fig. 3, a photoresist layer 137 is formed over the barrier layer 115. Photoresist layer 137 is patterned (e.g., using photolithographic techniques) to form openings 138 at locations where conductive pads 119 and conductive lines 118 (see fig. 4) are to be formed. The opening 138 exposes, for example, the seed layer of the barrier layer 115. After forming the opening 138, a descum process 110 is performed to clean residues left by the patterning of the photoresist layer 137. For example, the descumming process 110 may be a plasma process performed using a process gas that includes oxygen.

Next, in fig. 4, conductive pads 119 (e.g., 119A and 119B) and conductive lines 118 are formed in openings 138 over barrier layer 115. The conductive pad 119 and the conductive line 118 may include a conductive material such as copper or a copper alloy (e.g., a copper-silver alloy, a copper-cobalt alloy, etc.), and the conductive pad 119 and the conductive line 118 may be formed using a suitable formation method such as electroplating, electroless plating, or the like. After the conductive pad 119 and the conductive line 118 are formed, the photoresist layer 137 is removed by a suitable removal process such as ashing. Next, an etching process is performed to remove portions of the barrier layer 115 on the barrier layer 115 where the conductive pads 119 or the conductive lines 118 are not formed. As shown in fig. 4, a portion of the conductive material fills the opening 112 (see fig. 3) in the passivation layer 111 to form a via 119V that electrically couples the conductive pad 119 to the underlying interconnect structure 106 or conductive member of the MIM capacitor 113. The conductive pads 119 and the conductive lines 118 may be collectively referred to as a redistribution layer (RDL), and the vias 119V may be referred to as RDL vias. As an example, the shape of the cross section of the conductive pad 119 may be dome-shaped (e.g., having a curved upper surface), concave, polygonal, or rectangular (or square). For example, the RDL via 119V may have an area of about 0.9x0.9 μm²And about 3.5x3.5 μm²In the meantime.

Note that in fig. 4, some conductive pads 119 (e.g., 119A) are larger (e.g., have a larger width measured between opposing sidewalls) than other conductive pads 119 (e.g., 119B). In subsequent processing, C4 bumps will be formed on the larger conductive pads 119A (see, e.g., 125 in fig. 8A), and micro bumps will be formed on the smaller conductive pads 119B (see, e.g., 127 in fig. 8A). In the illustrated embodiment, the conductive line 118 is electrically coupled to a conductive element of the interconnect structure 106, for example, by a via 116 (see fig. 8C), which via 116 may not be in the cross-section of fig. 4. In other embodiments, the wires 118 are pseudowires (e.g., electrically isolated). As will be readily appreciated by the skilled artisan, the number of conductive pads 119 and the number of conductive lines 118 may be any suitable number and may be arranged in any order. In addition, the number of RDL vias 119V under each conductive pad 119 may be any suitable number, such as one, two, three, or more. Further, RDL via 119V under each conductive pad 119 may be centered with respect to conductive pad 119, or may be off-center with respect to conductive pad 119.

Next, in fig. 5, a passivation layer 121 is conformally formed over conductive pad 119, over conductive line 118, and over passivation layer 111. In some embodiments, passivation layer 121 has a multi-layer structure and includes an oxide layer (e.g., silicon oxide) and a nitride layer (e.g., silicon nitride) over the oxide layer. In other embodiments, passivation layer 121 has a single layer structure, e.g., has a single nitride layer. Passivation layer 121 may be formed using, for example, CVD, PVD, ALD, combinations thereof, and the like.

Next, in fig. 6, a photoresist layer 135 is formed over the passivation layer 121 by, for example, spin coating. The photoresist layer 135 is then patterned by, for example, photolithographic techniques to form openings 136 at the locations where the conductive bumps are to be formed. Next, an etching process is performed to remove portions of passivation layer 121 exposed by openings 136 in patterned photoresist layer 135. In some embodiments, the etching process is performed using a process including CF₄、CHF₃、N₂And Ar (e.g., a plasma etch process). Other process gases may also be used, for example, O may be used₂Substitute for CF₄. After the etching process, the conductive pad 119 is exposed. Next, the photoresist layer 135 is removed by a suitable removal process such as ashing.

Next, in fig. 7, a dielectric layer 131 is formed over the passivation layer 121, over the conductive pad 119, and over the passivation layer 111. An opening 132 is formed in dielectric layer 131 to expose the underlying conductive pad 119. The dielectric layer 131 may be formed of, for example, a polymer, Polyimide (PI), benzocyclobutene (BCB), an oxide (e.g., silicon oxide), or a nitride (e.g., silicon nitride). As a non-limiting example, the dielectric layer 131 is shown as a single layer in fig. 7. The dielectric layer 131 may have a multi-layered structure including a plurality of sub-layers formed of different materials.

In some embodiments, the dielectric layer 131 is a photosensitive material, such as a photopolymer material, and the opening 132 is formed by using a photolithographic technique. For example, the photosensitive material can be exposed to a patterned energy source (e.g., light) through, for example, a photomask. The impact of the energy causes a chemical reaction in those portions of the photosensitive material that are impacted by the patterned energy source, thereby changing the physical properties of the exposed portions of the photosensitive material such that the physical properties of the exposed portions of the photosensitive material are different from the physical properties of the unexposed portions of the photosensitive material. Then, for example, depending on whether a negative-type photosensitive material or a positive-type photosensitive material is used, the photosensitive material may be developed by removing an exposed portion of the photosensitive material or an unexposed portion of the photosensitive material with a developer. The remaining portions of the photosensitive material may be cured to form the patterned dielectric layer 131. By way of non-limiting example, the top corner of the dielectric layer 131 at the opening 132/132a is shown in fig. 7 as being sharp (e.g., comprising two intersecting lines). The top corner of the dielectric layer 131 at the opening 132/132a may be, for example, a rounded corner.

In fig. 7, larger openings 132, denoted as openings 132A, expose larger conductive pads 119A (e.g., for forming C4 bumps), and other smaller openings 132 expose smaller conductive pads 119B (e.g., for forming μ -bumps). Note that for each smaller opening 132, a first distance between opposing sidewalls 131S of dielectric layer 131 exposed by smaller opening 132 is greater than a second distance between opposing sidewalls 121S of passivation layer 121 exposed by smaller opening 132, such that upper surface 121U and sidewalls 121S of passivation layer 121 are exposed by smaller opening 132. In other words, the upper portion of the smaller opening 132 is wider than the lower portion of the smaller opening 132. It can be said that the dielectric layer 131 is pulled back from the sidewall of the passivation layer 121 at the smaller opening 132, and the opening having the shape of the smaller opening 132 is referred to as a pull-back opening. In some embodiments, all of the smaller openings 132 used to form the μ -bumps are pull-back openings. Due to the smaller size of the μ -bump and conductive pad 119B, it may be difficult to form the smaller opening 132 as an alignment opening or a pull-in opening, the details of which will be discussed below. On the other hand, due to the larger size of the C4 bump and conductive pad 119A, the larger opening 132A may be formed as a pull-back opening, a pull-in opening, or an alignment opening.

In the example of fig. 7, larger opening 132A is a pull-in opening, where upper surface 121U and sidewalls 121S of passivation layer 121 under larger opening 132A are covered by dielectric layer 131. Accordingly, larger opening 132A exposes the upper surface of larger conductive pad 119A and the sidewalls of dielectric layer 131, but the sidewalls of passivation layer 121 are not exposed by larger opening 132A. In some embodiments, the width of the larger opening 132A, measured between opposing sidewalls 131S of the dielectric layer 131 facing the larger opening 132A, is greater than the maximum width of the smaller opening 132.

Next, in fig. 8A, a conductive bump 127 is formed on the smaller conductive pad 119B, a conductive bump 125 is formed on the larger conductive pad 119A, and a dummy bump 128 is formed over the wire 118. In an exemplary embodiment, conductive bumps 127 are μ -bumps having a width (e.g., measured between opposing sidewalls) of, for example, between about 3 μm and about 30 μm, and conductive bumps 125 are C4 bumps having a width of between about 32 μm and about 80 μm. In some embodiments, dummy bumps 128 have the same width as conductive bumps 127. In other embodiments, the dummy bumps 128 have a width different from the width of the conductive bumps 127 and less than or equal to the width of the conductive bumps 125.

Conductive bumps 127/125 and dummy bumps 128 may be formed by forming a seed layer over dielectric layer 131 and along the sidewalls and bottom of opening 132/132 a; forming a patterned photoresist layer over the seed layer, wherein openings of the patterned photoresist layer are formed at locations where the conductive bumps 127/125 and the dummy bumps 128 are to be formed; forming (e.g., plating) a conductive material over the seed layer in the opening; removing the patterned photoresist layer; and removing portions of the seed layer over which the conductive bumps 127/125 or dummy bumps 128 are not formed. Note that portions of conductive material fill

openings

132 and 132A to form bump vias 127V and bump vias 125V, respectively, bump vias 127V/125V electrically coupling conductive bump 127/125 to underlying conductive pads 119B/119A. Dummy bumps 128 are electrically isolated (e.g., not electrically coupled to other conductive components of semiconductor device 100). After the conductive bump 127/125 and dummy bump 128 are formed, a solder region 129 may be formed on the upper surfaces of the conductive bump 127/125 and dummy bump 128.

The dummy bumps 128 may be formed to balance the bump density of the conductive bumps (e.g., the total area of the conductive bumps per unit area as measured in a top view of the device) and to improve coplanarity of the formed conductive bumps (e.g., 125, 127, 128). If the bump density of the conductive bumps in different areas of the semiconductor device 100 is not balanced, the conductive bumps in the low bump density areas may be formed higher than the conductive bumps in the high bump density areas during the plating process to form the conductive bumps, resulting in a reduced coplanarity of the conductive bumps. Accordingly, the dummy bumps 128 may be formed in areas of low bump density to make the bump density uniform between different areas of the semiconductor device and to achieve improved coplanarity of the formed conductive bumps.

In fig. 8A, as a non-limiting example, dummy bumps 128 are formed over three conductive lines 118. The number of conductive lines 118 under each dummy bump 128 may be any suitable number, such as one. As shown in fig. 8A, the number of

bump vias

127V or 125V under the corresponding conductive bump (e.g., 127 or 125) is 1. Of course, this is only a non-limiting example. The number of

bump vias

127V or 125V under a respective conductive bump (e.g., 127 or 125) may be any suitable number, such as one, two, three, or more. Further, one or

more bump vias

127V or 125V under each respective conductive bump (e.g., 127 or 125) may be centered with respect to the conductive bump or may be off-center with respect to the conductive bump. In some embodiments, when dummy bumps 128 are wider than wires 118, dummy bumps 128 are formed over more than one wire 118 to provide more support for dummy bumps 128 and higher integration density for wires 118.

Note that in fig. 8A, the bump through-hole 127V and the bump through-hole 125V have different shapes due to the difference in the shape of the opening 132 (e.g., the pull-back opening) and the shape of the opening 132A (e.g., the pull-in opening). For example, bump via 127V has an upper portion (e.g., a portion above the upper surface of passivation layer 121) and a lower portion (e.g., a portion below the upper surface of passivation layer 121), where the upper portion is wider than the lower portion such that there is a lateral offset between sidewalls of the upper portion and corresponding sidewalls of the lower portion. Specifically, the sidewalls of the upper portion of the bump via 127V contact the sidewalls of the dielectric layer 131 and extend along the sidewalls of the dielectric layer 131, and the sidewalls of the lower portion of the bump via 127V contact the sidewalls of the passivation layer 121 and extend along the sidewalls of the passivation layer 121. As shown in fig. 8A, there is a step change in the width of the bump via 127V between the upper and lower portions of the bump via 127V. In other words, there is an abrupt (e.g., discontinuous) change in the width of the bump via 127V at the interface between the upper and lower portions of the bump via 127V.

In contrast, the sidewalls of the bump via 125V in fig. 8A contact the sidewalls of the dielectric layer 131 and extend along the sidewalls of the dielectric layer 131. The width of the bump via 125V may be constant (e.g., having sidewalls perpendicular to the major upper surface of the substrate 101) or may gradually (e.g., continuously) vary as the bump via 125V extends toward the substrate 101. In the example of fig. 8A, the sidewalls of the bump via 125V have a linear profile (e.g., a slanted straight line), and the width of the bump via 125V gradually decreases as the bump via 125V extends toward the substrate 101. Note that there is a gap between the sidewalls of the bump via 125V and the corresponding sidewalls of the passivation layer 121, and the dielectric layer 131 fills the gap and contacts the upper surface of the conductive pad 119A. In other words, the bump via 125V is separated (e.g., spaced apart) from the passivation layer 121 by the dielectric layer 131.

In the example of fig. 8A, the thickness a of the portion of dielectric layer 131 disposed over passivation layer 121 on conductive line 118 is between about 2 μm and about 20 μm. The spacing S between the wire 118 and the adjacent conductive pad 119 is greater than about 1.5 μm if the conductive pad is a smaller conductive pad 119B (e.g., having a μ -bump formed thereon), or greater than about 4 microns if the conductive pad is a larger conductive pad 119A (e.g., having a C4 bump formed thereon). Fig. 8A also shows a thickness T of a sidewall portion of passivation layer 121 (e.g., along a sidewall of conductive pad 119 or along a portion of a sidewall of conductive line 118), and a thickness G of an upper portion of passivation layer 121 (e.g., along an upper surface of conductive pad 119 or along a portion of an upper surface of conductive line 118), where thickness G is between about 0.5 μm and about 5 μm, and where a ratio between T and G (e.g., T/G), referred to as a step coverage of passivation layer 121, is between about 30% and about 90%.

Fig. 8B illustrates an enlarged view of a portion of the semiconductor device 100 of fig. 8A including the conductive bump 125. The dimensions of the conductive bump 125 and its surrounding structures are discussed below. In addition to or in parallel with the discussion of the dimensions of conductive bump 125 (e.g., a C4 bump), the dimensions of conductive bump 127 (e.g., a μ -bump) are also discussed as appropriate. Note that some features, such as the thickness of passivation layer 121 or the cross-sectional shape of conductive pad 119, are independent of the type of conductive bump (e.g., a C4 bump or μ -bump). In addition, some features, such as the width B at the top of the opening in the dielectric layer 131, are suitable for forming embodiments of the dielectric layer 131.

As shown in fig. 8B, the width W of the conductive bump 125 (e.g., a C4 bump) is between about 32 μm and about 80 μm. In contrast, the width W of the conductive bump 127 (e.g., μ -bump) is between about 10 μm and about 30 μm. The width B at the top of the opening in dielectric layer 131 is between about 5 μm and about 25 μm for the pull-back opening for the μ -bump, and between about 10 μm and about 80 μm for the pull-back opening, the pull-in opening, and the alignment opening for the C4 bump. The width E at the bottom of the opening in the dielectric layer 131 is between about 5 μm and about 30 μm for the pull-back opening for the μ -bump, and between about 10 μm and about 80 μm for the pull-back opening, the pull-in opening, and the alignment opening for the C4 bump. The height D of the bump via 125V (or 127V) is greater than the thickness a of a portion of the dielectric layer 131 (see fig. 8A) and greater than the thickness G of the upper portion of the passivation layer 121 (see fig. 8A). For embodiments where the dielectric layer 131 is omitted (see fig. 15), the height D is equal to the thickness G.

Still referring to fig. 8B, the width L of the conductive pad 119 is between about 15 μm and about 90 μm if the conductive pad 119 is a larger conductive pad 119A having a C4 bump formed thereon, or between about 3.5 μm and about 15 μm if the conductive pad is a smaller conductive pad 119B having a μ -bump formed thereon. The ratio between the width L of the conductive pad 119 and the pitch S (see fig. 8A) is equal to or greater than one. The width E' of the opening in passivation layer 121 is between about 2 μm and about 28 μm for μ -bumps and between about 30 μm and about 50 μm for C4 bumps. The height J of the conductive pad 119 (or wire 118) is between about 2 μm and about 9 μm. Fig. 8B further illustrates an angle F ' between the sidewalls of dielectric layer 131 and the upper surface of conductive pad 119, and an angle F between the sidewalls of passivation layer 121 and the upper surface of conductive pad 119, where F can be between 5 degrees and 90 degrees (e.g., 5 < F < 90), and F ' is greater than 5 degrees and less than or equal to 90 degrees (e.g., 5 < F ' ≦ 90). If opening 132 or 132A is an aligned opening (see 132A in FIG. 13), then the corresponding F and F' are equal. Otherwise, F may be different from F'.

Fig. 8C shows a plan view of the semiconductor device 100 of fig. 8A, and fig. 8A corresponds to a sectional view along the section a-a of fig. 8C. Note that for simplicity, not all components are shown in fig. 8C. As a non-limiting example, conductive pad 119 in fig. 8C is shown as having an octagonal shape. Other shapes, such as circular, elliptical, rectangular, other polygonal shapes, etc., are also possible and are fully intended to be included within the scope of the present invention. As shown in fig. 8C, dummy bumps 128 are placed over conductive lines 118, and conductive lines 118 are electrically coupled to underlying conductive elements (e.g., interconnect structure 106) through vias 116.

Fig. 8D illustrates an example of an arrangement of conductive bumps (e.g., 125, 127) of the semiconductor device 100. Fig. 8D corresponds to a top view of a portion of the semiconductor device 100 of fig. 8A, which may be different from the portion shown in fig. 8A. Note that for simplicity, not all components are shown in fig. 8D. As shown in fig. 8D, conductive bumps 125 (e.g., C4 bumps) and conductive bumps 127 (e.g., μ -bumps) are interleaved (e.g., staggered) with each other in the same area of semiconductor device 100. For example, the conductive bumps 127 are disposed around the conductive bumps 125 and between the conductive bumps 125. In addition, each of the conductive bumps 125 is also interposed between the conductive bumps 127. The layout of the conductive bumps (e.g., 125, 127) in fig. 8D is different from other designs in which the C4 bumps and the μ -bumps are formed in different regions of the semiconductor device (e.g., without intervening therebetween), and thus, the layout may also be referred to as a hybrid layout (or hybrid bump scheme) for the conductive bumps. In some embodiments, conductive bumps 125 (e.g., C4 bumps) and conductive bumps 127 (e.g., μ -bumps) are formed in different groups in different regions of the semiconductor device (e.g., not interposed between each other).

The conductive bumps 127 in fig. 8D form a circle around each conductive bump 125. Of course, this is only a non-limiting example. As an example, the conductive bump 127 surrounding each conductive bump 125 may form any shape, such as a rectangle, a triangle, a circle, an oval, a polygon. In addition, the conductive bumps 127 around each conductive bump 125 may be formed in a plurality of rows and columns. In some embodiments, the spacing P1 between the conductive bumps 125 is between about 50 μm and about 180 μm, such as 75 μm, and the spacing P2 between the conductive bumps 127 is between about 10 μm and about 45 μm, such as 25 μm.

Advantages are realized by the semiconductor device 100 disclosed herein and other disclosed embodiments (e.g., 100A, 100B, 100C). For example, dummy bumps 128 are formed over conductive lines 118 rather than over dummy conductive pads. This eliminates the need to form dummy conductive pads under each dummy bump 128 and allows for more flexible design and layout. For example, the space under dummy bump 128 may now be used to route wire 118. As another example, the formation of the dielectric layer 131 eliminates some of the difficulties associated with forming conductive bumps (e.g., 125, 127, 128) and improves device reliability and manufacturing yield. Recall that to form the conductive bump, a seed layer is first formed and then the conductive bump is formed (e.g., plated) over the seed layer. Without dielectric layer 131, a seed layer must be conformally formed over conductive pad 119 and over conductive line 118. In advanced semiconductor manufacturing, small gaps between the conductive pads 119 and the conductive lines 118 may have a high aspect ratio, and it may be difficult to form a seed layer in these small gaps, which may result in an inaccurate formation of the conductive bumps. Furthermore, after the conductive bump is formed, a portion of the seed layer on which the conductive bump is not formed needs to be removed. If these portions of the seed layer are located in the small gap, it may be difficult to remove the seed layer, which may result in an electrical short between the conductive pads 119. In contrast, by forming dielectric layer 131, a seed layer is formed over dielectric layer 131 and in openings 132/132A, these openings 132/132A have a much smaller aspect ratio, and therefore, the seed layer can be easily formed in openings 132 and easily removed from openings 132. Furthermore, the hybrid layout allows more flexibility in placing conductive bumps in a design to accommodate different design requirements.

Fig. 9 and 10 illustrate cross-sectional views of a semiconductor device 100A at various stages of fabrication, according to another embodiment. Semiconductor device 100A is similar to semiconductor device 100 but has a pull-back opening 132A for conductive pad 119A. The process of fig. 9 follows the processes of fig. 1A, 1B, and 2-6. In fig. 9, dielectric layer 131 is formed and opening 132/132a is formed using the same or similar processes as discussed above with reference to fig. 7. Note that, in fig. 9, the opening 132A is formed as a pull-back opening. This may be accomplished, for example, by using a photomask having a larger opening at the location of opening 132A to form opening 132A during a photolithography process. Thus, in the example of fig. 9, all of the openings 132/132a are pull-back openings.

Next, in fig. 10, a conductive bump 125 (e.g., a C4 bump) is formed over the larger conductive pad 119A, a conductive bump 127 (e.g., a μ -bump) is formed over the smaller conductive pad 119B, and a dummy bump 128 is formed over the conductive line 118, in the same or similar process as in fig. 8A, the details of which are not repeated. In the example of fig. 10,

bump vias

125V and 127V have similar shapes (e.g., upper and lower portions having different widths, and a step change in width at the interface between the upper and lower portions). The details are the same as or similar to the bump via 127V in fig. 8A, and thus are not repeated.

Fig. 11-14 illustrate cross-sectional views of a semiconductor device 100B at various stages of fabrication, according to another embodiment. Semiconductor device 100B is similar to semiconductor device 100 but has an aligned opening 132A for conductive pad 119A.

The process of fig. 11 follows the processes of fig. 1A, 1B, and 2-5. In fig. 11, a patterned photoresist layer 135 is formed and an etching process is performed using the same or similar process as fig. 6 to form an opening 136 extending through passivation layer 121 to expose smaller conductive pad 119B. Note that unlike the process of fig. 6, no opening is formed over the larger conductive pad 119A. Thus, the larger conductive pad 119A is covered by the photoresist layer 135. The photoresist layer 135 is removed after the opening 136 is formed.

Next, in fig. 12, using the same or similar process as fig. 7, a dielectric layer 131 is formed and an opening 132 is formed to expose the underlying smaller conductive pad 119B. Note that unlike the process of fig. 7, no opening is formed in dielectric layer 131 over larger conductive pad 119A.

Next, in fig. 13, a photoresist layer 133 is formed over the dielectric layer 131. Photoresist layer 133 fills opening 132. Next, the photoresist layer 133 is patterned to form openings 132A over the larger conductive pads 119A. Patterned photoresist layer 133 is then used as an etch mask for a subsequent etch process, which may be the same as or similar to the etch process used to form opening 136 in fig. 6. As shown in fig. 13, after the etching process, an opening 132A as an alignment opening is formed above the underlying larger conductive pad 119A and exposes the underlying larger conductive pad 119A. For each alignment opening 132A, the sidewalls 131S of the dielectric layer 131 exposed by the opening and the corresponding sidewalls 121S of the passivation layer 121 exposed by the opening are aligned along the same line (e.g., a straight line or a diagonal line with respect to the major upper surface of the substrate 101), as shown in the example of fig. 13. In some embodiments, sidewalls 131S of dielectric layer 131 and corresponding sidewalls 121S of passivation layer 121 may intersect at an interface between dielectric layer 131 and passivation layer 121 without a lateral offset therebetween. The photoresist layer 133 is removed after the formation of the alignment opening 132A.

Next, in fig. 14, a conductive bump 125 (e.g., a C4 bump) is formed over the larger conductive pad 119A, a conductive bump 127 (e.g., a μ -bump) is formed over the smaller conductive pad 119B, and a dummy bump 128 is formed over the conductive line 118, in the same or similar process as in fig. 8A, and details are not repeated. In the example of fig. 14, the bump vias 127V (e.g., μ -bumps) of the conductive bumps 127 have the same shape as the bump vias 127V of fig. 8A. The sidewall of the bump via 125V contacts the sidewall 131S of the dielectric layer 131 and extends along the sidewall 131S of the dielectric layer 131, and the sidewall of the bump via 125V contacts the sidewall 121S of the passivation layer 121 and extends along the sidewall 121S of the passivation layer 121. In some embodiments, the bump vias 125V of the conductive bumps 125 (e.g., C4 bumps) have a width (e.g., measured between opposing sidewalls of the bump vias 125V) that is constant (e.g., having straight sidewalls) or continuously varying (e.g., gradually without a step change) as the bump vias 125V extend toward the substrate.

Fig. 15 shows a cross-sectional view of a semiconductor device 100C according to yet another embodiment. The semiconductor device 100C is similar to the semiconductor device 100 of fig. 8A, but without the dielectric layer 131. As shown in fig. 15, the conductive bump 125/127 and the dummy bump 128 are formed directly on (e.g., in physical contact with) the passivation layer 121.

Bump vias

125V and 127V extend through passivation layer 121 and electrically couple

conductive bumps

125 and 127 to underlying

conductive pads

119A and 119B, respectively. Note that dummy bumps 128 are electrically isolated from conductive lines 118 by passivation layer 121. In the example of fig. 15, the lower portions of dummy bumps 128 extend into the gaps between conductive lines 118 and are therefore closer to substrate 101 than conductive bumps 125/127.

Fig. 16A and 16B illustrate cross-sectional views of a semiconductor device 200 having a different processing sequence in accordance with some embodiments. The semiconductor device 200 may be formed by the same or similar process as the semiconductor device 100A of fig. 10. Fig. 16A and 16B show the effect of the sequence of processing steps on angles F and F ', where angle F is between sidewall 121S of passivation layer 121 and the upper surface of underlying conductive pad 119, and angle F' is between sidewall 131S of dielectric layer 131 and the upper surface of underlying passivation layer 121.

For semiconductor device 200 in fig. 16A, after passivation layer 121 is formed over conductive pad 119, dielectric layer 131 is formed over passivation layer 121. In an embodiment, the dielectric layer 131 is a photopolymer layer and is formed by spin coating. Next, the dielectric layer 131 (e.g., photopolymer layer) is exposed to a patterned energy source (e.g., light) and the dielectric layer 131 is developed to form the patterned dielectric layer 131. Patterned dielectric layer 131 is used as an etch mask in a subsequent etching process that etches through passivation layer 121 to form an opening that exposes conductive pad 119. After forming the opening in the passivation layer 121, the dielectric layer 131 (e.g., photopolymer layer) is cured, for example, by a thermal process. In other words, after forming the opening in the passivation layer 121, curing of the dielectric layer 131 is performed. Next, the

conductive bump

125 or 127 is formed according to the similar process as described above.

Note that in fig. 16A, by curing the dielectric layer 131 after forming an opening in the passivation layer 121, the angle F 'is greater than 5 degrees and equal to or less than 90 degrees (e.g., 5 ° < F' ≦ 90 °), and the angle F is greater than 5 degrees and less than 90 degrees (e.g., 5 ° < F ≦ 90 °).

The semiconductor device 200 in fig. 16B is formed by a process similar to that of fig. 16A, but curing of the dielectric layer 131 is performed before formation of the opening in the passivation layer 121. Specifically, after exposure and development, the dielectric layer 131 (e.g., photopolymer layer) is cured, for example, by a thermal process, to cure the dielectric layer 131. The cured patterned dielectric layer 131 is then used as an etch mask in a subsequent etching process that etches through the passivation layer 121 to form an opening that exposes the conductive pad 119. Next, the

conductive bump

125 or 127 is formed according to the similar process as described above.

Note that in fig. 16B, by curing the dielectric layer 131 before forming the opening in the passivation layer 121, the angle F 'is greater than 5 degrees and less than 90 degrees (e.g., 5 ° < F' < 90 °), and the angle F is greater than 5 degrees and less than 90 degrees (e.g., 5 ° < F < 90 °). In some embodiments, the processing sequence of fig. 16A (e.g., curing the dielectric layer 131 after forming the opening in the passivation layer 121) allows for a larger angle F' (e.g., steeper sidewalls of the dielectric layer 131) to be formed as compared to the processing sequence of fig. 16B (e.g., curing the dielectric layer 131 before forming the opening in the passivation layer 121). A larger angle F' may advantageously reduce stress in devices formed, for example, at the corners of the dielectric layer 131, and may prevent or reduce cracking or spalling of the material (e.g., 131) of the semiconductor device.

Embodiments of the present invention achieve some advantageous features. For example, dummy bumps 128 are formed over conductive lines 118 rather than over dummy conductive pads. This allows for more flexible design and layout. As another example, the formation of the dielectric layer 131 eliminates the difficulties associated with forming and removing seed layers in high aspect ratio gaps during the formation of conductive bumps (e.g., 125, 127, 128), thereby improving device reliability and product yield. Furthermore, the hybrid layout allows more flexibility in placing conductive bumps in a design to accommodate different design requirements.

Figure 17 illustrates a flow diagram of a method of fabricating a semiconductor structure, according to some embodiments. It should be understood that the implementation shown in fig. 17 is only one example of many possible implementations. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps as shown in fig. 17 may be added, removed, replaced, rearranged, or repeated.

Referring to fig. 17, at block 1010, an interconnect structure is formed over a substrate. At block 1020, a first conductive pad, a second conductive pad, and a wire are formed over the interconnect structure and electrically coupled to the interconnect structure, wherein the second conductive pad has a width greater than a width of the first conductive pad. At block 1030, a passivation layer is conformally formed over the first conductive pad, the second conductive pad, and the conductive line. At block 1040, first and second openings are formed in the passivation layer to expose the first and second conductive pads, respectively, while maintaining the conductive lines covered by the passivation layer. At block 1050, a first conductive bump, a second conductive bump, and a dummy bump are formed over the first conductive pad, the second conductive pad, and the wire, respectively. At block 1060, a first bump via is formed under the first conductive bump and a second bump via is formed under the second conductive bump, wherein the first and second bump vias extend through the passivation layer and electrically couple the first and second conductive bumps to the first and second conductive pads, respectively, wherein the dummy bumps are electrically isolated.

According to an embodiment of the present invention, a semiconductor device includes a substrate; an interconnect structure located over the substrate; a first passivation layer over the interconnect structure; a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to the conductive features of the interconnect structure; a conformal second passivation layer over and extending along the upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump and a second conductive bump over the first conductive pad and the second conductive pad, respectively, wherein the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and a dummy bump over the conductive line, wherein the dummy bump is spaced apart from the conductive line by a conformal second passivation layer. In an embodiment, the dummy bumps comprise the same conductive material as the first and second conductive bumps, wherein the dummy bumps are electrically isolated from the conductive lines and the interconnect structure. In an embodiment, the semiconductor device further comprises a dielectric layer between the conformal second passivation layer and the dummy bumps, wherein lower surfaces of the dummy bumps facing the substrate contact upper surfaces of the dielectric layer remote from the substrate and extend along the upper surfaces of the dielectric layer remote from the substrate. In an embodiment, the semiconductor device further includes a first bump via and a second bump via, wherein the first bump via extends through the dielectric layer and the conformal second passivation layer to electrically couple the first conductive bump to the first conductive pad, and wherein the second bump via extends through the dielectric layer and the conformal second passivation layer to electrically couple the second conductive bump to the second conductive pad. In an embodiment, the first width of the first conductive bump is smaller than the second width of the second conductive bump. In an embodiment, the third width of the dummy bumps is the same as the first width. In an embodiment, the first bump via extends from the upper surface of the dielectric layer to the first conductive pad, wherein a width of the first bump via has a step change. In an embodiment, the second bump via extends from an upper surface of the dielectric layer to the second conductive pad, wherein the dielectric layer is laterally disposed between a sidewall of the second bump via and a sidewall of the conformal second passivation layer facing the second bump via. In an embodiment, the second bump via extends from the upper surface of the dielectric layer to the second conductive pad, wherein a width of the second bump via has a step change. In an embodiment, the second bump via extends from the upper surface of the dielectric layer to the second conductive pad, wherein a width of the second bump via continuously varies as the second bump via extends toward the substrate. In an embodiment, the semiconductor device further comprises a metal-insulator-metal (MIM) capacitor embedded in the first passivation layer. In an embodiment, the first conductive bump is smaller than the second conductive bump in a top view, wherein the semiconductor device further comprises a third conductive bump having the same size as the second conductive bump, wherein the first conductive bump is disposed between the second conductive bump and the third conductive bump.

According to an embodiment of the present invention, a semiconductor device includes an interconnect structure located over a substrate; a first conductive pad, a second conductive pad, and a wire over and electrically coupled to the interconnect structure; a passivation layer over the first conductive pad, the second conductive pad, and the conductive line, wherein the passivation layer is conformal with and extends along the outer surfaces of the first conductive pad, the second conductive pad, and the conductive line; a first conductive bump, a second conductive bump and a dummy bump respectively located above the first conductive pad, the second conductive pad and the wire, wherein a first width of the first conductive bump is smaller than a second width of the second conductive bump; and first and second bump vias respectively located under the first and second conductive bumps, wherein the first bump via extends through the passivation layer and contacts the first conductive pad, wherein the second bump via extends through the passivation layer and contacts the second conductive pad, wherein the dummy bump is separated from the conductive line by the passivation layer, and the dummy bump is electrically isolated from the conductive line. In an embodiment, the semiconductor device further includes a dielectric layer over the passivation layer, wherein the first bump via extends into the dielectric layer and contacts the first upper surface of the first conductive pad, and wherein the second bump via extends into the dielectric layer and contacts the second upper surface of the second conductive pad. In an embodiment, the first bump via has a first sidewall contacting the dielectric layer and a second sidewall contacting the passivation layer, wherein there is a first lateral offset between the first sidewall and the second sidewall. In an embodiment, the second bump via has a third sidewall contacting the dielectric layer and a fourth sidewall contacting the passivation layer, wherein there is a second lateral offset between the third sidewall and the fourth sidewall. In an embodiment, sidewalls of the second bump via contact and extend along the dielectric layer and the passivation layer, wherein a distance between the sidewalls of the second bump via continuously varies as the second bump via extends toward the substrate. In an embodiment, the second bump via is separated from the passivation layer.

According to an embodiment of the present invention, a method of forming a semiconductor device includes forming an interconnect structure over a substrate; forming a first conductive pad, a second conductive pad, and a wire over the interconnect structure and electrically coupled to the interconnect structure, wherein a width of the second conductive pad is greater than a width of the first conductive pad; conformally forming a passivation layer over the first conductive pad, the second conductive pad, and the conductive line; forming a first opening and a second opening in the passivation layer to expose the first conductive pad and the second conductive pad, respectively, while keeping the conductive line covered by the passivation layer; forming a first conductive bump, a second conductive bump and a dummy bump over the first conductive pad, the second conductive pad and the wire, respectively; and forming a first bump via under the first conductive bump and a second bump via under the second conductive bump, wherein the first and second bump vias extend through the passivation layer and electrically couple the first and second conductive bumps to the first and second conductive pads, respectively, wherein the dummy bump is electrically isolated. In an embodiment, the method further includes forming a dielectric layer over the passivation layer after forming the first and second openings and before forming the first and second conductive bumps and the dummy bump, wherein the dielectric layer fills the first and second openings; and forming third and fourth openings over the locations of the first and second openings in the dielectric layer to expose the first and second conductive pads, respectively, wherein first and second bump vias are formed in the third and fourth openings, respectively, wherein the dummy bumps are separated from the conductive lines by the passivation layer and the dielectric layer after the dummy bumps are formed.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising:

a substrate;

an interconnect structure over the substrate;

a first passivation layer over the interconnect structure;

a first conductive pad, a second conductive pad, and a conductive line disposed over the first passivation layer and electrically coupled to a conductive feature of the interconnect structure;

a conformal second passivation layer over and extending along upper surfaces and sidewalls of the first conductive pad, the second conductive pad, and the conductive line;

a first conductive bump and a second conductive bump over the first conductive pad and the second conductive pad, respectively, wherein the first conductive bump and the second conductive bump extend through the conformal second passivation layer and are electrically coupled to the first conductive pad and the second conductive pad, respectively; and

a dummy bump over the conductive line, wherein the dummy bump is spaced apart from the conductive line by the conformal second passivation layer.

2. The semiconductor device of claim 1, wherein the dummy bump comprises the same conductive material as the first and second conductive bumps, wherein the dummy bump is electrically isolated from the conductive line and the interconnect structure.

3. The semiconductor device of claim 1, further comprising a dielectric layer between the conformal second passivation layer and the dummy bump, wherein a lower surface of the dummy bump facing the substrate contacts and extends along an upper surface of the dielectric layer away from the substrate.

4. The semiconductor device of claim 3, further comprising a first bump via and a second bump via, wherein the first bump via extends through the dielectric layer and the conformal second passivation layer to electrically couple the first conductive bump to the first conductive pad, wherein the second bump via extends through the dielectric layer and the conformal second passivation layer to electrically couple the second conductive bump to the second conductive pad.

5. The semiconductor device of claim 4, wherein a first width of the first conductive bump is less than a second width of the second conductive bump.

6. The semiconductor device of claim 5, wherein a third width of the dummy bumps is the same as the first width.

7. The semiconductor device of claim 4, wherein the first bump via extends from the upper surface of the dielectric layer to the first conductive pad, wherein a width of the first bump via has a step change.

8. The semiconductor device of claim 7, wherein the second bump via extends from the upper surface of the dielectric layer to the second conductive pad, wherein the dielectric layer is laterally disposed between a sidewall of the second bump via and a sidewall of the conformal second passivation layer facing the second bump via.

9. A semiconductor device, comprising:

an interconnect structure located over the substrate;

a first conductive pad, a second conductive pad, and a wire over and electrically coupled to the interconnect structure;

a passivation layer over the first conductive pad, the second conductive pad, and the conductive line, wherein the passivation layer is conformal with and extends along outer surfaces of the first conductive pad, the second conductive pad, and the conductive line;

a first conductive bump, a second conductive bump and a dummy bump respectively located above the first conductive pad, the second conductive pad and the wire, wherein a first width of the first conductive bump is less than a second width of the second conductive bump; and

a first bump via and a second bump via respectively located under the first conductive bump and the second conductive bump, wherein the first bump via extends through the passivation layer and contacts the first conductive pad, wherein the second bump via extends through the passivation layer and contacts the second conductive pad, wherein the dummy bump is separated from the conductive line by the passivation layer and is electrically isolated from the conductive line.

10. A method of forming a semiconductor device, the method comprising:

forming an interconnect structure over a substrate;

forming a first conductive pad, a second conductive pad, and a wire over the interconnect structure and electrically coupled to the interconnect structure, wherein a width of the second conductive pad is greater than a width of the first conductive pad;

conformally forming a passivation layer over the first conductive pad, the second conductive pad, and the conductive line;

forming a first opening and a second opening in the passivation layer to expose the first conductive pad and the second conductive pad, respectively, while keeping the conductive line covered by the passivation layer;

forming a first conductive bump, a second conductive bump and a dummy bump over the first conductive pad, the second conductive pad and the wire, respectively; and

forming a first bump via under the first conductive bump and a second bump via under the second conductive bump, wherein the first and second bump vias extend through the passivation layer and electrically couple the first and second conductive bumps to the first and second conductive pads, respectively, wherein the dummy bump is electrically isolated.