CN114464590A - Packaging substrate, preparation method and packaging body - Google Patents

Packaging substrate, preparation method and packaging body Download PDF

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Publication number
CN114464590A
CN114464590A CN202011242993.5A CN202011242993A CN114464590A CN 114464590 A CN114464590 A CN 114464590A CN 202011242993 A CN202011242993 A CN 202011242993A CN 114464590 A CN114464590 A CN 114464590A
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CN
China
Prior art keywords
metal
layer
exposed
metal piece
package substrate
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Pending
Application number
CN202011242993.5A
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Chinese (zh)
Inventor
阳小芮
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DIODES TECHNOLOGY (CHENGDU) CO LTD
Shanghai KaiHong Technology Co Ltd
Diodes Shanghai Co Ltd
Original Assignee
DIODES TECHNOLOGY (CHENGDU) CO LTD
Shanghai KaiHong Technology Co Ltd
Diodes Shanghai Co Ltd
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Application filed by DIODES TECHNOLOGY (CHENGDU) CO LTD, Shanghai KaiHong Technology Co Ltd, Diodes Shanghai Co Ltd filed Critical DIODES TECHNOLOGY (CHENGDU) CO LTD
Priority to CN202011242993.5A priority Critical patent/CN114464590A/en
Publication of CN114464590A publication Critical patent/CN114464590A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the layer connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

Abstract

A packaging substrate comprises a plastic packaging layer and at least one first metal piece embedded in the plastic packaging layer; the first surface of the plastic packaging layer exposes the first surface of the first metal part, and the exposed first surface of the first metal part is lower than the first surface of the plastic packaging layer, so that a chip is arranged on the exposed first surface of the first metal part.

Description

Packaging substrate, preparation method and packaging body
Technical Field
The present disclosure relates to the field of semiconductor packaging, and in particular, to a package substrate, a method for manufacturing the package substrate, and a package.
Background
MIS small packaging product is because the encapsulation size is little, and the condition that silver thick liquid spills over can take place under the great condition of chip, and the silver thick liquid that overflows exists the risk with other metal pad bridging to lead to the product to become invalid.
Specifically, fig. 1 is a schematic diagram illustrating a conventional MIS small package product in the art. As shown in fig. 1, the specific structure of the conventional MIS small package product is that a chip 3 is attached to a first metal piece 21 of a package substrate 1, and the chip 3 is electrically connected to a second metal piece 22 located at a wire bonding position through a metal wire 4.
As shown in fig. 1, in a conventional MIS small package product, a nickel layer 5 needs to be disposed on both upper and lower surfaces of a first metal piece 21 for carrying a chip and a second metal piece 22 at a wire bonding position exposed to a package substrate 1, and the chip 3 needs to be in full contact with the first metal piece 21 through a silver paste layer 6. Therefore, the size of the silver paste layer 6 needs to be changed with the size of the chip 3, and thus, in the structure shown in fig. 1, when the size of the chip 3 is larger, the edge of the silver paste layer 6 will be close to the edge of the package substrate 1, and there is a risk of overflow; in addition, the edge of the silver paste layer 6 is also close to the second metal piece 22 at the wire bonding position, so that the risk of chip failure caused by wire bonding position pollution exists. In addition, the conventional MIS small package product shown in fig. 1 has a high manufacturing cost due to the need of providing the nickel layer 5 at a plurality of positions.
Therefore, there is a need to provide a new package substrate to overcome the above-mentioned drawbacks.
Disclosure of Invention
The application aims to provide a packaging substrate, a preparation method of the packaging substrate and a packaging body applying the packaging substrate. In this application, through packaging substrate's structural design, effectively controlled the excessive scope on silver thick liquid layer, successfully avoided the silver thick liquid to spill over the encapsulation body or with the encapsulation in other metals take place the condition of bridging, also reduced noble metal's use amount simultaneously, effectively reduced manufacturing cost.
In order to achieve the above object, according to an aspect of the present application, a package substrate is provided, which includes a molding layer and at least one first metal element embedded in the molding layer; the first surface of the plastic packaging layer exposes the first surface of the first metal part, and the exposed first surface of the first metal part is lower than the first surface of the plastic packaging layer, so that a chip is arranged on the exposed first surface of the first metal part.
In some embodiments, the package substrate further comprises at least one second metal piece embedded in the molding layer, and the first surface of the molding layer exposes the first surface of the second metal piece; the exposed first surface of the second metal piece is flush with the first surface of the plastic packaging layer, or the exposed first surface of the second metal piece is lower than the first surface of the plastic packaging layer.
In some embodiments, the first surface of the second metal piece is exposed higher than the first surface of the first metal piece.
In some embodiments, a surface treatment layer is disposed on the exposed first surface of the second metal piece.
In some embodiments, the surface of the surface treatment layer exceeds the first surface of the plastic packaging layer, or the surface of the surface treatment layer is flush with the first surface of the plastic packaging layer.
In some embodiments, the molding compound layer further has a second surface opposite to the first surface, and the second surface of the molding compound layer exposes the second surface of the first metal part and the second surface of the second metal part.
In some embodiments, a surface treatment layer is disposed on the exposed second surface of the first metal part and the second surface of the second metal part.
In some embodiments, the surface treatment layer is a laminate of at least one metallic nickel layer and at least one metallic gold layer.
In some embodiments, a surface of the metallic nickel layer is configured to contact at least one of the second surface of the first metal part, the first surface of the second metal part, and the second surface of the second metal part; the other surface is used for contacting the metal gold layer.
According to another aspect of the present application, there is also provided a package including: the package substrate is provided with a chip arranged on the exposed first surface of the first metal piece, and a solder arranged on the exposed first surface of the first metal piece; wherein the solder is not formed on the first surface of the plastic packaging layer.
According to another aspect of the present application, there is also provided a method for manufacturing the package substrate, including the steps of:
forming a first metal part, a second metal part and a plastic packaging layer for packaging the first metal part and the second metal part on a carrier plate;
grinding to expose the second surface of the first metal piece and the second surface of the second metal piece;
after the carrier plate is removed, forming a surface treatment layer on the exposed second metal piece; and the number of the first and second groups,
etching to enable the first surface of the exposed first metal piece to be lower than the first surface of the plastic packaging layer.
In some embodiments, in the step of forming the surface treatment layer on the exposed second metal piece, a protective layer is formed on the exposed first metal piece to prevent the surface treatment layer from being formed on the first metal piece.
In some embodiments, prior to the step of forming a surface treatment layer on the exposed second metal piece, the method of making further comprises: and etching to enable the first surface of the second metal piece to be exposed to be lower than the first surface of the plastic packaging layer.
In some embodiments, in the step of etching to make the first surface of the exposed second metal part lower than the first surface of the plastic encapsulation layer, a protective layer is formed on the exposed first metal part to prevent the first metal part from being etched.
In this application, through control the surface that is used for pasting the metalwork of chip of packaging substrate is less than the encapsulated layer surface to it is sunken to form silver thick liquid layer department, thereby has controlled the excessive scope on silver thick liquid layer effectively, has successfully avoided the silver thick liquid to spill over the encapsulation body or take place the condition of bridging with other metals in the encapsulation body. Meanwhile, in the packaging body, the surface treatment layer is not arranged on the surface of the metal piece for mounting the chip, so that the manufacturing cost is effectively reduced.
Drawings
FIG. 1 is a schematic diagram of a conventional package product;
fig. 2A to 2C are schematic structural views of a package substrate according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a package according to an embodiment of the present application;
FIG. 4 is a flow chart of a method of fabricating a package substrate according to an embodiment of the present application;
FIGS. 5A to 5G are schematic views of the structures corresponding to FIG. 4;
fig. 6A and 6B are schematic structural views of a package substrate according to another embodiment of the present application.
Detailed Description
Hereinafter, the technology of the present application will be described in detail with reference to specific embodiments. It should be understood that the following detailed description is only for assisting those skilled in the art in understanding the present application, and is not intended to limit the present application.
As shown in fig. 2A to fig. 2C, in the present embodiment, a package substrate 100 is provided, which includes a molding layer 110, at least one first metal element 120 and at least one second metal element 130 embedded in the molding layer. It can be understood by those skilled in the art that the number of the first metal pieces 120 and the second metal pieces 130 can be set according to actual needs, and is not limited to the number shown in fig. 2A and 2B.
As shown in fig. 2A and 2B, the plastic package layer 110, the first metal part 120, and the second metal part 130 have an upper surface and a lower surface opposite to each other, that is, a first surface and a second surface. Specifically, as shown in fig. 2A and 2B, the molding layer 110 has a first surface 110A and a second surface 110B, the first metal piece 120 has a first surface 120A and a second surface 120B, and the second metal piece 130 has a first surface 130A and a second surface 130B.
As shown in fig. 2A, a first surface 110A of the molding layer 110 exposes the first surface 120A of the first metal element 120 and the first surface 130A of the second metal element 130, and a second surface 110B of the molding layer 110 exposes the second surface 120B of the first metal element 120 and the second surface 130B of the second metal element 130.
In this embodiment, as shown in fig. 2A, the exposed first surface 120A of the first metal part 120 and the exposed first surface 130A of the second metal part 130 are lower than the first surface 110A of the molding layer 110. It will be understood by those skilled in the art that the first surface 120A of the first metal piece 120 and the first surface 130A of the second metal piece 130 may be in the same plane or in different planes. Preferably, in order to better prevent silver paste overflow, as shown in fig. 2A, the first surface 120A of the first metal piece 120 is lower than the first surface 130A of the second metal piece 130.
As shown in fig. 2B, a chip 101 is directly disposed on the first surface 120A of the exposed first metal component 120 shown in fig. 2A on the package substrate 100. A surface treatment layer 102 is disposed on the first surface 130A of the exposed second metal part 130 shown in fig. 2A. As shown in fig. 2B, the surface treatment layer 102 may include a stack of at least one metal nickel layer 1021 and at least one metal gold layer 1022, wherein the metal nickel layer 1021 contacts the second metal element 130.
In the present embodiment, as shown in fig. 2B, the surface of the surface treatment layer 102 is flush with the first surface 110A of the molding layer 110. Of course, it can be understood by those skilled in the art that the surface of the surface treatment layer 102 may also extend beyond the first surface 110A of the molding layer 110, as shown in fig. 2C.
In addition, as shown in fig. 2B and 2C, the surface treatment layer 102 is also disposed on the second surface 120B of the first metal piece 120 and the second surface 130B of the second metal piece 130, which are exposed as shown in fig. 2A. Similarly, the surface treatment layer 102 may include a stack of at least one metal nickel layer 1021 and at least one metal gold layer 1022, wherein the metal nickel layer 1021 contacts the first metal element 120 and the second metal element 130.
Thus, when forming the package 200, as shown in fig. 3, a solder 103, such as a silver paste, is formed on the exposed first surface 120A of the first metal piece 120 shown in fig. 2A, so that the solder 103 is not formed on the first surface 110A of the molding layer 110. Therefore, in the package 200 shown in fig. 3, the overflow range of the solder 103 is limited on the first surface 120A of the first metal piece 120, and the situation that the solder 103 overflows the package or bridges with other metals in the package is successfully avoided. Meanwhile, as shown in fig. 3, in the package 200 of the present application, no surface treatment layer is disposed between the first metal parts 120 of the mounted chip 103, which effectively reduces the manufacturing cost.
Hereinafter, the method for manufacturing the package substrate 100 will be described in detail with reference to fig. 4 and 5A to 5G.
As shown in fig. 4 and 5A, the method for manufacturing the package substrate 100 includes step S1: a first metal part 120, a second metal part 130, and a plastic encapsulation layer 110 encapsulating the first metal part 120 and the second metal part 130 are formed on a carrier SP. As will be understood by those skilled in the art, in this step, the first metal part 120 and the second metal part 130 may be first formed on the carrier plate SP by a method known in the art, such as an electroplating method, a deposition method, and the like, and then the plastic encapsulation layer 110 is formed by a plastic encapsulation method known in the art.
As shown in fig. 4 and 5B, the method for preparing the package substrate 100 includes step S2: the molding layer 110 is polished to expose the second surface 120B of the first metal part 120 and the second surface 130B of the second metal part 130.
As shown in fig. 4 and 5C, the method for manufacturing the package substrate 100 includes step S3: forming a surface treatment layer 102 on the exposed second surface 120B of the first metal piece 120 and the second surface 130B of the second metal piece 130. It will be understood by those skilled in the art that, in this step, a metal nickel layer 1021 and a metal gold layer 1022 may be formed on the exposed second surface 120B of the first metal piece 120 and the second surface 130B of the second metal piece 130 by methods known in the art, such as electroplating, deposition, and the like.
As shown in fig. 4 and 5D, the method for manufacturing the package substrate 100 includes step S4: removing the carrier plate, and etching the exposed first surface 120A of the first metal piece 120 and/or the first surface 130A of the second metal piece 130 to obtain that the exposed first surface 120A of the first metal piece 120 is lower than the first surface 110A of the plastic encapsulation layer 110 as shown in fig. 2A.
Specifically, as shown in fig. 5E, the step S4 includes a step S41: a protection layer MP is disposed on the first surface 120A of the first metal part 120, and the exposed first surface 130A of the second metal part 130 is etched, so that the first surface 130A of the second metal part 130 is lower than the first surface 110A of the molding layer 110.
As shown in fig. 5F, the step S4 includes a step S42: a surface treatment layer 102 is formed on the first surface 130A of the second metal member 130. It will be understood by those skilled in the art that, in this step, the metallic nickel layer 1021 may be formed first on the exposed first surface 130A of the second metal piece 120 by a method known in the art, such as electroplating, deposition, etc., and then the metallic gold layer 1022 is formed.
As shown in fig. 5G, the step S4 further includes a step S43: the protection layer MP is removed, and the exposed first surface 120A of the first metal element 120 is etched, so that the first surface 120A of the first metal element 120 is lower than the first surface 110A of the molding layer 110.
In another embodiment of the present application, as shown in fig. 6A and 6B, a package substrate 300 is provided, which includes a molding layer 310, at least one first metal element 320 and at least one second metal element 330 embedded in the molding layer. It can be understood by those skilled in the art that the number of the first metal parts 320 and the second metal parts 330 can be set according to actual needs, and is not limited to the number shown in fig. 6A and 6B.
Similar to the package substrate 100, as shown in fig. 6A and 6B, the molding layer 310, the first metal element 320, and the second metal element 330 each have an upper surface and a lower surface, which are opposite to each other, and are the first surface and the second surface. Specifically, as shown in fig. 6A and 6B, the molding layer 310 has a first surface 310A and a second surface 310B, the first metal part 320 has a first surface 320A and a second surface 320B, and the second metal part 330 has a first surface 330A and a second surface 330B.
Unlike the package substrate 100 shown in fig. 2A, in the package substrate 300 shown in fig. 6A, the first surface 320A of the exposed first metal part 320 is lower than the first surface 310A of the molding layer 310, and the first surface 330A of the exposed second metal part 330 is flush with the first surface 310A of the molding layer 310.
Similar to the package substrate 100, as shown in fig. 6B, in the package substrate 300, a chip 101 is directly disposed on the first surface 320A of the exposed first metal element 320 shown in fig. 6A. A surface treatment layer 102 is disposed on the exposed first surface 330A of the second metal part 330 shown in fig. 6A. As shown in fig. 6B, the surface treatment layer 102 may include a stack of at least one metal nickel layer 1021 and at least one metal gold layer 1022, wherein the metal nickel layer 1021 contacts the second metal part 330.
Similar to the package substrate 100, as shown in fig. 6B, the surface treatment layer 102 is disposed on the second surface 320B of the first metal part 320 and the second surface 330B of the second metal part 330, which are exposed as shown in fig. 6A. Similarly, the surface treatment layer 102 may include a stack of at least one metal nickel layer 1021 and at least one metal gold layer 1022, wherein the metal nickel layer 1021 contacts the first metal element 120 and the second metal element 130.
It can be understood by those skilled in the art that the method for manufacturing the package substrate 300 is substantially the same as the method for manufacturing the package substrate 100, that is, the method for manufacturing the package substrate 300 includes the above-mentioned step S1, step S2, step S3, step S4, step S41, step S42, and step S43. In contrast, the method for manufacturing the package substrate 300 does not include the step of etching the exposed first surface 130A of the second metal part 130 in step S41, so that the first surface 130A of the second metal part 130 is lower than the first surface 110A of the molding layer 110. That is, step S42 of the method for manufacturing the package substrate 300 is: a protective layer MP is disposed on the first surface 320A of the first metal element 320. The contents of the remaining steps are the same as the preparation method of the package substrate 100, and are not described herein again.
The present application has been described in relation to the above embodiments, which are only examples for implementing the present application. It must be noted that the disclosed embodiments do not limit the scope of the application. Rather, modifications and equivalent arrangements included within the spirit and scope of the claims are included within the scope of the present application.

Claims (9)

1. The packaging substrate is characterized by comprising a plastic packaging layer and at least one first metal piece embedded in the plastic packaging layer; wherein the content of the first and second substances,
a first surface of the plastic package layer exposes the first surface of the first metal part, and,
the first surface of the exposed first metal piece is lower than the first surface of the plastic packaging layer, so that a chip is arranged on the first surface of the exposed first metal piece.
2. The package substrate of claim 1, wherein the package substrate further comprises at least a second metal embedded in the molding layer, and a first surface of the molding layer exposes a first surface of the second metal; the exposed first surface of the second metal piece is flush with the first surface of the plastic packaging layer, or the exposed first surface of the second metal piece is lower than the first surface of the plastic packaging layer.
3. The package substrate of claim 2, wherein a first surface of the second metal piece is exposed higher than a first surface of the first metal piece.
4. The package substrate of claim 2, wherein a surface treatment layer is disposed on the exposed first surface of the second metal piece.
5. The packaging substrate of claim 4, wherein a surface of the surface treatment layer exceeds the first surface of the molding layer or is flush with the first surface of the molding layer.
6. The package substrate of claim 2, wherein the molding layer further has a second surface opposite to the first surface, and the second surface of the molding layer exposes the second surface of the first metal part and the second surface of the second metal part.
7. The package substrate of claim 6, wherein a surface treatment layer is disposed on the exposed second surface of the first metal element and the second surface of the second metal element.
8. A package, comprising: the package substrate of any of claims 4 to 7, a chip disposed on the exposed first surface of the first metal piece, and a solder disposed on the exposed first surface of the first metal piece; wherein the solder is not formed on the first surface of the plastic packaging layer.
9. A method for manufacturing a package substrate, the method comprising:
forming a first metal part, a second metal part and a plastic packaging layer for packaging the first metal part and the second metal part on a carrier plate;
grinding to expose the second surface of the first metal piece and the second surface of the second metal piece;
forming a surface treatment layer on the exposed second surface of the first metal piece and the second surface of the second metal piece; and the number of the first and second groups,
and removing the carrier plate, and etching to enable the first surface of the exposed first metal piece to be lower than the first surface of the plastic packaging layer.
CN202011242993.5A 2020-11-09 2020-11-09 Packaging substrate, preparation method and packaging body Pending CN114464590A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011242993.5A CN114464590A (en) 2020-11-09 2020-11-09 Packaging substrate, preparation method and packaging body

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011242993.5A CN114464590A (en) 2020-11-09 2020-11-09 Packaging substrate, preparation method and packaging body

Publications (1)

Publication Number Publication Date
CN114464590A true CN114464590A (en) 2022-05-10

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
CN (1) CN114464590A (en)

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