CN114464585A

CN114464585A - Semiconductor substrate, semiconductor device, integrated circuit system and electronic equipment

Info

Publication number: CN114464585A
Application number: CN202210376468.5A
Authority: CN
Inventors: 王晓东; 曾维; 黄辰骏; 王海波; 刘志刚
Original assignee: Phytium Technology Co Ltd
Current assignee: Phytium Technology Co Ltd
Priority date: 2022-04-12
Filing date: 2022-04-12
Publication date: 2022-05-10
Anticipated expiration: 2042-04-12
Also published as: CN114464585B

Abstract

The invention provides a semiconductor substrate, a semiconductor device, an integrated circuit system and an electronic device, wherein the semiconductor substrate comprises a substrate main body and a plurality of first pins positioned on a first side of the substrate main body; the second side of the substrate main body can be used for packaging the chip, and the second side is opposite to the first side; the first side surface of the substrate main body at least comprises a first area and a second area, wherein a first pin in the first area comprises a power pin and a ground pin, the power pin and the ground pin can be respectively and electrically connected with two ends of a decoupling capacitor, and the distribution density of the first pin in the first area is determined by the size and the number of the decoupling capacitor; the distribution density of the first pins in the second region is greater than that of the first pins in the first region, so that decoupling capacitors with corresponding sizes and numbers are correspondingly arranged in the first region, the noise reduction effect of the decoupling capacitors meets the requirements, and meanwhile the area of the semiconductor substrate and the packaging area of a semiconductor device, namely a packaging chip, are reduced.

Description

Semiconductor substrate, semiconductor device, integrated circuit system and electronic equipment

Technical Field

The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor substrate, a semiconductor device, an integrated circuit system, and an electronic apparatus.

Background

In an integrated circuit, a processor chip, a memory chip, and semiconductor devices such as capacitors and resistors may be mounted on the same printed circuit board so as to be connected to and integrated with each other through the printed circuit board. Although the noise influence of other devices in the circuit on the chip can be reduced by mounting the decoupling capacitor on the printed circuit board, the packaging area of the chip needs to be matched with the size and the number of the decoupling capacitors, otherwise the noise reduction effect of the decoupling capacitor cannot meet the requirement.

Disclosure of Invention

In view of the above, the present invention is directed to a semiconductor substrate, a semiconductor device, an integrated circuit system and an electronic device, so as to further reduce the packaging area of a chip while ensuring that the noise reduction effect of a decoupling capacitor meets the requirements.

In a first aspect, the present application provides a semiconductor substrate comprising a substrate body and a plurality of first pins located at a first side of the substrate body; a second side of the substrate body may encapsulate a chip, the second side being disposed opposite the first side;

the first side surface of the substrate main body at least comprises a first area and a second area, and the plurality of first pins are respectively positioned in the first area and the second area;

the first pins in the first region comprise power pins and ground pins, the power pins and the ground pins can be respectively and electrically connected with two ends of a decoupling capacitor, and the distribution density of the first pins in the first region is determined by the size and the number of the decoupling capacitor; the distribution density of the first pins in the second area is greater than that of the first pins in the first area.

The distribution density of the first pins in the first area is determined by the size and the number of the decoupling capacitors needing to be electrically connected, so that the decoupling capacitors with corresponding size and number can be correspondingly arranged in the first area, and the noise reduction effect of the decoupling capacitors can meet the requirement; in addition, since the distribution density of the first pins in the second region is greater than the distribution density of the first pins in the first region, the area of the semiconductor substrate and the package area of the packaged chip including the semiconductor substrate can be further reduced by reducing the area of the second region.

Optionally, the first region is located in a central region of the substrate body, the second region is located in an edge region of the substrate body, and the second region surrounds the first region.

The smaller the distribution density of the first pins is, the greater the stress borne by the region where the first pins are located during welding, so that the region with the greater stress is arranged in the central region of the semiconductor substrate, and the phenomenon that the edge region is warped and the like due to the overlarge stress borne by the edge region can be avoided.

Optionally, the first pins in the first region and the first pins in the second region are uniformly distributed; and/or the presence of a gas in the gas,

the first pins in the first region and the first pins in the second region are distributed in a central symmetry mode.

Through making first pin evenly distributed, can guarantee sufficient space utilization, through making first pin central symmetry distribute, stress evenly distributed when can be so that the welding avoids certain regional stress too big, leads to semiconductor substrate to appear warpage scheduling problem.

Optionally, the pitch of the first pins in the first region is greater than or equal to the length of the decoupling capacitor, and the pitch of the first pins in the second region is smaller than the length of the decoupling capacitor, so that the projection of the decoupling capacitor on the semiconductor substrate covers the projections of the power pins and the ground pins electrically connected with the decoupling capacitor, so that each decoupling capacitor is arranged right below the power pins and the ground pins, and the noise reduction effect of the decoupling capacitors is optimized.

Optionally, the pitch of the first pins in the first region is greater than or equal to 0.9mm, and the pitch of the first pins in the second region is within a range of 0.7mm to 1mm, so as to reduce the area of the second region as much as possible and reduce the area of the semiconductor substrate and the packaged chip including the semiconductor substrate as much as possible on the basis of meeting the requirement that each first pin in the first region is correspondingly provided with a decoupling capacitor of 0402 specification.

Optionally, each of the power supply pins and one of the ground pins disposed adjacent thereto are electrically connected to one of the decoupling capacitors, so that a sufficient number of decoupling capacitors are provided to improve noise reduction.

Optionally, the semiconductor substrate further comprises a plurality of second pins located at a second side of the substrate body; the second pin may be electrically connected to the chip, and the second pin is electrically connected to the first pin through a first conductive member penetrating the substrate body.

Optionally, the first pins include pads with solder balls, and the second pins include pads, so as to package the chip by using ball grid array packaging technology.

In a second aspect, the present application provides a semiconductor device comprising a chip and a semiconductor substrate as described in any of the above, the chip being packaged on a second side of the semiconductor substrate.

The first region of the semiconductor substrate can be correspondingly provided with decoupling capacitors with corresponding sizes and numbers, so that the noise reduction effect of the decoupling capacitors meets the requirement, and the distribution density of the first pins in the second region is greater than that of the first pins in the first region, so that the area of the semiconductor substrate and the packaging area of a packaged chip including the semiconductor substrate, namely a semiconductor device, can be further reduced by reducing the area of the second region.

Optionally, the chip includes a power pin, a ground pin, and a signal pin, where the power pin is electrically connected to a power pin in the first region of the semiconductor substrate, the ground pin is electrically connected to a ground pin in the first region of the semiconductor substrate, and the signal pin is electrically connected to the first pin in the second region of the semiconductor substrate, where the pin is electrically connected to the first pin through the second pin of the semiconductor substrate and the first conductive component.

In a third aspect, the present application provides an integrated circuit system comprising a printed circuit board and a semiconductor device as described above mounted on the printed circuit board.

Since the semiconductor substrate and the packaged chip including the semiconductor substrate, i.e., the semiconductor device, have a small packaging area, it is possible to facilitate integration of various devices on a printed circuit board, and to facilitate integration and miniaturization of an integrated circuit system.

Optionally, the integrated circuit system includes a decoupling capacitor mounted on the printed circuit board, and the decoupling capacitor is electrically connected to a power pin and a ground pin in the first region of the semiconductor substrate in the semiconductor device, so as to reduce noise of the semiconductor device, i.e., the packaged chip, and provide stable power to the semiconductor device, i.e., the packaged chip, through the decoupling capacitor.

Optionally, the decoupling capacitor is mounted on a side of the printed circuit board facing away from the semiconductor device, and the decoupling capacitor is electrically connected to the semiconductor device through a second conductive component in the printed circuit board, so that the decoupling capacitor is disposed right below a power pin and a ground pin of the semiconductor device, and the noise reduction effect of the decoupling capacitor is optimized.

Optionally, each power pin in the first region and a ground pin arranged adjacent to the power pin are electrically connected with a decoupling capacitor; and the orthographic projection of each decoupling capacitor on the semiconductor substrate covers the orthographic projection of the power supply pin and the orthographic projection of the grounding pin which are electrically connected with the decoupling capacitor, so that each decoupling capacitor is arranged right below the power supply pin and the grounding pin, and the noise reduction effect of the decoupling capacitor is optimal.

In a fourth aspect, the present application provides an electronic device characterized by comprising an integrated circuit system as described in any of the above.

Since the integrated circuit system can be more integrated and miniaturized compared to the related art, miniaturization of the electronic device can be realized.

Drawings

The above and other objects, features and advantages of the present application will become more apparent by describing in more detail embodiments of the present application with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. In the drawings, like reference numbers generally represent like parts or steps.

Fig. 1 is a schematic cross-sectional view of a packaged chip.

Fig. 2 is a schematic top view of the semiconductor substrate shown in fig. 1 with the leads.

Fig. 3 is another schematic top view of the semiconductor substrate shown in fig. 1 with the leads.

Fig. 4 is a schematic cross-sectional view of a semiconductor substrate according to an embodiment of the invention.

Fig. 5 is a schematic cross-sectional view of a semiconductor substrate according to another embodiment of the invention.

Fig. 6 is a schematic top view of a first side of a semiconductor substrate according to an embodiment of the invention.

Fig. 7 is a schematic top view of a first side of a semiconductor substrate according to an embodiment of the invention.

Fig. 8 is a schematic top view of a first side of a semiconductor substrate according to an embodiment of the invention.

Fig. 9 is a schematic top view of a first side of a semiconductor substrate according to an embodiment of the invention.

Fig. 10 is a schematic top view of a semiconductor substrate according to an embodiment of the invention.

Fig. 11 is a schematic top view of a first side of a semiconductor substrate according to an embodiment of the invention.

Fig. 12 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Fig. 13 is a schematic structural diagram of an integrated circuit system according to an embodiment of the present invention.

Fig. 14 is a schematic bottom plan view of the printed circuit board shown in fig. 13.

Detailed Description

The technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention.

Fig. 1 is a schematic cross-sectional view of a packaged chip, as shown in fig. 1, the packaged chip includes a chip 10 and a semiconductor substrate 11 packaging the chip 10, a side of the semiconductor substrate 11 facing away from the chip 10 has a plurality of pins 12, and each pin 12 includes a pad 12a and a solder ball 12b connected to the pad 12 a. Wherein the packaged chip can be soldered on the printed circuit board by melting the solder balls 12b by heating.

Fig. 2 is a schematic top view of the semiconductor substrate 11 shown in fig. 1, which has a pin 12, and as shown in fig. 2, the pin 12 includes a power pin 120, a ground pin 121, and a signal pin 122. Also, the power pin 120 and the ground pin 121 are usually provided with a decoupling capacitor 13, and the decoupling capacitor 13 is electrically connected to the power pin 120 and the ground pin 121, so as to reduce the noise coupled to the power pin 120 from other components, so that the power pin 120 can provide stable power.

In order to ensure the uniformity of the soldering of the solder balls 12b, the plurality of pins 12 of the semiconductor substrate 11 are generally uniformly distributed, i.e., the pitch of each pin 12 is equal in size. Accordingly, as shown in fig. 2, if the distance D1 between the power supply pin 120 and the ground pin 121 is greater than or equal to the length D2 of the decoupling capacitor 13, the area of the semiconductor substrate 11 is increased, and the package area of the packaged chip including the semiconductor substrate is increased. As shown in fig. 3, fig. 3 is another schematic top view of the semiconductor substrate 11 shown in fig. 1, where the semiconductor substrate has a pin 12 side, and if the distance D1 between the power pin 120 and the ground pin 121 is smaller than the length D2 of the decoupling capacitor 13, some of the power pins 120 may not be provided with the decoupling capacitor 13, which results in poor noise reduction effect of the packaged chip and poor power stability of the packaged chip.

Based on this, embodiments of the present invention provide a semiconductor substrate, in which decoupling capacitors of a predetermined size and number are disposed by disposing power supply pins and ground pins, which need to be electrically connected to the decoupling capacitors, in the same region and making the distribution density of the pins in the region smaller, and other pins, which need not be electrically connected to the decoupling capacitors, are disposed in other regions and making the distribution density of the pins in the region larger, so as to reduce the area of the semiconductor substrate and the package area of a packaged chip including the semiconductor substrate.

As an optional implementation of the present disclosure, an embodiment of the present invention provides a semiconductor substrate. The semiconductor substrate may be a carrier of a chip package, i.e. the semiconductor substrate may also be referred to as a package substrate. In addition, the semiconductor substrate can provide the effects of electric connection, protection, support, heat dissipation, assembly and the like for the chip.

As shown in fig. 4, fig. 4 is a schematic cross-sectional structure diagram of a semiconductor substrate according to an embodiment of the present invention, where the semiconductor substrate 4 includes a substrate main body 40 and a plurality of first pins (pins) 41 located on a first side of the substrate main body 40. The second side of the substrate body 40 may be packaged with a chip, i.e. a chip may be packaged at the second side of the substrate body 40, which is opposite to the first side. Wherein the chip is a bare chip (Die).

In some embodiments of the present invention, each of the first pins 41 may include a pad 41a and a solder ball 41b connected to the pad 41 a. Also, the land 41a having the solder ball 41b may be electrically connected to a contact point on the printed circuit board by melting the solder ball 41b by heating.

In some alternative examples, the pads 41a may be partially located inside the substrate body 40 and partially located outside the substrate body 40, the inner portion of the pads 41a may be electrically connected to the traces inside the substrate body 40, and the outer portion of the pads 41a may be electrically connected to the solder balls 41b outside the substrate body 40. In other alternative examples, the pads 41a may be entirely located inside the substrate body 40, and the solder balls 41b are electrically connected to the pads 41a inside thereof through the openings of the substrate body 40.

Of course, the present invention is not limited thereto, and in other embodiments, as shown in fig. 5, fig. 5 is a schematic cross-sectional structure diagram of a semiconductor substrate according to another embodiment of the present invention, the bonding pads 41a in the first pins 41 may not be connected to the solder balls 41b, that is, the first pins 41 may only include the bonding pads 41 a. Wherein the pad 41a in fig. 5 is at least partially located outside the substrate main body 40. Also, the pad 41a may be electrically connected to a contact point on the printed circuit board by a conductive paste or the like.

It is understood that whether the bonding pad 41a in the first pin 41 is externally connected to the solder ball 41b may be determined by the packaging form of the chip. For example, when a chip is packaged by ball grid array packaging technology, the pads 41a necessarily circumscribe the solder balls 41 b.

In some embodiments of the present invention, as shown in fig. 4, the cross-sectional shape of the solder ball 41b is circular, but the present invention is not limited thereto, and in other embodiments, the cross-sectional shape of the solder ball 41b may also be oval. The cross-sectional shape of the pad 41a may be circular, square, or diamond.

In an embodiment of the present invention, as shown in fig. 4 and fig. 6, fig. 6 is a schematic top view structure diagram of a first side of a semiconductor substrate according to an embodiment of the present invention, a surface of the first side of the substrate main body 40 at least includes a first area a1 and a second area a2, and a plurality of first pins 41 are respectively located in the first area a1 and the second area a 2.

Also, the first pins 41 in the first region a1 include power pins 410 and ground pins 411, and the first pins 41 in the second region a2 include signal pins. The power pin 410 and the ground pin 411 may be electrically connected to two ends of the decoupling capacitor, respectively, to reduce noise through the decoupling capacitor, so that the power pin 410 provides a stable power signal.

The power pin 410 may be electrically connected to a power terminal of the pcb to transmit a power signal provided by the pcb to the chip, the ground pin 411 may be electrically connected to a ground terminal of the pcb to transmit a ground signal provided by the pcb to the chip, and the signal pin 412 may be electrically connected to a signal terminal of the pcb to transmit an input signal provided by the pcb to the chip and/or transmit an output signal of the chip to the pcb.

In some embodiments of the present invention, the first pins 41 in the first region a1 are all power pins 410 and ground pins 411, and the first pins 41 in the second region a2 are all signal pins 412. However, the invention is not limited thereto, and in other embodiments, the first pins 41 in the second area a2 may be partly the power pins 410 and the ground pins 411, and partly the signal pins 412. That is, in some embodiments of the present invention, only the power pins 410 and the ground pins 411 that need to be electrically connected to the decoupling capacitors may be disposed in the first region a1, and the power pins 410 and the ground pins 411 that do not need to be electrically connected to the decoupling capacitors may be disposed in the second region a 2.

Wherein the distribution density of the first pins 41 in the first area a1 is determined by the size and number of the decoupling capacitors. For example, whether each power pin 410 is provided with a corresponding decoupling capacitor may be determined according to the requirement of noise reduction effect, if each power pin 410 is provided with a corresponding decoupling capacitor, the number of the decoupling capacitors may be determined according to the number of the power pins 410, and if some power pins 410 are provided with corresponding decoupling capacitors, the number of the decoupling capacitors may be determined according to the number of the some power pins 410. In addition, the decoupling capacitor can be determined to be a decoupling capacitor of a certain specification according to the noise reduction effect requirement and the size of the packaged chip, and then the size of the decoupling capacitor of the specification can be determined.

After determining the number and size of the decoupling capacitors, the number of the first pins 41 in the first area a1 may be determined according to the number of the decoupling capacitors, and the pitch of the first pins 41 in the first area a1 may be determined according to the size of the decoupling capacitors, so that the distribution density of the first pins 41 in the first area a1 may be determined.

Further, the distribution density of the first pins 41 in the second region a2 may be determined such that the distribution density of the first pins 41 in the second region a2 is greater than the distribution density of the first pins 41 in the first region a 1. For example, the distribution density of the first pins 41 in the second region a2 is determined as the maximum density that can be achieved by the packaging process, so as to reduce the area of the second region a2 to the greatest extent possible.

It is understood that, in the embodiment of the present invention, the sizes of the first pins 41 may be the same, and based on this, the distribution density of the first pins 41 in the second region a2 is greater than the distribution density of the first pins 41 in the first region a1, which may be understood as that the pitch L2 of the first pins 41 in the second region a2 is smaller than the pitch L1 of the first pins 41 in the first region a 1.

In the embodiment of the present invention, the first pins 41, that is, the power pins 410 and the ground pins 411, which need to be correspondingly connected to the decoupling capacitors are disposed in the first area a1, and the distribution density of the first pins 41 in the first area a1 is determined by the decoupling capacitors with preset size and number, so that the decoupling capacitors with preset size and number can be correspondingly disposed in the first area a1, and the noise reduction effect of the decoupling capacitors can meet the requirements.

In the embodiment of the present invention, the signal pins 412, which are the other first pins 41 that do not need to be electrically connected to the decoupling capacitor, are provided in the second region a2, and the distribution density of the first pins 41 in the second region a2 is made greater than the distribution density of the first pins 41 in the first region a1, so that the area of the second region a2 can be reduced, the area of the semiconductor substrate 4 can be reduced, and the package area of the packaged chip including the semiconductor substrate 4 can be reduced.

In some embodiments of the present invention, as shown in fig. 6, the first region a1 is located in the central region of the substrate body 40, the second region a2 is located in the edge region of the substrate body 40, and the second region a2 surrounds the first region a1, so that the pins of the semiconductor substrate 4 are arranged in a sparse-middle and dense-periphery manner. Since the smaller the distribution density of the first pins 41, the greater the stress applied to the region where the first pins are located during soldering, the larger the stress applied to the region is set in the central region of the semiconductor substrate 4, and it is possible to avoid deformation such as warpage of the edge region due to the excessive stress applied to the edge region.

Of course, the present invention is not limited thereto, and if the distribution density of the first pins 41 in the first region a1 is not much different from the distribution density of the first pins 41 in the second region a2, and deformation such as warpage does not occur in the edge region, in other embodiments, as shown in fig. 7 and 8, fig. 7 is a schematic top view structure diagram of the first side of the semiconductor substrate according to another embodiment of the present invention, fig. 8 is a schematic top view structure diagram of the first side of the semiconductor substrate according to another embodiment of the present invention, the first region a1 may also be located in the edge region of the substrate main body 40, and the second region a2 semi-surrounds the first region a 1.

In some embodiments of the present invention, as shown in fig. 6 to 8, the first pins 41 in the first area a1 and the second area a2 are uniformly distributed, and/or the first pins 41 in the first area a1 and the second area a2 are centrosymmetrically distributed. Wherein, through making first pin 41 evenly distributed, can guarantee sufficient space utilization, through making first pin 41 central symmetry distribute, can be so that the stress evenly distributed when welding, avoid certain regional stress too big, lead to semiconductor substrate 4 to appear warpage scheduling problem.

Of course, the present invention is not limited thereto, and in other embodiments, as shown in fig. 9, fig. 9 is a schematic top view structure diagram of the first side of the semiconductor substrate according to another embodiment of the present invention, the first pins 41 in the first area a1 may be distributed without central symmetry according to some specific design requirements, so that the first pins 41 in the first area a1 are also distributed unevenly, which is not described herein again.

In some embodiments of the present invention, as shown in fig. 10, fig. 10 is a schematic top view structure diagram of a first side of a semiconductor substrate according to another embodiment of the present invention, each power pin 410 and a ground pin 411 disposed adjacent thereto are disposed corresponding to and electrically connected to a decoupling capacitor 42, so as to improve noise reduction effect by disposing a sufficient number of decoupling capacitors 42.

Further, the pitch L1 of the first pins 41 in the first region a1 is greater than or equal to the length L of the decoupling capacitor 42, so that the projection of the decoupling capacitor 42 on the semiconductor substrate 4 overlaps the projections of the power pin 410 and the ground pin 411 electrically connected thereto, so that each decoupling capacitor 42 is disposed directly below the power pin 410 and the ground pin 411, to optimize the noise reduction effect of the decoupling capacitor 42. In addition, the pitch L2 of the first pins 41 in the second region a2 may be smaller than the length L of the decoupling capacitor 42, and may even be smaller than the width of the decoupling capacitor 42, in order to minimize the area of the semiconductor substrate 4.

In some embodiments of the present invention, the semiconductor substrate 4 is a substrate for packaging a microchip, for example, the length and width of the semiconductor substrate 4 are both equal to 25mm, and the semiconductor substrate 4 can be electrically connected to a 0402 size decoupling capacitor. This is because the 0402 size decoupling capacitors have greater stability in industrial or other more hostile environments than capacitors of smaller size.

Based on this, the pitch of the first pins 41 in the first region a1 is greater than or equal to 0.9mm, and the pitch of the first pins 41 in the second region a2 is in the range of 0.7mm to 1mm, so as to reduce the area of the second region a2 as much as possible and the area of the semiconductor substrate 4 and the packaged chip including the semiconductor substrate 4 as much as possible while satisfying the requirement that the decoupling capacitor of 0402 size is correspondingly provided for each first pin 41 in the first region a 1.

In some alternative examples, the pitch of the first pins 41 in the first region a1 is 1mm, and the pitch of the first pins 41 in the second region a2 is 0.8 mm.

In the embodiment of the present invention, the semiconductor substrate 4 may be a silicon substrate, a germanium substrate, a gallium arsenide substrate, or the like. As shown in fig. 11, fig. 11 is a schematic cross-sectional structure view of a semiconductor substrate according to another embodiment of the present invention, the semiconductor substrate 4 further includes a plurality of second pins 43 located on a second side of the substrate body 40, the second pins 43 are electrically connected to the chip, and the second pins 43 are electrically connected to the first pins 41 through first conductive parts 44 penetrating through the substrate body 40.

The first conductive part 44 includes a metal via 440 penetrating through the substrate body 40, and at least one metal layer 441, a via 442 connecting the metal layer and the pin, a via (not shown) connecting adjacent metal layers, and the like, so as to electrically connect the second pin 43 and the first pin 41.

In general, the area of the chip is smaller than the area of the semiconductor substrate 4 but larger than the area of the first region a1, and therefore, the position of the chip power supply pin does not correspond to the position of the power supply pin 410, and the position of the second pin 43 connected to the chip power supply pin may or may not correspond to the position of the chip power supply pin. If the two positions correspond to each other, the chip power supply pin may be electrically connected to the second pin 43 through a solder ball, etc., and if the two positions do not correspond to each other, the chip power supply pin may be electrically connected to the second pin 43 through a gold wire, etc.

In some embodiments of the present invention, the distribution density of the second pins 43 electrically connected to the first pins 41 in the first region a1 may be greater than the distribution density of the second pins 43 electrically connected to the first pins 41 in the second region a 2. The positions of the second pins 43 electrically connected to the first pins 41 in the first region a1 may correspond to the positions of the first region a1, and the positions of the second pins 43 electrically connected to the first pins 41 in the second region a2 may correspond to the positions of the second region a2, for example, the second pins 43 electrically connected to the first pins 41 in the first region a1 may be located in the central region, and the second pins 43 electrically connected to the first pins 41 in the second region a2 may be located in the edge region, so that the metal layer and the via hole design of the first conductive member 44 may be simplified.

Of course, the present invention is not limited thereto, and in other embodiments, the second pins 43 may not be disposed corresponding to the first pins 41, so that the positions of the second pins 43 can match the pin positions of a plurality of chips, so that the semiconductor substrate 4 can be suitable for packaging a plurality of chips.

As an alternative implementation of the disclosure, an embodiment of the present invention provides a semiconductor device, as shown in fig. 12, fig. 12 is a schematic cross-sectional structure diagram of the semiconductor device provided in an embodiment of the present invention, where the semiconductor device includes a chip 5 and a semiconductor substrate 4, and the semiconductor substrate 4 may be the semiconductor substrate provided in any one of the above embodiments.

The semiconductor substrate 4 includes a substrate body and a plurality of first pins and the like located on a first side of the substrate body, and a second side of the substrate body encapsulates the chip 5, and the second side is opposite to the first side. Wherein the chip 5 is a bare chip (Die).

In some embodiments of the present invention, as shown in fig. 12, the chip 5 includes a plurality of pins 50, and the pins 50 include a power pin, a ground pin and a signal pin, wherein the power pin is electrically connected to a power pin of the first pins in the first region a1 of the semiconductor substrate 4, the ground pin is electrically connected to a ground pin of the first pins in the first region a1 of the semiconductor substrate, and the signal pin is electrically connected to a first pin in the second region a2 of the semiconductor substrate.

The pins 50 include a pad and a solder ball, and the pins 50 can be electrically connected to the second pins of the semiconductor substrate 4 by heating the solder ball, so that the pins 50 are electrically connected to the first pins. Of course, the present invention is not limited thereto, and in other embodiments, the leads 50 may also include only a pad, and the pad is electrically connected to the second pins of the semiconductor substrate 4 by gold wires or the like.

After all the leads 50 of the chip 5 are electrically connected to the second pins on the semiconductor substrate 4, the chip 5 may be fabricated into a package, that is, the chip 5 may be sealed by the package layer 51. Since the second pins of the semiconductor substrate 4 are electrically connected to the first pins, the first pins of the semiconductor substrate 4 can be electrically connected to the contact points of the flexible substrate, which are in turn electrically connected to other devices through the wires on the printed circuit board, so that the chip 5 can be interconnected to other devices through the printed circuit board.

As an alternative implementation of the disclosure, an embodiment of the present invention provides an integrated Circuit system, as shown in fig. 13, fig. 13 is a schematic structural diagram of the integrated Circuit system provided in an embodiment of the present invention, where the integrated Circuit system includes a Printed Circuit Board (PCB) 6 and a semiconductor device, the semiconductor device is the semiconductor device provided in any one of the above embodiments, and the semiconductor device is mounted on the Printed Circuit Board 6. The semiconductor device includes a semiconductor substrate 4 and a packaged chip 5, which may also be referred to as a packaged chip. The first pin of the semiconductor device is electrically connected to the printed circuit board 6, so that the chip 5 is electrically connected to other devices mounted on the printed circuit board 6.

The printed circuit board 6 is usually mounted with basic components such as a processor chip, a memory, a storage, a power module, a clock module, a peripheral module, an interface connector, and a resistor capacitor. These basic components are connected to each other via the printed circuit board 6 to form a system motherboard, or a combination of these basic components and the printed circuit board 6 forms a system motherboard. It is understood that the processor chip may be a packaged chip, i.e., a semiconductor device, provided by embodiments of the present invention.

The power supply module may supply a power supply signal to the chip 5 through the printed circuit board 6 and the semiconductor substrate 4, and the clock module and other modules may supply other data signals, clock signals, and the like to the chip 5 through the printed circuit board 6 and the semiconductor substrate 4.

In some embodiments of the present invention, the integrated circuit system includes a decoupling capacitor 7, the decoupling capacitor 7 being mounted on the printed circuit board 6, the decoupling capacitor 7 being electrically connected to a power pin and a ground pin in the first region of the semiconductor substrate 4 in the semiconductor device.

In some embodiments of the invention, as shown in fig. 13, a decoupling capacitor 7 is mounted on the side of the printed circuit board 6 facing away from the semiconductor device, the decoupling capacitor 7 being electrically connected to the semiconductor device via a second conductive component (not shown) in the printed circuit board 6. Of course, the invention is not limited thereto, and in other embodiments the decoupling capacitors 7 may also be mounted on the same side of the semiconductor device.

It will be appreciated that the second conductive part may also comprise metal vias through the printed circuit board 6, as well as at least one metal layer, vias connecting the metal layer and the pins, vias connecting adjacent metal layers, etc. to enable electrical connection of the decoupling capacitor 7 and the first pin of the semiconductor substrate 4.

As shown in fig. 14, fig. 14 is a schematic bottom plan view of the printed circuit board shown in fig. 13, each power pin 410 and a ground pin 411 disposed adjacent to the power pin 410 in the first area a1 are electrically connected to a decoupling capacitor 7, and an orthographic projection of each decoupling capacitor 7 on the semiconductor substrate 4 covers the orthographic projection of the power pin 410 and the ground pin 411 electrically connected to the power pin 410, so that each decoupling capacitor 42 is disposed directly below the power pin 410 and the ground pin 411 to optimize the noise reduction effect of the decoupling capacitor 42.

As shown in fig. 14, the decoupling capacitor 7 includes a first electrode 71 and a second electrode 72, the first electrode 71 and the first electrode 72 are respectively located at both ends of the decoupling capacitor 7, and the first electrode 71 and the second electrode 72 are electrically connected to a power supply pin 410 and a ground pin 411, respectively.

It should be noted that, the arrangement of the decoupling capacitor 7 corresponds to the arrangement of the power pin 410 and the ground pin 411 array, which is not limited in the present invention, and the arrangement obtained by rotating or flipping the decoupling capacitor 7 is within the protection scope of the present invention.

As an alternative implementation of the disclosure, an embodiment of the present invention provides an electronic device, which includes the integrated circuit system provided in any of the above embodiments. The electronic equipment comprises a smart phone, a tablet computer, a digital camera, a server and the like.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor substrate comprises a substrate main body and a plurality of first pins positioned on a first side of the substrate main body; a second side of the substrate body may encapsulate a chip, the second side being disposed opposite the first side;

the first pins in the first area comprise power pins and grounding pins, the power pins and the grounding pins can be respectively and electrically connected with two ends of a decoupling capacitor, and the distribution density of the first pins in the first area is determined by the size and the number of the decoupling capacitor; the distribution density of the first pins in the second area is greater than that of the first pins in the first area.

2. The semiconductor substrate of claim 1, wherein the first region is located at a central region of the substrate body, the second region is located at an edge region of the substrate body, and the second region surrounds the first region.

3. The semiconductor substrate according to claim 1 or 2, wherein the first pins in the first region and the first pins in the second region are uniformly distributed; and/or the presence of a gas in the gas,

4. The semiconductor substrate according to claim 1, wherein a pitch of the first pins in the first region is greater than or equal to a length of the decoupling capacitor, and a pitch of the first pins in the second region is smaller than the length of the decoupling capacitor.

5. The semiconductor substrate according to claim 4, wherein the pitch of the first pins in the first region is greater than or equal to 0.9mm, and the pitch of the first pins in the second region is in a range of 0.7mm to 1 mm.

6. The semiconductor substrate according to claim 1, wherein each of the power supply pins and one of the ground pins disposed adjacent thereto are electrically connected to one of the decoupling capacitors.

7. The semiconductor substrate of claim 1, further comprising a plurality of second pins located on a second side of the substrate body; the second pin may be electrically connected to the chip, and the second pin is electrically connected to the first pin through a first conductive member penetrating the substrate body.

8. The semiconductor substrate according to claim 7, wherein the first pin comprises a pad with a solder ball, and the second pin comprises a pad.

9. A semiconductor device comprising a chip and the semiconductor substrate according to any one of claims 1 to 8, wherein the chip is packaged on the second side of the semiconductor substrate.

10. The semiconductor device according to claim 9, wherein the chip comprises a power pin electrically connected to a power pin among the first pins in the first region of the semiconductor substrate, a ground pin electrically connected to a ground pin among the first pins in the first region of the semiconductor substrate, and a signal pin electrically connected to the first pins in the second region of the semiconductor substrate, wherein the pins of the chip are electrically connected to the first pins through the second pins and the first conductive members of the semiconductor substrate.

11. An integrated circuit system comprising a printed circuit board and the semiconductor device according to claim 9 or 10, the semiconductor device being mounted on the printed circuit board.

12. The integrated circuit system of claim 11, comprising a decoupling capacitor mounted on the printed circuit board, the decoupling capacitor electrically connected to a power pin and a ground pin in a first region of a semiconductor substrate in the semiconductor device.

13. The integrated circuit system of claim 12, wherein the decoupling capacitor is mounted on a side of the printed circuit board facing away from the semiconductor device, the decoupling capacitor being electrically connected to the semiconductor device through a second conductive feature in the printed circuit board.

14. The integrated circuit system of claim 13, wherein each power pin and a ground pin disposed adjacent thereto in the first region are electrically connected to a decoupling capacitor; and the orthographic projection of each decoupling capacitor on the semiconductor substrate covers the orthographic projection of the power supply pin and the grounding pin which are electrically connected with the decoupling capacitor.

15. An electronic device comprising the integrated circuit system of any one of claims 11-14.