CN114464584A - 具有瓶形硅穿孔的半导体元件结构及其制备方法 - Google Patents
具有瓶形硅穿孔的半导体元件结构及其制备方法 Download PDFInfo
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- CN114464584A CN114464584A CN202111010904.9A CN202111010904A CN114464584A CN 114464584 A CN114464584 A CN 114464584A CN 202111010904 A CN202111010904 A CN 202111010904A CN 114464584 A CN114464584 A CN 114464584A
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Abstract
本公开提供一种半导体元件结构及其制备方法。该半导体元件结构包括:一硅层,设置在一第一半导体晶粒上;以及一第一遮罩层,设置在该硅层上。该半导体元件结构亦包括一第二半导体晶粒,设置在该第一遮罩层上;以及一硅穿孔,穿经该硅层与该第一遮罩层。该硅穿孔的一下表面大于该硅穿孔的一上表面,以及该硅穿孔的该上表面大于该硅穿孔的一剖面,该剖面位于该硅穿孔的该下表面与该上表面之间,且该剖面平行于该硅穿孔的该下表面与该上表面。
Description
交叉引用
本公开主张2020年11月10日申请的美国正式申请案第17/093,974号的优先权及益处,该美国正式申请案的内容以全文引用的方式并入本文中。
技术领域
本公开涉及一种半导体元件结构及其制备方法。特别涉及一种具有一瓶形硅穿孔的半导体元件结构及其制备方法。
背景技术
对于许多现代应用,半导体元件是不可或缺的。随着电子科技的进步,半导体元件的尺寸变得越来越小,于此同时提供较佳的功能以及包含较大的集成电路数量。由于半导体元件的规格小型化,实现不同功能的半导体元件的不同形态与尺寸规模,是整合(integrated)并封装(packaged)在一单一模块中。再者,许多制造步骤执行于各式不同形态的半导体装置的整合(integration)。
然而,该等半导体元件的制造与整合包含许多复杂步骤与操作。在该等半导体元件中的整合变得越加复杂。该等半导体元件的制造与整合的复杂度的增加可造成多个缺陷。据此,有持续改善该等半导体元件的制造流程的需要,以便对付该等缺陷并可加强其效能。
上文的“现有技术”说明仅是提供背景技术,并未承认上文的“现有技术”说明公开本公开的标的,不构成本公开的现有技术,且上文的“现有技术”的任何说明均不应作为本公开的任一部分。
发明内容
本公开的一实施例提供一种半导体元件结构。该半导体元件结构包括:一硅层,设置在一第一半导体晶粒上;以及一第一遮罩层,设置在该硅层上。该半导体元件结构亦包括一第二半导体晶粒,设置在该第一遮罩层上;以及一硅穿孔,穿经该硅层与该第一遮罩层。该硅穿孔的一下表面大于该硅穿孔的一上表面,以及该硅穿孔的该上表面大于该硅穿孔的一剖面,该剖面位于该硅穿孔的该下表面与该上表面之间,且该剖面平行于该硅穿孔的该下表面与该上表面。
在一些实施例中,该硅穿孔直接接触在该第一半导体晶粒中的一第一导电垫以及在该第二半导体晶粒中的一第二导电垫。在一些实施例中,该半导体元件结构还包括一第三导电垫,设置在该第一半导体晶粒中,并邻近该第一导电垫设置;以及一第四导电垫,设置在该第二半导体晶粒中,并邻近该第二导电垫设置,其中,在该第一半导体晶粒中的该第三导电垫与该第一导电垫之间的一横向距离,大于在该第二半导体晶粒中的该第四导电垫与该第二导电垫之间的一横向距离。在一些实施例中,该半导体元件结构还包括一第二遮罩层,设置在该第一遮罩层与该第二半导体晶粒之间,其中,该硅穿孔穿经该第二遮罩层,以及其中,该第一遮罩层与该第二遮罩层包含不同材料。
在一些实施例中,该第二遮罩层的一侧壁相对于该第一遮罩层的一侧壁倾斜。在一些实施例中,该半导体元件结构还包括一保护层,覆盖该第二遮罩层的该侧壁、该第一遮罩层的该侧壁以及该硅层的一上侧壁,其中,该硅层的该上侧壁大致对准该第一遮罩层的该侧壁。在一些实施例中,该硅穿孔包括一导电层;一阻障层,覆盖该导电层的各侧壁与一下表面,其中,该阻障层直接接触该第一半导体晶粒;以及一衬垫层,覆盖该阻障层的各侧壁。
本公开的另一实施例提供一种半导体元件结构。该半导体元件结构:包括一硅层,设置在一第一半导体晶粒上;以及一第一遮罩层,设置在该硅层上。该半导体元件结构亦包括一第二遮罩层,设置在该第一遮罩层上;以及一第二半导体晶粒,设置在该第二遮罩层上。该半导体元件结构还包括一硅穿孔,穿经该硅层、该第一遮罩层以及该第二遮罩层,以电性连接该第一半导体晶粒与该第二半导体晶粒。该硅穿孔具有一瓶形部,该瓶形部被该第一遮罩层与该硅层的一上部所围绕,以及该硅穿孔与该第一半导体晶粒之间的一界面面积,大于该硅穿孔与该第二半导体晶粒之间的一界面面积。
在一些实施例中,该第一半导体晶粒具有一第一临界尺寸(criticaldimension),以及该第二半导体晶粒具有一第二临界尺寸,而该第一临界尺寸大于该第二临界尺寸。在一些实施例中,该硅穿孔还包括一上部,被该第二遮罩层所围绕;以及一下部,被该硅层的一下部所围绕;其中,该硅穿孔的该瓶形部夹置在该硅穿孔的该上部与该下部之间,以及该硅穿孔的该上部具有一锥形轮廓,该锥形轮廓朝该硅穿孔的该瓶形部逐渐变细。
在一些实施例中,该硅穿孔的该下部具有多个圆形及凸面上角落。在一些实施例中,该硅穿孔的该瓶形部与该上部通过一保护层而与该第一遮罩层、该第二遮罩层以及该硅层的该上部分隔开。在一些实施例中,该硅穿孔的该下部直接接触该硅层的该下部。在一些实施例中,该保护层包含氧化铝。
本公开的另一实施例提供一种半导体元件的制备方法。该制备方法包括:形成一硅层在一第一半导体晶粒上;以及形成一第一遮罩层在该硅层上。该制备方法亦包括形成一第一开孔以穿经该第一遮罩层,以及形成一第二开孔以穿经该硅层;以及沉积一保护层在该第一遮罩层上。延伸该保护层以覆盖该第一遮罩层的一侧壁以及该硅层的一上侧壁。该制备方法还包括通过使用该保护层当作一遮罩以蚀刻该硅层,进而底切该硅层的一上部,以便形成一放大的第二开孔。此外,该制备方法包括以一硅穿孔充填该第一开孔与该放大的第二开孔;以及形成一第二半导体晶粒在该硅穿孔上。
在一些实施例中,该制备方法还包括形成一第二遮罩层在该第一遮罩层上;以及在穿经该第一遮罩的该第一开孔形成之前,形成一第三开孔以穿经该第二遮罩层。在一些实施例中,在形成穿经该硅层的该第二开孔期间,蚀刻该第二遮罩层以形成一放大的第三开孔,以及该放大的第三开孔具有一锥形轮廓,该锥形轮廓朝向该第一开孔逐渐变细。
在一些实施例中,该保护层的制作技术包含一非共形(non-conformal)沉积工艺。在一些实施例中,该制备方法还包括在该硅穿孔形成之前,移除该保护层。在一些实施例中,该硅层的该上部覆盖该硅穿孔的一下部。
本公开的一些实施例提供一半导体元件结构及其制备方法。在一些实施例中,该半导体元件结构具有一硅穿孔。该硅穿孔的下表面大于该硅穿孔的上表面,以及该硅穿孔的上表面大于该硅穿孔的一剖面,该剖面是位于该硅穿孔的上表面与下表面之间,且该剖面平行于该硅穿孔的上表面与下表面。因此,该硅穿孔可用于电性连接在垂直方向及具有不同设计规则的两个半导体晶粒(或半导体晶圆)。结果,可增加功能密度(functionaldensity)(亦即,单位芯片面积之内连接装置的数量),并提供多个好处,例如提高生产效率、降低成本以及改善效能。
上文已相当广泛地概述本公开的技术特征及优点,从而使下文的本公开详细描述得以获得较佳了解。构成本公开的权利要求标的的其它技术特征及优点将描述于下文。本公开所属技术领域中技术人员应了解,可相当容易地利用下文公开的概念与特定实施例作为修改或设计其它结构或工艺而实现与本公开相同的目的。本公开所属技术领域中技术人员亦应了解,这类等效建构无法脱离权利要求所界定的本公开的构思和范围。
附图说明
参阅实施方式与权利要求合并考量附图时,可得以更全面了解本公开的披露内容,附图中相同的元件符号是指相同的元件。
图1例示本公开一些实施例的一半导体元件结构的剖视示意图。
图2例示本公开一些实施例的图1的放大示意图。
图3例示本公开一些实施例的一改良半导体元件结构的剖视示意图。
图4例示本公开一些实施例的一图3的放大示意图。
图5例示本公开一些实施例的一半导体元件结构的制备方法的流程示意图。
图6例示本公开一些实施例的一中间阶段的剖视示意图,其中,该中间阶段在该半导体元件结构形成期间,形成一硅层在一第一半导体晶粒上。
图7例示本公开一些实施例的一中间阶段的剖视示意图,其中,该中间阶段在该半导体元件结构形成期间,依序形成一第一遮罩层以及一第二遮罩层在该硅层上。
图8例示本公开一些实施例的一中间阶段的剖视示意图,其中,该中间阶段在该半导体元件结构形成期间,形成一开孔在该第二遮罩层中。
图9例示本公开一些实施例的一中间阶段的剖视示意图,其中,该中间阶段在该半导体元件结构形成期间,形成一开孔在该第一遮罩层中。
图10例示本公开一些实施例的一中间阶段的剖视示意图,其中,该中间阶段在该半导体元件结构形成期间,形成一开孔在该硅层中。
图11例示本公开一些实施例的一中间阶段的剖视示意图,其中,该中间阶段在该半导体元件结构形成期间,沉积一保护层。
图12例示本公开一些实施例的一中间阶段的剖视示意图,其中,该中间阶段在该半导体元件结构形成期间,通过使用该保护层当作一遮罩以蚀刻该硅层。
图13例示本公开一些实施例的一中间阶段的剖视示意图,其中,该中间阶段在该半导体元件结构形成期间,移除该保护层。
图14例示本公开一些实施例的一中间阶段的剖视示意图,其中,该中间阶段在该半导体元件结构形成期间,形成一衬垫材料在该第一遮罩层、该第二遮罩层与该硅层的各开孔中。
图15例示本公开一些实施例的一中间阶段的剖视示意图,其中,该中间阶段在该半导体元件结构形成期间,蚀刻该衬垫材料以形成一衬垫层。
图16例示本公开一些实施例的一中间阶段的剖视示意图,其中,该中间阶段在该半导体元件结构形成期间,形成一阻障材料在该衬垫层上。
图17例示本公开一些实施例的一中间阶段的剖视示意图,其中,该中间阶段在该半导体元件结构形成期间,形成一导电材料在该阻障材料上。
图18例示本公开一些实施例的一中间阶段的剖视示意图,其中,该中间阶段在一半导体元件结构形成期间,平坦化该导电材料与该阻障材料以形成一硅穿孔(throughsiliconvia)。
图19例示本公开一些实施例的一中间阶段的剖视示意图,其中,该中间阶段在一改良半导体元件结构形成期间,形成一衬垫材料在该保护层上。
图20例示本公开一些实施例的一中间阶段的剖视示意图,其中,该中间阶段在一改良半导体元件结构形成期间,蚀刻该衬垫材料以形成一衬垫层。
图21例示本公开一些实施例的一中间阶段的剖视示意图,其中,该中间阶段在一改良半导体元件结构形成期间,形成一阻障材料在该衬垫层上。
图22例示本公开一些实施例的一中间阶段的剖视示意图,其中,该中间阶段在一改良半导体元件结构形成期间,形成一导电材料在该阻障材料上。
图23例示本公开一些实施例的一中间阶段的剖视示意图,其中,该中间阶段在一改良半导体元件结构形成期间,平坦化该导电材料与该阻障材料以形成一硅穿孔。
附图标记说明:
10:制备方法
100:半导体元件结构
101:半导体基底
103:介电层
105a:导电垫
105b:导电垫
105c:导电垫
110:第一半导体晶粒
111:硅层
111L:下部
111U:上部
113:第一遮罩层
115:第二遮罩层
117:图案化遮罩
120:开孔
130:开孔
130’:开孔
140:开孔
150:开孔
161:保护层
161’:保护层
163:衬垫材料
163’:衬垫层
165:阻障材料
165’:阻障层
167:导电材料
167’:导电层
169:硅穿孔
169a:上部
169b:瓶颈形状部
169B:下表面
169c:下部
169T:上表面
171:半导体基底
173:介电层
175a:导电垫
175b:导电垫
175c:导电垫
175d:导电垫
175e:导电垫
180:第二半导体晶粒
200:半导体元件结构
263:衬垫材料
263’:衬垫层
265:阻障材料
265’:阻障层
267:导电材料
267’:导电层
269:硅穿孔
269a:上部
269b:瓶颈形状部
269B:下表面
269c:下部
269T:上表面
C:上角落
CS:剖面
D1:横向距离
D2:横向距离
S11:步骤
S13:步骤
S15:步骤
S17:步骤
S19:步骤
S21:步骤
S23:步骤
S25:步骤
S27:步骤
S29:步骤
SW1:侧壁
SW2:侧壁
USW:上侧壁
W1:宽度
W2:宽度
W3:下宽度
W4:上宽度
W5:下宽度
W6:上宽度
θ:角度
具体实施方式
以下描述了组件和配置的具体范例,以简化本公开的实施例。当然,这些实施例仅用以例示,并非意图限制本公开的范围。举例而言,在叙述中第一部件形成于第二部件之上,可能包含形成第一和第二部件直接接触的实施例,也可能包含额外的部件形成于第一和第二部件之间,使得第一和第二部件不会直接接触的实施例。另外,本公开的实施例可能在许多范例中重复参照标号及/或字母。这些重复的目的是为了简化和清楚,除非本文中特别说明,其本身并非代表各种实施例及/或所讨论的配置之间有特定的关系。
此外,为易于说明,本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对关系用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对关系用语旨在除图中所示出的取向外亦囊括元件在使用或操作中的不同取向。所述装置可具有其他取向(旋转90度或处于其他取向)且本文中所用的空间相对关系描述语可同样相应地进行解释。
图1例示本公开一些实施例的一半导体元件结构的剖视示意图。如图1所示,半导体元件结构100包括一第一半导体晶粒110;一硅层111,设置在第一半导体晶粒100上;一第一遮罩(掩膜,mask)层113,设置在硅层111上;一第二遮罩层115,设置在第一遮罩层113上;以及一第二半导体晶粒180,设置在第二遮罩层115上。
在一些实施例中,第一半导体晶粒110具有一半导体基底101;一介电层103,设置在半导体基底101上;以及多个导电垫105a、105b、105c,设置在介电层103上。在一些实施例中,该等导电垫105a、105b、105c面对硅层111配置。类似于第一半导体晶粒110,第二半导体晶粒180具有一半导体基底171;一介电层173;以及多个导电垫175a、175b、175c、175d、175e,设置在介电层173上。在一些实施例中,导电垫175a、175b、175c、175d、175e面对第二遮罩层115配置。
仍请参考图1,依据一些实施例,半导体元件结构100亦包括一硅穿孔169,其穿经硅层111、第一遮罩层113以及第二遮罩层115。在一些实施例中,硅穿孔169将在第一半导体晶粒110中的导电垫105c电性连接到在第二半导体晶粒180中的导电垫175d。在一些实施例中,硅穿孔169设置在一排除区(keep-out zone)中,该排除区用于界定没有主动元件置放在其中的一区域。
尤其是,硅穿孔169包括一导电层167’;一阻障层165’,围绕导电层167’设置;以及一衬垫层163’,围绕阻障层165’设置。在一些实施例中,阻障层165’覆盖导电层167’的下表面与各侧壁,而衬垫层163’覆盖阻障层165’的各侧壁。在一些实施例中,阻障层165’与衬垫层163’直接接触导电垫105c,而导电层167’是通过阻障层165’而与导电垫105c分隔开。
再者,如图1所示,依据一些实施例,硅穿孔169具有一瓶形(bottle-shaped)轮廓。此外,依据一些实施例,第二遮罩层115的各侧壁SW2相对于第一遮罩层113的各侧壁SW1倾斜,以及第一遮罩层113的各侧壁SW1大致对准硅层111的各上侧壁USW。在本公开的内容中,字词“大致地(substantially)”指较佳者为至少90%,更佳者为95%,再更佳者为98%,以及最佳者为99%。
再者,依据一些实施例,第一半导体晶粒110的临界尺寸大于第二半导体晶粒180的临界尺寸。在一些实施例中,第二半导体晶粒180的图案密度大于第一半导体晶粒110的图案密度。在一些实施例中,直接接触硅穿孔169的导电垫105c具有一宽度W1,直接接触硅穿孔169的导电垫175d具有一宽度W2,而宽度W1大于宽度W2。在一些实施例中,在第一半导体晶粒110中的两个相邻导电垫105之间的一横向距离,大于在第二半导体晶粒180中的两个相邻导电垫175之间的一横向距离。举例来说,横向距离D1大于横向距离D2。由于硅穿孔169具有一瓶形轮廓,所以硅穿孔169可用于电性连接具有不同设计规则(例如不同图案密度或是不同临界尺寸)的第一半导体晶粒110与第二半导体晶粒180。举例来说,具有较大宽度W1的导电垫105c接触硅穿孔169的一较宽下部,而具有较小宽度W2的导电垫175d接触硅穿孔169的一上部。
图2例示本公开一些实施例之图1的放大示意图。图2例示硅穿孔169及其周围。在一些实施例中,硅穿孔169包括一上部169a、一下部169c以及一瓶颈形状部169b,瓶颈形状部169b夹置在上部169a与下部169c之间。虚线I-I’是表示上部169a与瓶颈形状部169B的边界,以及虚线II-II’是表示瓶颈形状部169b与下部169c的边界。如上所述,依据一些实施例,硅穿孔169具有一下宽度W3(亦即下部169c的最下面宽度)以及一上宽度W4(亦即上部169a的最上面宽度),下宽度W3大于上宽度W4。请参考图1及图2,硅穿孔169的下部169c接触具有较大宽度W1的导电垫105c,以及硅穿孔169的上部169a接触具有较小宽度W2的导电垫175d。因此,硅穿孔169可用于电性连接具有不同设计规则的第一半导体晶粒110与第二半导体晶粒180。
在一些实施例中,硅穿孔169的上部169a被第二遮罩层115所围绕,且硅穿孔169的上部169a具有一锥形轮廓,朝向硅穿孔169的瓶颈形状部169b逐渐变细。换言之,硅穿孔169的上部169a的各宽度沿从下到上的一方向逐渐增加。在一些实施例中,硅穿孔169的瓶颈形状部169b被第一遮罩层113与硅层111的一上部111U所围绕,以及硅穿孔169的瓶颈形状部169b的各宽度大致相同。
再者,硅穿孔169的下部169c被硅层111的一下部111L所围绕。在一些实施例中,硅穿孔169的下部169c具有多个圆形及凸面的上角落C。在一些实施例中,硅穿孔169的下部169c部分被硅层111所覆盖。此外,硅穿孔169具有一上表面169T(亦即硅穿孔169与在第二半导体晶粒180中的导电垫175d之间的界面)以及一下表面169B(亦即硅穿孔169与在第一半导体晶粒110中的导电垫105c之间的界面)。在一些实施例中,下表面169B大于上表面169T,以及上表面169T大于硅穿孔169的一剖面,该剖面在上表面169T与下表面169B之间,且平行于上表面169T与下表面169B,例如瓶颈形状部169B的剖面CS。亦即,依据一些实施例,硅穿孔169的下宽度W3大于硅穿孔169的上宽度W4。
图3例示本公开一些实施例的一改良半导体元件结构200的剖视示意图,而半导体元件结构200为半导体元件结构100的另外的实施例。出于一致性及清楚的原因,同时在图1及图3所出现的类似元件,标示相同的元件编号。
类似于半导体元件结构100,半导体元件结构200具有一硅穿孔269,设置在一排除区中。硅穿孔269具有一导电层267’;一阻障层265’,围绕导电层267’设置;以及一衬垫层263’,围绕阻障层265’设置。半导体元件结构100与200之间的一差异还包括一保护层161’。如图3所示,依据一些实施例,第二遮罩层115的各侧壁SW2、第一遮罩层113的各侧壁SW1以及硅层111的各上侧壁USW被保护层161’所覆盖。
图4例示本公开一些实施例的一图3的放大示意图。图4例示硅穿孔269、保护层161’及其周围。在一些实施例中,硅穿孔269具有一上部269a、一下部269c以及一瓶颈形状部269b,而瓶颈形状部269b夹置在上部269a与下部269c之间。虚线I-I’表示上部269a与瓶颈形状部269b的边界,而虚线II-II’表示瓶颈形状部269b与下部269c的边界。
在一些实施例中,硅穿孔269的上部269a被第二遮罩层115所围绕,以及硅穿孔269的上部269a具有一锥形轮廓,朝向硅穿孔269的瓶颈形状部269b逐渐变细。换言之,硅穿孔269的上部269a的各宽度沿从下到上的一方向逐渐增加。在一些实施例中,硅穿孔269的瓶颈形状部269b被第一遮罩层113与硅层111的一上部111U所围绕,以及硅穿孔269的瓶颈形状部269b的各宽度大致相同。
再者,硅穿孔269的下部269c被硅层111的一下部111L所围绕。在一些实施例中,硅穿孔269的下部269c具有多个圆形及凸面上角落C。在一些实施例中,硅穿孔269的下部269c部分被硅层111所覆盖。此外,硅穿孔269具有一上表面269T(亦即硅穿孔269与在第二半导体晶粒180中的导电垫175d之间的界面)以及一下表面269B(亦即硅穿孔269与在第一半导体晶粒110中的导电垫105c之间的界面)。在一些实施例中,下表面269B大于上表面269T,以及上表面269T大于硅穿孔269的一剖面,该剖面位于上表面269T与下表面269B之间,请平行于上表面269T与下表面269B,例如瓶颈形状部269b的剖面CS。在一些实施例中,硅穿孔269具有一下宽度W5(亦即下部269c的最下面宽度)以及一上宽度W6(亦即上部269a的最上面宽度),以及下宽度W5大于上宽度W4。请参考图3及图4,硅穿孔269的下部269c接触具有较大宽度W1的导电垫105c,而硅穿孔269的上部269a接触具有较小宽度W2的导电垫175d。因此,硅穿孔269可用于电性连接具有不同设计规格的第一半导体晶粒110与第二半导体晶粒180。
应当理解,依据一些实施例,第一遮罩层113、第二遮罩层115以及硅层111的上部111U是通过保护层161’而与硅穿孔269分隔开。在一些实施例中,硅穿孔269的上部269a与瓶颈形状部269b被保护层161’所围绕。在一些实施例中,硅穿孔269的下部269c直接接触硅层111的下部111L。
图5例示本公开一些实施例的一半导体元件结构(包括半导体元件结构100与改良的半导体元件结构200)的制备方法10的流程示意图,制备方法10包括步骤S11、S13、S15、S17、S19、S21、S23、S25、S27以及S29。图5的该等步骤S11到S29结合下列附图进行详细说明。
图6到图18例示本公开一些实施例在半导体元件结构100形成期间的各中间阶段的剖视示意图。如图6所示,依据一些实施例,提供具有半导体基底101、介电层103以及导电垫105a、105b、105c的第一半导体晶粒110,以及硅层111形成在第一半导体晶粒110上。其个别步骤是示出在如图5所示的制备方法10中的步骤S11。
第一半导体晶粒110可为集成电路(IC)芯片的一部分,其具有各式不同的被动与主动微电子元件,例如电阻器、电容器、电感器、二极管、p型场效晶体管(pFETs)、n型场效晶体管(nFETs)、金属氧化物半导体场效晶体管(MOSFETs)、互补式金属氧化物半导体(complementary metal-oxide-semiconductor,CMOS)晶体管、双极性晶体管(bipolarjunction transistor,BJTs)、横向扩散MOS(laterally diffused MOS,LDMOS)晶体管、高电压晶体管、高频率晶体管、鳍式场效晶体管(FinFETs)、其他适合的IC元件或其组合。
取决于IC的制造阶段,第一半导体晶粒110可包括各式不同的材料层(例如介电层、半导体层及/或导电层),经配置以形成IC特征(例如掺杂区、绝缘区、栅极特征、源极/漏极特征、内连接特征、其他特征或其组合)。为了清楚起见,已简化第一半导体晶粒110。应当理解,可在第一半导体晶粒110中加入额外的特征,以及下列所描述的一些特征可在其他实施例中被取代、改良或排除。在一些实施例中,硅层111外延地生长在第一半导体晶粒110上。
接着,如图7所示,依据一些实施例,第一遮罩层113形成在硅层111上,以及第二遮罩层115形成在第一遮罩层113上。其个别步骤是示出在如图5所示的制备方法10中的步骤S13。在一些实施例中,第一遮罩层113与第二遮罩层115包含介电材料,例如氧化硅、氮化硅、氮氧化硅,且其制作技术包含多个沉积工艺,例如化学气相沉积(CVD)工艺、物理气相沉积(PVD)工艺、旋转涂布工艺。再者,依据一些实施例,一图案化遮罩117形成在第二遮罩层115上。在一些实施例中,图案化遮罩117具有一开孔(opening)120,暴露第二遮罩层115的一部分。
接下来,如图8所示,依据一些实施例,通过使用图案化遮罩117当作一遮罩以蚀刻第二遮罩层115,以便形成穿经第二遮罩层115的一开孔130。其个别步骤示出在如图5所示的制备方法10中的步骤S15。在一些实施例中,第一遮罩层113的一部分通过在第二遮罩层115中的开孔130而暴露。该蚀刻工艺可为一干蚀刻工艺、一湿蚀刻工艺或其组合。在该蚀刻工艺之后,可移除图案化遮罩117。
然后,如图9所示,依据一些实施例,通过使用第二遮罩层115当作一遮罩以蚀刻第一遮罩层113,以便形成穿经第一遮罩层113的一开孔140。其个别步骤示出在如图5所示的制备方法10中的步骤S17。在一些实施例中,硅层111的一部分通过在第一遮罩层113中的开孔140而暴露。该蚀刻工艺可为一干蚀刻工艺、一湿蚀刻工艺或其组合。在一些实施例中,在第一遮罩层113中的开孔140的侧壁大致对准在第二遮罩层115中的开孔130的侧壁。
如图10所示,依据一些实施例,在开孔130与140形成之后,通过使用第一遮罩层113当作一遮罩以蚀刻硅层111,以便形成穿经硅层111的一开孔150。其个别步骤示出在如图5所示的制备方法10中的步骤S19。该蚀刻工艺可为一干蚀刻工艺、一湿蚀刻工艺或其组合。
在一些实施例中,导电垫105c通过开孔150而暴露。在一些实施例中,第二遮罩层115包含一材料,相较于第一遮罩层113的材料,第二遮罩层115的该材料具有一高蚀刻选择性。因此,在用于形成位于硅层111中的开孔150的蚀刻工艺期间,蚀刻第二遮罩层115以形成一放大的开孔130’。
在一些实施例中,放大的开孔130’具有一锥形轮廓,朝向位于第一遮罩层113中的开孔140逐渐变细。在一些实施例中,第二遮罩层115相对于第一遮罩层113的各侧壁具有多个倾斜侧壁,以及一角度θ位于第二遮罩层115的该等倾斜侧壁与下表面之间。在一些实施例中,角度θ介于大约46度到大约60度的范围内。第二遮罩层115的该等侧壁细可提供改善的阶梯覆盖(step coverage)给接下来形成的保护层161。
接着,如图11所示,依据一些实施例,保护层161沉积在第二遮罩层115上,并覆盖第二遮罩层115的各侧壁、第一遮罩层113的各侧壁以及硅层111的各上侧壁(亦即硅层111的上部111U的各侧壁)。其个别步骤示出在如图5所示的制备方法10中的步骤S21。应当理解,硅层111的各下侧壁(亦即硅层111的下部111L的各侧壁)并未被保护层161所覆盖。
图11的虚线用于图例说明硅层111的上部111U与下部111L的边界。在一些实施例中,保护层161的制作技术包含一非共形的沉积工艺,例如一非共形的线状原子层沉积法(non-conformal liner atomic layer deposition,NOLA)工艺。在一些实施例中,保护层161包括一氧化物材料,例如氧化铝。
然后,如图12所示,依据一些实施例,通过使用保护层161当作一遮罩以蚀刻硅层111。其个别步骤示出在如图5所示的制备方法10中的步骤S23。在一些实施例中,硅层111的下部111L为横向蚀刻,同时因为被保护层161所遮蔽,所以硅层111的上部111U保持完整。
在一些实施例中,通过用于形成放大的开孔150’的蚀刻工艺以底切硅层111的上部111U。在一些实施例中,放大的开孔150’的制作技术可包含一等向性蚀刻工艺。该等向性蚀刻工艺可为一湿蚀刻工艺、一干蚀刻工艺或其组合。在一些实施例中,包含硝酸(nitricacid,HNO3)与氢氟酸(hydrofluoric acid,HF)的一蚀刻溶液用于形成放大的开孔150’。在一些实施例中,该蚀刻溶液还包含磷酸(phosphoric acid,H3PO4)。在其他实施例中,氟基等离子体(fluorine-basedplasma)用于形成放大的开孔150’。
如图13所示,依据一些实施例,在放大的开孔150’形成之后,移除保护层161。其个别步骤示出在如图5所示的制备方法10中的步骤S25。可通过一湿蚀刻工艺、一干蚀刻工艺或其组合而移除保护层161。在一些实施例中,包含磷酸(H3PO4)的一蚀刻溶液可用于移除保护层161。
接着,如图14所示,依据一些实施例,一衬垫材料163形成在第二遮罩层115上,并覆盖开孔130’的各侧壁、开孔140的各侧壁以及开孔150’的各侧壁与下表面。换言之,第二遮罩层115的各倾斜侧壁、第一遮罩层113的各侧壁、硅层111的各侧壁以及导电垫105c的暴露表面,被衬垫材料163所覆盖。
衬垫材料163共形地沉积在图13的结构上,以及衬垫材料163用于将接下来所形成的多个导电层与硅层111分隔开。在一些实施例中,衬垫材料163包含氧化硅、四乙氧基硅烷(tetraethylorthosilicate,TEOS)氧化物、氮化硅、聚酰亚胺(polyimide)、其他可应用的介电材料或其组合。再者,衬垫材料163的制作技术可包含一热氧化工艺、一CVD工艺、一PVD工艺或其他可应用的沉积工艺。
然后,如图15所示,依据一些实施例,在衬垫材料163上执行一非等向性蚀刻工艺,以在所有位置垂直地移除相同数量的衬垫材料163,在开孔130’、140、150的各侧壁上留下衬垫层163’。执行在衬垫材料163上的非等向性蚀刻工艺可为一干蚀刻工艺。依据一些实施例,在非等向性蚀刻工艺执行之后,通过开孔150’、140、130’暴露导电垫105c。
接下来,如图16所示,依据一些实施例,一阻障材料165形成在第二遮罩层115与衬垫层163’上。在一些实施例中,导电垫105c的暴露表面并未被阻障材料165所覆盖。阻障材料165当作是一扩散阻障以避免金属扩散,且阻障材料165当作在衬垫层163’与接下来所形成的导电材料之间的一粘着层。在一些实施例中,阻障材料165包含TaN、Ta、Ti、TiN、TiSiN、WN、CoW或其组合。阻障材料165的制作技术可包含一CVD工艺、一PVD工艺、一喷溅工艺或其他可应用的工艺。
然后,如图17所示,依据一些实施例,一导电材料167形成在阻障材料165上。在一些实施例中,开孔130’、140、150’的该等余留部分被导电材料167所填满。在导电材料167形成之前,一晶种层(图未示)可形成在阻障材料165上。
晶种层可为一铜晶种层,且其制作技术可包含一CVD工艺、一PVD工艺、一喷溅工艺、一镀覆工艺,或其他可应用的工艺。在一些实施例中,导电材料167包含一低电阻率(resistivity)导电材料,例如铜(Cu)。在一些其他实施例中,导电材料167包含钨(W)、铝(Al)、钛(Ti)、钽(Ta)、金(Au)、银(Ag)、其组合,或其他可应用的导电材料。导电材料167的制作技术可包含一CVD工艺、一PVD工艺、一喷溅工艺、一镀覆工艺,或其他可应用的工艺。
请参考图18,依据一些实施例,在导电材料167形成之后,在导电材料167与阻障材料165上执行一平坦化工艺,以形成硅穿孔169,且硅穿孔169包括衬垫层163’、阻障层165’以及导电层167’。该瓶碳化工艺可包括一化学机械研磨(CMP)工艺,其移除导电材料167与阻障材料165在第二遮罩层115上的该等多余部分。其个别步骤示出在如图5所示的制备方法10中的步骤S27。
接着,如图1所示,依据一些实施例,第二半导体晶粒180形成在第二遮罩层115上。其个别步骤示出在如图5所示的制备方法10中的步骤S29。在一些实施例中,第二半导体晶粒180接合到图17的结构,以使导电垫175a、175b、175c、175d、175e面对硅穿孔169。在第二半导体晶粒180形成之后,获得半导体元件结构100。
类似于第一半导体晶粒110,第二半导体晶粒180可为IC芯片的一部分,其包括各式不同的被动与主动微电子元件,而且第二半导体晶粒180可包括各式不同的材料层,经配置以形成多个IC特征。在一些实施例中,硅穿孔169电性连接第一半导体晶粒110的导电垫105c与第二半导体晶粒180的导电垫175d。由于第二半导体晶粒180在硅穿孔169之后所形成,所以在用于形成硅穿孔169工艺期间,可降低损伤在第二半导体晶粒180中的导电垫175a、175b、175c、175d、175e的风险。
图19到图23例示本公开一些实施例在半导体元件结构200形成期间的各中间阶段的剖视示意图。如图19所示,依据一些实施例,在通过使用保护层161当作一遮罩以蚀刻硅层111之后(亦即图12的接下来的步骤),一衬垫材料263形成在保护层161上。使用于形成衬垫材料263的一些材料与工艺,类似于或相同于使用于形成图14的衬垫材料163的材料与工艺,且其详细说明不再在文中重复。
接着,如图20所示,依据一些实施例,在衬垫材料263上执行一非等向性蚀刻工艺,以在所有位置垂直地移除相同数量的衬垫材料263,在开孔130’、140、150’的各侧壁上留下衬垫层263’。在衬垫材料263上所执行的非等向性蚀刻工艺可为一干蚀刻工艺。依据一些实施例,在非等向性蚀刻工艺执行之后,通过开孔150’、140、130’暴露导电垫105c。
接下来,如图21所示,依据一些实施例,一阻障材料265形成在保护层161与衬垫层263’上。使用于形成阻障材料265的一些材料与工艺,类似于或相同于使用于形成图16的阻障材料165的材料与工艺,其详细说明不再在文中重复。
然后,如图22所示,依据一些实施例,一导电材料267形成在阻障材料265上。在一些实施例中,开孔130’、140、150’的该等余留部分被导电材料267所填满。在导电材料267形成之前,一晶种层(图未示)可形成在阻障材料265上。使用于形成导电材料267的一些材料与工艺,类似于或相同于使用于形成图17的导电材料167的材料与工艺,且其详细说明不再在文中重复。
如图23所示,依据一些实施例,在导电材料267形成之后,在导电材料267、阻障材料265与保护层161上执行一平坦化工艺,一形成硅穿孔269以及保护层161’的一余留部分。硅穿孔269包括衬垫层263’、阻障层265’以及导电层267’。该平坦化工艺可包括一CMP工艺,其移除导电材料267、阻障材料265与保护层161在第二遮罩层115上的该等多余部分。
接着,如图3所示,依据一些实施例,第二半导体晶粒180形成在第二遮罩层115上。在一些实施例中,第二半导体晶粒180接合到图23的结构,以使导电垫175a、175b、175c、175d、175e面对硅穿孔269。在一些实施例中,保护层161’直接接触第二半导体晶粒180。在第二半导体晶粒180形成之后,获得半导体元件结构200。
在一些实施例中,硅穿孔269电性连接第一半导体晶粒110的导电垫105c与第二半导体晶粒180的导电垫175d。由于第二半导体晶粒180在硅穿孔169之后所形成,所以在用于形成硅穿孔169的工艺期间,可降低损伤在第二半导体晶粒180中的导电垫175a、175b、175c、175d、175e的风险。
本公开是提供半导体元件结构100与200的一些实施例。在一些实施例中,形成穿经硅层111、第一遮罩层113以及第二遮罩层115的硅穿孔169与269,以电性连接在垂直方向的第一半导体晶粒110与第二半导体晶粒180。硅穿孔169与269具有瓶形轮廓。举例来说,硅穿孔169的下表面169B大于硅穿孔169的上表面169T,以及硅穿孔169的上表面169T大于硅穿孔169的一剖面(例如剖面CS),该剖面在硅穿孔169的上表面169T与下表面169B之间,且平行于硅穿孔169的上表面169T与下表面169B。因此,硅穿孔169与269可用于电性连接具有不同设计规则(例如不同图案密度或不同临界尺寸)的第一半导体晶粒110与第二半导体晶粒180。结果,可增加功能密度(functional density)(亦即,单位芯片面积之内连接装置的数量),并提供多个好处,例如提高生产效率、降低成本以及改善效能。
本公开的一实施例提供一种半导体元件结构。该半导体元件结构包括一硅层,设置在一第一半导体晶粒上;以及一第一遮罩层,设置在该硅层上。该半导体元件结构亦包括一第二半导体晶粒,设置在该第一遮罩层上;以及一硅穿孔,穿经该硅层与该第一遮罩层。该硅穿孔的一下表面大于该硅穿孔的一上表面,以及该硅穿孔的该上表面大于该硅穿孔的一剖面,该剖面是位于该硅穿孔的该下表面与该上表面之间,且该剖面平行于该硅穿孔的该下表面与该上表面。
本公开的另一实施例提供一种半导体元件结构。该半导体元件结构包括一硅层,设置在一第一半导体晶粒上;以及一第一遮罩层,设置在该硅层上。该半导体元件结构亦包括一第二遮罩层,设置在该第一遮罩层上;以及一第二半导体晶粒,设置在该第二遮罩层上。该半导体元件结构还包括一硅穿孔,穿经该硅层、该第一遮罩层以及该第二遮罩层,以电性连接该第一半导体晶粒与该第二半导体晶粒。该硅穿孔具有一瓶形部,该瓶形部被该第一遮罩层与该硅层的一上部所围绕,以及该硅穿孔与该第一半导体晶粒之间的一界面面积,大于该硅穿孔与该第二半导体晶粒之间的一界面面积。
本公开的另一实施例提供一种半导体元件的制备方法。该制备方法包括形成一硅层在一第一半导体晶粒上;以及形成一第一遮罩层在该硅层上。该制备方法亦包括形成一第一开孔以穿经该第一遮罩层,以及形成一第二开孔以穿经该硅层;以及沉积一保护层在该第一遮罩层上。延伸该保护层以覆盖该第一遮罩层的一侧壁以及该硅层的一上侧壁。该制备方法还包括通过使用该保护层当作一遮罩以蚀刻该硅层,进而底切该层的一上部,以便形成一放大的第二开孔。此外,该制备方法包括以一硅穿孔充填该第一开孔与该放大的第二开孔;以及形成一第二半导体晶粒在该硅穿孔上。
本公开的该等实施例硅具有一些有利的特征。通过形成具有一瓶形轮廓的一硅穿孔,该硅穿孔可用于电性连接在垂直方向及具有不同设计规则的二半导体晶粒(或半导体晶圆)。如此,可提升生产效率,可降低成本,并可改善效能。
虽然已详述本公开及其优点,然而应理解可进行各种变化、取代与替代而不脱离权利要求所定义的本公开的构思与范围。例如,可用不同的方法实施上述的许多工艺,并且以其他工艺或其组合替代上述的许多工艺。
再者,本公开的范围并不受限于说明书中所述的工艺、机械、制造、物质组成物、手段、方法与步骤的特定实施例。该技艺的技术人士可自本公开的披露内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质上相同结果的现存或是未来发展的工艺、机械、制造、物质组成物、手段、方法、或步骤。据此,这些工艺、机械、制造、物质组成物、手段、方法、或步骤是包含于本公开的权利要求内。
Claims (20)
1.一种半导体元件结构,包括:
一硅层,设置在一第一半导体晶粒上;
一第一遮罩层,设置在该硅层上;
一第二半导体晶粒,设置在该第一遮罩层上;以及
一硅穿孔,穿经该硅层与该第一遮罩层,其中,该硅穿孔的一下表面大于该硅穿孔的一上表面,以及该硅穿孔的该上表面大于该硅穿孔的一剖面,该剖面位于该硅穿孔的该下表面与该上表面之间,且该剖面平行于该硅穿孔的该下表面与该上表面。
2.如权利要求1所述的半导体元件结构,其中该硅穿孔直接接触在该第一半导体晶粒中的一第一导电垫以及在该第二半导体晶粒中的一第二导电垫。
3.如权利要求2所述的半导体元件结构,还包括:
一第三导电垫,设置在该第一半导体晶粒中,并邻近该第一导电垫设置;以及
一第四导电垫,设置在该第二半导体晶粒中,并邻近该第二导电垫设置,其中,在该第一半导体晶粒中的该第三导电垫与该第一导电垫之间的一横向距离,大于在该第二半导体晶粒中的该第四导电垫与该第二导电垫之间的一横向距离。
4.如权利要求1所述的半导体元件结构,还包括一第二遮罩层,设置在该第一遮罩层与该第二半导体晶粒之间,其中,该硅穿孔穿经该第二遮罩层,以及其中,该第一遮罩层与该第二遮罩层包含不同材料。
5.如权利要求4所述的半导体元件结构,其中该第二遮罩层的一侧壁相对于该第一遮罩层的一侧壁倾斜。
6.如权利要求5所述的半导体元件结构,还包括一保护层,覆盖该第二遮罩层的该侧壁、该第一遮罩层的该侧壁以及该硅层的一上侧壁,其中,该硅层的该上侧壁大致对准该第一遮罩层的该侧壁。
7.如权利要求1所述的半导体元件结构,其中该硅穿孔包括:
一导电层;
一阻障层,覆盖该导电层的各侧壁与一下表面,其中,该阻障层直接接触该第一半导体晶粒;以及
一衬垫层,覆盖该阻障层的各侧壁。
8.一种半导体元件结构,包括:
一硅层,设置在一第一半导体晶粒上;
一第一遮罩层,设置在该硅层上;
一第二遮罩层,设置在该第一遮罩层上;
一第二半导体晶粒,设置在该第二遮罩层上;以及
一硅穿孔,穿经该硅层、该第一遮罩层以及该第二遮罩层,以电性连接该第一半导体晶粒与该第二半导体晶粒,其中,该硅穿孔具有一瓶形部,该瓶形部被该第一遮罩层与该硅层的一上部所围绕,以及该硅穿孔与该第一半导体晶粒之间的一界面面积,大于该硅穿孔与该第二半导体晶粒之间的一界面面积。
9.如权利要求8所述的半导体元件结构,其中该第一半导体晶粒具有一第一临界尺寸,以及该第二半导体晶粒具有一第二临界尺寸,而该第一临界尺寸大于该第二临界尺寸。
10.如权利要求8所述的半导体元件结构,其中该硅穿孔还包括:
一上部,被该第二遮罩层所围绕;以及
一下部,被该硅层的一下部所围绕;
其中,该硅穿孔的该瓶形部夹置在该硅穿孔的该上部与该下部之间,以及该硅穿孔的该上部具有一锥形轮廓,该锥形轮廓朝该硅穿孔的该瓶形部逐渐变细。
11.如权利要求10所述的半导体元件结构,其中该硅穿孔的该下部具有多个圆形及凸面上角落。
12.如权利要求10所述的半导体元件结构,其中该硅穿孔的该瓶形部与该上部是通过一保护层而与该第一遮罩层、该第二遮罩层以及该硅层的该上部分隔开。
13.如权利要求12所述的半导体元件结构,其中该硅穿孔的该下部直接接触该硅层的该下部。
14.如权利要求12所述的半导体元件结构,其中该保护层包含氧化铝。
15.一种半导体元件的制备方法,包括:
形成一硅层在一第一半导体晶粒上;
形成一第一遮罩层在该硅层上;
形成一第一开孔以穿经该第一遮罩层,以及形成一第二开孔以穿经该硅层;
沉积一保护层在该第一遮罩层上,其中,延伸该保护层以覆盖该第一遮罩层的一侧壁以及该硅层的一上侧壁;
通过使用该保护层当作一遮罩以蚀刻该硅层,进而底切该硅层的一上部,以便形成一放大的第二开孔;
以一硅穿孔充填该第一开孔与该放大的第二开孔;以及
形成一第二半导体晶粒在该硅穿孔上。
16.如权利要求15所述的半导体元件的制备方法,还包括:
形成一第二遮罩层在该第一遮罩层上;以及
在穿经该第一遮罩的该第一开孔形成之前,形成一第三开孔以穿经该第二遮罩层。
17.如权利要求16所述的半导体元件的制备方法,其中在形成穿经该硅层的该第二开孔期间,蚀刻该第二遮罩层以形成一放大的第三开孔,以及该放大的第三开孔具有一锥形轮廓,该锥形轮廓朝向该第一开孔逐渐变细。
18.如权利要求15所述的半导体元件的制备方法,其中该保护层的制作技术包含一非共形沉积工艺。
19.如权利要求15所述的半导体元件的制备方法,还包括在该硅穿孔形成之前,移除该保护层。
20.如权利要求15所述的半导体元件的制备方法,其中该硅层的该上部覆盖该硅穿孔的一下部。
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