CN114464536A - TRENCH MOSFET optimization process integrated with ESD diode - Google Patents
TRENCH MOSFET optimization process integrated with ESD diode Download PDFInfo
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
The invention relates to a TRENCH MOSFET optimization process of an integrated ESD diode, which is mainly applied to TRENCH MOSFET products of conventional N tubes and P tubes, improves the antistatic capability of the products and reduces the level of ISGS electric leakage, improves the phenomenon of large ISGS electric leakage caused by unreasonable process flow of the TRENCH MOSFET products of the prior integrated ESD diodes, proposes that after ESD intrinsic polycrystalline silicon grows, P-type impurity injection is not carried out firstly, but the ESD intrinsic polycrystalline silicon is firstly subjected to heat treatment with high temperature in a BODY region, the intrinsic polycrystalline silicon particles after the high temperature treatment are tighter, then the P-type impurity injection, ESD photoetching and etching are carried out, the subsequent steps are processed together, ESD region N + and the P region are formed by utilizing the last step of reflow heat treatment, the N + impurity push-junction resistance is small, the N + can be ensured to diffuse the whole polycrystalline silicon completely, the N + region on an ESD structure can reasonably diffuse the whole polycrystalline silicon layer completely, an NPNPNPN tube structure with only a transverse structure is formed.
Description
Technical Field
The invention relates to the technical field of TRENCH MOSFET product manufacturing, in particular to a TRENCH MOSFET optimization process integrating an ESD diode.
Background
A TRENCH-type (tree) Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) has a low switching loss and a high switching speed due to its high integration level, low on-resistance, low gate-drain charge density, and large current capacity, and is widely used in the Field of low-voltage power. Two conventional process flows of a tree MOSFET product integrated with an ESD diode at present are as follows, the conventional process includes six layers of photomasks (including a passivation layer), and the following two conventional process flows are both explained mainly by using an N-transistor MOSFET:
the first conventional process flow is as follows: hard mask layer-opening groove-sacrificial oxidation-gate polycrystalline deposition-back etching-depositing TEOS oxide layer with a certain thickness-depositing ESD intrinsic polycrystalline silicon-ESD polycrystalline silicon common injection-ESD polycrystalline silicon thin oxygen oxidation-ESD polycrystalline silicon photoetching, back etching-BODY injection-BODY high temperature annealing-source region and ESD polycrystalline silicon photoetching-source region injection-NDR annealing (PMOS does not need the step) -BPSG deposition, reflux heat treatment-lead hole photoetching, etching-lead hole silicon etching-CT injection-RTA annealing-TI/TIN deposition and RTP annealing-W deposition/AL, Cu deposition-metal etching-passivation-thinning back gold;
and a second conventional process flow: hard mask layer-opening groove-sacrificial oxidation-gate polycrystalline deposition-back etching-BODY injection-depositing silicon nitride and TEOS oxide film with a certain thickness-depositing ESD intrinsic polycrystalline silicon-ESD polycrystalline silicon general injection-ESD polycrystalline silicon thin oxygen oxidation-ESD polycrystalline silicon photoetching, back etching-BODY high-temperature annealing-source region and ESD polycrystalline silicon photoetching-source region injection-NDR annealing (PMOS does not need the step) -BPSG deposition, reflux heat treatment-lead hole photoetching, etching-lead hole silicon etching-CT injection-RTA annealing-TI/TIN deposition and RTP annealing-W deposition/AL, Cu deposition-metal etching-passivation-thinning back metal.
The first process flow is the same as the second process flow, and mainly differs from the second process flow in that the ESD polysilicon deposition is performed before or after BODY injection, from the viewpoint of structural safety, the second process flow is relatively reasonable, the difference of IGSS forward and reverse electric leakage is small, and the first process flow possibly causes the large difference of forward and reverse IGSS due to the fact that the ESD polysilicon does not have the BODY region below, but has common defects no matter the first process flow or the second process flow: the IGSS leakage is too large in absolute value, which results in increased switching loss of the device, and is easy to generate heat, thereby reducing the reliability of the device. IGSS electric leakage of the ESD diode is larger, the best horizontal electric leakage control in the industry at present is between 2uA and 8uA, even some electric leakage reaches about 10uA, the electric leakage above microampere level seriously influences the popularization and application of TRENCH MOSFET products with the ESD diode, and the reason of large ISGS electric leakage is mainly caused by inherent defects of structures formed by the two processes, specifically, referring to FIG. 1, a TRENCH N-MOSFET with a standard integrated structure is described by taking a conventional process flow two as the standard integrated structure, due to the process characteristics of the TRENCH MOSFET, silicon etching needs to be continuously carried out to form a groove after all oxide layers are opened by a lead hole, the depth of the groove needs to be deeper than that of a source region N +, the junction depth of most of the source region N + is 0.3um, the processing depth of the hole groove needs to be between 0.35 and 0.40um, and the bottom of the hole groove needs to be subjected to concentrated P + implantation processing, ensuring that the source region N + and the PBODY region can be well shorted longitudinally, because the polysilicon N + region corresponding to the ESD is processed together with the cell source region N +, the method ensures that the polysilicon of the ESD is not etched thoroughly when silicon is etched in the hole groove, and ensures that the polysilicon thickness of the ESD must be between 6000-8000A, so that the process flow can find that no matter the flow I or the flow II, P-type impurity injection is firstly carried out after the ESD intrinsic polysilicon is grown, and then high-temperature push-knot treatment is carried out together with the PBODY, so that the subsequent ESD region N + is reversely pushed and knotted on the polysilicon which is completely and heavily P-shaped, the N + push-knot resistance is large, the knot depth cannot penetrate through the longitudinal P-type layer, and the finally formed ESD polycrystalline structure is an NPNPN series-parallel connection abnormal structure formed by the suspended shallow N + and the transverse longitudinal P-type region, which is caused by unreasonable matching of process conditions, the IGSS leakage is large, and the IGSS leakage cannot be reduced to be below the microampere level; in the prior art, for ion implantation, as in patent document 1, it is considered that it is sometimes necessary to perform precise fixed-point implantation at a specific point of a substrate instead of the conventional whole-wafer ion implantation, and therefore, a cover plate structure capable of moving laterally and longitudinally is provided, and by providing the cover plate structure, the precise fixed-point implantation can be performed by ion implantation, but the ion implantation apparatus is not suitable for source region implantation in the present application, and the implantation efficiency is low, and cannot perform implantation on a plurality of substrates; as another example, patent document 2 discloses an ion implantation mechanism for a chip, which includes a support capable of driving an ion implanter to move and a support structure capable of moving the chip, so as to solve the problem that the current chip ion implantation equipment has a small working area and can only perform single-point implantation on a substrate to be implanted, and thus the production efficiency is low.
[ patent document 1] CN 109256314B;
[ patent document 2] CN 107346723B.
In summary, on the basis of fully analyzing the root cause of the problems in the current process flow, aiming at the problem that the current TRENCH MOSFET product integrating the ESD diode has larger ISGS electric leakage caused by unreasonable process flow, the invention carries out innovation and improvement on the basis of comprehensively analyzing the current conventional process flow, and aims to ensure that an N + region on the ESD structure can reasonably diffuse the whole polycrystalline silicon layer to form an NPNPNPN tube structure only with a transverse structure, and proposes that after ESD intrinsic polycrystalline silicon grows, P-type impurity injection is not carried out firstly, but the intrinsic polycrystalline silicon particles are firstly heat-treated with the BODY region at high temperature, are tighter, then P-type impurity injection, ESD photoetching and etching are carried out, and the subsequent steps are processed together, and the ESD region N + and the P region are formed by utilizing the last reflux heat treatment, because the junction resistance of the N + impurity is small, the N + can ensure that the whole polycrystalline silicon is diffused, the finally formed structure is shown in fig. 2, and only the NPNPN tube structure with the transverse structure is adopted, so that the antistatic capability of the product is improved, and the ISGS leakage level is reduced. Furthermore, aiming at the source region implantation process in the optimized process, the invention also provides a specially-applicable ion implantation device which can well perform N+When the region impurity is injected, the injection precision and the injection efficiency are improved, and the region impurity can be gradually injected into a plurality of chips.
Disclosure of Invention
In order to overcome the defects of the existing TRENCH MOSFET process, the invention provides a technical scheme, and the TRENCH MOSFET optimization process integrating an ESD diode comprises the following steps:
1) forming a hard mask layer: providing a substrate, and forming a hard mask layer on the substrate;
2) opening the groove: forming a groove by etching or laser beam processing;
3) sacrificial oxidation: forming a sacrificial oxide layer by thermal oxidation;
4) gate oxidation-gate polycrystalline deposition-back etching-BODY injection;
5) depositing a TEOS layer with a certain thickness, depositing ESD intrinsic polysilicon, oxidizing polysilicon thin oxygen and carrying out BODY high-temperature annealing;
6) ESD polysilicon common injection: performing P-type impurity implantation by using an ion implanter;
7) ESD polysilicon photoetching, reverse etching-source region and ESD polysilicon photoetching;
8) source region injection: performing N in a source region+Injecting impurities;
9) NDR annealing;
10) BPSG deposition, reflow heat treatment, lead hole photoetching, etching, lead hole silicon etching, CT injection, RTA annealing, TI and/or TIN deposition and RTP annealing, W deposition and/or Al and Cu deposition;
11) metal etching-passivation-thinning back gold.
Preferably, N is used in the whole BODY high-temperature annealing process in the step 5)2And (6) annealing.
Preferably, the PMOS does not require the step 9) NDR anneal.
Preferably, the step 8) is completed by adopting ion implantation equipment, the ion implantation equipment comprises an implantation chamber, an ion implanter, a cover plate, a driving cylinder, a supporting cylinder and a chip support, the chip support comprises a main body supporting section, a first screw thread section and a second screw thread section, the first screw thread section and the second screw thread section are arranged at two ends of the main body supporting section, the main body supporting section is of a cylindrical structure, a plurality of supporting frames are uniformly distributed on the main body supporting section along the axial direction of the main body supporting section in the circumferential direction, a chip supporting plate is arranged on each supporting frame, a chip is detachably and fixedly arranged on each chip supporting plate, the driving cylinder comprises a first supporting frame and a first cylinder wall, a first driving thread is arranged on the first cylinder wall, the first driving thread is meshed with the first screw thread section, a driving cylinder is fixedly arranged on the first supporting frame, the right end of the driving cylinder is abutted against the left end of the chip support, the ion implanter is fixedly arranged at the upper end of the implantation chamber, and the cover plate is fixedly arranged at the lower end of the ion implanter, the cover plate is provided with an ion injection hole and a sliding cover plate capable of opening or closing the ion injection hole, the sliding cover plate slides under the drive of the cover plate driving mechanism, the ion injection machine completes the ion injection of the chip through the ion injection hole, a vacuumizing device is further arranged in the injection cavity, and the vacuumizing device can vacuumize and vacuumize the injection cavity.
Preferably, the thread pitch of the first thread section and the first driving thread are set to be that after the driving cylinder extends out to drive the chip to rotate for a circle along the axis of the chip support, the distance that the chip moves along the axis of the chip support is two N times that the chip needs to be injected in the step 8)+The spacing of the regions L.
Preferably, before the step 8), a plurality of chips are loaded on the chip supporting plate, the area needing ion implantation is aligned with the ion injection port, then the sliding cover plate is made to close the ion injection port, the vacuumizing device is made to act to make the implantation chamber be in a vacuum state, the ion implanter is started to enter the step 8), after the ions sprayed out by the ion implanter are stabilized, the ion injection port is opened, the first chip is implanted with ions, after the implantation is completed, the ion injection port is closed, the driving cylinder is made to extend out, the chip support is pushed to slide rightwards, the screw thread is driven to rotate the support frame, when the second chip is rotated to be aligned with the ion injection port, the driving of the driving cylinder is stopped, the ion injection port is opened, the ion implanter performs ion implantation on the second chip, the operation is continued, and after the first chip rotates to the ion injection port, can also perform adjacent N+And repeating the ion implantation of the region, finally completing the source region implantation of all the chips, closing the ion implanter, and taking out all the chips to perform the operation of the next step.
Preferably, the supporting cylinder comprises a second cylinder wall and a second supporting frame, a recovery cylinder is fixedly arranged on the second supporting frame, a second threaded section is arranged on the second cylinder wall and is meshed with the second driving threaded section, and the chip support can slide leftwards after the recovery cylinder extends out, so that the initial position of the chip support can be recovered.
Preferably, the number of the support frames is 4, 6, 8 or 12.
Preferably, the ion injection port is of a strip-shaped hole structure;
preferably, the ion injection mouth is circular hole structure, at this moment, the rotatable setting on the support frame of chip backup pad, can rotate along the axis of support frame, thereby can adjust the rotation angle of chip, when the ion injection mouth is circular hole structure, when carrying out ion implantation to first chip, make the driving cylinder slowly extend simultaneously, thereby the rotation through the support frame, make the ion implantation machine can carry out the linear injection of ion on the chip through the ion injection mouth, when carrying out the ion implantation this moment, at first the angle of adjustment chip, make the lines that the ion implantation formed on the chip satisfy the processing requirement of chip.
Preferably, the ESD polysilicon implantation in step 6) is also performed by the ion implantation apparatus, which can be implemented by adjusting the opening size of the ion injection port, and one ion implantation apparatus is shared with step 8), so that the ion injection port is switched between fully open and fully closed to perform the ion implantation operation on the chip when step 6) is performed, and the ion injection port is switched between fully closed and opened by a certain gap to perform the ion implantation operation on the chip when step 8) is performed.
The invention has the beneficial effects that:
1) after the improved optimized process flow is adopted, the finally formed ESD structure is formed by a series diode consisting of standard transverse NPNPN tubes, the forward and reverse directions of IGSS electric leakage are within microamperes, specific data are about 500nA, the electric leakage is reduced by about 75%, the switching loss of a device is reduced, and the reliability of the device is effectively improved;
2) furthermore, the optimized process places the impurities of the ESD polysilicon which are commonly injected for the first time and the impurities which are the same as the source region for the second time in BODY is injected after high-temperature annealing, and through process improvement, both impurities can completely penetrate ESD polysilicon, and the principle is that the two impurities are synchronously thermally annealed on intrinsic polysilicon although polysilicon N+The region is already preceded by P-type impurity implantation, but N is not activated in advance+The impurity in the region is very concentrated to easily neutralize the inactive P-type impurity and then easily diffuse the entire polycrystalline layer, although N is different from the polycrystalline silicon due to the difference in structure+The final junction depth of the impurities in the cellular region is only about 0.3um, but the junction depth on the polycrystalline silicon can reach about 0.8um, even if the polycrystalline silicon has the thickness of 8000A, N+The polycrystalline silicon can be completely expanded under the new process, so that the aim of reducing electric leakage is fulfilled;
3) furthermore, in order to adapt to the source region implantation step, the ion implantation equipment is provided, the ion implantation equipment can simultaneously perform ion implantation operation on a plurality of chips, does not need to frequently turn off or turn on an ion implanter when performing the ion implantation operation on the plurality of chips, can reasonably arrange the interval size of each N + region, and can efficiently and accurately complete the ion implantation;
4) furthermore, the ion implantation equipment is provided with a chip support structure with a threaded section structure, a plurality of support frames are circumferentially arranged on the chip support, each support frame is provided with a chip to be implanted with ions, and the chip support can rotate when sliding rightwards by using a transversely moving driving cylinder structure, so that the chips aligned to the ion injection openings are adjusted, and the ion implantation process of the chips is continuously completed;
5) furthermore, the ion implantation equipment can adapt to ESD polysilicon common implantation and source region implantation steps in the process, the utilization rate of the equipment is improved, and when the common implantation is carried out, only the ion injection opening needs to be switched between full opening and full closing;
6) furthermore, the ion implantation equipment is adapted to the optimization process of the application, the efficiency and the quality of chip forming can be further improved by using the ion implantation equipment, the defect that the position between a chip and an ion implanter needs to be continuously adjusted during the existing ion implantation so as to obtain a chip with an ideal effect is avoided, the chip position only needs to be adjusted initially by using the ion implantation equipment, the subsequent ion implantation is automatically completed, the efficiency is improved, and the ion implantation quality of the chip is also ensured, so that the quality of a final finished product is ensured.
Drawings
FIG. 1 is a schematic diagram of a transistor obtained after a conventional TRENCH MOSFET process flow;
FIG. 2 is a schematic diagram of a transistor obtained after an optimized TRENCH MOSFET process flow;
fig. 3 is a front view of the ion implantation apparatus of the present invention;
FIG. 4 is a view A-A of FIG. 3;
fig. 5 is a top view of the cover plate.
Description of the reference symbols
1. Injecting into the chamber; 2. an ion implanter; 3. a cover plate; 4. a drive cylinder; 5. a support cylinder; 6. a chip holder; 7. a chip; 8. a drive cylinder; 9. a first thread section; 10. a main body support section; 11. a second thread section; 12. a support frame; 13. a chip support plate; 14. a first support frame; 15. a first cylinder wall; 16. driving the first screw thread; 17. a second support frame; 18. a second cylinder wall; 19. a second driving thread section; 20. recovering the cylinder; 21. a left support cylinder; 22. a right support cylinder; 23. a sliding seat; 24. an ion injection port; 25. a support frame; 26. and (4) sliding the cover plate.
Detailed Description
The present invention is further illustrated by the following examples, which are not intended to be limiting in any way, and any modifications or alterations based on the teachings of the present invention are intended to fall within the scope of the present invention.
A TRENCH MOSFET optimization process for integrating ESD diodes comprises the following steps:
1) forming a hard mask layer: providing a substrate, and forming a hard mask layer on the substrate;
2) opening the groove: forming a groove by etching or laser beam processing;
3) sacrificial oxidation: forming a sacrificial oxide layer by thermal oxidation;
4) gate oxidation-gate polycrystalline deposition-back etching-BODY injection;
5) depositing a TEOS layer with a certain thickness, depositing ESD intrinsic polysilicon, oxidizing polysilicon thin oxygen and carrying out BODY high-temperature annealing;
6) ESD polysilicon common injection: performing P-type impurity implantation by using an ion implanter;
7) ESD polysilicon photoetching, reverse etching-source region and ESD polysilicon photoetching;
8) source region injection: performing N in a source region+Injecting impurities;
9) NDR annealing;
10) BPSG deposition, reflow heat treatment, lead hole photoetching, etching, lead hole silicon etching, CT injection, RTA annealing, TI/TIN deposition and RTP annealing, W deposition/AL, Cu deposition;
11) metal etching-passivation-thinning back gold;
n is used in the whole BODY high-temperature annealing process in the step 5)2Annealing;
the PMOS does not need NDR annealing in the step 9);
the step 8) is completed by adopting specially-applicable ion implantation equipment, as shown in fig. 3-5, the ion implantation equipment comprises an implantation chamber 1, an ion implanter 2, a cover plate 3, a driving cylinder 4, a supporting cylinder 5 and a chip support 6, the chip support 6 comprises a main body supporting section 10, and a first threaded section 9 and a second threaded section 19 which are arranged at two ends of the main body supporting section 10, the main body supporting section 10 is of a cylindrical structure, a plurality of supporting frames 12 are uniformly distributed on the main body supporting section 10 along the circumferential direction of the axis, chip supporting plates 13 are arranged on the supporting frames 12, chips 7 are detachably fixed on the chip supporting plates 13, the driving cylinder 4 comprises a first supporting frame 14 and a first cylinder wall 15, a first driving thread 16 is arranged on the first cylinder wall 15, the first driving thread 16 is engaged with the first threaded section 9, a driving cylinder 8 is fixedly arranged on the first supporting frame 14, the right end of the driving cylinder 8 is abutted against the left end of the chip support 6, an ion implanter 2 is fixedly arranged at the upper end of the implantation chamber 1, and a cover plate 3 is fixedly arranged at the ion implanter 2The lower end, be provided with ion injection mouth 24 on the cover plate 3 to and can open or close the slip apron 26 of ion injection mouth 24, slip apron 26 slides under the drive of apron actuating mechanism, ion implantation machine 2 accomplishes the ion implantation of chip 7 through ion injection mouth 24, the screw pitch of screw thread section one 9 and drive screw thread one 16 sets up to, after the axis that actuating cylinder 8 stretches out to drive chip 7 and rotate along chip support 6 and pass a week, the distance that chip 7 removed along the axis of chip support 6 is two N that need pour into in step 8)+Interval L (two N) of regions+The width of the P-type impurity region between the regions), a vacuum pumping and evacuating device (not shown) is further disposed in the implantation chamber 1, and the vacuum pumping and evacuating operation can be performed on the implantation chamber 1.
Before the step 8), a plurality of chips 7 are loaded on the chip supporting plate 13, the area needing ion implantation is aligned with the ion injection port 24, then the sliding cover plate 26 is made to close the ion injection port 24, the vacuumizing device is operated to make the implantation chamber 1 in a vacuum state, the ion implanter 2 is started to enter the step 8), after the ions sprayed by the ion implanter 2 are stabilized, the ion injection port 24 is opened, the first chip is implanted with ions, after the implantation is finished, the ion injection port 24 is closed, the driving cylinder 8 is made to extend out, the chip support 6 is pushed to slide rightwards, the screw thread 16 is driven to rotate the support frame 12, when the second chip is rotated to be aligned with the ion injection port 24, the driving of the driving cylinder 8 is stopped, the ion injection port 24 is opened at the same time, and the ion implanter 2 performs ion implantation on the second chip, the operation is continued, and after the first chip rotates to the ion injection opening 24, the adjacent N can be carried out again+And repeating the ion implantation of the regions, finally completing the source region implantation of all the chips, closing the ion implanter 2, and taking out all the chips to perform the operation of the next step.
Preferably, the manner of mounting the chip 7 in the chip supporting plate 13 may be realized by vacuum adsorption, mechanical clamping, electromagnetic clamping, etc., and it is ensured that the chip 7 does not fall off when the supporting frame 12 is turned over, which is not a key point of the present invention and thus is not described herein again.
Preferably, in order to adjust the distance between the ion implanter 2 and the wafer, the lower end of the driving cylinder 4 is fixedly provided with a left supporting cylinder 21, and the lower end of the supporting cylinder 5 is fixedly provided with a right supporting cylinder 22; preferably, in order to facilitate taking of the chip, the side wall of the injection chamber 1 is provided with a door capable of being opened and closed, the left support cylinder 21 and the right support cylinder 22 are both fixedly arranged on the sliding seat 23, the sliding seat 23 is slidably arranged at the bottom of the injection chamber 1, when the chip is required to be mounted and dismounted, the door of the side wall is opened, and then the sliding seat 23 is pulled out, so that the chip on the chip support plate 13 can be mounted and dismounted conveniently.
Preferably, in order to ensure that the main body support section 10 can perform stable sliding, rotation and initialization, the support cylinder 5 comprises a second cylinder wall 18 and a second support frame 17, a recovery cylinder 20 is fixedly arranged on the second support frame 17, a second threaded section 19 is arranged on the second cylinder wall 18, the second threaded section 19 is engaged with the second drive threaded section 11, and after the recovery cylinder 20 extends out, the chip support 6 can slide leftwards, so that the initial position of the chip support 6 can be recovered.
Preferably, the plurality of support frames 12 are preferably 4, 6, 8, 12.
Preferably, in order to accurately control the sliding distance of the chip holder 6, each thread section is of a screw rod structure; preferably, the right end of the drive cylinder 8 and the left end of the recovery cylinder 20 are each rotatably fixedly connected to the left and right ends of the main body support section, respectively.
Preferably, the sliding cover plate 26 can also select the degree of covering the ion injection port 24, so that the adjustment can be performed according to the sizes of different ion injection regions; preferably, the cover plate driving mechanism is selected to be a driving cylinder, a driving oil cylinder or a screw rod driving mechanism, so long as the sliding cover plate 26 can be driven to slide.
Preferably, the ion injection inlet 24 has a strip-shaped hole structure;
preferably, the ion injection port 24 may also be a circular hole structure, at this time, the chip supporting plate 13 is rotatably disposed on the supporting frame 12, and can rotate along the axis of the supporting frame 12, so as to adjust the rotation angle of the chip 7, when the ion injection port 24 is a circular hole structure, when ion injection is performed on a first chip, the driving cylinder 8 is slowly extended, so that the ion implanter 2 can perform linear ion injection on the chip 7 through the ion injection port 24 by rotating the supporting frame 12, when ion injection is performed at this time, the angle of the chip 7 is first adjusted, so that lines formed on the chip 7 by ion injection meet the processing requirements of the chip 7, and a situation of oblique line ion injection cannot occur;
preferably, if the ion injection port 24 is a circular hole structure, the number of the supporting frames 12 is such that the chip 7 can surround the main body supporting section 10, at this time, the ion injection port 24 does not need to be opened or closed continuously, and when the chip 7 is subjected to ion injection, the driving cylinder 8 can push the chip support 6 to move rightward at a constant speed, so that the ion implanter 2 can perform uninterrupted ion injection operation on all chips placed on the chip supporting plate 13, thereby improving the ion injection efficiency.
Preferably, the cover plate 3 is fixedly arranged at the upper end of the support cylinder 5 through a support frame 25.
Preferably, the slide seat 23 may be provided with a driving wheel structure so that it can automatically slide out of or into the injection chamber 1.
Preferably, the positions of the supporting frames 12 may be set such that when the driving cylinder 8 pushes the chip holder 6 to slide rightward, and the chip 7 to be ion-implanted rotates to the position corresponding to the ion injection port 24 for the first time, the position of each chip 7 for the first ion implantation is the same, so as to ensure that all chips produced after the ion implantation by the ion implanter 2 are the same.
Preferably, the sequence and timing of the operation of the cylinders and the driving mechanism may be set by a program, or may be operated by remote control, which is not important here and will not be described again.
Preferably, whether each chip 7 reaches a position corresponding to the ion injection port 24 may be monitored by providing a video monitoring device, or may be determined by a preset position.
Preferably, a band-type brake mechanism is arranged on the driving cylinder 4 and/or the supporting cylinder 5, and the band-type brake mechanism can tightly hold the main body supporting section 10, so that the main body supporting section 10 can stay at a predetermined rotating position, and the smoothness of the ion implanter 2 in processing wafers is improved. Preferably, the band-type brake mechanism may be an electromagnetic band-type brake mechanism, which clamps the main body support section 10 when the band-type brake mechanism needs to be tightened, and releases the band-type brake mechanism when the main body support section 10 needs to be rotated, which is not a key point of the present invention and thus is not described herein again.
Preferably, the ESD polysilicon implantation in step 6) can also be performed by the ion implantation apparatus, which can be implemented by adjusting the opening size of the ion injection opening 24, and the specific ion implantation process is similar to that in step 8), but here, the ion injection opening 24 is preferably selected to have a strip-shaped hole structure, if the same ion implantation apparatus is selected in step 6) and step 8), the ion injection opening 24 is switched between full-open and full-closed in step 6) to perform the ion implantation operation on the chip, and the ion injection opening 24 is switched between full-closed and open with a certain gap in step 8) to perform the ion implantation operation on the chip.
Preferably, the position of the chip 7 to be subjected to ion implantation can be adjusted in real time through the actions of the left support cylinder 21, the right support cylinder 22 and the chip support plate 13, so that the ion implantation of the special position of the chip 7 is realized, and the diversity of the ion implantation is greatly improved.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make numerous possible variations and modifications to the present invention, or modify equivalent embodiments to equivalent variations, without departing from the scope of the invention, using the teachings disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention should fall within the protection scope of the technical scheme of the present invention, unless the technical spirit of the present invention departs from the content of the technical scheme of the present invention.
Claims (10)
1. A TRENCH MOSFET optimization process for integrating ESD diodes is characterized in that: the method comprises the following steps:
1) forming a hard mask layer: providing a substrate, and forming a hard mask layer on the substrate;
2) opening the groove: forming a groove by etching or laser beam processing;
3) sacrificial oxidation: forming a sacrificial oxide layer by thermal oxidation;
4) gate oxidation-gate polycrystalline deposition-back etching-BODY injection;
5) depositing a TEOS layer with a certain thickness, depositing ESD intrinsic polysilicon, oxidizing polysilicon thin oxygen and carrying out BODY high-temperature annealing;
6) ESD polysilicon common injection: performing P-type impurity implantation by using an ion implanter;
7) ESD polysilicon photoetching, reverse etching-source region and ESD polysilicon photoetching;
8) source region injection: performing N in a source region+Injecting impurities;
9) NDR annealing;
10) BPSG deposition, reflow heat treatment, lead hole photoetching, etching, lead hole silicon etching, CT injection, RTA annealing, TI and/or TIN deposition and RTP annealing, W deposition and/or Al and Cu deposition;
11) metal etching-passivation-thinning back gold.
2. A tree MOSFET optimization process integrating an ESD diode as claimed in claim 1, wherein: n is used in the whole BODY high-temperature annealing process in the step 5)2And (6) annealing.
3. A tree MOSFET optimization process integrating an ESD diode as claimed in claim 1, wherein: the PMOS does not require the NDR anneal of step 9).
4. A tree MOSFET optimization process integrating an ESD diode as claimed in claim 1, wherein: the step 8) is completed by adopting ion implantation equipment, soThe ion implantation equipment comprises an implantation chamber (1), an ion implanter (2), a cover plate (3), a driving cylinder (4), a supporting cylinder (5) and a chip support (6), wherein the chip support (6) comprises a main body supporting section (10), and a first screw thread section (9) and a second screw thread section (19) which are arranged at two ends of the main body supporting section (10), the main body supporting section (10) is of a cylindrical structure, a plurality of supporting frames (12) are uniformly distributed on the main body supporting section (10) along the axial direction of the main body supporting section in the circumferential direction, a chip supporting plate (13) is arranged on each supporting frame (12), a chip (7) is detachably and fixedly arranged on each chip supporting plate (13), the driving cylinder (4) comprises a first supporting frame (14) and a first cylinder wall (15), a first driving screw thread (16) is arranged on the first cylinder wall (15), and the first driving screw thread (16) is meshed with the first screw thread section (9), a driving cylinder (8) is fixedly arranged on the first support frame (14), the right end of the driving cylinder (8) is abutted against the left end of the chip support (6), the ion implanter (2) is fixedly arranged at the upper end of the implantation chamber (1), the cover plate (3) is fixedly arranged at the lower end of the ion implanter (2), an ion injection opening (24) is arranged on the cover plate (3), and a sliding cover plate (26) capable of opening or closing the ion injection hole (24), wherein the sliding cover plate (26) slides under the driving of a cover plate driving mechanism, the ion implantation of the chip (7) is completed by the ion implanter (2) through the ion injection hole (24), the thread pitches of the first thread section (9) and the first driving thread (16) are set, after the driving cylinder (8) extends out to drive the chip (7) to rotate for a circle along the axis of the chip bracket (6), the distance that the chip (7) moves along the axis of the chip support (6) is two N that need to be implanted in step 8).+And at the interval L of the areas, a vacuumizing and vacuumizing device is also arranged in the injection chamber (1) and can vacuumize and vacuumize the injection chamber (1).
5. A TRENCH MOSFET optimization process integrating ESD diodes as claimed in claim 4, wherein: before the step 8), a plurality of chips (7) are arranged on a chip supporting plate (13), the area needing ion implantation is aligned to an ion injection hole (24), then a sliding cover plate (26) is made to seal the ion injection hole (24), a vacuumizing device is made to act to enable the interior of an implantation chamber (1) to be in a vacuum state, an ion implanter (2) is started to enter the step 8), and after ions sprayed out by the ion implanter (2) are stabilized, the ion injection hole is opened(24) Carry out ion implantation to first chip, wait to pour into the back into, close ion injection mouth (24), make actuating cylinder (8) stretch out simultaneously, promote chip support (6) and slide right, drive screw thread (16) simultaneously make support frame (12) rotatory, after rotating second chip and aim at ion injection mouth (24), stop the drive of actuating cylinder (8), make ion injection mouth (24) open simultaneously, ion implantation machine (2) carry out ion implantation to second chip, so continue to move, wait that first chip again rotates behind ion injection mouth (24), can carry out adjacent N again+And repeating the ion implantation of the regions, finally completing the source region implantation of all the chips, closing the ion implanter (2), and taking out all the chips to carry out the operation of the next step.
6. A TRENCH MOSFET optimization process integrating ESD diodes as claimed in claim 5, wherein: the supporting cylinder (5) comprises a cylinder wall II (18) and a supporting frame II (17), a recovery cylinder (20) is fixedly arranged on the supporting frame II (17), a thread section II (19) is arranged on the cylinder wall II (18), the thread section II (19) is meshed with the driving thread section II (11), and the recovery cylinder (20) can slide the chip support (6) leftwards after extending out, so that the initial position of the chip support (6) can be recovered.
7. A tree MOSFET optimization process integrating an ESD diode as claimed in claim 3, wherein: the number of the support frames (12) is 4, 6, 8 or 12.
8. A tree MOSFET optimization process integrating an ESD diode as claimed in claim 3, wherein: the ion injection opening (24) is of a strip-shaped hole structure.
9. A tree MOSFET optimization process integrating an ESD diode as claimed in claim 3, wherein: ion injection mouth (24) are the circular hole structure, at this moment, the rotatable setting in support frame (12) of chip backup pad (13), can rotate along the axis of support frame (12), thereby can adjust the rotation angle of chip (7), when ion injection mouth (24) are the circular hole structure, when carrying out ion implantation to first chip, make driving cylinder (8) carry out slow extension simultaneously, thereby the rotation through support frame (12), make ion implantation machine (2) can carry out the linear injection of ion on chip (7) through ion injection mouth (24), when carrying out the ion implantation this moment, at first the angle of adjustment chip (7), make the lines that ion implantation formed on chip (7) satisfy the processing requirement of chip (7).
10. A tree MOSFET optimization process integrating an ESD diode as claimed in claim 3, wherein: the ESD polysilicon common injection in the step 6) is also finished by the ion injection equipment, the ESD polysilicon common injection can be realized by only adjusting the opening size of the ion injection opening (24), the ESD polysilicon common injection and the step 8) share one ion injection equipment, the ion injection opening (24) is switched between full opening and full closing when the step 6) is carried out, the ion injection operation is carried out on the chip, and the ion injection opening (24) is switched between full closing and a certain gap opening when the step 8) is carried out, and the ion injection operation is carried out on the chip.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116779666A (en) * | 2023-08-22 | 2023-09-19 | 深圳芯能半导体技术有限公司 | IGBT chip with ESD structure and manufacturing method thereof |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5454879A (en) * | 1994-03-17 | 1995-10-03 | Bolger; Stephen R. | Helically grown monolithic high voltage photovoltaic devices and method therefor |
| JPH11288680A (en) * | 1998-04-02 | 1999-10-19 | Ulvac Corp | Ion implanter and ion implanting method |
| US20040256578A1 (en) * | 2002-11-11 | 2004-12-23 | Applied Materials, Inc. | Ion implanter and a method of implanting ions |
| US20130234238A1 (en) * | 2012-03-12 | 2013-09-12 | Force Mos Technology Co., Ltd. | Semiconductor power device integrated with esd protection diodes |
| CN107346723A (en) * | 2017-07-13 | 2017-11-14 | 厦门芯光润泽科技有限公司 | A kind of ion implantation device for chip |
| CN109256314A (en) * | 2018-10-11 | 2019-01-22 | 中国电子科技集团公司第四十八研究所 | A kind of the fixed point ion implantation apparatus and method for implanting of substrate |
| US20190051488A1 (en) * | 2017-08-08 | 2019-02-14 | Infineon Technologies Ag | Ion Implantation Apparatus and Method of Manufacturing Semiconductor Devices |
| CN111490094A (en) * | 2020-04-20 | 2020-08-04 | 中国电子科技集团公司第五十八研究所 | Manufacturing method of trench split gate DMOS device with ESD protection structure |
| US20210104510A1 (en) * | 2019-10-02 | 2021-04-08 | Nami MOS CO., LTD. | Shielded gate trench mosfet with esd diode manufactured using two poly-silicon layers process |
-
2022
- 2022-02-17 CN CN202210145943.8A patent/CN114464536B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5454879A (en) * | 1994-03-17 | 1995-10-03 | Bolger; Stephen R. | Helically grown monolithic high voltage photovoltaic devices and method therefor |
| JPH11288680A (en) * | 1998-04-02 | 1999-10-19 | Ulvac Corp | Ion implanter and ion implanting method |
| US20040256578A1 (en) * | 2002-11-11 | 2004-12-23 | Applied Materials, Inc. | Ion implanter and a method of implanting ions |
| US20130234238A1 (en) * | 2012-03-12 | 2013-09-12 | Force Mos Technology Co., Ltd. | Semiconductor power device integrated with esd protection diodes |
| CN107346723A (en) * | 2017-07-13 | 2017-11-14 | 厦门芯光润泽科技有限公司 | A kind of ion implantation device for chip |
| US20190051488A1 (en) * | 2017-08-08 | 2019-02-14 | Infineon Technologies Ag | Ion Implantation Apparatus and Method of Manufacturing Semiconductor Devices |
| CN109256314A (en) * | 2018-10-11 | 2019-01-22 | 中国电子科技集团公司第四十八研究所 | A kind of the fixed point ion implantation apparatus and method for implanting of substrate |
| US20210104510A1 (en) * | 2019-10-02 | 2021-04-08 | Nami MOS CO., LTD. | Shielded gate trench mosfet with esd diode manufactured using two poly-silicon layers process |
| CN111490094A (en) * | 2020-04-20 | 2020-08-04 | 中国电子科技集团公司第五十八研究所 | Manufacturing method of trench split gate DMOS device with ESD protection structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116779666A (en) * | 2023-08-22 | 2023-09-19 | 深圳芯能半导体技术有限公司 | IGBT chip with ESD structure and manufacturing method thereof |
| CN116779666B (en) * | 2023-08-22 | 2024-03-26 | 深圳芯能半导体技术有限公司 | IGBT chip with ESD structure and manufacturing method thereof |
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