CN114461559A

CN114461559A - Hot plug method, system on chip and computer equipment

Info

Publication number: CN114461559A
Application number: CN202111560418.4A
Authority: CN
Inventors: 俎鹏宇; 王兴珍; 陈才; 张道明; 张明; 朱青山; 李信德
Original assignee: Phytium Technology Co Ltd
Current assignee: Phytium Technology Co Ltd
Priority date: 2021-12-17
Filing date: 2021-12-17
Publication date: 2022-05-10

Abstract

The invention discloses a hot plug method, a system on a chip and computer equipment, wherein the hot plug method comprises the following steps: acquiring the state of a register through a PCIE controller to determine the communication state between the system on chip and the peripheral; when the state of the register is in an L0 state, judging whether a link between the system on chip and the peripheral falls off, if so, adjusting the value of a register state flag bit to recover the communication between the system on chip and the peripheral; if not, the normal link state between the system on chip and the peripheral is indicated. The invention can make up the inherent defects of the hardware platform and stably realize the hot plug of the PCIE.

Description

Hot plug method, system on chip and computer equipment

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a hot plug method for a hardware platform that does not support hot plug for PCIE devices, a system on a chip, and a computer device.

Background

In the prior art, the PCIE card has two sideband signals — PRSNT1# and PRSNT2# for hot-plug mechanism. These two signals on a PCIE card device are shorted, and the PRSNT1# of the PCIE slot is fixedly connected to ground, while PRSNT2# is pulled up. When a PCIE card device is not fully inserted into a slot, the PRSNT2# signal of the slot will always be in a high-point-flat state due to the pull-up. When the PCIE card device is fully inserted into the slot, the PRSNT2# signal on the slot is connected to ground by the short-circuited line of the PCIE card device, so that it goes low. In other words, from the perspective of the slot, when the PRSNT2# bit is high, it is considered that the PCIE card device is not correctly inserted or is not provided with a PCIE card device; when PRSNT2# is low, it indicates that the PCIE card device is properly inserted into the slot. The CPU of the computer can judge the insertion condition of the PCIE card by detecting the two sideband signals and generate an interrupt signal, thereby realizing the hot plug of the PCIE card.

However, for some hardware platforms using a specific CPU, in the hardware design, a circuit for detecting a drop signal of a PCIE device is not designed, so that the CPU cannot detect sideband signals of PRSNT1# and PRSNT2#, and cannot generate an interrupt, so that a PCIE card slot cannot be scanned normally, resources cannot be allocated to the PCIE device, and a PCIE hot plug function is not supported. However, in the hardware platform of this type, there is still a requirement for PCIE hot plug, and therefore, research is needed, and a hot plug solution is proposed in a hardware platform that does not support hot plug, so as to better exert the performance of the hardware platform and improve the applicability of the hardware platform.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides a hot-plugging method, a system on a chip and computer equipment, which are used for overcoming the functional defects of a hardware platform which does not support PCIE hot-plugging.

In order to solve the technical problems, the technical scheme provided by the invention is as follows:

a hot plug method is applied to a system on chip, the system on chip comprises a PCIE controller and a register, the PCIE controller is connected with the register, and the system on chip and peripheral equipment realize communication through a bus interface; the register is provided with a target storage space, and the target storage space is correspondingly provided with a status flag bit; the state flag bit is used for indicating the state of the system on chip when communicating with the peripheral; the method comprises the following steps: (ii) a

Acquiring the state of a register through a PCIE controller;

when the state of the register is in the L0 state, judging whether a link between the system on chip and the peripheral falls off, if so, setting a state flag bit corresponding to the target storage space to a preset value so as to restore the communication between the system on chip and the peripheral; if not, the normal link state between the system on chip and the peripheral is indicated.

Further, the system on chip further includes a memory connected to the PCIE controller, and the method further includes:

and indicating the memory to allocate a configuration space for the peripheral equipment through the PCIE controller so as to ensure information interaction between the system on chip and the peripheral equipment.

Further, when the peripheral device is set as a first type device, after the state of the register is acquired by the PCIE controller, if the state of the register is a detect state, the link state attribute of the register is modified, the communication link between the system on chip and the peripheral device is trained, and the state of the register is reacquired by the PCIE controller.

Further, the method also comprises the step of identifying that the peripheral executes the pulling operation: and checking the data content stored in the memory through a PCIE controller, judging that the configuration space is abnormal when the data content is an abnormal value, and identifying that the peripheral executes the pulling-out operation.

Further, instructing, by the PCIE controller, the memory to allocate a configuration space for the peripheral specifically includes: when the state of the register is in the state of L0, if a communication link between the system on chip and the peripheral falls, the PCIE controller instructs the memory to dynamically allocate a configuration space according to the requirement of the peripheral; and training a communication link between the system on chip and the peripheral when the state of the register does not reach the L0 state until the state of the register is in the L0 state.

Further, the step of the PCIE controller instructing the memory to dynamically allocate the configuration space according to the peripheral requirement includes: acquiring a link state of a register, preventing a TLP (TLP packet) sent by a PCIE (peripheral component interface express) controller and informing a memory to redistribute a configuration space, modifying the link state of the register and releasing a TLP packet signal if the link state of the register is a target value, and informing the memory to distribute the corresponding configuration space in real time according to the peripheral requirement.

The invention also provides a system on chip, which comprises a PCIE controller and a register, wherein the PCIE controller is connected with the register, the system on chip is communicated with external equipment through a bus interface, the register is provided with a target storage space, and the target storage space is correspondingly provided with a state flag bit; the state flag bit is used for indicating the state of the system on chip when communicating with the peripheral; the PCIE controller is configured to:

acquiring the state of a register;

when the state of the register is in an L0 state, judging whether a link between the system on chip and the peripheral falls off, if so, setting a state flag bit corresponding to the target storage space to a preset value so as to restore the communication between the system on chip and the peripheral; if not, the normal link state between the system on chip and the peripheral is indicated.

Further, the system on chip further includes a memory coupled to the PCIE controller, and the PCIE controller is further configured to: and indicating the memory to allocate configuration space for the peripheral to ensure information interaction between the system on chip and the peripheral.

Further, when the peripheral device is set as a first type device, the PCIE controller is configured to: after the state of the register is obtained, if the state of the register is a detect state, the link state attribute of the register is modified, a communication link between the system on chip and the peripheral is trained, and the state of the register is obtained again. .

The invention also provides computer equipment, wherein a system on chip is arranged in the computer equipment, the system on chip comprises a PCIE controller and a register, the PCIE controller is connected with the register, and the system on chip and the peripheral realize communication through a bus interface; the PCIE controller is used for executing any hot plug method.

Compared with the prior art, the invention has the advantages that:

1. the invention aims at standard PCIE equipment, judges whether the PCIE card is inserted into the PCIE card slot or not by monitoring the state of the register, determines whether the link state of the PCIE card is normal or not by link connection and drop detection, and determines whether the PCIE card is pulled out from the PCIE card slot or not by detecting the configuration space content of the memory, thereby overcoming the functional defect that a hardware platform based on a specific CPU does not support the PCIE hot plug and realizing the PCIE hot plug.

2. According to the technical scheme, on the basis of hot plug of the standard PCIE equipment, for the non-standard PCIE equipment (FPGA equipment), the state of the register is monitored, the link state attribute of the register is modified when the state is the detect state, and then the link training is restarted, so that the technical scheme can be applicable to the hot plug of the FPGA equipment.

3. The technical scheme of the invention bypasses the function defects of a hardware platform of a specific CPU, can simply and efficiently realize the hot plug of standard PCIE equipment and non-standard PCIE equipment, and has good stability; meanwhile, the technical scheme of the invention can process and configure the link state register and the configuration space corresponding to each PCIE card slot, thereby realizing hot plug operation aiming at a single PCIE device and not influencing the normal work of other PCIE devices on a hardware platform.

Drawings

FIG. 1 is a diagram illustrating steps of a hot-plug method according to the present invention.

Fig. 2 is a schematic flow chart according to a first embodiment of the present invention.

Fig. 3 is a schematic diagram of state machine state transition logic of the Ltssm state register according to the first embodiment of the present invention.

Fig. 4 is a flowchart illustrating a second embodiment of the present invention.

Fig. 5 is a schematic diagram of a system on chip according to a third embodiment of the invention.

Detailed Description

The invention is further described below with reference to the drawings and specific preferred embodiments of the description, without thereby limiting the scope of protection of the invention.

In the prior art, hot plug detection is performed by detecting changes of two sideband signals, namely PRSNT1# and PRSNT2# of a PCIE slot, PRSNT1# is fixedly located at a low level state, PRSNT2# is located at a high level state when a PCIE card device is not completely inserted into the PCIE slot, PRSNT2# is changed to a low level state after the PCIE card device is completely inserted into the PCIE slot, a CPU determines the insertion condition of the PCIE card by detecting the two sideband signals, when no PCIE card device is inserted into the PCIE slot or the PCIE card device is not completely inserted into the PCIE slot, the CPU detects that PRSNT1# is located at the low level and PRSNT2# is located at the high level, determines that the PCIE card device is not inserted, maintains the state of the entire platform, and when the PCIE card device is completely inserted into the PCIE slot, the CPU detects that PRSNT1# and prt 2# are both located at the low level, determines that the PCIE card device is inserted into the slot, generates an interrupt, and allocates a PCIE card space, thereby realizing hot plug.

Introduction of related terms:

PCIE: PCI-express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard, and the connection between any two PCIe devices is called a link and is constructed from a collection of one or more lanes. All devices must minimally support single channel (x 1) links. The device may optionally support a wider link consisting of 2,4,8,12,16 or 32 lanes. PCIe sends all control messages, including interrupts, over the same link as the data. PCIe Express links reliably transfer Transaction Layer Packets (TLPs) between two endpoints through acknowledgement protocols (ACK and NAK signaling) that explicitly require replay of unacknowledged/bad TLPs.

A CPU: a Central Processing Unit (CPU) is a final execution unit for information processing and program operation, and serves as an operation and control core of a computer system.

And (3) link training: before the PCIe Link can work normally, Link Training is required for the PCIe Link, and in this process, a Link Training and Status State Machine (LTSSM) is used, and this State Machine is in the physical layer of the PCIe bus. The LTSSM contains 11 top-level states: detect, Polling, Configuration, Recovery, L0, L0s, L1, L2, Hot Reset, Loopback, and Disable. After various resets (Reset), the change of the state machine is: detect > Polling > Configuration > L0. Standard data interaction can be performed in the L0 state.

Introduction of standard PCIE devices:

the standard PCIE equipment is used as an Add-In card to be matched with a PCIE slot, and the PRSNT1# signal and the PRSNT2# signal of the standard PCIE equipment are directly connected, so that when the Add-In card is completely inserted into the PCIE slot, the PRSNT2# signal of the PCIE slot is communicated with the PRSNT1# signal through the Add-In card, and at the moment, the PRSNT2# signal is low. When the hot plug function is realized, the standard PCIE equipment needs to use a 'long and short pin' structure, and the length of the gold finger used by the PRSNT1# and PRSNT2# signals is half of that of other signals, so when the PCIE equipment is inserted into a slot, the PRSNT1# and PRSNT2# signals are in complete contact with the PCIE slot at other gold fingers, and can be in complete contact with the PCIE slot after a period of time delay; when the standard PCIE device is pulled out from the PCIE slot, the two signals are disconnected from the PCIE slot first, and after a period of delay, other signals can be disconnected from the slot. The system software may use this delay to perform some hot-plug processing.

Introduction of FPGA equipment:

FPGA (field Programmable Gate array) is a product of further development on the basis of Programmable devices such as PAL, GAL and the like. The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs), not only solves the defects of custom circuits, but also overcomes the defect that the number of gate circuits of the original programmable device is limited, and adopts the concept of a Logic Cell Array (LCA), wherein the Logic Cell array internally comprises a Configurable Logic Block (CLB), an input-Output block (IOB) and an internal connecting line (Interconnect). A Field Programmable Gate Array (FPGA) is a programmable device that has a different structure than traditional logic circuits and gate arrays (such as PAL, GAL and CPLD devices). The FPGA utilizes small lookup tables (16 × 1RAM) to realize combinational logic, each lookup table is connected to the input end of a D flip-flop, and the flip-flops drive other logic circuits or drive I/O (input/output) circuits, so that basic logic unit modules capable of realizing both combinational logic functions and sequential logic functions are formed, and the modules are connected with each other or connected to an I/O (input/output) module by utilizing metal connecting wires. The logic of the FPGA is implemented by loading programming data into the internal static memory cells, the values stored in the memory cells determine the logic function of the logic cells and the way of the connections between the modules or between the modules and the I/O and finally the functions that can be implemented by the FPGA, which allows an unlimited number of programming.

Compared with a standard PCIE device, the FPGA accelerator card based on the PCIE interface is used as a complete programming device, does not actively perform link training in the PCIE hot plug process, and needs a controller to send a link training request, so that the device rebuilds a link.

Example one

The scheme provides a hot plug method for a hardware platform, wherein the hardware platform does not support PCIE hot plug, and the hot plug method is applied to a system on chip, the system on chip comprises a PCIE controller, a register and a memory, the PCIE controller is respectively connected with the register and the memory, the system on chip and peripheral equipment realize communication through a bus interface, the register is provided with a target storage space, and the target storage space is correspondingly provided with a status flag bit, for example, the status flag bit can be bit 0; the state flag bit0 is used for indicating the state of the system on chip when communicating with the peripheral; the PCIE controller indicates the memory to allocate configuration space for the peripheral equipment so as to ensure information interaction between the system on chip and the peripheral equipment; as shown in fig. 1, the method includes:

acquiring the state of a register through a PCIE controller, wherein when the state of the register is a Detect state, the peripheral executes an inserting operation;

when the state of the register is in the L0 state, the peripheral and the system on chip can start data interaction, at this time, whether a link between the system on chip and the peripheral drops or not is judged, if yes, a state flag bit0 is set to be a preset value, so that communication between the system on chip and the peripheral is recovered; if not, the normal link state is established between the system on chip and the peripheral equipment, and when the normal link state is established between the system on chip and the peripheral equipment, the system on chip identifies the inserted peripheral equipment;

and checking data contents stored in a configuration space allocated to the peripheral equipment by the memory through a PCIE controller, judging that the configuration space is abnormal when the data contents are abnormal values, identifying that the peripheral equipment executes the pulling-out operation, otherwise judging that the configuration space is normal, identifying that the peripheral equipment does not execute the pulling-out operation, and maintaining data interaction with the system on chip.

According to the scheme, whether the PCIE card is inserted into the PCIE card slot or not is judged by monitoring the state of the register, the PCIE card is connected through the link and is dropped for detection, whether the link state of the PCIE card is normal or not is determined, and whether the PCIE card is pulled out of the PCIE card slot or not is determined by detecting the configuration space content of the PCIE, so that the functional defect that a hardware platform based on a specific CPU does not support PCIE hot plug can be overcome, and the PCIE hot plug is realized.

In this embodiment, for a situation that an external FPGA device is set, the FPGA device of the PCIE interface is used as the first type device, as shown in fig. 2, the hot plug method of this embodiment, for the first type device, includes the following steps:

s1, monitoring the state of a PEU link state register through a PCIE controller, modifying a link state attribute of the PEU link state register into disable when the state of the PEU link state register is monitored, starting retraining of a communication link between the system on chip and the peripheral equipment, monitoring the state of the PEU link state register, indicating a memory to dynamically distribute a configuration space of the peripheral equipment, and jumping to a step S2 when the state of the PEU link state register reaches an L0 state;

s2, the PCIE controller detects whether a link falls in the communication between the system on chip and the peripheral equipment in a preset time period, when the link falls, the state flag bit0 of the register can be set to be 0, and the step S3 is skipped; otherwise, keeping the allocated configuration space of the peripheral unchanged and jumping to step S3;

s3, the PCIE controller checks whether the configuration space of the peripheral equipment in the memory is normal or not, and if the configuration space is normal, hot insertion of the PCIE equipment is completed; otherwise, recognizing that the peripheral executes the pulling operation, and re-instructing the memory to dynamically allocate the configuration space of the rest peripheral. The above examples are merely illustrative and should not be construed as limiting.

In this embodiment, the corresponding PCIE link status may be checked by checking the ltsm status register, and whether the L0 status is reached is determined by the value of the ltsm status register. Specifically, the state machine of the Ltssm state register covers 11 states, including Detect, poll, Configuration, Recovery, L0, L0s, L1, L2, Hot Reset, Loopback, Disable. The logic for transitioning between these 11 states is shown in fig. 3. When the PCIE link is retrained, the state is called Recovery; and L0 is the power state where the PCIE link can work normally; under normal conditions, the PCIE link training state transition process sequentially includes: detect- > Polling- > Configuration- > L0. When the state of the monitoring PEU link status register is in a Detect state, it indicates that the PCIE card has been inserted into the PCIE card slot, and when the state of the monitoring PEU link status register is in an L0 state, the PCIE link may start to work normally.

In this embodiment, the step S3 of checking whether the configuration space of the peripheral device in the memory is normal includes: the data content stored in the configuration space allocated by the memory for the peripheral is checked through the PCIE controller, and when the data content is an abnormal value, it is determined that the configuration space is abnormal, otherwise, it is determined that the configuration space is normal.

Specifically, the configuration space of the PCIE may adopt a fixed address space, for example, the range of the fixed address space is: 0x40000000-0x4FFFFFFF, with a memory size of 256M. Whether the configuration space of the PCIE is normal can be judged by checking whether the value in the address is normal, and when the data stored in the configuration space is all F, the configuration space is abnormal, which indicates that the corresponding peripheral equipment is pulled out; the value in the address is a specific numerical value allocated to the device, for example, 0012e 010000087020000201000033 c22 and the like, which indicates that the configuration space is normal, and it indicates that the corresponding peripheral device is normally operated after being inserted, when there is only one PCIE device, the configuration space allocated to the device is the size of the entire storage space in the memory, and when the corresponding configuration space is abnormal when the PCIE device is pulled out, the data of the entire storage space in the memory is all "F"; when there are multiple PCIE devices, the memory dynamically allocates the size of the corresponding configuration space to each inserted PCIE device according to the requirements of the devices, and if a single PCIE device is pulled out and the configuration space corresponding to the pulled-out device is abnormal, the data stored in the local address corresponding to the PCIE device in the memory is all displayed as "F", and other areas are not affected.

In this embodiment, the step S1 and the step S3 of allocating the memory allocation configuration space include: if the link state module and the link drop state module are in normal states, the corresponding configuration space size is dynamically allocated to each inserted PCIE device according to the needs of the device, in general, the configuration space of the PCIE device can be normally reallocated after the above processing procedure, and if the PCIE link does not reach the working state of the normal link L0, link training needs to be performed again, so that the PCIE link can be normally allocated.

Specifically, when allocating a configuration space of a PCIE device, first, the corresponding PCIE link state is checked by checking an Ltssm state register, whether the corresponding PCIE link state reaches the L0 state is determined by a value of the Ltssm state register, and if the corresponding PCIE link state reaches the L0 state, then, whether a link state bit of the Ltssm state register is 1 is observed, at this time, the PCIE controller is prevented from sending a TLP notifying that the configuration space is reallocated to the memory, and if the link state bit is 1, the link state position is 0, and a TLP signal is released, and the memory is notified to allocate the corresponding configuration space to each inserted PCIE device in real time according to a requirement of the device; if the link status bit is 0, preventing the TLP signal from being released, and keeping the current configuration space size of each inserted PCIE device; if the value of the Ltssm status register does not reach the L0 status, it indicates that the PCIE link does not reach the working status of the normal link L0, and at this time, the PCIE link training is performed again to correct the error.

In step S1 of this embodiment, after recognizing that the peripheral executes the insert operation, modify the link state attribute of the PEU link state register to disable, and perform PCIE link training again. This is because the FPGA device based on the PCIE interface does not actively perform link training in the process of performing PCIE hot plug, and therefore the link rate of interaction between the inserted system on chip and the peripheral device is not the highest rate, which limits the performance of the peripheral device. Therefore, when the state of the PEU link state register is monitored to be a Detect state, it indicates that the FPGA device of the PCIE interface is inserted into the PCIE card slot, because the FPGA device does not actively perform link training in the process of performing PCIE hot plug, therefore, after the device is inserted into the PCIE card slot, the link connection is disconnected, then the retraining of the PEU link is started, therefore, the corresponding configuration space size is dynamically distributed to each hot-plugged FPGA device according to the requirement of the device and the link connection is reestablished, meanwhile, because the FPGA equipment can support higher transmission rate, and the retraining can also carry out Speed Change, the parameters of Bit Lock, Symbol Lock and the like of the PCIE link are acquired again, and readjusting the Width of the PCIE link to enable the link speed to be adjusted to 5.0GT/s or 8.0GT/s from 2.5GT/s of the state of entering the L0 for the first time, thereby being more suitable for the speed requirement of the FPGA equipment.

Example two

In this embodiment, for a situation that an external device is set as a standard PCIE device, the standard PCIE device is used as a second type device, as shown in fig. 4, the hot plug method in this embodiment is applied to the second type device, and includes the following steps:

s1, a PCIE controller monitors the state of a PEU link state register, indicates a memory to dynamically allocate a configuration space of the peripheral, and jumps to a step S2 when the state of the PEU link state register reaches an L0 state from a Detect state;

s2, the PCIE controller detects whether a link falls in the communication between the system on chip and the peripheral equipment in a preset time period, when the link falls, a state flag bit0 of the register is set to be 0, and the step S3 is skipped; otherwise, keeping the allocated configuration space of the peripheral unchanged and jumping to step S3;

s3, the PCIE controller checks whether the configuration space of the peripheral equipment in the memory is normal or not, and if the configuration space is normal, hot insertion of the PCIE equipment is completed; otherwise, recognizing that the peripheral executes the pulling operation, and re-instructing the memory to dynamically allocate the configuration space of the rest peripheral.

In this embodiment, the step S3 of checking whether the configuration space of the peripheral device in the memory is normal includes: the data content stored in the configuration space allocated to the peripheral by the memory is checked by the PCIE controller, and when the data content is an abnormal value, it is determined that the configuration space is abnormal, otherwise, it is determined that the configuration space is normal.

In this embodiment, the step S1 and the step S3 of dynamically allocating the configuration space for the memory include: if the link state module and the link drop state module are in normal states, the corresponding configuration space size is dynamically allocated to each inserted PCIE device according to the needs of the device, in general, the configuration space of the PCIE device can be normally reallocated after the above processing procedure, and if the PCIE link does not reach the working state of the normal link L0, link training needs to be performed again, so that the PCIE link can be normally allocated.

It is noted that while for simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present disclosure is not limited by the order of acts, as some steps may, in accordance with the present disclosure, occur in other orders and concurrently. Further, those skilled in the art will also appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules referred to are not necessarily required by the disclosure.

It should be further noted that, taking fig. 1 as an example, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily executed in sequence as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 1 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

EXAMPLE III

Corresponding to the methods in the first and second embodiments, this embodiment provides a system on a chip, as shown in fig. 5, including a PCIE controller and a register, where the PCIE controller is connected to the register, the register is provided with a target storage space, and the target storage space is corresponding to a status flag bit; the state flag bit is used for indicating the state of the system on chip when communicating with the peripheral; the system on chip and the peripheral realize communication through a bus interface, wherein:

the register is configured to save a state of the link training;

the memory is configured for dynamically allocating configuration space for the peripheral;

the PCIE controller is configured to instruct the memory to allocate a configuration space for the peripheral device, and is further configured to obtain a state of the register, where when the state of the register is in an L0 state, it is determined whether a link between the system on chip and the peripheral device drops, and if so, a status flag bit corresponding to a target storage space is set to a preset value, for example, in this embodiment, the status flag bit0 may be set to 0, so as to recover communication between the system on chip and the peripheral device; if not, the normal link state is established between the system on chip and the peripheral equipment, and when the normal link state is established between the system on chip and the peripheral equipment, the system on chip identifies the inserted peripheral equipment.

In this embodiment, the PCIE controller is further configured to check data contents stored in the configuration space that has been allocated to the peripheral by the memory, when the data contents are abnormal values, all of the abnormal values are "F" in this embodiment, determine that the configuration space is abnormal, identify that the peripheral performs a pull-out operation, re-instruct the memory to dynamically allocate the configuration space of the remaining peripheral, otherwise determine that the configuration space is normal, identify that the peripheral does not perform a pull-out operation, and complete hot plug of the peripheral.

In this embodiment, when the external device is an FPGA device with a PCIE interface, the PCIE controller is further configured to modify a link state attribute of the register to disable after acquiring the state of the register and when the state of the register is a detect state, start retraining of a communication link between the system on chip and the external device, and acquire the state of the register again.

The embodiment further provides a computer device, where a system on chip is disposed in the computer device, where the system on chip includes a PCIE controller and a register, the PCIE controller is connected to the register, and the system on chip and the peripheral device realize communication through a bus interface; the PCIE controller is configured to execute the hot plug method described in the first embodiment or the second embodiment.

Embodiments of the present application also provide a computer storage medium having stored therein instructions, which when executed on a computer or processor, cause the computer or processor to perform one or more steps of any of the above-described method embodiments.

Based on the understanding that the constituent modules of the above-described apparatus, if implemented in the form of software functional units and sold or used as independent products, may be stored in a computer-readable storage medium, and that, in essence, a part of the technical solution of the present application or all or part of the technical solution may be embodied in the form of a software product, and the computer product is stored in the computer-readable storage medium.

The computer-readable storage medium may be an internal storage unit of the device of the foregoing embodiment, such as a hard disk or a memory. The computer readable storage medium may be an external storage device of the above-described apparatus, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like. Further, the computer-readable storage medium may include both an internal storage unit and an external storage device of the device. The computer-readable storage medium is used for storing the computer program and other programs and data required by the apparatus. The above-described computer-readable storage medium may also be used to temporarily store data that has been output or is to be output.

Those skilled in the art can understand that all or part of the processes in the methods of the above embodiments can be implemented by instructing the relevant hardware by a computer program, where the computer program can be stored in a computer-readable storage medium, and when executed, the computer program can include the processes of the embodiments of the methods as described above. And the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.

The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to execute some steps of the methods according to the embodiments of the present application. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention should fall within the protection scope of the technical scheme of the present invention, unless the technical spirit of the present invention departs from the content of the technical scheme of the present invention.

Claims

1. A hot plug method is characterized in that the method is applied to a system on chip, the system on chip comprises a PCIE controller and a register, the PCIE controller is connected with the register, and the system on chip and peripheral equipment realize communication through a bus interface; the register is provided with a target storage space, and the target storage space is correspondingly provided with a status flag bit; the state flag bit is used for indicating the state of the system on chip when communicating with the peripheral; the method comprises the following steps:

acquiring the state of a register through a PCIE controller;

2. The hot plug method of claim 1, wherein the system-on-chip further comprises a memory coupled to the PCIE controller, the method further comprising:

3. A hot plug method according to claim 1, wherein when the peripheral device is the first type device, after the state of the register is acquired by the PCIE controller, if the state of the register is a detect state, the link state attribute of the register is modified, the communication link between the system on chip and the peripheral device is trained, and the state of the register is reacquired by the PCIE controller.

4. The hot plug method according to claim 2, further comprising the step of identifying that the peripheral device performs a unplugging operation: and checking the data content stored in the memory through a PCIE controller, judging that the configuration space is abnormal when the data content is an abnormal value, and identifying that the peripheral executes the pulling-out operation.

5. The hot plug method according to claim 2, wherein the instructing, by the PCIE controller, the memory to allocate the configuration space to the peripheral specifically comprises: when the state of the register is in the state of L0, if a communication link between the system on chip and the peripheral falls, the PCIE controller instructs the memory to dynamically allocate a configuration space according to the requirement of the peripheral; and training a communication link between the system on chip and the peripheral when the state of the register does not reach the L0 state until the state of the register is in the L0 state.

6. The hot plug method of claim 4, wherein the PCIE controller instructing the memory to dynamically allocate the configuration space according to the peripheral device's requirements comprises: acquiring a link state of a register, preventing a TLP (TLP packet) sent by a PCIE (peripheral component interface express) controller and informing a memory to redistribute a configuration space, modifying the link state of the register and releasing a TLP packet signal if the link state of the register is a target value, and informing the memory to distribute the corresponding configuration space in real time according to the peripheral requirement.

7. A system on a chip, characterized by: the system on chip comprises a PCIE controller and a register, wherein the PCIE controller is connected with the register, the system on chip and peripheral equipment realize communication through a bus interface, the register is provided with a target storage space, and the target storage space is correspondingly provided with a status flag bit; the state flag bit is used for indicating the state of the system on chip when communicating with the peripheral; the PCIE controller is configured to:

acquiring the state of a register;

8. The system on a chip of claim 7, further comprising a memory coupled to the PCIE controller, the PCIE controller further configured to: and indicating the memory to allocate configuration space for the peripheral to ensure information interaction between the system on chip and the peripheral.

9. The system on a chip of claim 7, wherein the peripheral device is configured to, when configured as a first type of device, the PCIE controller is configured to: after the state of the register is obtained, if the state of the register is a detect state, the link state attribute of the register is modified, a communication link between the system on chip and the peripheral is trained, and the state of the register is obtained again.

10. A computer device is characterized in that a system on chip is arranged in the computer device, the system on chip comprises a PCIE controller and a register, the PCIE controller is connected with the register, and the system on chip and the peripheral realize communication through a bus interface; the PCIE controller is used for executing the hot plug method of any one of claims 1-6.